Intrinsic Silicon Properties • Read textbook, section 3.2.1, 3.2.2, 3.2.3 • Intrinsic Semiconductors – undoped (i.e., not n+ or p+) silicon has intrinsic charge carriers – electron-hole pairs are created by thermal energy 10 -3 – intrinsic carrier concentration ≡ ni = 1.45x10 cm , at room temp. – function of temperature: increase or decrease with temp? – n = p = ni, in intrinsic (undoped) material •n ≡ number of electrons, p ≡ number of holes 2 – mass-action law, np = ni • applies to undoped and doped material ECE 410, Prof. A. Mason Lecture Notes 6.1 Extrinsic Silicon Properties •doping, adding dopants to modify material properties n-type Donor – n-type = n+, add elements with extra an electron + • (arsenic, As, or phosphorus, P), Group V elements + - P P electron free •nn ≡ concentration of electrons in n-type material group V ion element carrier -3 •nn = Nd cm , Nd ≡ concentration of donor atoms •p ≡ concentration of holes in n-type material n n+/p+ defines region 2 •Nd pn = ni , using mass-action law as heavily doped, – always a lot more n than p in n-type material typically ≈ 1016-1018 cm-3 less highly doped regions – p-type = p+, add elements with an extra hole generally labeled n/p • (boron, B) (without the +) •pp ≡ concentration of holes in p-type material p-type Acceptor -3 - •pp = Na cm , Na ≡ concentration of acceptor atoms B B + + •np ≡ concentration of electrons in p-type material hole free 2 group III ion •Na np = ni , using mass-action law element carrier – always a lot more p than n in p-type material do example on board 2 20 –if both Nd and Na present, nn = Nd-Na, pp=Na-Nd ni = 2.1x10 ECE 410, Prof. A. Mason Lecture Notes 6.2 Conduction in Semiconductors • doping provides free charge carriers, alters conductivity • conductivity, σ, in semic. w/ carrier densities n and p -19 – σ = q(μnn + μpp), q ≡ electron charge, q = 1.6x10 [Coulombs] 2 • μ≡mobility [cm /V-sec], μn ≅ 1360, μp ≅ 480 (typical values) • in n-type region, nn >> pn mobility = average velocity per Mobility often assumed constant – σ≈qμnnn unit electric field but is a function of μn > μp • in p-type region, pp >> np Temperature and Doping electrons more mobile than holes Concentration – σ≈qμpnp ⇒conductivity of n+ > p+ • resistivity, ρ = 1/σ t • resistance of an n+ or p+ region –R = ρ l , A = wt w l A • drift current (flow of charge carriers in presence of an electric field, Ex) – n/p drift current density: Jxn = σn Ex = qμnnnEx, Jxp = σp Ex = qμpppEx – total drift current density in x direction Jx = q(μnn + μpp) Ex = σ Ex ECE 410, Prof. A. Mason Lecture Notes 6.3 pn Junctions: Intro contact contact • What is a pn Junction? to p-side to n-side depletion region boundaries p+ n+ – interface of p-type and dielectric n “well” pn diode insulator n-type semiconductor junction (oxide) p-type Si wafer – junction of two materials forms a diode p-type n-type p-type + + + + - - - n-type • In the Beginning… - - - - + + + -+ -+ -+ -+ + + - - - - 3 - - – ionization of dopants + + + + 3 N acceptors/cm N donors/cm A D hole diffusion - at material interface hole current + donor ion and electron free carrier electron diffusion + electron current - acceptor ion and hole free carrier • Diffusion -movement of charge to regions of lower concentration electric field – free carries diffuse out depletion region E – leave behind immobile ions p-type - - + + n-type – region become depleted of - - + free carriers - + + 3 - + 3 N acceptors/cm - N donors/cm – ions establish an electric field A - + + D x x immobile acceptor ions p n immobile donor ions • acts against diffusion (negative-charge) (positive-charge) W ECE 410, Prof. A. Mason Lecture Notes 6.4 pn Junctions: Equilibrium Conditions electric field E • Depletion Region depletion region p-type - + + n-type – area at pn interface - - + - + + void of free charges NA - ND 3 - + 3 N acceptors/cm - N donors/cm A - + + D – charge neutrality x x immobile acceptor ions p n immobile donor ions • must have equal charge on both sides (negative-charge) (positive-charge) W •q A xp NA = q A xn ND , A=junction area; xp, xn depth into p/n side • ⇒ xp NA = xn ND • depletion region will extend further into the more lightly doped side of the junction • Built-in Potential – diffusion of carriers leaves behind immobile charged ions – ions create an electric field which generates a built-in potential ⎛ NN ⎞ =Ψ V ln⎜ DA ⎟ 0 T ⎜ 2 ⎟ ⎝ ni ⎠ •where VT = kT/q = 26mV at room temperature ECE 410, Prof. A. Mason Lecture Notes 6.5 pn Junctions: Depletion Width dec fiieleltrc • Depletion Width ongie ronietplde E use Poisson’s equation & charge neutrality p-tpye - + + n-tpye - - + - + + x = –Wp + xn NA - ND 3 - + 3 1 N msc/orept acc - N /cmsr dono 1 A - + + D 2 2 ⎡2εΨ()0 VN +RD⎤ ⎡2εΨ()0 VN +RA⎤ x x x = xn = ⎢ ⎥ ons cireptoe acmobilim p n ons iore donbimolim p ⎢ ⎥ qN() N+ N rge)cvha-enegati( ge)char-eitvposi( qN⎣ ADA() N+ ⎦ N ⎣ DDA⎦ W NN⎛ ⎞ V e r e hR is •w applied reverse bias ⎜ AD⎟ is the permittivity of Si Ψ0 V =T ln 2 1 ε ⎜ n ⎟ 2 ε = 1.04x10-12 F/cm ⎝ i ⎠ ⎡2εΨ()0 V +R NNDA+ ⎤ ε = K ε , where ε = 8.85x10-14 F/cm W = ⎢ ⎥ S 0 0 and K = 11.8 is the relative permittivity of silicon ⎣ q NNDA ⎦ S • ne-sided Step JunctionO 1 ⎡ ⎤ 2 N f –i>>N (p+n diode) 2εΨ()0 V +R A D W≅n x =⎢ ⎥ • most of junction on n-side ⎣ qN D ⎦ 1 2 N f –iD>>NA (n+p diode) ⎡2εΨ()0 V +R ⎤ • most of junction on p-sideW≅p x =⎢ ⎥ ⎣ qN A ⎦ ECE 410, Prof. A. Mason ecLture Notes 6.6 pn Junctions - Depletion Capacitance • Free carriers are separated by the depletion layer • Separation of charge creates junction capacitance –Cj = εA/d ⇒ (d = depletion width, W) 1 q⎡ ε N N ⎤ 2 ⎛ 1 ⎞ ε is the permittivity of Si AD ⎜ ⎟ ε = 11.8⋅ε = 1.04x10-12 F/cm CAj = ⎢ ⎥ 0 2NN+ ⎜ ⎟ V = applied reverse bias ⎣ ()AD ⎦ ⎝ Ψ0 V +R ⎠ R – A is complex to calculate in semiconductor diodes • consists of both bottom of the well and side-wall areas ⎛ ⎞ ⎜ ⎟ – Cj is a strong function of biasing 1 ⎜ C jo ⎟ ⎡qε N N ⎤ 2 C j = ⎜ ⎟ AD CAjo = ⎢ ⎥ • must be re-calculated if ⎜ VR ⎟ Ψ2 NN + ⎜ 1+ ⎟ ⎣ 0 ()AD ⎦ bias conditions change ⎝ Ψ0 ⎠ ⎛ ⎞ – CMOS doping is not linear/constant ⎜ ⎟ ⎜ C jo ⎟ C j = ⎜ ⎟ • graded junction approximation ⎜ VR ⎟ 3 1+ ⎜ Ψ ⎟ • Junction Breakdown ⎝ 0 ⎠ – if reverse bias is too high (typically > 30V) can get strong reverse current flow ECE 410, Prof. A. Mason Lecture Notes 6.7 Diode Biasing and Current Flow I + V - + V - D D D p n V V I I f D D D • Forward Bias; VD > Ψ0 – acts against built-in potential – depletion width reduced – diffusion currents increase with VD • minority carrier diffusion ⎛ 1 1 ⎞ VVDT ⎜ ⎟ I= I e −1 IAS∝⎜ + ⎟ DS( ) NN⎝ DA⎠ • Reverse Bias; VR = -VD > 0 – acts to support built-in potential – depletion width increased – electric field increased – small drift current flows • considered leakage • small until VR is too high and breakdown occurs ECE 410, Prof. A. Mason Lecture Notes 6.8 MOSFET Capacitor • MOSFETs move charge from drain to source underneath the gate, if a conductive channel exists under the gate • Understanding how and why the conductive channel is produced is important • MOSFET capacitor models the gate/oxide/substrate region G – source and drain are ignored S D gate G – substrate changes with applied gate voltage gate oxide •Consider an nMOS device channel = – Accumulation, VG < 0, (-)ve charge on gate Si substrate = bulk B • induces (+)ve charge in substrate B • (+)ve charge accumulate from substrate holes (h+) – Depletion, V > 0 but small V < 0 V > 0 V >> 0 G G G G • creates depletion region in substrate + + + + + + + + + + + - - - - - - - + + + + + + + + + + + + + + + + + • (-)ve charge but no free carriers + + + + + + + - - - - - - - - - - - - depletion- - -layer - - - - depletion- - - layer - - – Inversion, VG > 0 but larger • further depletion requires high energy p-type Si substrate p-type Si substrate p-type Si substrate BB B • (-)ve charge pulled from Ground Accumulation Depletion Inversion • electron (e-) free carriers in channel ECE 410, Prof. A. Mason Lecture Notes 6.9 Capacitance in MOSFET Capacitor • In Accumulation – Gate capacitance = Oxide capacitance 2 – Cox = εox/tox [F/cm ] • In Depletion – Gate capacitance has 2 components – 1) oxide capacitance Cox – 2) depletion capacitance of the substrate depletion region Cdep •Cdep= εsi/xd, xd = depth of depletion region into substrate – Cgate = Cox (in series with) Cdep = Cox Cdep / (Cox+Cdep) < Cox • C’s in series add like R’s in parallel Cgate • In Inversion Cox – free carries at the surface – Cgate = Cox V accumulation inversion G depletion ECE 410, Prof. A. Mason Lecture Notes 6.10 Inversion Operation • MOSFET “off” unless in inversion – look more deeply at inversion operation • Define some stuff – Qs = total charge in substrate –VG = applied gate voltage – Vox = voltage drop across oxide – φs = potential at silicon/oxide interface (relative to substrate-ground) –Qs = -Cox VG –VG = Vox + φs • During Inversion (for nMOS) –VG > 0 applied to gate – Vox drops across oxide (assume linear) – φs drops across the silicon substrate, most near the surface ECE 410, Prof. A. Mason Lecture Notes 6.11 Surface Charge •QB = bulk charge, ion charge in depletion region under the gate 1 ⎡2εφ ⎤ 2 –Q= - q N x , x = depletion depth s B A d d xd = ⎢ ⎥ 1/2 ⎣ qN A ⎦ –QB = - (2q εSi NA φs) = f(VG) – charge per unit area • Qe = charge due to free electrons at substrate surface •Qs = QB + Qe < 0 (negative charge for nMOS) depletion electron region QB, bulk layer, Qe charge ECE 410, Prof.