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Lecture 06 – Capacitors (8/18/14) Page 06-1 Lecture 06 – Capacitors (8/18/14) Page 06-1 LECTURE 06 - CAPACITORS LECTURE ORGANIZATION Outline • Introduction • pn junction capacitors • MOSFET gate capacitors • Conductor-insulator-conductor capacitors • Deviation from ideal behavior in capacitors • Summary CMOS Analog Circuit Design, 3rd Edition Reference Pages 46-52 and 654-657 CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-2 INTRODUCTION Types of Capacitors for CMOS Technology 1.) PN junction (depletion) d xd - + capacitors - + - + - + - + - + W 1 W2 060204-01 v + D - G D,S,B 2.) MOSFET gate capacitors Cox n+ n+ p+ Cjunction p-well 060207-01 3.) Conductor-insulator-conductor Top Conductor Bottom capacitors Dielectric Conductor Insulating layer 060206-02 CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-3 Characterization of Capacitors What characterizes a capacitor? 1.) Losses in a capacitor characterized by the quality factor of a capacitor is a measure of the imaginary to real part of the impedance or admittance 1 Q = = CRp CRs where Rp is the equivalent resistance in parallel with the capacitor, C, and Rs is the electrical series resistance (ESR) of the capacitor, C. 2.) Parasitic capacitors to ground from each node of the capacitor. 3.) The density of the capacitor in Farads/area. 4.) The absolute and relative accuracies of the capacitor. 5.) The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when the capacitor is used as a variable capacitor (varactor). 6.) The variation of a variable capacitance with the control voltage. 7.) Linearity, q = Cv. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-4 PN JUNCTION CAPACITORS PN Junction Capacitors in a Well Generally made by diffusion into the well. Anode Cathode Substrate rD C Cj Cj Cw VA VB + + + + Anode n p n p Rwj Cathode Rwj Rwj Rw Rs Depletion n-well Region p- substrate Fig. 2.5-011 Layout: n+ diffusion Minimize the distance between the p+ and n+ diffusions. Two different versions have been tested. p+ dif- 1.) Large islands – 9µm on a side fusion n-well 2.) Small islands – 1.2µm on a side Fig. 2.5-1A CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-5 PN-Junction Capacitors – Continued The anode should be the floating node and the cathode must be connected to ac ground. Experimental data (Q at 2GHz, 0.5µm CMOS)†: Cmax Cmin Qmin Qmax 4 120 3.5 100 ) Small Islands F 3 C p Anode Cathode ( Large Islands 80 e 2.5 e d d R-X Cathode o Small Islands o n 2 n 60 Bridge Voltage A A C C 1.5 Anode Cathode Q 40 Large Islands 1 R-X Cathode Bridge Voltage 0.5 20 0 0 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 Cathode Voltage (V) Cathode Voltage (V) 060206-03 Terminal Small Islands (598 1.2µm x1.2µm) Large Islands (42 9µm x 9µm) Under Test Cmax/Cmin Qmin Qmax Cmax/Cmin Qmin Qmax Anode 1.23 94.5 109 1.32 19 22.6 Cathode 1.21 8.4 9.2 1.29 8.6 9.5 Electrons as majority carriers lead to higher Q because of their higher mobility. The resistance, Rwj, is reduced in small islands compared with large islands higher Q † E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-6 MOSFET GATE CAPACITORS MOSFET Gate Capacitor Structure The MOSFET gate capacitors have the gate as one terminal of the capacitor and some combination of the source, drain, and bulk as the other terminal. In the model of the MOSFET gate capacitor shown below, the gate capacitance is really two capacitors in series depending on the condition of the channel. 1 C = gate 1 1 + Cox Cj S G D B G Cox Channel Resistance Cox S D n+ n+ p+ Cjunction p-well Cjunction 060207-02 B Bulk Resistance CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-7 MOSFET Gate Capacitor as a function of VGS with D=S=B G D,S,B Capacitance Cox Cox Cox Weak n+ n+ p+ Accumulation Inv. Strong C Inversion junction p-well Depletion Moderate VG-VD,S,B Operation: Inversion 060207-03 In this configuration, the MOSFET gate capacitor has 5 regions of operation as VGS is varied. They are: 1.) Accumulation 2.) Depletion 3.) Weak inversion 4.) Moderate inversion 5.) Strong inversion For the first four regions, the gate capacitance is the series 1 C = combination of Cox and Cj given as, gate 1 1 + Cox Cj CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-8 Use of a 3 Segment Model to Explain the Gate Capacitor Variation Region Channel R Cox and Cj Cgate 3-Segment Model Accumulation Large In series and Cgate ≈ Cox Cj > Cox C ≈ 0.5C Depletion Large In series and gate ox ≈ 0.5C Cj ≈ Cox j Weak Large In series and Cgate ≈ Cj Inversion Cj < Cox Moderate Moderate In series and Cj < Cgate < Inversion Cj < Cox Cox Strong Small In parallel and Cgate ≈ Cox Inversion Cj < Cox CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-9 MOSFET Gate Capacitor as a function of VGS with Bulk Fixed (Inversion Mode) G D,S B Capacitance Cox B=D= S Cox Cox + + n n p+ Inversion VT shift Mode MOS if VBS ≠ 0 Cjunction p-well 0 VG-VD,S 060207-04 Conditions: • D = S, B = VSS • Accumulation region removed by connecting bulk to ground • Nonlinear • Channel resistance: L Ron = 12KP'(VBG-|VT|) • LDD transistors will give lower Q because of the increased series resistance CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-10 Inversion Mode NMOS Capacitor Best results are obtained G D,S Shown in inversion mode when the drain-source are D,S connected to ac ground. Cov C Bulk Rsj Cj Cox ov B p+ n+ n+ C Rd Cd Csi d Rd G - p substrate/bulk Rsi n- LDD Fig. 2.5-2 Experimental Results (Q at 2GHz, 0.5µm CMOS)†: Cmax Cmin Qmax Qmin 4.5 38 RX VG = 2.1V 36 RX 4 Meter VG = 2.1V Meter V G VD,S 34 VG VD,S ) 3.5 F 32 p e ( t VG = 1.8V 3 a e t 30 V = 1.8V G a G G Q 28 C 2.5 VG = 1.5V VG = 1.5V 26 2 24 1.5 22 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 Drain/Source Voltage (V) Drain/Source Voltage (V) 070617-06 VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9) † E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-11 Accumulation Mode NMOS Gate Capacitor G B Capacitance C Cox ox Depletion n+ n+ Inversion Accumulation VG-VD,S,B 060207-05 Conditions: • Build the NMOS in a n-well or the PMOS in a p-well – channel is present with no bias • Implements a variable capacitor with a larger transition region between the maximum and minimum values. • Reasonably linear capacitor for values of VG-VD,S,B > 0 CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-12 Accumulation Mode Capacitor – Continued Best results are Shown in depletion mode. G D,S obtained when the D,S drain-source are on Cov C Cox ov ac ground. Bulk Cw B p+ n+ n+ Rs Rw Rd Rd G Cd Cd n- well n- LDD p- substrate/bulk Fig. 2.5-5 Experimental Results (Q at 2GHz, 0.5µm CMOS)†: Cmax Cmin Qmax Qmin 4 45 RX V = 0.3V RX G Meter Meter V 3.6 VG V G VD,S VG = 0.9V D,S 40 ) e F 3.2 t VG = 0.6V a p ( V = 0.6V G G e 35 t Q V = 0.9V a 2.8 G G C 30 2.4 VG = 0.3V 2 25 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 Drain/Source Voltage (V) Drain/Source Voltage (V) 070617-07 VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6) † E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-13 CONDUCTOR-INSULATOR-CONDUCTOR CAPACITORS Polysilicon-Oxide-Polysilicon (Poly-Poly) Capacitors LOCOS Technology: A very linear capacitor with minimum bottom plate parasitic. DSM Technology: A very linear capacitor with small bottom plate parasitic. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-14 Metal-Insulator-Metal (MiM) Capacitors In some processes, there is a thin dielectric between a metal layer and a special metal layer called “capacitor top metal”.
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