Lecture 06 – Capacitors (8/18/14) Page 06-1

LECTURE 06 - CAPACITORS LECTURE ORGANIZATION Outline • Introduction • pn junction capacitors • MOSFET gate capacitors • Conductor-insulator-conductor capacitors • Deviation from ideal behavior in capacitors • Summary CMOS Analog Circuit Design, 3rd Edition Reference Pages 46-52 and 654-657

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-2

INTRODUCTION Types of Capacitors for CMOS Technology 1.) PN junction (depletion) d xd - + capacitors - + - + - + - + - + W1 W 2 060204-01 + vD - G D,S,B 2.) MOSFET gate capacitors Cox

n+ n+ p+

C junction p-well 060207-01

3.) Conductor-insulator-conductor Top Conductor Bottom capacitors Dielectric Conductor Insulating layer 060206-02

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-3

Characterization of Capacitors What characterizes a capacitor? 1.) Losses in a capacitor characterized by the quality factor of a capacitor is a measure of the imaginary to real part of the impedance or admittance 1 Q = = CRp CRs where Rp is the equivalent resistance in parallel with the capacitor, C, and Rs is the electrical series resistance (ESR) of the capacitor, C. 2.) Parasitic capacitors to ground from each node of the capacitor. 3.) The density of the capacitor in Farads/area. 4.) The absolute and relative accuracies of the capacitor. 5.) The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when the capacitor is used as a variable capacitor (varactor). 6.) The variation of a variable capacitance with the control voltage. 7.) Linearity, q = Cv.

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-4

PN JUNCTION CAPACITORS PN Junction Capacitors in a Well Generally made by diffusion into the well. Anode Cathode Substrate

rD C Cj Cj Cw VA VB + + + + Anode n p n p Rwj Cathode Rwj Rwj Rw Rs Depletion n-well Region p- substrate Fig. 2.5-011 Layout: Minimize the distance between the p+ and n+ diffusions. n+ diffusion Two different versions have been tested. p+ dif- 1.) Large islands – 9µm on a side fusion 2.) Small islands – 1.2µm on a side n-well

Fig. 2.5-1A CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-5

PN-Junction Capacitors – Continued The anode should be the floating node and the cathode must be connected to ac ground. Experimental data (Q at 2GHz, 0.5µm CMOS)†: Cmax Cmin Qmin Qmax 4 120 3.5 100 ) Small Islands F 3 C

p Anode Cathode

( Large Islands

e 2.5

e d

d R-X Cathode

o Small Islands

o n

2 n 60 Bridge Voltage

A A

C C 1.5 Anode Cathode Q 40 Large Islands 1 R-X Cathode Bridge Voltage 0.5 20 0 0 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 Cathode Voltage (V) Cathode Voltage (V) 060206-03 Terminal Small Islands (598 1.2µm x1.2µm) Large Islands (42 9µm x 9µm) Under Test Cmax/Cmin Qmin Qmax Cmax/Cmin Qmin Qmax Anode 1.23 94.5 109 1.32 19 22.6 Cathode 1.21 8.4 9.2 1.29 8.6 9.5 Electrons as majority carriers lead to higher Q because of their higher mobility.

The resistance, Rwj, is reduced in small islands compared with large islands  higher Q

† E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-6

MOSFET GATE CAPACITORS MOSFET Gate Capacitor Structure The MOSFET gate capacitors have the gate as one terminal of the capacitor and some combination of the source, drain, and bulk as the other terminal. In the model of the MOSFET gate capacitor shown below, the gate capacitance is really two capacitors in series depending on the condition of the channel. 1 C = gate 1 1 + Cox Cj S G D B G Cox Channel Resistance

Cox S D

n+ n+ p+

Cjunction p-well Cjunction Bulk Resistance 060207-02 B

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-7

MOSFET Gate Capacitor as a function of VGS with D=S=B G D,S,B Capacitance

Cox Cox Cox Weak n+ n+ p+ Accumulation Inv. Strong Inversion Cjunction p-well Depletion Moderate VG-VD,S,B Operation: Inversion 060207-03 In this configuration, the MOSFET gate capacitor has 5 regions of operation as VGS is varied. They are: 1.) Accumulation 2.) Depletion 3.) Weak inversion 4.) Moderate inversion 5.) Strong inversion For the first four regions, the gate capacitance is the series 1 C = combination of Cox and Cj given as, gate 1 1 + Cox Cj

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-8

Use of a 3 Segment Model to Explain the Gate Capacitor Variation Region Channel R Cox and Cj Cgate 3-Segment Model

Accumulation Large In series and Cgate ≈ Cox Cj > Cox

C ≈ 0.5C Depletion Large In series and gate ox ≈ 0.5C Cj ≈ Cox j

Weak Large In series and Cgate ≈ Cj Inversion Cj < Cox

Moderate Moderate In series and Cj < Cgate < Inversion Cj < Cox Cox

Strong Small In parallel and Cgate ≈ Cox Inversion Cj < Cox

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-9

MOSFET Gate Capacitor as a function of VGS with Bulk Fixed (Inversion Mode) G D,S B Capacitance

Cox B=D= S Cox Cox

+ + n n p+ Inversion VT shift Mode MOS if VBS ≠ 0 Cjunction p-well 0 VG-VD,S 060207-04 Conditions: • D = S, B = VSS • Accumulation region removed by connecting bulk to ground • Nonlinear • Channel resistance: L Ron = 12KP'(VBG-|VT|) • LDD transistors will give lower Q because of the increased series resistance

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-10

Inversion Mode NMOS Capacitor Best results are obtained G D,S Shown in inversion mode when the drain-source are D,S connected to ac ground. Cov C Bulk Rsj Cj Cox ov B p+ n+ n+ C Rd Cd Csi d Rd G - p substrate/bulk Rsi n- LDD Fig. 2.5-2 Experimental Results (Q at 2GHz, 0.5µm CMOS)†: Cmax Cmin Qmax Qmin 4.5 38 RX VG = 2.1V 36 RX 4 Meter VG = 2.1V Meter V G VD,S 34 VG VD,S

) 3.5

F 32

( t VG = 1.8V

3 a e

t 30

V = 1.8V G

a G G Q 28 C 2.5 VG = 1.5V VG = 1.5V 26 2 24 1.5 22 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 Drain/Source Voltage (V) Drain/Source Voltage (V) 070617-06 VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)

Accumulation Mode NMOS Gate Capacitor G B Capacitance

C Cox ox Depletion n+ n+ Inversion Accumulation

VG-VD,S,B 060207-05 Conditions: • Build the NMOS in a n-well or the PMOS in a p-well – channel is present with no bias • Implements a variable capacitor with a larger transition region between the maximum and minimum values. • Reasonably linear capacitor for values of VG-VD,S,B > 0

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-12

Accumulation Mode Capacitor – Continued Best results are Shown in depletion mode. G D,S obtained when the D,S drain-source are on Cov C Cox ov ac ground. Bulk Cw B p+ n+ n+ Rs Rw Rd Rd G Cd Cd n- well n- LDD p- substrate/bulk Fig. 2.5-5 Experimental Results (Q at 2GHz, 0.5µm CMOS)†: Cmax Cmin Qmax Qmin 4 45 RX V = 0.3V RX G Meter Meter V 3.6 VG V G VD,S

VG = 0.9V D,S 40

)

e F

3.2 t VG = 0.6V

a p

( V = 0.6V G G

e 35 t Q V = 0.9V

a 2.8 G

G C 30 2.4 VG = 0.3V

2 25 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 Drain/Source Voltage (V) Drain/Source Voltage (V) 070617-07 VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)

CONDUCTOR-INSULATOR-CONDUCTOR CAPACITORS Polysilicon-Oxide-Polysilicon (Poly-Poly) Capacitors LOCOS Technology: A very linear capacitor with minimum bottom plate parasitic.

DSM Technology: A very linear capacitor with small bottom plate parasitic.

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-14

Metal-Insulator-Metal (MiM) Capacitors In some processes, there is a thin dielectric between a metal layer and a special metal layer called “capacitor top metal”. Typically the capacitance is around 1fF/µm2 and is at the level below top metal.

Protective Insulator Layer

Metal Via Top Vias connecting top Metal Capacitor plate to top metal dielectric Capacitor Top Metal Second level Inter- from top metal mediate Vias connecting bottom Capacitor bottom plate Oxide plate to lower metal Third level Layers Vias connecting bottom from top metal plate to lower metal Fourth level from top metal

060530-01

Good matching is possible with low parasitics.

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-15

Metal-Insulator-Metal Capacitors – Lateral and Vertical Flux Capacitance between conductors on the same level and use lateral flux. Fringing field Top view:

Metal Metal

Metal 3 + - + - Side view:

Metal 2 - + - +

Metal 1 + - + - Fig2.5-9 These capacitors are sometimes called fractal capacitors because the fractal patterns are structures that enclose a finite area with a near-infinite perimeter. The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-16

More Detail on Horizontal Metal Capacitors† Some of the possible metal capacitor structures include: 1.) Horizontal parallel plate (HPP).

030909-01 2.) Parallel wires (PW):

Lateral View 030909-02 Top View

† R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3, March 2002, pp. 384-393. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-17

Horizontal Metal Capacitors - Continued 3.) Vertical parallel plates (VPP):

Vias

030909-03 4.) Vertical bars (VB):

Vias

030909-04 Lateral View Top View

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-18

Horizontal Metal Capacitors - Continued

Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24µm, tox = 0.7µm and tmetal = 0.53µm for the bottom 5 layers of metal. All capacitors = 1pF.

Structure Cap. Caver. Area Cap. Std.  fres. Q @ Break- 2 (1 pF) Density (pF) (µm ) Enhanc Dev. Caver. (GHz) 1 GHz down (aF/µm2) ement (fF) (V) VPP 1512.2 1.01 670 7.4 5.06 0.0050 > 40 83.2 128 VB 1281.3 1.07 839.7 6.3 14.19 0.0132 37.1 48.7 124 HPP 203.6 1.09 5378 1.0 26.11 0.0239 21 63.8 500 MIM 1100 1.05 960.9 5.4 - - 11 95 - Histogram of the capacitance distribution:

Result: The horizontal metal capacitors have a matching accuracy that is equivalent of the better capacitors – poly- poly and MIM.

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-19

DEVIATION FROM IDEAL BEHAVIOR IN CAPACITORS Capacitor Errors 1.) Dielectric gradients 2.) Edge effects 3.) Process biases 4.) Parasitics 5.) Voltage dependence 6.) Temperature dependence

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-20

Capacitor Errors - Oxide Gradients Error due to a variation in dielectric thickness across the wafer. Common centroid layout - only good for one-dimensional errors: No common centroid layout Common centroid layout 2C C 2C C

060207-07

An alternate approach is to layout numerous repetitions and connect them randomly to achieve a statistical error balanced over the entire area of interest. Improved matching of three components, A, B, and C:

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-21

Capacitor Errors - Edge Effects There will always be a randomness on the definition of the edge. However, etching can be influenced by the presence of adjacent structures. For example, Matching of A and B are disturbed by the presence of C.

C A B

Improved matching achieve by matching the surroundings of A and B.

C A B

CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-22

Process Bias on Capacitors Consider the following two capacitors:

If L1 = L2 = 2µm, W2 = 2W1 = 4µm and x = 0.1µm, the ratio of C to C can 2 1 be written as, C2 (2-.2)(4-.2) 3.8 = = = 2.11 → 5.6% error in matching C1 (2-.2)(2-.2) 1.8 How can this matching error be reduced? The capacitor ratios in general can be expressed as, 2x 1 -  C2 (L2-2x)(W2-2x) W2 W2  W2 2x 2x W2 2x 2x = =  1 - 1 +   1 - +  C (L -2x)(W -2x) W  2x W W W W W W 1 1 1 11 -  1 2  1  1 2 1   W1  Therefore, if W2 = W1, the matching error should be minimized. The best matching results between two components are achieved when their geometries are identical.

Replication Principle Based on the previous result, a way to minimize the matching error between two or more geometries is to insure that the matched components have the same area to periphery ratio. Therefore, the replication principle requires that all geometries have the same area-periphery ratio. Correct way to match the previous capacitors (the two C2 capacitors are connected together):

If L1 = L2 = 2µm, W2 = 2W1 = 2µm and x = 0.1µm, the ratio of C2 to C1 can be written as,

C2 2(2-.2)(2-.2) 2·1.8 = = = 2 → 0% error in matching C1 (2-.2)(2-.2) 1.8 The replication principle works for any geometry and includes transistors, resistors as well as capacitors.

Capacitor Errors - Relative Accuracy Capacitor relative accuracy is proportional to the area of the capacitors and inversely proportional to the difference in values between the two capacitors. For example, 0.04

Unit Capacitance = 0.5pF

0.03

c a

r Unit Capacitance = 1pF

c c

A 0.02

a l

e 0.01 R Unit Capacitance = 4pF 0.00 1 2 4 8 16 32 64 Ratio of Capacitors

How to Keep the Relative Accuracy Constant as Ratio Increases The following scheme will tend to keep the relative accuracy constant as a function of the ratio of capacitors. Of course the tradeoff for this accuracy is area.

1:2 2 2 1 1 2 2

4 4 4 4 1 1 4 4 4 4 1:4 4 4 4 4 1 1 4 4 4 4

4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4

4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4 1:8 4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4

4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4

120625-01

Capacitor Errors - Parasitics Parasitics are normally from the top and bottom plate to ac ground which is typically the substrate. Top Plate

Top plate Desired parasitic Capacitor Bottom Bottom Plate plate parasitic 060702-08

Top plate parasitic is 0.01 to 0.001 of Cdesired

Bottom plate parasitic is 0.05 to 0.2 Cdesired

Layout Considerations on Capacitor Accuracy Decreasing Sensitivity to Edge Variation: Fringing Fringing Field Field ? ? Sensitive to alignment errors in the Insensitive to alignment errors and the upper and lower plates and loss of flux reaching the bottom plate is larger capacitance flux (smaller capacitance). resulting in large capacitance. 060207-09 A structure that minimizes the ratio of perimeter to area (circle is best). Bottom Plate

Top Plate

060207-10 Reduced bottom plate parasitic.

Accurate Matching of Capacitors† Accurate matching of capacitors depends on the following influence: 1.) Mismatched perimeter ratios 2.) Proximity effects in unit capacitor photolithography 3.) Mismatched long-range fringe capacitance 4.) Mismatched interconnect capacitance 5.) Parasitic interconnect capacitance Long-range fringe capacitance:

Obviously there will be a tradeoff between matching and speed.

† M.J. McNutt, S. LeMarquis and J.L.Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. of Solid-State Circuit, vo. 29, No. 5, May 1994, pp. 611-616. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 06 – Capacitors (8/18/14) Page 06-29

Shielding The key to shielding is to determine and control the electric fields. Consider the following noisy conductor and its influence on the substrate: Increased Parasitic Capacitance Noisy Conductor Noisy Conductor Separate Ground

Shield Substrate Substrate 060118-10 Use of bootstrapping to reduce capacitor bottom plate parasitic: Top Plate

+1 Bottom Plate 2Cpar Cpar 2Cpar Shield Substrate Substrate 060316-02

Definition of Temperature and Voltage Coefficients In general a variable y which is a function of x, y = f(x), can be expressed as a Taylor series, 2 3 y(x)  y(x0) + a1(x- x0) + a2(x- x0) + a3(x- x0) + ··· where the coefficients, ai, are defined as, df(x) | 1 d2f(x) | a = , a = , …. 1 dx x=x0 2 2 dx2 x=x0

The coefficients, ai, are called the first-order, second-order, …. temperature or voltage coefficients depending on whether x is temperature or voltage. Generally, only the first-order coefficients are of interest. In the characterization of temperature dependence, it is common practice to use a term called fractional temperature coefficient, TCF, which is defined as, 1 df(T) | TCF(T=T0) = parts per million/°C (ppm/°C) f(T=T0) dT T=T0 or more simply, 1 df(T) TCF = f(T) dT parts per million/°C (ppm/°C) A similar definition holds for fractional voltage coefficient.

Capacitor Errors - Temperature and Voltage Dependence MOSFET Gate Capacitors: Absolute accuracy  ±10% Relative accuracy  ±0.2% Temperature coefficient  +25 ppm/C° Voltage coefficient  -50ppm/V Polysilicon-Oxide-Polysilicon Capacitors: Absolute accuracy  ±10% Relative accuracy  ±0.2% B Silicide A Thin depletion regions Temperature coefficient  +25 ppm/C° Silicide Effective dielectric Voltage coefficient  -20ppm/V thickness

Metal-Dielectric-Metal Capacitors: Shallow Trench Isolation 140310-03 Absolute accuracy  ±10% Relative accuracy  ±0.6% Temperature coefficient  +40 ppm/C° Voltage coefficient  -20ppm/V, 5ppm/V2 Accuracies depend upon the size of the capacitors.

SUMMARY • Capacitors are made from: - pn junctions (depletion capacitors) - MOSFET gate capacitors - Conductor-insulator-conductor capacitors • Capacitors are characterized by: - Q, a measure of the loss - Density - Parasitics - Absolute and relative accuracies • Deviations from ideal capacitor behavior include; - Dielectric gradients - Edge effects (etching) - Process biases - Parasitics - Voltage and temperature dependence