Module 3: MOSFET Evolution

• Section 1: Evolution & ITRS

[1]

Module 3: MOSFET Evolution

• Section 2: Multigate Technology & Variability 2017 Update

Intel, 2017, Technology and Manufacturing Day

EE230B – Vivek Subramanian Slide 3-1 [1] R. Chau, et al. Nature Materials, 2007 EE230B – Vivek Subramanian Slide 3-2

Module 3: MOSFET Evolution Module 3: MOSFET Evolution

Section 3: Multigate Transport and Electrostatics • Section 4: Multigate Reliability

290D, 2013 - Lecture 3 [1] K.K. Lin, H. Sheng, Synopsis, Enabling 14nm FinFET Design, 2013

Slide 3-3 EE230B – Vivek Subramanian Slide 3-4

1 History of the ITRS

MOSFET EVOLUTION & THE ITRS

EE231 – Vivek Subramanian Slide 3-5 EE230B – Vivek Subramanian Slide 3-6

Why we need the ITRS – scheduled invention ITRS 2.0 Roadmapping– Post 2013

• ITRS 2.0 connects ‘emerging system product drivers’ to device roadmapping: – Mobile Devices – Datacenters –IoT • Top-down framework defining new requirements for IC’s & manufacturing

EE230B – Vivek Subramanian Slide 3-7 EE230B – Vivek Subramanian Slide 3-7

2 ITRS Technology Node Definitions More Moore Roadmap - 2015

• Individual roadmaps are defined for high- performance, low-power, etc.

EE230B – Vivek Subramanian Slide 3-8 EE230B – Vivek Subramanian Slide 3-10

ITRS - New Device Technologies ITRS Projected Power & Delay Scaling

Progress to 2024 and beyond relies on new device technologies Ion is predicted to saturate and then decrease c. 2023, but with improved low-voltage performance switching energy will continue to scale down

[1] FinFET LGAA VGAA *Replotted from [1]

[1] ITRS 2.0, Executive Report, 2015 EE230B – Vivek Subramanian Slide 3-11 EE230B – Vivek Subramanian Slide 3-12

3 What about Lg? ITRS Projected Gate Length Scaling

• The channel length is typically not the same as the gate length Physical Gate Length Lg is predicted to scale until 2021 Why is 10nm the limit?

Vertical Devices Projected

*Replotted from [1] Why are S/D designed to overlap with gate?

[1] ITRS 2.0, Executive Report, 2015 EE230B – Vivek Subramanian Slide 3-13 EE230B – Vivek Subramanian Slide 3-14

Mobile Driver Trends Datacenter Trends

• Mobile devices will add cores and increase memory bandwidth. • Datacenters will scale up in the next decade, with more cores • Heterogeneous integration will increase # sensors and more memory

EE230B – Vivek Subramanian Slide 3-15 EE230B – Vivek Subramanian Slide 3-16

4 Datacenter Trends IoT Trends

• Energy-efficient devices will use less power per operation, • IoT devices will have more sensors and require more efficient improving the efficiency of computing at data centers wireless communication

EE230B – Vivek Subramanian Slide 3-17 EE230B – Vivek Subramanian Slide 3-18

IoT Device Trends Litho Challenges

• Battery powered devices operate intermittently • EUV will compete with ArF multiple patterning • MOSFET off-state leakage dominates system power • EUV multiple patterning may be required as soon as 2021

EE230B – Vivek Subramanian Slide 3-19 EE230B – Vivek Subramanian Slide 3-20

5 General Industry Trends Low-k Dielectric Scaling

• Heterogeneous integration will extend and • Low-k scaling for interlayer dielectrics has develop new functionalities slowed due to decreased mechanical • 3D-system in package architectures are to reliability and adhesion. become the primary technologies

EE230B – Vivek Subramanian Slide 3-21 [1] ITRS2015_Interconnects EE230B – Vivek Subramanian Slide 3-22

Low-k Dielectric Scaling What problems are we trying to solve? • Leakage • Air gap is the ultimate low-k dielectric – As we scale devices, short channel effects become more important – Degraded S, DIBL, bulk punchthrough • Mobility / On-current – Velocity saturation limits improvement – Low-field mobility is very important for switching, high doping degrades this • Series resistance – Series resistance gets worse as we scale • Variability – Many techniques we use for device engineering increase variability as devices are scaled

[1] ITRS2015_Interconnects EE230B – Vivek Subramanian Slide 3-23 EE230B – Vivek Subramanian Slide 3-24

6 Ioff / Ion Benchmarking

•Ioff / Ion plots compare the performance and variability of different CMOS technologies

• Captures Vt tunability for HP vs LP logic • Displays tradeoff between active and standby power

Intel 22nm Trigate Technology

MOS TECHNOLOGY BENCHMARKING

[1] C. Arthur, VLSI, 2012

EE230B – Vivek Subramanian Slide 3-25 EE230B – Vivek Subramanian Slide 3-26

Ioff / Ion Benchmarking Delay & Power Benchmarking

• Which phenomena explain the low Ioff and • Power and speed matter for efficient high Ioff portions of this plot? computing (e.g. datacenters)

Intrinsic Delay = CV/I Normalized Energy-Delay Product

R. Chau, IEEE Trans. Nano, 2005.

EE230B – Vivek Subramanian Slide 3-27 EE230B – Vivek Subramanian Slide 3-28

7 Benchmarking Device Variability Benchmarking Device Variability

• Pelgrom plot expresses Vt variation vs inverse • Pelgrom plot slope can compare processes area from different nodes or different fabs • Assumes model w/

AVT can be used to compare different MOS technologies

Slope = Avt

[1] O. Weber, IEDM 2008

EE230B – Vivek Subramanian Slide 3-29 EE230B – Vivek Subramanian Slide 3-30

Sources of Variability

VARIABILITY

EE230B – Vivek Subramanian Slide 3-31 EE230B – Vivek Subramanian Slide 3-32

8 Random Dopant Fluctuation Implications

• Nanoscale devices have higher relative random fluctuations in doping (RDF) • RDF can be correlated to LER

M. Hane, SISPAD, 2003

EE230B – Vivek Subramanian Slide 3-33 EE230B – Vivek Subramanian Slide 3-34

Solutions to RDF Line Edge Roughness

EE230B – Vivek Subramanian Slide 3-35 EE230B – Vivek Subramanian Slide 3-36

9 Granularity FinFET Variability

• MGG is an important issue for HKMG devices s s( • FinFET variability depends strongly on (RSD) • Metal gate granularity influences Vt) and causes variations in surface potential •RSD fluctuations can account for > 50% of variability in I at V = V • Grain orientation variability causes nanoscale on gs gmax workfunction variations

TiN

% Contribution to DID / ID

2 fins 20 fins

A.R. Brown, EDL, 2010

EE230B – Vivek Subramanian Slide 3-37 [1] T. Karatsori, IEEE ICMTS, 2017 EE230B – Vivek Subramanian Slide 3-38

MOSFET Variability Corner Analysis Reliability implications on variability

• Performance targets are selected to relax variability requirements • Yield statistics and economics determine tolerable variability and target performance

K. Qian, PhD Thesis, UCB, 2015

EE230B – Vivek Subramanian Slide 3-39 EE230B – Vivek Subramanian Slide 3-40

10 Bond breaking view

INCREASING MOBILITY

EE230B – Vivek Subramanian Slide 3-41 EE230B – Vivek Subramanian Slide 3-42

Why mobility is still important Strained

• Mobility in silicon can be enhanced by straining it. This increases carrier mobility in both and holes, due to changes in the • Source-side injection depends on µs energy structure of the conduction / valence sub-bands

• Electrons: Idsat = qNsvs vs = µsEs vs

• 4 subbands go up in energy, while 2 go down, reducing intervalley scattering and enhancing mobility

EE230B – Vivek Subramanian Slide 3-43 EE230B – Vivek Subramanian Slide 4-44

11 Strained PMOS Stress-Induced Hole Band Splitting

• Holes: • Strain reinforces subband splitting, adding to QM confinement effects discussed in Module 1 • Biaxial strain and confinement oppose each other, reducing effectiveness of biaxial strain

S.E. Thompson, TED, 2004

• Heavy hole subband moves down, and therefore, majority of holes populate light hole subband, increasing mobility

• Solution: Use strain in both NMOS and PMOS to enhance mobility in both devices, increasing circuit speed.

[1] S.E. Thompson, TED, 2006.

EE230B – Vivek Subramanian Slide 3-45 EE230B – Vivek Subramanian Slide 3-46

Methods of achieving strain Original (obsolete in Si) method: Virtual Substrate

• Uniaxial strain is more effective and simpler to implement • Strain is usually achieved by growing a thin silicon layer over a relaxed SiGe layer (which has a larger lattice constant) • % strain is determined by %SiGe in the “virtual substrate”

S.E. Thompson, TED, 2004

T. Ghani, IEDM, 2003

S.E. Thompson, TED, 2004 EE230B – Vivek Subramanian Slide 3-47 EE230B – Vivek Subramanian Slide 3-48

12 Typical Structure of Strained Si Defect issues in virtual substrates

EE230B – Vivek Subramanian Slide 3-49 EE230B – Vivek Subramanian Slide 3-50

Process Integration Issues FinFET Strain Integration

• Thermal budget • Strain transfer to is less effective and more – Too much Dt and strain will relax non-uniform due to 3D fin geometry –Isolation • Strain imposed by wrap around metal gate adds to – Dopant Activation contribution from SiGe eS/D – Gate Oxidation

• Ge diffusion causes high Nit

• Salicide – Many germanides have high resistance – Ge segregation

• Junction formation – Enhanced leakage due to relaxion-induced defects – Dopant segregation issues [1] S. Majumdar, IEEE TED, 2012. EE230B – Vivek Subramanian Slide 3-51 EE230B – Vivek Subramanian Slide 3-52

13 FinFET Strain Integration Strain relaxation: Critical Thickness

• Strain transfer to FinFETs is less effective and more Critical thickness non-uniform due to 3D fin geometry J. Welser [9] for strain relaxation • Strain imposed by wrap around metal gate adds to  decreases with contribution from SiGe eS/D increases in Ge content and temperature  provides upper limit of strain-Si thickness ex. Ge30% g 9 - 40 nm

[1] S. Majumdar, IEEE TED, 2012. EE230B – Vivek Subramanian Slide 3-53 EE230B – Vivek Subramanian Slide 3-54

Mobility Enhancement Band structure

Increases due to continued depopulation of heavy Flattens due to hole subband complete suppression of intervalley scattering

EE230B – Vivek Subramanian Slide 3-55 EE230B – Vivek Subramanian Slide 3-56

14 Band structure in inversion Other Methods

STI induces compressive strain STI STI

Local strain Strain from from STI and Strain from capping poly-Si gate, layers, including S/D regions stress memorization

EE230B – Vivek Subramanian Slide 3-57 EE230B – Vivek Subramanian Slide 3-58

Other benefits of strain: Overshoot Intel 50nm Strained-Si Channel FET

• Drive current enhancement • NMOS 10~20% • PMOS >50% • Used epitaxial SiGe in S/D to compressively strain channel

EE230B – Vivek Subramanian Slide 3-59 EE230B – Vivek Subramanian Slide 3-60

15 PMOS Strain Enhancement PMOS Process Flow

EE230B – Vivek Subramanian Slide 3-61 EE230B – Vivek Subramanian Slide 3-62

NMOS Strain Enhancement The next channel material?

EE230B – Vivek Subramanian Slide 3-63 EE230B – Vivek Subramanian Slide 3-64

16 RF Device Scaling Ge as a channel material

• III-V devices afford higher, mm-wave ft and fmax • GaAs dominates power for cellular comm.

EE230B – Vivek Subramanian Slide 3-65 EE230B – Vivek Subramanian Slide 3-66

Ge issues Gate dielectrics for Ge MOSFETs

EE230B – Vivek Subramanian Slide 3-67 EE230B – Vivek Subramanian Slide 3-68

17 Ge MOSFET + high-K/metal gate Compound on Si

EE230B – Vivek Subramanian Slide 3-69 EE230B – Vivek Subramanian Slide 3-70

Integration using mismatch management NMOS Implementation

EE230B – Vivek Subramanian Slide 3-71 EE230B – Vivek Subramanian Slide 3-72

18 III-V MOSFET Scaling PMOS Performance Enhancement III-V Material Design Tradeoffs

e • Lower bandgap, higher r , lower m*  high mobility • Why are SCE worse for III-V? • III-V materials have fewer available subbands to allow /phonon scattering  can operate closer to ballistic limit

EE230B – Vivek Subramanian Slide 3-73 SH Park, et al., IEDM, 2012 EE230B – Vivek Subramanian Slide 3-61

Logic Device Taxonomy Logic Device Taxonomy

State Var.

Spin Wave Spin Logit Logic Nanomagnetic Logic STMG Non-Charge

Si FET TFET SpinFET Piezo

NW FET III-V Neg-Cg FET Structure / CNT FET Ge NEMS Mott FET Charge Materials Conventional Novel

EE230B – Vivek Subramanian Slide 3-75 EE230B – Vivek Subramanian Slide 3-76

19 Logic Device Taxonomy

Carbon Nanomaterials TFET NW FET NEMS Spin-Torque Logic SOI Lateral Bipolar Piezotronic spinFET 2D Channel FET BisFET Collective-spin Devices Neg-Capacitance FET SOI AND ULTRA-THIN BODY Mott FET Atomic

[1] 2014 ERD Emerging Logic Devices Workshop

EE230B – Vivek Subramanian Slide 3-77 EE230B – Vivek Subramanian Slide 3-78

SOI: Elimination of the leakage path SOI – formation

Single-crystal Si ~0.1 µm SiO2 ~ 0.4 µm Si ~ 500 µm

SIMOX (separation by implantation of oxygen)

150 keV, 1018 cm-2 @600°C oxygen annealed at >1300°C G S D

n+ pSiOn+ 2

SiO2 Si

EE230B – Vivek Subramanian Slide 3-79 EE230B – Vivek Subramanian Slide 3-80

20 Wafer Bonding and Etch Back Capacitance Reduction using SOI

Si SiO2 SiO2 n+ Si n+ p+ Si p+ SiO SiO 2 Si 2 Smart Cut (SOITECH), Unibond H2 Higher performance • reduction of capacitance

H2 2nd wafer P bulk SiO2 SOI

1st wafer Vdd2

SiO2 Si

EE230B – Vivek Subramanian Slide 3-81 EE230B – Vivek Subramanian Slide 3-82

Types of SOI Floating-Body Effect in Partially Depleted SOI

•SOI MOSFET does not have “body bias effect” • Impact ionization generates holes. Since there is no •Idsat may be raised by “floating body effect” •Subthreshold swing can be better body contact, these accumulate in the body, raising Two types of SOI technology - Partial and full Depletion the body potential

+ p + T >X n + n si dmax Si h

dep drain-body leakage n+ n+ • Consequences I partially depleted SOI SiO2 d Neutual Si – Kink in DC IV, bad for analog – May provide large Id – History-dependent Vt complicates Tsi

21 FBE and history dependent switching Fully-depleted SOI Issues: SCE and Self-heating

• Since FD SOI has no depletion region, the drain can couple to the • Charge buildup is slow, therefore VT changes depending on duration of time device undergoes impact ionization channel via the BOX (Buried oxide), degrading SCE PD & bulk VT

n+ n+

FD SiO2 L Worse SCE

• Additionally, due to the complete encapsulation by SiO2, which is thermally insulating, the device can heat up during operation, reducing

mobility and IDsat (called Self-Heating). This is more severe in FD-SOI.

Id

Vd

EE230B – Vivek Subramanian Slide 3-85 EE230B – Vivek Subramanian Slide 3-86

Choice of SOI Film Thickness SOI Electrostatics

•Partially Depleted Device Technology compatibility with bulk technology FBE is severe. •Fully Depleted Device Good subthreshold swing for long L; but poor short channel effect due to loss of ground plane (back gate). Series resistance

hurts Idsat. Floating body effect is less severe; this makes circuit design easier. •Thin Body Device Even thinner SOI film than FD. Thick(raised) S/D. Attractive for L<50nm.

EE230B – Vivek Subramanian Slide 3-87 EE230B – Vivek Subramanian Slide 3-88

22 Partially depleted SOI Fully depleted SOI

EE230B – Vivek Subramanian Slide 3-89 EE230B – Vivek Subramanian Slide 3-90

FD-SOI Electrostatics FD-SOI Electrostatics

EE230B – Vivek Subramanian Slide 3-91 EE230B – Vivek Subramanian Slide 3-92

23 FD-SOI Electrostatics FD-SOI Electrostatics

EE230B – Vivek Subramanian Slide 3-93 EE230B – Vivek Subramanian Slide 3-94

FD-SOI Electrostatics FD-SOI Electrostatics

EE230B – Vivek Subramanian Slide 3-95 EE230B – Vivek Subramanian Slide 3-96

24 FD-SOI Electrostatics Variation of channel potentials using VBG

EE230B – Vivek Subramanian Slide 3-97 EE230B – Vivek Subramanian Slide 3-98

Effect of back-gate on VT Region-specific operation

EE230B – Vivek Subramanian Slide 3-99 EE230B – Vivek Subramanian Slide 3-100

25 Region 1: Back inverted Region 3: Back accumulated

• Not useful, since channel is shorted through back-channel

EE230B – Vivek Subramanian Slide 3-101 EE230B – Vivek Subramanian Slide 3-102

Region 2: Back depleted Region 2: Back depleted

• At the front side, since we are determining VT:

• Further, at the back side:

EE230B – Vivek Subramanian Slide 3-103 EE230B – Vivek Subramanian Slide 3-104

26 Region 2: Back depleted Overall picture

EE230B – Vivek Subramanian Slide 3-105 EE230B – Vivek Subramanian Slide 3-106

Subthreshold swing in FD-SOI Subthreshold swing in FD-SOI

• Defining swing as previously done for bulk, we have: • We have: Need to find • Further, for the back-gate, we have:

• We know: • If we assume VGB is fixed, this gives us:

• Which gives:

EE230B – Vivek Subramanian Slide 3-107 EE230B – Vivek Subramanian Slide 3-108

27 Subthreshold swing in FD-SOI The ultra-thin body MOSFET

• Putting these together, we have: • Advantages – Ultrathin body greatly suppressed leakage – Can used undoped channel (no dopant-induced VT fluctuation) and use gate-workfunction to control VT • Disadvantages – Need very thin-body (typically

EE230B – Vivek Subramanian Slide 3-109 EE230B – Vivek Subramanian Slide 3-110

Process Flow Threshold voltage effects

Issues: • We can control VT by doping, but this makes us susceptible to dopant • Need very thin SOI – problematic fluctuation effects. • Series resistance is problem, so need raised S/D • The only option is to use gate workfunction for control Problem: • No easy way to control VT if using undoped channel UTB • The VT and SCE effects depend greatly on body thickness, which limits manufacturability

BOX

BOX Vt [V] Nsub=1x1016 cm-3

S D G BOX EE230B – Vivek Subramanian Slide 3-111 EE230B – Vivek Subramanian Slide 3-112

28 Another series resistance solution Multi-gate MOSFETs

• We can use a schottky S/D. These are not favored in bulk devices due to the increased junction leakage, but make more sense for SOI since • Concept: there is a very small junction area – Use gates on opposite sides of the channel to suppress SCE • Needs: in thicker films – Low barrier electrodes for both N and P devices to minimize contact • Advantages resistance – More scalable than UTB devices – Twice the on-current • Disadvantages – Process complexity Gate Gate Source Drain Source Drain Oxide Gate

EE230B – Vivek Subramanian Slide 3-113 EE230B – Vivek Subramanian Slide 3-114

Symmetric Double Gate MOSFET Double gate MOSFET Electrostatics

EE230B – Vivek Subramanian Slide 3-115 EE230B – Vivek Subramanian Slide 3-116

29 Swing benefits of DG-MOSFET Scaling of tSOI • Thicker SOI • Thinner SOI

EE230B – Vivek Subramanian Slide 3-117 EE230B – Vivek Subramanian Slide 3-118

Reduced band bending in thin body DG-FET How to define VT in an undoped body

EE230B – Vivek Subramanian Slide 3-119 EE230B – Vivek Subramanian Slide 3-120

30 Definition of body potential Regions of operation

EE230B – Vivek Subramanian Slide 3-121 EE230B – Vivek Subramanian Slide 3-122

DIBL benefits Swing Benefits

Bulk MOSFET Double-gate MOSFET MOSFET gate gate1 Vg 150 Source Drain Source Drain C C Vch GC G1C 125

C C C DC G2C DC SOI 100 Vg Vch Substrate gate2 75 Substrate Lg=50 nm leakage path leakage path N =1016 cm-3 50 B Double-gate Vds=1.0 V 25 Vch Subthreshold swing (mV/dec.) Vg 020406080 SOI thickness (nm)

EE230B – Vivek Subramanian Slide 3-123 EE230B – Vivek Subramanian Slide 3-124

31 Effect of body thickness on inversion Potential profiles and carrier distribution

B. Majkusiak et al., T-ED 45, p.1127, 1998

EE230B – Vivek Subramanian Slide 3-125 EE230B – Vivek Subramanian Slide 3-126

Quantum Confinement Quantum Confinement: Effect on VT

h2 n 2 En-1= 2m* tSOI H. Majima et al., iedm’99

EE230B – Vivek Subramanian Slide 3-127 EE230B – Vivek Subramanian Slide 3-128

32 Quantum Confinement: Effect on C

FINFET & GAA FET

EE230B – Vivek Subramanian Slide 3-129 EE230B – Vivek Subramanian Slide 3-130

Geometric Considerations Quick History: Planar Channel DG-FET

virtual real self-aligned double-gate double-gate double-gate

Planar-channel

T. Tanaka et al., iedm’91 F. Balestra et al., K. W. Guarini et al., EDL 8, p. 410, 1987 Iedm’01

Vertical-channel Fin-channel M. Jurczak et al., T-ED 47, p.2179, 2000 L. Geppert., IEEE SPECTRUM Oct., 2002 EE230B – Vivek Subramanian Slide 3-131 EE230B – Vivek Subramanian Slide 3-132

33 Vertical Channel DG-FET FinFET family of devices

Vertical Double-gate Thinning Self-aligned

S. Nishimatsu et al., JJAP suppl.16-1, p.179, 19771)

B. Goebel et al., Iedm’0217) Epi-channel

J. M. Hergenrother W. F. Richardson et al., iedm’9919) et al., iedm’8515) H. Takato et al., T-ED 38, p.573, 199116) H. Gossner et al., Electronics Lett., vol.31, p.1394, 199518) EE230B – Vivek Subramanian Slide 3-133 EE230B – Vivek Subramanian Slide 3-134

FinFET: a quasi-planar DG-FET Critical performance issues for DG-FETs Crucial problem: gate-gate alignment S/D-gate alignment overlap capacitance Thin-film resistance

offset resistance

Disadvantage parasitic capacitance parasitic resistance Advantages performance improvement layout free EE230B – Vivek Subramanian Slide 3-135 EE230B – Vivek Subramanian Slide 3-136

34 The need for self-alignment Density vs. planarity/granularity trade-offs Allowable alignment tolerance consideration ITRS parasitic capacitance Layout density of Fin channels 2.4x10-16 F/m 2.0

C +C 1.8 GS GD

1.6 CGD 16 stages 16

1.4 Overlap length

CGS 5 nm@EOT=1.5 nm 1.2 7 nm@EOT=2.0 nm .

Simulated relative gate delay gate relative Simulated 1.0 . 10-16 10-15 35 nm@EOT=10 nm G-S/D Capacitance (F/m) S. Tang, et al., ISSCC’0131)

EE230B – Vivek Subramanian Slide 3-137 EE230B – Vivek Subramanian Slide 3-138

Access Resistance of FinFETs GAA MOSFETs

• Access resistance degrades FinFETs & GAA FETs • Gate-all-around designs have optimal electrostatics, • The abrupt fin-width change at S/D extension reducing DIBL beyond FinFET limits corresponds to a different subband energy e1 , causing scattering • Modified S/D extension shape can help

Topdown View P. Zheng, UC Berkeley PhD Dissertation 2015

V. Moroz, EDTM, 2017 IMEC, VLSI, 2016

EE230B – Vivek Subramanian Slide 3-139 EE230B – Vivek Subramanian Slide 3-140

35 Stacked GAA NW MOSFET Fabrication Density vs. planarity/granularity trade-offs

• Stacked NW GAA FETs are needed to outperform Layout density of Fin channels FinFETs • Si / SiGe alternating epitaxy allows etch selectivity to create NW

S. Tang, et al., ISSCC’0131) P. Zheng, UC Berkeley PhD Dissertation 2015

EE230B – Vivek Subramanian Slide 3-141 EE230B – Vivek Subramanian Slide 3-142

SOI Self-Heating

• Bulk MOSFETs dissipate heat to body • BOX layers thermally insulate channel • Thinner BOX allows greater thermal conductivity • High operating temps can cause reliability problems • Depends on device layout as well

MULTIGATE DEVICE RELIABILITY

J.H. Lee, Springer Nano Devices and Circuit Technologies, 2016 EE230B – Vivek Subramanian Slide 3-143 EE230B – Vivek Subramanian Slide 3-144

36 PBTI vs NBTI Stress in CMOS Circuits

• Positive Bias-Temperature Instability and Negative Bias- • BTI combines with hot carrier effects to influence Temperature Instability are key reliability issue in MOSFETs circuit-level performance • NBTI usually is more detrimental to device performance – attributed to Si / SiO2 interface traps • Which effects dominate when Vin = VDD ? Vin = 0? • Influenced by device architecture factors such as gate/drain overlap area ? Intel FinFET NBTI / PBTI -

? ?

• BTI accelerated testing and modeling enable VLSI applications

[1] M. Wang, EDL, 2013 EE230B – Vivek Subramanian Slide 3-145 EE230B – Vivek Subramanian Slide 3-146

Multigate PBTI / NBTI PBTI / NBTI + LER/RDF

• As discussed before, FinFETs operate at a lower • Reliability and process variability are connected transverse field • NBTI / PBTI can amplify initial statistical variation due • PBTI lifetime greatly enhanced vs bulk devices to processing • LER / RDF influence PBTI / NBTI trapped charge y distribution by causing non-uniformity in S

[1]

[1] M. Wang, EDL, 2013 EE230B – Vivek Subramanian Slide 3-147 [1] B. Cheng, IEEE EDL, 2010 EE230B – Vivek Subramanian Slide 3-148

37 PBTI / NBTI in HKMG Stacks

• HKMG stacks have multiple interfaces for trap generation • NBTI remains problematic due to IL issues

[1] S. Mahapatra, Springer: Advanced Microelectronics, (52) EE230B – Vivek Subramanian Slide 3-149

38