Rochester Institute of Technology RIT Scholar Works Theses 5-2017 Design Strategies for Ultralow Power 10nm FinFETs Abhijeet M. Walke
[email protected] Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Walke, Abhijeet M., "Design Strategies for Ultralow Power 10nm FinFETs" (2017). Thesis. Rochester Institute of Technology. Accessed from This Thesis is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact
[email protected]. Design Strategies for Ultralow Power 10nm FinFETs by ABHIJEET M. WALKE A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science in Electrical Engineering Department of Electrical & Microelectronic Engineering Kate Gleason College of Engineering Rochester Institute of Technology Rochester, NY May 2017 i Design Strategies for Ultralow Power 10nm FinFETs ABHIJEET M. WALKE A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science in Electrical Engineering Approved by: Dr. Santosh Kurinec Date Professor, (Thesis Advisor) Dr. Karl Hirschman Date Professor, (Committee Member) Dr. Robert Pearson Date Professor, (Committee Member) Dr. Garrett Schlenvogt Date Silvaco, Inc, (External Committee Member) Dr. Sohail Dianat Date Professor, (Department Head) Department of Electrical and Microelectronic Engineering Rochester Institute of Technology Rochester, New York May, 2017 ii Acknowledgements Before getting to the core of this master thesis, I would like to take some time to thank all those people who made this project possible. Firstly, I would like to express my sincere gratitude to my advisor Prof.