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Circuit-Level Design Impact on Variability and Soft Errors Robustness

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Circuit-Level Design Impact on Variability and Soft Errors Robustness UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL INSTITUTO DE INFORMÁTICA PROGRAMA DE PÓS-GRADUAÇÃO EM MICROELETRÔNICA LEONARDO HEITICH BRENDLER Circuit-Level Design Impact on Variability and Soft Errors Robustness Thesis presented in partial fulfillment of the requirements for the degree of Master of Microelectronics Advisor: Prof. Dr. Ricardo Augusto da Luz Reis Coadvisor: Prof. Dr. Cristina Meinhardt Porto Alegre July 2020 CIP — CATALOGING-IN-PUBLICATION Brendler, Leonardo Heitich Circuit-Level Design Impact on Variability and Soft Errors Robustness / Leonardo Heitich Brendler. – Porto Alegre: PGMI- CRO da UFRGS, 2020. 137 f.: il. Thesis (Master) – Universidade Federal do Rio Grande do Sul. Programa de Pós-Graduação em Microeletrônica, Porto Alegre, BR–RS, 2020. Advisor: Ricardo Augusto da Luz Reis; Coadvi- sor: Cristina Meinhardt. 1. FinFET technology. 2. Microelectronics. 3. Multi-level de- sign. 4. Radiation effects. 5. Variability. I. Reis, Ricardo Augusto da Luz. II. Meinhardt, Cristina. III. Título. UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL Reitor: Prof. Rui Vicente Oppermann Vice-Reitora: Profa. Jane Fraga Tutikian Pró-Reitor de Pós-Graduação: Prof. Celso Giannetti Loureiro Chaves Diretora do Instituto de Informática: Profa. Carla Maria Dal Sasso Freitas Coordenador do PGMICRO: Prof. Tiago Roberto Balen Bibliotecária-chefe do Instituto de Informática: Beatriz Regina Bastos Haro “Those who fall in love with practice without science are like a sailor who enters a ship without a helm or a compass, and who never can be certain whither he is going.” —LEONARDO DA VINCI ABSTRACT Physical limitations were found in MOSFET devices with the advancement in microelec- tronics. To overcome these limitations, multigate devices, such as the FinFET technology, were introduced, allowing the continuity of the technology scaling below 22nm. The evo- lution in the manufacturing process of integrated circuits has resulted in increasingly smaller devices and made the lithography stage more complicated, which can lead to circuits operating outside their specification ranges. Moreover, integrated circuits are ex- posed to different sources of radiation, considering space or even terrestrial applications. All of these factors impact the reliability of the circuits and may cause a deviation in expected behavior. In that way, the study of new guidelines capable of dealing with the challenges posed by technological development is of utmost importance. Some circuits can be designed using different transistor arrangements. A specific transistor arrange- ment can influence the performance of logic cells; complex logic gates can be used to minimize area, delay and power consumption. However, with the increasing relevance of nanometric challenges, it is also necessary to consider the variability and radiation ef- fects at the logic level design with the adoption of different topologies, as the multi-level logic. This work explores circuit-level techniques to mitigate the radiation and process variability effects at 7nm FinFET technology. The process variability impact, through the work-function fluctuations (WFF), and the Single Event Transient (SET) response under WFF are evaluated using different transistor arrangements for a set of logic functions, versions of C17 benchmark (ISCAS85) and majority voters. Results show the impact of different transistor arrangements in the radiation and process variability robustness. The multi-level logic topology is more robust to the radiation effects than complex topology; the Threshold Linear Energy Transfer (LETth) values are, on average, 55% higher con- sidering or not the process variability impact. The LETth values of the different majority voter circuits can vary by up to 65%. All the analyzed circuits independently of the topol- ogy are more sensitive (LETth values, on average, 20% smaller) to the SETs considering the process variability impact. Keywords: FinFET technology. microelectronics. multi-level design. radiation effects. variability. Impacto do projeto em nível de circuito na robustez à variabilidade e erros leves RESUMO Com o avanço da microeletrônica, limitações físicas foram encontradas em dispositi- vos MOSFET. Para superar essas limitações, foram introduzidos dispositivos multigate, como a tecnologia FinFET, permitindo a continuidade do dimensionamento tecnológico a abaixo de 22 nm. A evolução no processo de fabricação de circuitos integrados re- sultou em dispositivos cada vez menores e tornou a etapa de litografia mais complicada, podendo levar os circuitos a operarem fora de suas faixas de especificação. Ainda, os circuitos integrados são expostos a diferentes fontes de radiação, considerando aplicações espaciais ou mesmo terrestres. Todos esses fatores afetam a confiabilidade dos circui- tos e podem causar um desvio no comportamento esperado. Dessa forma, o estudo de novas diretrizes capazes de lidar com os desafios colocados pelo desenvolvimento tec- nológico é de extrema importância. Alguns circuitos podem ser projetados utilizando diferentes arranjos de transistores. Um arranjo de transistores específico pode influenciar o desempenho de células lógicas; portas lógicas complexas podem ser usadas para mini- mizar a área, o atraso e o consumo de potência. No entanto, com a crescente relevância dos desafios nanométricos, também é necessário considerar os efeitos de radiação e da variabilidade no design de nível lógico com a adoção de diferentes topologias, como a lógica multinível. Este trabalho explora técnicas em nível de circuito para mitigar os efei- tos de radiação e da variabilidade de processo na tecnologia FinFET de 7nm. O impacto da variabilidade do processo, através das flutuações da função de trabalho (WFF), e a resposta de Eventos Únicos Transientes (SET) sob WFF são avaliados usando diferentes arranjos de transistores para um conjunto de funções lógicas, versões do benchmark C17 (ISCAS85) e votadores majoritários. Os resultados mostram o impacto de diferentes ar- ranjos de transistores na robustez à radiação e variabilidade de processo. A topologia de lógica multinível é mais robusta aos efeitos de radiação do que a topologia complexa; os valores da Transferência Linear de Energia Limiar (LETth) são, em média, 55% maiores considerando ou não o impacto da variabilidade de processo. Os valores de LETth dos di- ferentes circuitos de votadores majoritários podem variar em até 65%. Todos os circuitos analisados, independentemente da topologia, são mais sensíveis (valores de LETth, em média, 20% menores) aos SETs, considerando o impacto da variabilidade de processo. Palavras-chave: FinFET, microeletrônica, design multinível, radiação, variabilidade. LIST OF ABBREVIATIONS AND ACRONYMS AOI And-Or-Inverter ARM Advanced RISC Machine ASAP7 7nm Arizona State Predictive Design Kit BEOL Back End Of Line BTI Bias Temperature Instability CMOS Complementary Metal-Oxide-Semiconductor DD Displacement Damage DRC Design Rule Check DRAM Dynamic Random Access Memory EDA Electronic Design Automation EUV Extreme Ultraviolet FD-SOI Fully Depleted Silicon On Insulator FEOL Front End Of Line FET Field Effect Transistor GND Ground HFIN Fin Height IG Independent Gate INV Inverter IRPS International Reliability Physics Symposium L Length LELE Litho-Etch Litho-Etch LET Linear Energy Transfer LFIN Gate Length LVS Layout Versus Schematic MGG Metal Gate Granularity MOL Middle of line MOS Metal Oxide Semiconductor MUX Multiplexer NAND Not AND NFET N-Channel FET NIEL Non-ionizing Energy Loss NMOS N-Channel MOSFET NOR Not OR OAI Or-And-Inverter OPC Optical Proximity Correction PDK Process Design Kit PDP Power-Delay-Product PFET P-Channel FET PMOS P-Channel MOSFET RET Resolution Enhancement Techniques SAA South Atlantic Anomaly SADP Self-Aligned Double Patterning SAQP Self-Aligned Quadruple Patterning SCE Short Channel Effects SE Soft Error SEB Single Event Burnout SEE Single Event Effects SEGR Single Event Gate Rupture SEL Single Event Latch-up SET Single Event Transient SEU Single Event Upset SG Shorted Gate SHE Single Hard Error SOI Silicon on Insulator SPICE Simulation Program with Integrated Circuit Emphasis SRAM Static Random Access Memory TCAD Technology Computer-Aided Design TID Total Ionizing Dose TMR Triple Modular Redundancy TSI Fin Width UV Ultraviolet Rays VDD Supply Voltage VLSI Very large-system Integration W Width WFF Work-Function Fluctuation XOR Exclusive OR LIST OF FIGURES Figure 2.1 Structure and geometric parameters of a FinFET device. .............................20 Figure 2.2 Two configurations of FinFET devices: (a) SG - FinFET; (b) IG - FinFET..21 Figure 2.3 Structure of a FinFET device with one fin and multi-fin...............................22 Figure 2.4 Three-Universe model proposed by Pradhan et al.(1996). ...........................23 Figure 2.5 Degradation of a pulse by electric masking. Depending on the width of the generated pulse (a) this, when propagating through the circuit, can be attenuated (b) or filtered (c), characterizing the electric masking. .........................23 Figure 2.6 Logical masking example in combinational circuit.......................................24 Figure 2.7 Latching Window masking............................................................................24 Figure 3.1 Classification of variations observed at different phases of the manufac- turing process..........................................................................................................25 Figure 3.2 Evolution of lithographic wavelength and technology nodes........................27 Figure 3.3
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