[VOLUME 6 I ISSUE 2 I APRIL – JUNE 2019] e ISSN 2348 –1269, Print ISSN 2349-5138 http://ijrar.com/ Cosmos Impact Factor 4.236 PERFORMANCE ENHANCEMENT OF MULTIGATE MOSFET USING ENGINEERING TECHNIQUE-A REVIEW

NEERAJ GUPTA1 1Assistant Professor, Amity School of Engineering & Technology, Gurugram, India

Received: February 28, 2019 Accepted: April 11, 2019

ABSTRACT: : The design of future VLSI circuits using conventional MOSFET has become a challenge for the device engineers. The presence of short channel effects at nanoscale has becomes the limiting factor for the futuristic devices. The dielectric engineering along with gate and channel engineering effectively reduce the SCEs and outcomes in improved performance in terms of transconductance and sub-threshold behavior. In this paper, the consequences of engineering technique on the multigate have been explored and reported.

Key Words: Gate engineering, Dielectric engineering, Channel engineering, Multigate MOSFETs, SCEs

I INTRODUCTION The future generation devices demands for small size . As the size of traditional MOSFETs is scaled down, the performance of device diminishes due to the occurrence of short-channel-effects (SCEs) [1]. Multigate MOSFETs have paved the way to enhance the performance in nanoscale regime. The reduction in device dimensions causes the close proximity between the source and drain which diminutive the capacity of the gate electrode to control the channel. The presence of short channel effects at scaled devices squeezes the MOSFETs [2]. The researchers are trying to find out a device which has small size and negligible presence of short channel effects. The multigate MOSFET is the most promising device which shows higher performance. This structure includes double-gate (DG), triple-gate (TG) and gate-all-around (GAA) MOSFET which amends performance in comparison to traditional single gate MOSFETs [3–5]. In double gate MOSFETs, two gates are present to control the channel current. But SCEs are still present in this device. To avoid the SCEs, device should be fully surrounded by the gate material and device is known as gate-all-around (GAA) MOSFET. At smaller channel lengths, it is a huge task to reduce the leakage currents [6]. The gate and channel engineering techniques are used to further boost up the device efficiency. This review paper points out i) Gate engineering technique and its influence on threshold voltage, transconductance to drain current ratio and sub-threshold behavior, ii) Dielectric engineering technique to reduce the leakage current, iii) Channel engineering technique to improve the mobility degradation and iv) conclusion of the study.

II GATE ENGINEERING TECHNIQUE Gate engineering was introduced by Long et al. [7] and it produced a dual material gate MOSFETs (DMG). This device has two different metals at the gate with distinct work functions that produces step potential profile which suppresses the SCEs as compared to a single gate MOSFET. Gate engineering techniques involves dual material gate (DMG) or tri-material gate (TMG) in which two or three materials are used for the gate region. A higher work function gate metal is used near the source end which is known as control gate and a lower work function gate metal is used near the drain end, prevents any variation in the drain voltage which is also known as screening gate. This method produces a step potential profile along the channel at the interface [8]. This kind of potential scale down the sub-threshold leakage current and DIBL values and increases the transconductance. Currently, diverse gate engineering structures have been examined. One such device structure Triple material gate has been investigated. In this TMG structure three dissimilar electrodes are utilized with disparate work function. This disparity produces step potential profile and crest field in the channel. It boosts up the carrier transportation efficiency and therefore overcome the SCEs [8]. Ghosh et al. [9-10] have developed a drain current model for DMG-CG MOSFET and derived the expression for transconductance and drain conductance. The impact of technology parameter variations and work function difference has also been described. If the metal work function near the source side increases then sub-threshold currents decreases. This indicates enhancement in performance. The result depicts that DMG SGT device has superior performance than SMG SGT MOSFET.

Research Paper IJRAR- International Journal of Research and Analytical Reviews 431헑 [ VOLUME 6 I ISSUE 2 I APRIL– JUNE 2019] E ISSN 2348 –1269, PRINT ISSN 2349-5138 Superposition method was used to develop surface potential model for TMSG MOSFETs by Wang et al. [11]. But the approach is somewhat difficult and complex. Hence to make the model simple, the method of parabolic approximation is proposed in this work to develop a model for threshold voltage. Since, the approximation will have uniform profile all through the approximation using the parabolic approximation method. 2.1 Threshold Voltage T.K. Chiang [12] has applied 2D Poisson equation to determine the threshold voltage of fully depleted cylindrical surrounding gate MOSFETs. The concept of minimum surface potential is used to find the threshold voltage model. The thin film and gate oxide can reduce the roll-off of threshold voltage. But the superposition method is used to find the threshold voltage which involves 1D & 2D equations. Auth et al. [13] proposed a threshold model for surrounding-gate MOSFETs. The threshold voltage for the device is equal to perimeter weighted sum of the threshold voltages. The subthreshold slope and DIBL are also discussed and compared with DG-MOSFETs. This is only used for the non-gate engineered structures of surrounding gate MOSFETs. K.P. Pradhan et al. [14] proposed the center potential model for calculating the threshold voltage of a CGAA MOSFET using poisson’s equation. The impact of variation in device parameter on threshold voltage is also described. Furthermore, a comparative study between surface and center potential model was carried out and find out that center potential model is more accurate for calculation of threshold voltage. N.B. Balamurgan et al. [15] presented a threshold voltage models for Cylindrical and Rectangular Surrounding Gate . The effect of various device parameters like silicon film thickness, gate oxide thickness, and drain bias on the threshold voltage of a Cylindrical and Rectangular surrounding gate MOSFETs are analyzed. The performance of rectangular gate device is influenced by corner effect which causes the premature inversion and SCEs occurs. But cylindrical gate device is not affected by corner effects. Himangi sood et al. [16] presented the numerical modeling for the Gaussian doped and undoped cylindrical surrounding gate (CSG) MOSFETs. The analytical results of undoped CSG depicts that the potential depends upon the gate voltage. The surface potential variation above the Vt does not depends upon silicon thickness and can be change by changing the work function. The surface potential at the drain and source sides are used to represent drain current and capacitances. The solution of surface potential is derived by using taylor series expansion. The desired value of threshold voltage can be obtained by carefully selection of projected range and stagger factor. The result shows that SG MOSFET has tremendous performance in terms unilateral and maximum stable power gain. Kumar et al. [17] has presented a new analytical model for the threshold voltage of a dual-material surrounding-gate MOSFETs. The model results accurately predict the threshold-voltage roll-off for channel lengths even less than 90nm. The SCEs are reduced in DM-SGT device. M. Jagdesh Kumar et al. [18] developed the threshold voltage model for DMG SG MOSFETs. This model precisely tracks the roll off of threshold voltage with decreasing channel length. The effect on DMG SG MOSFET with varying device parameters is also studied and analyzed. Sarvesh Dubey et al. [19] developed a threshold voltage model for a TMCGAA MOSFET by using parabolic approximation. The 2D poisson equation in cylindrical coordinate system is used to find out the center and surface potential. Then center potential model is used to formulate the threshold voltage model and DIBL is also investigated. This paper also presented the impact of device parameter variation on threshold voltage. By increasing the screen gate length ratio, there is decrease in the DIBL and hot carrier effect (HCE) but it increases the other SCEs. So, optimum values of device parameters are selected for appropriate value of threshold voltage. P. Suveetha et al. [20] has proposed an analytical model for the TMSG MOSFET and its solution is given by the Poisson equation. In TMSG, gate electrode consists of three materials with different work function. The model describes the analytical modeling of surface potential, field and threshold voltage using parabolic approximation method. The SCEs are reduced due to the step in the surface potential profile and carrier transport efficiency is also improved. HK Wang et al. [11] developed an analytical model of threshold voltage for TM-SGT MOSFETs, which deteriorate the SCEs as compared to DM-SGT and TM-DG MOSFETs. The roll-off of threshold-voltage with decreasing channel length is also traced by the model. The effect of variation in the device parameters on the SCEs is also analyzed for TM-SGT MOSFETs. The superposition method is used to find out the surface potential. P. Suveetha et al. [21] presented the threshold voltage model of a TMSG MOSFET by using the Poisson equation. The results delineate the significance of gate engineering in MOSFETs. The result shows that SCEs are reduced with gate engineering structure as compared to conventional MOSFETs. The variation in 432헑 IJRAR- International Journal of Research and Analytical Reviews Research Paper [VOLUME 6 I ISSUE 2 I APRIL – JUNE 2019] e ISSN 2348 –1269, Print ISSN 2349-5138 http://ijrar.com/ Cosmos Impact Factor 4.236 threshold voltage is analyzed and studied for various device parameters like silicon thickness, oxide thickness, gate length ratios, doping concentration. Jai Hind Kumar Verma et al. [22] presented the physics based mathematical model for Cylindrical Surrounding Double Gate (CSDG) Nano- MOSFET. The superposition method is used to find out the potential, field and threshold voltage. CSDG MOSFET has better gate controllability as compared to conventional surrounding gate MOSFET. The effect of variation in channel length on different electrical characteristics has also studied. Cong et al. [23] employs halo doping in surrounding gate (HDSG) MOSFET. A 2D Poisson’s equation in cylindrical coordinates is solved to find out the threshold voltage and subthreshold current for HDSG MOSFETs. It is observed from this paper that superposition technique shows higher accuracy than parabolic approximation technique especially when the oxide thickness is much smaller than the thickness of the silicon channel. The threshold voltage characteristics can be further improved by considering thin gate oxide thickness, small value of channel radius and halo doping. But it is not suitable for gate engineered structures. The analytical modeling of SH-TMSG MOSFET was developed by P.Suveetha. The parabolic approximation method is used to find out the threshold voltage and subthreshold current. The roll-off of threshold voltage is reduced which clearly indicates suppression of SCEs [21]. In the literature, Threshold voltage model has been developed by using 1D analysis. Some of the developed models are specific so that cannot be applied to DH-DD-TMSG MOSFETs. Many models require complex mathematical calculation and did not show the threshold voltage roll-off when the channel length decreases. To avoid these problems associated with existing threshold voltage models, it is determined by solving poisson equation. So the analytical model of proposed device DH-DD-TMSG MOSFET is determined by parabolic approximation method. 2.2 Sub-Threshold Characteristics Liu & Hsieh [24] proposed a model for sub-threshold behavior of MOSFET. The model assumes that potential difference between the drain and the source is small for the threshold voltage above the gate to source voltage. But these assumptions are not applicable to triple material structures. Arun Kumar et al. [25] developed mathematical models of sub-threshold current and swing for double gate all around MOSFETs including quantum confinement effects. The Pao-Sah’s formula is used to find out the sub-threshold current. Carrier confinement is added in the model that causes introduction of quantum effects in the device. The virtual cathode method has been used to model the sub-threshold swing. The variation in sub-threshold characteristics with device design parameters has been studied. B. Jena et al. [26] systematically analyzed the performance of an undoped CGAA MOSFET with process parameters such as work function of gate metals, channel thickness and length. In traditional MOSFET, channel doping is high to provide more current but causes more variation in threshold voltage. So, the undoped behavior of GAA MOSFET solves the above problem. The result reveals that ultra thin body and higher metal gate work function can improve the performance and reduce the SCEs. The proper selection of silicon thickness and gate work function can give optimum value of threshold voltage. Sonam Rewari et al. [27] have been presented a Junctionless Double Surrounding Gate(JLDSG) MOSFET for subthreshold current and swing using superposition method. The effects of variation in channel length, silicon and oxide film thickness have also been studied. The results obtained from JLDSG MOSFET have been compared with traditional Junctionless Surrounding Gate (JLSG) MOSFET and shows tremendous performance. Vadthiya Narendar et al. [28] proposed the 2D analytical model for surface potential, transconductance and sub-threshold current. The underlap DM-DG MOSFET has been considered to increase the analog and RF performance of DG MOSFET. The significant reduction in sub-threshold current has been observed when underlap length increases because, the control of gate over the channel increases. DMG structure ameliorate analog figure of merit such as TGF, output conductance and gain frequency product. So make the device suitable for analog/RF applications. T.K. Chiang et al. [29] presented the sub-threshold behavior model for DMSG MOSFETs. The DMSG MOSFETs shows excellent performance than their counterpart SMSG MOSFET by reducing HCE and SCEs. The device can achieve good sub-threshold behavior with thin gate oxide and thin silicon body. The superposition method is used to find out the surface potential and threshold voltage. The sub-threshold current and swings are also determined for DMSG MOSFETs. Gautam et al. [30] presented a model for cylindrical gate all around MOSFET using the impact of localized charges. This is a charge dependent model which is indirect way of finding the sub-threshold current. Tiwari Research Paper IJRAR- International Journal of Research and Analytical Reviews 433헑 [ VOLUME 6 I ISSUE 2 I APRIL– JUNE 2019] E ISSN 2348 –1269, PRINT ISSN 2349-5138 et al. [31] proposed the sub-threshold characteristics of TM-DG MOSFET by using virtual cathode concept. The similar approach was adopted by P.Suveetha Dhanaselvam et al. [32] to identify the sub-threshold characteristics of TM-SG MOSFET. The sub-threshold characteristics of DH-DD-TM-CGAA MOSFET has not been reported till now in literature and therefore the virtual cathode technique by considering the drift and diffusion components of current densities is used in finding the sub-threshold characteristics of the device. The performance of the device is investigated with different device parameters and the characteristics are analyzed and compared with other exiting devices. 2.3 Transconductance to Drain Current Ratio (TDCR) TDCR is a key metric to access the performance of a device instead of transconductance which is also known as the quality factor of MOSFET devices. A new design methodology is presented by Rajendran et al. [33] using the surface potential technique to find the TDCR and body factor (n) of fully depleted double-gate SOI MOSFETs and its influence on electrical parameters are also studied and analyzed. The technique is suitable for low power VLSI circuits where the weak and average inversion is used. The dependence of TDCR on temperature is also considered. The result reveals that DG SOI MOSFET has a higher TDCR and optimum body factor values than conventional and SOI MOSFET. Kranti et al. [34] presented an analytical model to enhance the TDCR (gm/Id) for a vertical surrounding gate (VSG) MOSFET. The VSG MOSFETs obtained more TDCR values than DG MOSFET at all sets of device parameters. The results show that reduction in silicon film thickness (tsi) is essential to obtain larger value of gm/Id ratio. But this above models cannot be applied to triple material surrounding gate devices. Santosh Gupta and S. Baishya [35] have presented the suitability analysis of cylindrical gate all around MOSFET for low power and analog applications. By using CGAA MOSFET, further downscaling of conventional MOSFET is possible with immunity against SCEs. At lower gate length, transconductance is more and output resistance is small which makes it suitable for analog applications. Sonam Rewari et al. [36] proposed a dual metal insulated shallow extension (DMISE) technique to reduce the problem of Gate Inducted Drain leakage (GIDL) current in CGAA MOSFET. The proposed device reduces the gate leakage current by reducing the tunneling from valance band to conduction band. The DMISE MOSFET has compared with traditional GAA MOSFET and proposed MOSFET shows large value of transconductance and drain current. It also achieved ideal value of sub-threshold slope and large on to off state current ratio. Balamurgan et al. [37] explained a TDCR model for dual metal surrounding gate MOSFET and the surface potential is calculated on the basis of boundary conditions derived for that particular MOSFET. TDCR value of DM-SG MOSFETs does not lessen as in the case of DG MOSFETs at smaller lengths and larger film and oxide thickness. So transconductance generation efficiency of DM-SG MOSFETs is better than DG MOSFETs. Recently a model is reported by P.Suveetha Dhanaselvam et al. [32] for Triple material surrounding gate MOSFETs. The solution of Poisson equation gives TDCR and electric field distribution profile in TMSG MOSFETs. It is observed from the results that device exhibits higher performance when the length of the control gate is more than that of remaining gate lengths. The model presented in this paper also includes the impact of silicon and gate oxide thickness on sub-threshold characteristics. The TDCR of TMSG MOSFET is also compared with other DG MOSFETs. The TMSG MOSFETs shows more value of TDCR as compared to DG MOSFETs. No work has yet been reported on the gm/Id ratio for DH-DD-TM-CGAA MOSFET.

III DIELECTRIC ENGINEERING In lieu of SiO2, high dielectric constant oxide as a gate insulator are used to inhibit the direct tunneling leakage current which arises due to downscaling of device dimensions .The study shows that superseding of SiO2 and attached high K dielectrics decrease the performance of the device and control of gate over the channel. So a narrow interfacial oxide layer is used along with high K dielectrics to decrease the density of interface trap charge. Therefore it minimizes the gate-leakage and increases the electric field inside the channel. Thus it improves carrier transportation efficiency [38]. Yeap et al. [39] studied the influence of high-K gate dielectric on device turn-off/on characteristics and it decreases due to fringing induced barrier lowering (FIBL). The potential barrier of the channel reduces due to fringing of electric field which causes lower threshold voltage and enhancement in standby power. By using interfacial oxide layer, FIBL can be reduced completely for K≤25. Zhang et al. [40] modeled the roll-off of threshold voltage using high-K and gate stack structure. The proposed model considers the impact of fringing field on single and double stacked layer insulators. The introduction of ultra thin low-K layer between the high-K and substrate improves the SECs. 434헑 IJRAR- International Journal of Research and Analytical Reviews Research Paper [VOLUME 6 I ISSUE 2 I APRIL – JUNE 2019] e ISSN 2348 –1269, Print ISSN 2349-5138 http://ijrar.com/ Cosmos Impact Factor 4.236 Yeo et al. [41] described the future material for gate dielectrics. Leakage from gate is the major issue in scaled devices. The existing SiO2 should be replaced by alternate gate dielectric which can be used for future devices. In this paper, the different gate dielectrics are compared on the basis of tunneling effective mass. So high-K gate dielectrics are suitable for low standby power techniques. B.C. Mech & J. Kumar [42] studies the important aspects of selection of gate dielectrics to minimize the SCEs. The comparative study of silicon dioxide (SiO2), aluminium oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O3) and titanium dioxide (TiO2) as gate dielectrics for scaled devices was carried out. The results show that titanium oxide is the best gate dielectric among all. But dielectric constant is high which causes increase in capacitance and degrade the performance in ac analysis. Wong et al. [43] analyzed the importance of oxide thickness for future generation CMOS devices. The channel length has to be reduced for further downscaling of MOSFET. But device performance degrades such as the rise in off current due to gate leakage. The channel and gate engineering will be the only solution to control the current in the deca nanometer devices. The equivalent oxide thickness (EOT) has to be scaled aggressively in order to minimize the off current efficiently. The major problem is that metal gate & high-K interface are not directly scalable. In this paper, these issues were highlighted from the fabrication points of view. S.K. Mohapatra et al. [44] analyzed the DG-GS MOSFET with gate and channel engineering. Comparison is carried out between single metal (SM) DG-GS, dual metal (DM) DG-GS and DM-SH-GS-DG MOSFETs on the basis of TGF and early voltage, intrinsic gain and transconductance coefficient. The result reveals that DM- DG MOSFET with gate stack shows more performance than SM counterpart. D. Nirmal et al. [45] presented the behavior of DMG MOSFET with diverse high-k dielectric. The velocity of HfO2 is 31% higher than SiO2 which enhance the carrier transport efficiency. The ION/IOFF ratio, DIBL, gain and transconductance generation factor (TGF) are studied for both dielectrics. DIBL of HfO 2 shows a reduction of 61.5% overSiO2. The TGF shows an improvement of 35%. The CMOS inverter has been designed using high-K dielectric. It shows reduction in delay and power dissipation. The HfO2 will be the best alternative for the future multigate devices. D.M. Thomas et al. [46] analyzed the effect of high-K dielectrics on gate engineering structures. The performance of DMDG MOSFET is extracted in terms of surface potential and transconductance. Equivalent Oxide Thickness (EOT) can be reduced by high-K dielectric at gate oxide. The gate engineered device with high-K dielectric depicts an enhancement in the analog performance. This device shows a remarkable improvement in current by 5% in the sub-threshold regime and a 3% enhancement in transconductance. Sonam Rewari et al. [47] developed an analytical model considering the influence of gate induced drain leakage current of dual-metal hetero-dielectric (DM-HD) cylindrical gate all around (CGAA) MOSFET. The device structure consists of silicon dioxide as a gate dielectric at source side and vacuum dielectric at drain side, which reduces the off state leakage current. The off state leakage current is reduced in DM-HD-CGAA MOSFET as compared to traditional CGAA MOSFET. The analysis of off state leakage current is also done at elevated temperature. Rajni Gautam et al. [48] proposed the GAA MOSFET with vacuum gate dielectric (VGD). The RF performance of proposed device is compared with conventional GAA MOSFET. It has been observed that GAA with VGD is much better than SiO2 dielectric in terms of hot carrier reliability due to low drain field. But it suffers from poor on current and transconductance. To improve these parameters, gate and channel engineering is used. So it improves the overall performance of the device. Aniruddh Sharma et al. [49] presented a gate stack structure in which dielectric is the combination of vacuum and High-K. This gate stack architecture minimizes the effects of impact ionization, BTBT and electric field at the drain side. Hence, an overall result is reduction in SCEs. An analytical model has been proposed for the junctonless cylindrical surrounding gate (JL-CSG) MOSFET using Poisson equation in cylindrical coordinate system. A comparison has been made between JL-CSG, gate stack JL-CSG and CSG. The proposed device shows reduction in hot carrier effect and improving the current driving capability. Nidhi Singh et al. [50] developed the 2D analytical modeling of surface potential for TMGS-DG MOSFET. The model is described with the help of Poisson’s equation with sufficient boundary conditions. The impact of dielectric thickness on the potential barrier has been analyzed. No work has yet been reported on the dual dielectric for DH-DD-TM-CGAA MOSFET.

IV CHANNEL ENGINEERING The Channel engineering concern with the halo implants to vary the doping profile in channel. Halo implant is basically of two types: symmetrical and asymmetrical. It is also known as pocket implants. The device Research Paper IJRAR- International Journal of Research and Analytical Reviews 435헑 [ VOLUME 6 I ISSUE 2 I APRIL– JUNE 2019] E ISSN 2348 –1269, PRINT ISSN 2349-5138 performance was affected when the depletion layers near to source and drain become nearly equal to the channel length L in scaled devices. By increasing the doping in substrate region, reduces the width of depletion layers and SCEs. On the other side increase in substrate doping causes increase in threshold voltage and lower the carrier mobility. But increasing doping near to source side can reduce the SCEs without reducing the carrier mobility. This is known as lateral asymmetric channel devices. The surface potential decreases due to the incorporation of pocket implants in the MOSFET. These halo profile introduces an extra step function in addition to steps produced due to gate engineered structures. The benefit of reduction in surface potential is the reduction of the drain induced barrier lowering and threshold voltage roll-off. The extra benefit of using dual halo devices is the large doping at the drain side inhibits the field penetration from drain side to source side. So the dual halo further reduces the DIBL and gives better control over the channel. Zanchetta et al. [51] introduced the halo doping in MOSFET to control the SCEs. A quasi-2D model has developed and result shows that the halo implant concept reduce the off current of MOSFET which makes it suitable for low power applications. The subthreshold drain current model for pocket implanted halo MOSFET has been introduced by S. Baishya [52]. The surface potential is calculated by solving a pseudo-2D Poisson’s equation. But the model consists of complex mathematical equations. So it is not suitable for surrounding gate MOSFETs. Srimanta Baishya et al. [53] presented the sub-threshold potential model for dual halo MOSFET. This model includes the effect of depletion layer width near the source and drain junctions on channel depletion layer width. Gauss law is applied to find out the surface potential. Sarkar et al. [54] presents a device which integrates the benefit of both gate and channel engineering methods. This device is known as Double-Halo Dual Material gate (DHDMG) MOSFETs and Single Halo Dual Material gate (SHDMG) MOSFET. The analytical model of sub-threshold surface potential was developed by using the pseudo-2D analysis. The Gauss’s law was applied to an elementary rectangular box in the channel depletion region. The accurate estimation of sub-threshold surface potential considers the varying depth of channel depletion layer in association with the inner fringing potential in the source and the drain ends. The same procedure is adopted to calculate the threshold voltage and sub-threshold behavior for DHDMG and SHDMG MOSFETs. The DHDMG device structure shows better suppression of the SCEs among all the pocket implanted and SHDMG. This Gauss Law technique involves the device physics concept which is very difficult to evaluate. Harshit Aggarwal et al. [55] have reported the anomalous behavior of halo implanted MOSFET in linear and saturation regions for transconductance. The transconductance curve shows the sharp change of slope in saturation. The reason for this behavior has been found out for halo and uniformly doped transistors. The impact of oxide thickness variation on gm is also analyzed. The gm characteristics using efficient SPICE model is also proposed. Reddy & Kumar [56] have proposed the asymmetrical single halo doped double gate MOSFET. This work presents the simulation studies of the threshold voltage roll-off, DIBL and sub-threshold slope and have better performance than a conventional DG MOSFET. The step functions in the surface potential due to the existence of single halo near to source side, which protect source from the variations in drain bias. But the analytical model of the structure was not described. N. Mohan Kumar et al. [57] have reported the lateral asymmetric halo doping with gate engineering technique. The performance of the dual metal technology with halo doping was investigated with respect to surface potential, electric field, drain current, DIBL and transconductance. The leakage current and SCEs in the device decreases due to the lateral asymmetric channel (LAC). In this method, the channel doping near to source side is more than drain side. This causes reduction in the sub-threshold leakage current. The Single halo dual metal DG MOSFET shows better immunity against SCEs as compared to single halo DG MOSFETs. But the analytical modeling of the device was not elaborated. Luan et al. [58] proposed a model for asymmetrical halo dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET. The halo doping is done near to source region. The channel potential was calculated by using the 2D Poisson’s equation. The sub-threshold behavior of the device was determined by using the drift-diffusion theory. The model is developed only for DMGMOSFET and not suitable for . T.K. Chiang [59] developed an analytical model of threshold voltage and sub-threshold swing for asymmetrical dual-material double-gate (ADMDG) MOSFET’s. The device parameter such as , gate oxide and small length of screen gate is preferred to suppress the SCEs. The superposition method is used to find out the solution which involves complex mathematical equations. Z. Chao [60-61] carried out the performance analysis of symmetrical halo-doped cylindrical surrounding gate MOSFETs. The performance of the device is studied in terms of analytical model of surface potential 436헑 IJRAR- International Journal of Research and Analytical Reviews Research Paper [VOLUME 6 I ISSUE 2 I APRIL – JUNE 2019] e ISSN 2348 –1269, Print ISSN 2349-5138 http://ijrar.com/ Cosmos Impact Factor 4.236 and threshold voltage by using parabolic approximation. The symmetrical halo doping profile illustrate higher performance in quenching roll-off of threshold voltage and drain induced barrier lowering than uniformly doped surrounding gate MOSFETs. But model was not suitable for channel length below 50nm. Li Cong et al. [62] developed an analytical model of surface potential, threshold voltage, electric field and sub-threshold current for halo doped SGMOSFETs. The threshold voltage shows higher accuracy than parabolic approximation method. The variation with device parameters like oxide thickness, doping concentration and silicon thickness was also discussed. The mathematical model was described by using superposition technique that consists of 1D and 2D equations. The model seems to be complex and tedious to find out the solution. Harsupreet Kaur et al. [63] presented a model for graded channel surrounding gate (GCSG) MOSFET. The low doping at the drain side in comparison to source side increased the mobility and decreases the electric field. The drain current model also incorporates the DIBL and channel length modulation (CLM) for GCSG MOSFET. P.Suveetha et al. developed a 2D analytical model for single halo triple material surrounding gate (SHTMSG) MOSFETs. The parabolic approximation method is used to derive the threshold voltage and sub-threshold current. By introducing halo in TMSG, the roll off of threshold voltage is reduced which clearly indicates reduction in SCEs. But effect of dual halo on TMSG was not described [21].

V CONCLUSION In the literature, the SH is studied for dual metal surrounding gate MOSFET and TM-SG MOSFET. The concept of dual halo has not been continued to triple metal gate structure. Hence it is beneficial to combine triple metal, dual dielectric and halo structure to design a new device which is known as dual-halo dual- dielectric triple-material cylindrical gate all around (DH-DD-TM-CGAA) MOSFET. The DH-DD-TM-SG MOSFET structure is designed and the analytical model for the surface potential, electric field, threshold voltage and sub-threshold current is developed. The analytical model is verified by TCAD results.

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Research Paper IJRAR- International Journal of Research and Analytical Reviews 439헑