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Lecture 31: Devices and Integrated Circuit Formation

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Lecture 31: Devices and Integrated Circuit Formation Lecture 31: Devices and Integrated Circuit formation Contents 1 Introduction 1 2 Resistors 2 3 Capacitors 4 4 Diodes 5 5 Transistors 7 5.1 BJT . .7 5.2 MOSFET . .9 6 MEMS systems 10 6.1 MEMS calorimeter . 13 1 Introduction Integrated circuits are made of various electronic components, which are assembled as per the micro architecture design, to form the final circuit. Some typical circuit components in an IC are as follows 1. Resistors and conductors 2. Capacitors 3. Diodes 4. Transistors 5. Fuses 1 MM5017: Electronic materials, devices, and fabrication Figure 1: Relation between resistance, resistivity, and material dimensions. Resistivity is a material property, independent of the dimensions, unlike re- sistance. Adapted from Microchip fabrication - Peter van Zant. These devices are fabricated using the various processes described in previous chapters and ultimately form the IC. 2 Resistors Resistors are used for controlling the current flow. Every doped or undoped region in a wafer is a resistor. Dopant concentration is used for controlling the resistance. Resistors can be formed by isolating regions of the wafer by using suitable dielectrics. For a region of length L and area A, the resistance is given by R = ρLA (1) where ρ is the resistivity of Si (shown in figure 1 ). A doped resistor can be made by patterning and exposing a certain region on the wafer, which is then doped to the desired concentration. The steps for forming doped resistors are shown in figure 2. Electrical contacts are provided by Ohmic contacts and the resistor region is separated from the rest of the wafer by either silicon oxide or nitride. Resistors can be linear or serpentine. Serpentine resistors are used for increasing resistance by increas- ing total length. These are shown in figure 3. Epi resistors are formed by isolating a section of an epitaxial Si layer that 2 MM5017: Electronic materials, devices, and fabrication Figure 2: Stages in the fabrication of a doped resistor. (a) Pattering of the top oxide layer to create an opening (b) Doping to achieve the required concentration (c) Growth of a new oxide layer and patterning for contacts (d) Deposition of metal layer and removal of excess metal. Adapted from Microchip fabrication - Peter van Zant. Figure 3: (a) Linear vs. (b) serpentine resistors. For the same lateral di- mensions, serpentine resistors have a longer overall length and hence, higher resistance. Adapted from Microchip fabrication - Peter van Zant. 3 MM5017: Electronic materials, devices, and fabrication Figure 4: EPI resistor formed by isolating an epitaxial Si layer. The resis- tance depends on the thickness and dopant concentration of the EPI layer. It is usually isolated by fabricating trenches in the wafer. Adapted from Microchip fabrication - Peter van Zant. Figure 5: Pinch resistors formed in vertical pnp transistor configuration. The n region (base) is the pinched resistor since it is lightly doped and has the highest resistivity. Adapted from Microchip fabrication - Peter van Zant. has been deposited by chemical vapor deposition process. Figure 4 shown a epi resistor. The resistor is isolated using trenches and the contacts are patterned through the oxide layer on top. Pinch resistors are formed by having alternately doped regions (like a npn BJT). The base region between the junctions are the pinch resistors, shown in figure 5. 3 Capacitors A capacitor is a dielectric region sandwiched between two electrodes. The simplest dielectric structure is the metal oxide semiconductor (MOS) struc- ture, shown in figure 6. The contact can be a metal layer or heavily doped poly Si. These structures are similar to those created for the MOSFETs, ex- cept for the absence of the source and drain. The arrangement of the MOS 4 MM5017: Electronic materials, devices, and fabrication Figure 6: Metal oxide semiconductor capacitor. The charge is stored in the oxide (insulator) layer and contacts are formed by patterning, on the wafer and the oxide layer. Adapted from Microchip fabrication - Peter van Zant. capacitor is similar to a parallel plate capacitor. The dielectric material can be silicon oxide or oxy-nitride or a high-k dielectric material. Another technique to form capacitors, is to use the depletion region, which is formed between p − n junction. The junction capacitance value is important for circuit design since it affects the speed of the circuit. The natural junction capacitance has the effect of slowing down the circuit. In order to save space, capacitors can also be fabricated perpendicular to the wafer surface. These are called trench capacitors, shown in figure 7. Trench capacitors are typi- cally grown by CVD, since they are high aspect ratio structures. One of the contacts is poly Si while oxide is the dielectric material. 4 Diodes The simplest diode that can be fabricated is the planar pn junction diode. The various steps in the fabrication of this diode are shown in figure 8. The starting material is a n type Si wafer. An oxide layer is grown on top to form a hard mask for patterning and also for electrical isolation. A window is opened in the oxide layer (by lithography and dry etching) for incorporating the p type dopant. Depending on the size of the window and the stage in processing, either furnace doping or ion implantation can be used. The dopant concentration and profile depends the junction depth and that can be controlled. Finally, metal contacts are fabricated after a second lithography and deposition step. The metal is annealed post deposition to form Ohmic contacts at the junction. 5 MM5017: Electronic materials, devices, and fabrication Figure 7: Schematic of a trench capacitors. Trench capacitors are preferred since they occupy less space on the surface. Usually, chemical vapor deposi- tion is used to grow the poly silicon layer in a deep trench that is etched in the silicon wafer. Adapted from Microchip fabrication - Peter van Zant. Figure 8: Steps in the fabrication of the planar pn junction diode. (a) Oxide growth on a n-type wafer (b) Patterning is done to create an opening for doping (c) Doping is carried out to form the pn diode and define the location of the junction (d) Final device with electrical contacts deposited. I repre- sents the direction of external current. Adapted from Microchip fabrication - Peter van Zant. 6 MM5017: Electronic materials, devices, and fabrication Figure 9: A simple Schottky junction diode. The metal contact is deposited through a patterned oxide layer so that it makes contact with the wafer. The contact to the silicon is not shown in this figure. Adapted from Microchip fabrication - Peter van Zant. Similar to the rectification action of pn diodes, Schottky junction diodes are also rectifiers. A schematic of the device is shown in figure 9. The semiconductor is lightly doped and there is one patterning step for depositing the metal and the contacts. 5 Transistors 5.1 BJT Bipolar junction transistors (BJT) consist of three differently doped regions i.e. pnp or npn arrangement. The emitter region is heavily doped, while the base is lightly doped, and the collector has a larger width than the other two regions, for the injected carriers. The collector dopant concentration is usually the same as the starting wafer dopant concentration. The emitter and base are formed by compensation doping of this wafer, to form the respective regions. The dopant concentrations and annealing temperatures and adjusted such that the concentration profile, shown in figure 10 can be obtained. The base concentration is a Gaussian profile (obtained by solid state diffusion) while the emitter concentration is an error function profile obtained by diffusion from a gas/liquid source. Lateral and vertical BJT structures are shown in figure 11. These can be obtained by using suitable lithography masks for creating openings for doping. 7 MM5017: Electronic materials, devices, and fabrication Figure 10: Dopant profile generated in a BJT by successive diffusion steps. The base region is created by diffusion from a solid source (Gaussian profile) while the collector region is created by diffusion from a gaseous or liquid source (error function profile). Adapted from Microchip fabrication - Peter van Zant. Figure 11: (a)Lateral and (b) vertical fabricated bipolar junction transistor. The oxide layer is used to pattern the contacts and trenches are used to separate adjacent transistors. Adapted from Microchip fabrication - Peter van Zant. 8 MM5017: Electronic materials, devices, and fabrication Figure 12: Schematic of a metal oxide field effect transistor. The base wafer is p type while the source and drain are n type. There is a gate oxide separating the metal gate and the silicon. Adapted from Microchip fabrication - Peter van Zant. 5.2 MOSFET MOSFETs belong to the class of field effect transistors, where a metal/heavily doped poly Si gate is used to create the channel for electron flow. The metal gate MOS transistor is shown in figure 12. MOSFET is the basic building block of the IC. Unlike the BJT, the channel has to be created by applying an external voltage. If the source and drain are of n type, then a n-channel must be created for conduction to occur. This is the NMOS. Similarly when the source and drain are of p type, then it is called PMOS. The steps in fabrication of the MOSFET are shown in figure 13. When a metal gate is used, the gate is usually deposited at the end, since it cannot withstand high temperatures during annealing. Doped poly Si is also used for forming the gate. This is better than a metal gate, since a lower threshold voltage is required for forming the channel and the gate can also withstand high tem- perature. Poly Si gate also means that the gate can be patterned first, called self-aligned gate, since this can be used to align the source and drain.
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