Module 3: MOSFET Evolution • Section 1: MOSFETs Evolution & ITRS [1] Module 3: MOSFET Evolution • Section 2: Multigate Technology & Variability 2017 Update Intel, 2017, Technology and Manufacturing Day EE230B – Vivek Subramanian Slide 3-1 [1] R. Chau, et al. Nature Materials, 2007 EE230B – Vivek Subramanian Slide 3-2 Module 3: MOSFET Evolution Module 3: MOSFET Evolution Section 3: Multigate Transport and Electrostatics • Section 4: Multigate Reliability 290D, 2013 - Lecture 3 [1] K.K. Lin, H. Sheng, Synopsis, Enabling 14nm FinFET Design, 2013 Slide 3-3 EE230B – Vivek Subramanian Slide 3-4 1 History of the ITRS MOSFET EVOLUTION & THE ITRS EE231 – Vivek Subramanian Slide 3-5 EE230B – Vivek Subramanian Slide 3-6 Why we need the ITRS – scheduled invention ITRS 2.0 Roadmapping– Post 2013 • ITRS 2.0 connects ‘emerging system product drivers’ to semiconductor device roadmapping: – Mobile Devices – Datacenters –IoT • Top-down framework defining new requirements for IC’s & manufacturing EE230B – Vivek Subramanian Slide 3-7 EE230B – Vivek Subramanian Slide 3-7 2 ITRS Technology Node Definitions More Moore Roadmap - 2015 • Individual roadmaps are defined for high- performance, low-power, etc. EE230B – Vivek Subramanian Slide 3-8 EE230B – Vivek Subramanian Slide 3-10 ITRS - New Device Technologies ITRS Projected Power & Delay Scaling Progress to 2024 and beyond relies on new device technologies Ion is predicted to saturate and then decrease c. 2023, but with improved low-voltage performance switching energy will continue to scale down [1] FinFET LGAA VGAA *Replotted from [1] [1] ITRS 2.0, Executive Report, 2015 EE230B – Vivek Subramanian Slide 3-11 EE230B – Vivek Subramanian Slide 3-12 3 What about Lg? ITRS Projected Gate Length Scaling • The channel length is typically not the same as the gate length Physical Gate Length Lg is predicted to scale until 2021 Why is 10nm the limit? Vertical Devices Projected *Replotted from [1] Why are S/D designed to overlap with gate? [1] ITRS 2.0, Executive Report, 2015 EE230B – Vivek Subramanian Slide 3-13 EE230B – Vivek Subramanian Slide 3-14 Mobile Driver Trends Datacenter Trends • Mobile devices will add cores and increase memory bandwidth. • Datacenters will scale up in the next decade, with more cores • Heterogeneous integration will increase # sensors and more memory EE230B – Vivek Subramanian Slide 3-15 EE230B – Vivek Subramanian Slide 3-16 4 Datacenter Trends IoT Trends • Energy-efficient devices will use less power per operation, • IoT devices will have more sensors and require more efficient improving the efficiency of computing at data centers wireless communication EE230B – Vivek Subramanian Slide 3-17 EE230B – Vivek Subramanian Slide 3-18 IoT Device Trends Litho Challenges • Battery powered devices operate intermittently • EUV will compete with ArF multiple patterning • MOSFET off-state leakage dominates system power • EUV multiple patterning may be required as soon as 2021 EE230B – Vivek Subramanian Slide 3-19 EE230B – Vivek Subramanian Slide 3-20 5 General Industry Trends Low-k Dielectric Scaling • Heterogeneous integration will extend and • Low-k scaling for interlayer dielectrics has develop new functionalities slowed due to decreased mechanical • 3D-system in package architectures are to reliability and adhesion. become the primary technologies EE230B – Vivek Subramanian Slide 3-21 [1] ITRS2015_Interconnects EE230B – Vivek Subramanian Slide 3-22 Low-k Dielectric Scaling What problems are we trying to solve? • Leakage • Air gap is the ultimate low-k dielectric – As we scale devices, short channel effects become more important – Degraded S, DIBL, bulk punchthrough • Mobility / On-current – Velocity saturation limits improvement – Low-field mobility is very important for switching, high doping degrades this • Series resistance – Series resistance gets worse as we scale • Variability – Many techniques we use for device engineering increase variability as devices are scaled [1] ITRS2015_Interconnects EE230B – Vivek Subramanian Slide 3-23 EE230B – Vivek Subramanian Slide 3-24 6 Ioff / Ion Benchmarking •Ioff / Ion plots compare the performance and variability of different CMOS technologies • Captures Vt tunability for HP vs LP logic • Displays tradeoff between active and standby power Intel 22nm Trigate Technology MOS TECHNOLOGY BENCHMARKING [1] C. Arthur, VLSI, 2012 EE230B – Vivek Subramanian Slide 3-25 EE230B – Vivek Subramanian Slide 3-26 Ioff / Ion Benchmarking Delay & Power Benchmarking • Which phenomena explain the low Ioff and • Power and speed matter for efficient high Ioff portions of this plot? computing (e.g. datacenters) Intrinsic Delay = CV/I Normalized Energy-Delay Product R. Chau, IEEE Trans. Nano, 2005. EE230B – Vivek Subramanian Slide 3-27 EE230B – Vivek Subramanian Slide 3-28 7 Benchmarking Device Variability Benchmarking Device Variability • Pelgrom plot expresses Vt variation vs inverse • Pelgrom plot slope can compare processes area from different nodes or different fabs • Assumes model w/ AVT can be used to compare different MOS technologies Slope = Avt [1] O. Weber, IEDM 2008 EE230B – Vivek Subramanian Slide 3-29 EE230B – Vivek Subramanian Slide 3-30 Sources of Variability VARIABILITY EE230B – Vivek Subramanian Slide 3-31 EE230B – Vivek Subramanian Slide 3-32 8 Random Dopant Fluctuation Implications • Nanoscale devices have higher relative random fluctuations in doping (RDF) • RDF can be correlated to LER M. Hane, SISPAD, 2003 EE230B – Vivek Subramanian Slide 3-33 EE230B – Vivek Subramanian Slide 3-34 Solutions to RDF Line Edge Roughness EE230B – Vivek Subramanian Slide 3-35 EE230B – Vivek Subramanian Slide 3-36 9 Metal Gate Granularity FinFET Variability • MGG is an important issue for HKMG devices s s( • FinFET variability depends strongly on (RSD) • Metal gate granularity influences Vt) and causes variations in surface potential •RSD fluctuations can account for > 50% of variability in I at V = V • Grain orientation variability causes nanoscale on gs gmax workfunction variations TiN % Contribution to DID / ID 2 fins 20 fins A.R. Brown, EDL, 2010 EE230B – Vivek Subramanian Slide 3-37 [1] T. Karatsori, IEEE ICMTS, 2017 EE230B – Vivek Subramanian Slide 3-38 MOSFET Variability Corner Analysis Reliability implications on variability • Performance targets are selected to relax variability requirements • Yield statistics and economics determine tolerable variability and target performance K. Qian, PhD Thesis, UCB, 2015 EE230B – Vivek Subramanian Slide 3-39 EE230B – Vivek Subramanian Slide 3-40 10 Bond breaking view INCREASING MOBILITY EE230B – Vivek Subramanian Slide 3-41 EE230B – Vivek Subramanian Slide 3-42 Why mobility is still important Strained silicon • Mobility in silicon can be enhanced by straining it. This increases carrier mobility in both electrons and holes, due to changes in the • Source-side injection depends on µs energy structure of the conduction / valence sub-bands • Electrons: Idsat = qNsvs vs = µsEs vs • 4 subbands go up in energy, while 2 go down, reducing intervalley scattering and enhancing mobility EE230B – Vivek Subramanian Slide 3-43 EE230B – Vivek Subramanian Slide 4-44 11 Strained PMOS Stress-Induced Hole Band Splitting • Holes: • Strain reinforces subband splitting, adding to QM confinement effects discussed in Module 1 • Biaxial strain and confinement oppose each other, reducing effectiveness of biaxial strain S.E. Thompson, TED, 2004 • Heavy hole subband moves down, and therefore, majority of holes populate light hole subband, increasing mobility • Solution: Use strain in both NMOS and PMOS to enhance mobility in both devices, increasing circuit speed. [1] S.E. Thompson, TED, 2006. EE230B – Vivek Subramanian Slide 3-45 EE230B – Vivek Subramanian Slide 3-46 Methods of achieving strain Original (obsolete in Si) method: Virtual Substrate • Uniaxial strain is more effective and simpler to implement • Strain is usually achieved by growing a thin silicon layer over a relaxed SiGe layer (which has a larger lattice constant) • % strain is determined by %SiGe in the “virtual substrate” S.E. Thompson, TED, 2004 T. Ghani, IEDM, 2003 S.E. Thompson, TED, 2004 EE230B – Vivek Subramanian Slide 3-47 EE230B – Vivek Subramanian Slide 3-48 12 Typical Structure of Strained Si Defect issues in virtual substrates EE230B – Vivek Subramanian Slide 3-49 EE230B – Vivek Subramanian Slide 3-50 Process Integration Issues FinFET Strain Integration • Thermal budget • Strain transfer to FinFETs is less effective and more – Too much Dt and strain will relax non-uniform due to 3D fin geometry –Isolation • Strain imposed by wrap around metal gate adds to – Dopant Activation contribution from SiGe eS/D – Gate Oxidation • Ge diffusion causes high Nit • Salicide – Many germanides have high resistance – Ge segregation • Junction formation – Enhanced leakage due to relaxion-induced defects – Dopant segregation issues [1] S. Majumdar, IEEE TED, 2012. EE230B – Vivek Subramanian Slide 3-51 EE230B – Vivek Subramanian Slide 3-52 13 FinFET Strain Integration Strain relaxation: Critical Thickness • Strain transfer to FinFETs is less effective and more Critical thickness non-uniform due to 3D fin geometry J. Welser [9] for strain relaxation • Strain imposed by wrap around metal gate adds to decreases with contribution from SiGe eS/D increases in Ge content and temperature provides upper limit of strain-Si thickness ex. Ge30% g 9 - 40 nm [1] S. Majumdar, IEEE TED, 2012. EE230B – Vivek Subramanian Slide 3-53 EE230B – Vivek Subramanian Slide 3-54 Mobility Enhancement Band structure