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Teil 1: Prozessorstrukturen Teil 1: Prozessorstrukturen Inhalt: • Mikroprogrammierung • Assemblerprogrammierung • Motorola 6809: ein einfacher 8-Bit Mikroprozessor • Mikrocontroller • Koprozessoren • CISC- und RISC-Prozessoren • Intel Pentium Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 1 Was ist ein Mikrocontroller ? Als Mikrocontroller bezeichnet man • CPU • Speicher (RAM, ROM und/oder EEPROM) kombiniert mit mehreren E/A-Komponenten, wie z.B. • programmierbarer Timer • A/D- und D/A-Wandler • parallele E/A-Schnittstelle • serielle asynchrone E/A-Schnittstelle • serielle synchrone E/A- Schnittstelle auf einem einzigen Chip ! Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 2 Klassen von Mikrocontrollern Mikrokontroller für einfache Mikrokontroller für komplexe Anwendungen: Anwendungen: • i.a. 8-Bit CPU • i.a. 32-Bit CPU • geringe Taktfrequenz (< 10 MHz) • mittlere Taktfrequenz (< 100 MHz) • programmiert in Assembler, ggf. • Gleitkommaeinheit für IEEE in C oder BASIC „double precision“ Format • sehr kleiner RAM-Bereich • programmiert in Hochsprache (typisch < 1 Kbyte) • kleiner RAM-Bereich • kleiner ROM/EEPROM-Bereich (typisch < 32 KByte) (typisch < 16 Kbyte) • großer EEPROM-Bereich • Chip mit ca. 40-80 Pins (typisch < 512 Kbyte) • Beispiele: Intel 8051, Motorola • Chip mit ca. 200-300 Pins 68HC5, 68HC11 • Beispiele: Motorola MPC555, AMD Elan Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 3 Eigenschaften eines Mikrocontrollers Mikrocontroller sind optimiert zum Einsatz in eingebetteten Systemen: • ohne weitere externe Bausteine betriebsbereit • geringer Platzbedarf auf Platine • viele Konfigurationen mit unterschiedlichen Kombinationen von E/A- Komponenten verfügbar • auch Taktgenerator bereits auf dem Chip • geringer Stromverbrauch, Standby-Modus verfügbar • für großen Temperaturbereich ausgelegt • geringer Preis bei hohen Stückzahlen • dediziert für eine Anwendung, die durch die Software festgelegt ist • maskenprogrammiertes ROM oder EEPROM enthält Betriebssystem bzw. Monitorprogramm sowie das Anwendungsprogramm • Hauptanwendungsgebiet: Steuerungsaufgaben Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 4 Eigenschaften von Mikrokontrollern (Forts.) • mehrere hardwaremäßig (d.h. über spezielle Eingabeleitungen) wählbare Arbeitsmodi, z.B.: – „single chip mode“ (fast alle Pins des Chips stehen können für E/A- Leitungen genutzt werden) – „expanded mode“ (Adreß- und Datenbus wird nach außen geführt ) – „bootstrap mode“ (ROM beinhaltet eine Urlader-Routine zum Laden eines kleinen Programms über die eingebaute serielle E/A-Schnittstelle ins RAM, anschließend Sprung an eine feste Startadresse, z.B. 0000H) • Kommunikation zwischen E/A-Bausteinen und CPU über – an bestimmte E/A-Adressen in den Adreßraum eingeblendete lesbare und /oder schreibbare Kontroll- und Datenregister („memory mapped I/O“) – Interrupts, die von CPU durch das Setzen eines bestimmten Bits in einem Kontrollregister des jeweiligen E/A-Bausteins gesperrt werden können Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 5 E/A-Bausteine • E/A-Baustein verfügt neben Kontrollregister über Datenregister – zur Zwischenpufferung von einzulesenden oder auszugebenden Daten (nötig, da E/A-Geräte zumeist langsamer als CPU sind und zudem asynchron zur CPU arbeiten) – häufig separate Eingabe- und Ausgaberegister an gleicher E/A-Adresse (z.B. für bidirektionalen Datentransfer). und Statusregister – dient zum Austausch von Statusinformationen zwischen E/A-Baustein und CPU (z.B. Verfügbarkeit eines neuen Eingabewertes im Eingaberegister, Ausgabegerät hat Zeichen aus Ausgaberegister gelesen) – E/A-Baustein setzt/löscht entsprechende Bits im Statusregister selbständig – Abfrage des Statusregisters von CPU in einer Schleife („Polling“) • die vier wichtigsten E/A-Bausteine (programmierbarer Timer, parallele Schnittstelle, asynchrone serielle Schnittstelle, A/D- Wandler) sollen hier kurz vorgestellt werden ... Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 6 Programmierbarer Timer • typischer Aufbau (aus 68HC11): – interner 16-Bit Zähler mit einem vorgeschalteten programmierbaren Frequenzteiler („prescaler“) – 16-Bit Komparator(en) mit ladbaren 16-Bit Register(n) – 16-Bit Latch(es) – Interrupt-Logik mit lesbarem Flag-Register sowie Mask-Register zur Maskierung nicht benötigter Interrupts • drei Arbeitsmodi: – „input capture“: Festhalten des aktuellen Zählerstands im Latch bei Signal – „output compare“ : Setzen eines Signals bei Erreichen eines Zählerstands – „overflow“ : Generieren eines Interrupts bei Zählerüberlauf Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 7 Parallele Schnittstelle • typischer Aufbau (aus 68HC11): • Eigenschaften: – uni- oder bidirektionale Ports; E/A-Pins zumeist mit Funktionen anderer Schnittstellen kombiniert – Ausgabe erfolgt durch Beschreiben des „output register“ – bidirektionaler Port hat neben den Datenregistern ein zusätzliches Richtungsregister („data direction register“), dessen i-tes Bit die Richtung für das i-te E/A-Bit angibt (z.B. 0=Eingabe, 1=Ausgabe) – über optionalen Strobe-Eingang wird Zeitpunkt des Einlesens in Eingabe- register („input latch“) festgelegt Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 8 Asynchrone serielle Schnittstelle • zwei gebräuchliche Bezeichnungen: – UART = „Universal Asynchronous Receiver Transmitter“, – SCI = „Serial Commmunication Interface“ • bidirektionaler Betrieb („full-duplex“) mit festem Format, i.a. 1 Start-Bit (stets 0), 8 Daten-Bits, 1 Stop-Bit (stets 1) • je ein 10-Bit Schieberegister für Senden („Transmit“, „Tx“) und Empfangen („Receive“, „Rx“) • Frequenz („baud rate“), identisch für beide Richungen, typischerweise im Bereich von 75 bis 76800 Baud (Bit/Sek.) durch programmierbares Baudratenregister einstellbar • separate Sende- und Empfangsregister („TxDR“, „RxDR“) • Steuerung über Signale („TxDR Empty“, „Transmit Complete“, „RxDR Full“, „Rx Idle“) mittels Polling oder Interrupt Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 9 Asynchrone serielle Schnittstelle (Forts.) • typischer Aufbau (aus 68HC11): • Statussignale: – TDRE („TxDR Empty“) – TC („Transmit Complete“) – RDRF („RxDR Full“) – IDLE („Rx line idle“) – OR („Overrun Error“) – NF („Noise Error Flag“) – FE („Framing Error“) • Kontrollsignale: – TE/RE („Tx/Rx Enable“) – TIE („TDRE Interrupt Enable“) – TCIE („TC Interrupt Enable“) – RIE („RDRF Interrupt Enable“) – ILIE („Idle Interrupt Enable“) Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 10 A/D-Wandler • Umwandlung eines analogen Signals in einen digitalen Wert an bestimmten Abtastzeitpunkten • Eingangsspannung V aus endlichem Intervall [VL, VH] • typischer Aufbau (aus 68HC11): – Auflösung: 8 Bit – 2 Referenzspannungen nötig (VRL ® $00, VRH ® $FF) – mehrere Kanäle Vi über analogen Multiplexer wählbar – Genauigkeit: ±1 Bit – sukzessive Approximation in 8 Schritten – Kontrollregister mit Signal CCF („Conversion Complete Flag“) Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 11 Beispiel: Motorola 68HC11 8-Bit Mikrocontroller mit • CPU ähnlich Motorola 6809 • HCMOS-Technologie, maximale Taktfrequenz: 3 bis 5 MHz • Speicher je nach Modell: • 0, 256, 512 oder 768 Byte RAM • 0, 4, 12 oder 20 Kbyte ROM • 0, 512 Byte oder 2KByte EEPROM • Integrierte E/A-Bausteine: • 16-Bit Timer: 3(4) ´ „input capture“, 5(4) ´ „output capture“ (Port A) • serielle Schnittstellen: SCI, SPI (Port D) • 8-Kanal 8-Bit A/D-Wandler (Port E) • 8-Bit Puls-Akkumulator (Port A • bis zu 38 parallele E/A-Leitungen (16 ´ bidirektional, 11 ´ nur Eingabe, 11 ´ nur Ausgabe, Ports A bis E) Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 12 Beispiel: Motorola 68HC11 (Forts.) Aufbau: Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 13 Beispiel: Motorola 68HC11 (Forts.) • 4 Arbeitsmodi, wählbar durch MODB MODA Arbeitsmodus Beschaltung der externen Ein- 1 0 „single chip“ gabeleitungen MODA, MODB: 1 1 „expanded“ 0 0 „bootstrap“ 0 1 „special test“ • im „single chip“ Modus stehen alle 5 Ports für E/A-Leitungen zur Verfügung • im „extended“ Modus arbeiten Port B und Port C als Adress- und Datenbus im Multiplexbetrieb: • bei AS=1 wird über beide Ports eine 16-Bit Adresse ausgegeben • bei AS=0 wird über Port C ein 8-Bit Datenwort geschrieben/gelesen (Richtung wird über Signal R/W festgelegt) • im „bootstrap“ Modus wird nach Reset die serielle Schnittstelle initialisiert und hierüber ein Programm in das RAM geladen Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 14 Beispiel: Motorola 68HC11 (Forts.) Speichermodell (von 68HC11E2): Technische Informatik II, WS 2001/02 Kapitel 1.4 : Mikrocontroller A. Strey, Universität Ulm 15 Beispiel: Motorola 68HC11 (Forts.) Speichermodell (Forts.): • Zugriff auf alle Register der vorhandenen E/A-Bausteine über einen 64-Byte Registerblock • Startadresse von RAM, EEPROM und Registerblock in 4 Kbyte Schritten beliebig verschiebbar • statisches RAM behält im Standby sämtliche Informationen – im STOP-Modus (d.h. nach Abschaltung des Prozessortaktes durch Ausführung einer STOP-Instruktion) – im WAIT-Modus (d.h. nach Anhalten
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