DOCSLIB.ORG

Pipelining I

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Pipelining I University of Central Florida EEL 4768 Predication Prof. Mark Heinrich School of Electrical Engineering and Computer Science [email protected] Announcements . Lab 4 rubric in place and being actively graded . Lab 5 due Today • Lab sections as normally scheduled this week . HW #4 is posted, due Tuesday December 1st . Today • Predication • Intel IA-64 Architecture UCF EEL 4768 — Computer Architecture Increasing ILP . We’ve seen several compiler techniques to increase ILP • Loop unrolling • Software pipelining • Trace scheduling . But gains are limited if branch behavior unknown . Can we do something besides hw speculation? . Want a set of techniques that always increase ILP • Conditional moves • Predication UCF Conditional Instructions . Have an instruction refer to a condition • If condition is TRUE, execute instruction • If condition is FALSE, instruction is a NOP . Many architectures include conditional move instructions • Alpha, MIPS, PowerPC, SPARC • Pentium Pro -- (only user insts added between P5 and P6) . Conditional move moves a value from one register to another • Only if the condition is TRUE . Can use conditional moves to completely eliminate branches UCF Conditional Move Example . If (A==0) S=T; . Assume r1, r2, r3 hold the latest values of A,S,T… . Code without conditional move: . bnez r1, L . mov r2, r3 . L: . This entire fragment can be replaced with 1 instruction • cmovz r2, r3, r1 ; executed only if r1==0 . Control dependence is converted into a data dependence • Dependence can be resolved later in the pipeline (WB) • Have to maintain the conditions! • Another register file port? UCF Using Conditional Instructions . Can use conditional instructions to improve schedule • Schedule time-critical instructions into idle slots . lw r1,40(r2) add r3,r4,r5 . nop add r6,r3,r7 . beqz r10,L nop . lw r8,20(r10) nop . lw r9,0(r8) nop . 2nd load after branch depends on 1st, branch protects following load (don’t want to load if r10 is 0) . Can imagine a conditional load instruction that loads unless a third operand is 0… UCF Using Conditional Instructions II . Schedule with the conditional load: . lw r1,40(r2) add r3,r4,r5 . lwc r8,20(r10),r10 add r6,r3,r7 . beqz r10,L nop . lw r9,0(r8) nop . Improves performance by eliminating the stall and scheduling the data dependence . If compiler mispredicts branch, instruction will have no effect • Conditional load is speculative • Have to worry about exceptions – Above, incorrect execution may cause fatal exception • In general, conditional instructions have restrictions UCF Predication . Intel IA-64 architecture uses full predication • Every register-writing instruction can be conditional • Has 64 1-bit predicate registers • Estimates you lose 20-30% in branch mispredictions • Mahlke et al. claim can remove 50% of branches – And 40% of the mispredictions! . Idea: Since branches chop up ILP opportunity • Execute both sides of the branch! • Fill available slots with useful work • Tag each instruction with a predicate condition • Instruction commits only if predicate is true • Can combine predicates (make compound predicates) UCF cmp Predication Example then cmp P1 P2 else P1 P2 P1 P2 . Removes branches • Executes multiple paths simultaneously . Increases performance by exposing parallelism • Reduces critical path • Better utilization of wide machines UCF Combining Predicates p1, p2 (p2) p3,p4 p2&p3 p2&p4 (p3)… (p4)… . Predicates can be combined to predicate many if-then-else levels • This is difficult to do with simple conditional instructions • Intel cites study – cmove: 39% more instructions, 23% worse performance UCF Limitations of Conditional Instructions . Is predication really a good idea? • Open question (Intel hoped so) . Potential disadvantages and limitations • Conditional instructions that are annulled (predicate is false) still take execution time and occupy a potential issue slot. There is “zero cost” only if potential instruction fills an otherwise idle slot • Need swanky compiler technology • Compound predicates must be computed (more slots) • Full benefits of predication still require speculation • Conditional instructions may have a speed penalty compared with unconditional insts (lower clock rate?) • If branch prediction accuracy is high, can be better to be greedy and not execute both sides of every branch • Room for multithreading? UCF Intel/HP EPIC Architecture . EPIC (Explicitly Parallel Instruction Computing) • Similar philosophy to VLIW • Tries to overcome VLIW limitations . IA-64 is the ISA, Intel now calls Intel Itanium Architecture • As opposed to IA-32 (x86) in Pentium line • HP, Compaq (Alpha), and SGI (MIPS) all signed on . Itanium (Merced), and Itanium II (McKinley) • Itanium III (Madison) (2003) 410 million transistors! • Itanium IV (Montecito) 2006, dual-core CMP • latest version from Intel (Montvale) 2007 (another 2010 – Tukwila) . Intel produced x86-64 Xeon in 2004… UCF Itanium Characteristics . Explicitly parallel • ILP encoded in machine binary • Compiler looks beyond basic block scheduling . Advanced ILP techniques • Full predication • ISA support for control and data speculation • HW support for SW pipelining (modulo scheduling) . IA-32 hardware support . Massive hardware resources • Lots of FUs, tons of registers UCF Instruction Format . 3 instructions packaged in 128-bit bundles • Instructions are 41 bits each • 5-bit template at the end of each bundle . Template bits encode dependences • Both within (using stops) and between bundles • Also identify type of packet to help decode • More efficient and flexible than fixed VLIW format . Each instruction • Has a 6-bit field specifying 1 of 64 predicate registers • Has a max of 3 7-bit register specifiers UCF Itanium Architecture Features . 128 integer registers, 128 FP registers • 32 fixed, 96 “rotating” • Int registers are 65 bits! (NaT bit, later) . 64 predicate registers • 16 fixed, 48 “rotating” . Register stack on function calls • Similar to SPARC’s register windows . Multi-way branches (more than 1 branch unit) . Parallel compares (AND, OR, ANDOR) UCF Control Speculation Traditional Architectures IA-64 ld.s instr 1 instr 1 instr 2 . instr 2 br Barrier br Load chk.s use use Allows elevation of load, even above a branch . Improve memory latency by speculation at compile time . Defer exceptions by setting NaT (bit 65) • ld.s sets NaT, chk.s checks it, branches to recovery code UCF Hoisting Uses as Well IA-64 ld.s ld.s instr 1 instr 1 instr 2 instr 2 uses br br Recovery code chk.s chk.s ld use (Home Block) uses br home . Uses of speculative loads can execute speculatively • Distinguishes speculation from simple prefetch . NaT propagates down the dependent inst chain • Single chk.s instruction handles recovery UCF Data Speculation Traditional Architectures IA-64 instr 1 ld8.a instr 2 instr 1 . instr 2 Store(*) Barrier st8 Load (*) ld.c use use . Compiler can hoist load prior to preceding, possibly conflicting store . ALAT (Advanced Load Address Table) is used to check address of every store in-between UCF Hoisting Uses (again) ld8.a ld8.a instr 1 instr 1 use instr 2 instr 2 st8 st8 Recovery code ld.c chk.a ld8 use uses br home . Can also hoist uses past dependent store . chk.a jumps to recovery code if mis-speculation UCF Rotating Registers . Instructions contain “virtual” register number • Rotating Register Base (RRB) + VRN = PRN • Int and FP regs 32-127 can rotate (each has RRB) . Predicate registers can also rotate . Avoids code expansion from unrolling loops and code explosion from prologue/epilogue • Fewer cache misses • Can now SW pipeline small loops with unknown number of iterations (typical in integer code) UCF Itanium II Implementation (McKinley) . 0.18u process, 220 million transistors • Intel announced 65nm process . 10-stage in-order pipe, 1 GHz • Executes 2 bundles/CLK • 11 issue ports, 6 integer ALUs, 2 LD & 2 ST per cycle . Caches • L1 – 2 16KB, 1 cycle • L2 – 256KB, 5 cycles • L3 – 3MB, 12 cycles on chip! . Addressing • 50-bit PA, 64-bit VA UCF Itanium “Tukwila” (2008, 2009, 2010) . Intel data from 4/2008: . 4 cores . 6MB $/core, 24MB $ total . ~2.0 GHz . 698mm2 in 65nm CMOS!!!!! . 170W . Over 2 billion transistors UCF Itanium Sales UCF Itanium Reception . EPIC Fail in the marketplace, initial delays and underperformance . “Unobtanium” . “The Itanium approach … was supposed to be so terrific—until it turned out that the wished-for compilers were basically impossible to write.” – Donald Knuth . The “Itanic”. Huge monetary investment – quick demise . “…one of the great fiascos of the last 50 years” – John C. Dvorak • “The Macintosh uses an experimental pointing device called a ‘mouse’. There is no evidence that people want to use these things. I don’t want one of these new fangled devices.” . In 1987 IBM took its ball and went home, and developed the PS/2 • The world did not follow and stuck with cheap PC clones • IBM never recovered its position in the PC industry… UCF AMD Hammer Family . “The other white meat” • AMD calls architecture x86-64 • Released in 2003 • Why bother with all this EPIC stuff? • “Biggie” size it! . Extend x86 registers to 64-bits • Automatic backward compatibility to IA-32 . Two instances • Clawhammer (256KB L2) and Sledgehammer (1MB) • Much like P4 (w/o HT) but with integrated MC and better MP support UCF .
Load more

Recommended publications
  • Introduction to the Poulson (Intel 9500 Series) Processor Openvms Advanced Technical Boot Camp 2015 Keith Parris / September 29, 2015
    Introduction to the Poulson (Intel 9500 Series) Processor OpenVMS Advanced Technical Boot Camp 2015 Keith Parris / September 29, 2015 © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Information on Poulson from Intel’s ISSCC Paper © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Poulson information from Intel’s ISSCC Paper http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-poulson-isscc-paper.pdf 3 © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Poulson information from Intel’s ISSCC Paper http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-poulson-isscc-paper.pdf 4 © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Poulson information from Intel’s ISSCC Paper http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-poulson-isscc-paper.pdf 5 © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Poulson information from Intel’s ISSCC Paper • Intel presented a paper on Poulson at the International Solid-State Chips Conference (ISSCC) in July 2011. From this, we learned: • Poulson would be in a 32 nm process (2 process generations ahead from Tukwila, which was at 65 nm, skipping the 45 nm process) • The socket would be compatible with Tukwila • Poulson would have 8 cores, of a brand new core design • The front end (instruction fetch) would be decoupled from the back end (instruction execution) • Poulson could execute and retire as many as 12 instructions per cycle, double Tukwila’s 6 instructions http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-poulson-isscc-paper.pdf 6 © Copyright 2015 Hewlett-Packard Development Company, L.P.
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • A 65 Nm 2-Billion Transistor Quad-Core Itanium Processor
    18 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 A 65 nm 2-Billion Transistor Quad-Core Itanium Processor Blaine Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul Gronowski, Dan Krueger, Charles Morganti, and Steve Troyer Abstract—This paper describes an Itanium processor imple- mented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105 C. High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s. Index Terms—65-nm process technology, circuit design, clock distribution, computer architecture, microprocessor, on-die cache, voltage domains. I. OVERVIEW Fig. 1. Die photo. HE next generation in the Intel Itanium processor family T code named Tukwila is described. The 21.5 mm by 32.5 mm die contains 2.05 billion transistors, making it the first two billion transistor microprocessor ever reported. Tukwila combines four ported Itanium cores with a new system interface and high speed serial interconnects to deliver greater than 2X performance relative to the Montecito and Montvale family of processors [1], [2]. Tukwila is manufactured in a 65 nm process with 8 layers of copper interconnect as shown in the die photo in Fig. 1. The Tukwila die is enclosed in a 66 mm 66 mm FR4 laminate package with 1248 total landed pins as shown in Fig.
    [Show full text]
  • Poulson: an 8 Core 32 Nm Next Generation Intel* Itanium* Processor
    Poulson: An 8 Core 32 nm Next Generation Intel® Itanium® Processor Steve Undy Intel® 1 I NTEL CONFIDENTIAL This slide MUST be used with any slides removed from this presentation Legal Disclaimer • INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLI ED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR I MPLI ED WARRANTY, RELATING TO SALE AND/ OR USE OF INTEL® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTI CULAR PURPOSE, MERCHANTABI LI TY, OR I NFRI NGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RI GHT. I NTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. • Intel may make changes to specifications and product descriptions at any time, without notice. • Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. • Configurations: [describe config + what test used + who did testing]. For more information go to http://www.intel.com/performance • Intel does not control or audit the design or implementation of third party benchmarks or Web sites referenced in this document.
    [Show full text]
  • Intel Developer Forum Day 1 News Disclosures from Shanghai
    Intel Corporation 2200 Mission College Blvd. P.O. Box 58119 Santa Clara, CA 95052-8119 News Fact Sheet CONTACTS: Claudine Mangano George Alfs Connie Brown 408-765-0146 408-219-7588 503-791-2367 [email protected] [email protected] [email protected] INTEL DEVELOPER FORUM DAY 1 NEWS DISCLOSURES FROM SHANGHAI April 2, 2008: Intel Corporation is holding its Intel Developer Forum in Shanghai on April 2-3. Below are brief summaries of each executive’s Day 1 keynote speech and news highlights. Anand Chandrasekher, “The Heart of a New Generation” Intel Senior Vice President and General Manager, Ultra Mobility Group Describing how the Internet continues to grow and flourish globally, Chandrasekher said that personal mobility is a key catalyst driving people to embrace the Internet in new places and ways. Chandrasekher formally introduced five Intel® Atom™ processors (formerly codenamed “Silverthorne”) and Intel Centrino® Atom™ processor technology for Mobile Internet Devices (MIDs), outlined a series of innovations in the new platform and highlighted the growing momentum in the MID software and device ecosystem. Also covered were the benefits of the new Atom Microarchitecture, including performance features, Internet and software compatibility, and the drastic reductions that Intel has made in power and packaging to achieve this new technology platform. Chandrasekher also offered insight into the company’s future silicon roadmap. Intel Launches Centrino Atom Processor Technology – Chandrasekher introduced Intel Centrino Atom Processor Technology, the company’s first-generation low-power platform for MIDs designed to enable the best Internet experience in a device that fits in your pocket.
    [Show full text]
  • Intel® Processor Architecture
    Intel® Processor Architecture January 2013 Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Agenda •Overview Intel® processor architecture •Intel x86 ISA (instruction set architecture) •Micro-architecture of processor core •Uncore structure •Additional processor features – Hyper-threading – Turbo mode •Summary Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. 2 Intel® Processor Segments Today Architecture Target ISA Specific Platforms Features Intel® phone, tablet, x86 up to optimized for ATOM™ netbook, low- SSSE-3, 32 low-power, in- Architecture power server and 64 bit order Intel® mainstream x86 up to flexible Core™ notebook, Intel® AVX, feature set Architecture desktop, server 32 and 64bit covering all needs Intel® high end server IA64, x86 by RAS, large Itanium® emulation address space Architecture Intel® MIC accelerator for x86 and +60 cores, Architecture HPC Intel® MIC optimized for Instruction Floating-Point Set performance Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. 3 Itanium® 9500 (Poulson) New Itanium Processor Poulson Processor • Compatible with Itanium® 9300 processors (Tukwila) Core Core 32MB Core Shared Core • New micro-architecture with 8 Last Core Level Core Cores Cache Core Core • 54 MB on-die cache Memory Link • Improved RAS and power Controllers Controllers management capabilities • Doubles execution width from 6 to 12 instructions/cycle 4 Intel 4 Full + 2 Half Scalable Width Intel • 32nm process technology Memory QuickPath Interface Interconnect • Launched in November 2012 (SMI) Compatibility provides protection for today’s Itanium® investment Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation.
    [Show full text]
  • Impact of the New Generation of X86 on the Server Market
    Impact of the New Generation of x86 on the Server Market Gartner RAS Core Research Note G002012320, George J. Weiss, Jeffrey Hewitt, 3 June 2010, R3598 07042011 Intel and OEMs have driven performance and reliability of the Intel Xeon 7500 processor series (code-named Nehalem-EX) to a level overlapping what Gartner judges to be about 80% of the RISC/Itanium function/feature set, but at a much lower price point. The result will cause increased server technology consolidation toward a bipolar distribution: x86-based platforms and one primary market-share-leading RISC technology (IBM Power), complementing the prevailing legacy of mainframes. Key Findings • A bipolar technology distribution of one strong RISC (Power) and x86 will drive at least 70% to 80% of the market’s total revenue, while other technologies subsist with minor single-digit revenue share; beyond this decade, a unipolar market will exist in which x86 technology becomes the standard, predominant server technology. • Unix has receded by $4 billion in the past three years. Migrations from Unix to Linux or Windows continue, according to Gartner client discussions. • Users continue to optimize costs (such as through virtualization, lower hardware costs, open-source software and cloud computing) primarily on x86. • Of the three non-x86 technologies, IBM’s has had a recent track record of sustained market share growth. Recommendations • Calculate an approximate x86 total cost of ownership (TCO) equivalence or line item cost analysis for comparison as if these applications were to be hosted on x86 for similar performance/availability, when considering Unix upgrades. • Make the comparison to an approximately equivalent x86 configuration when evaluating price quotes.
    [Show full text]
  • Static Scheduling, VLIW, EPIC & Speculation Beating the IPC=1
    Static Scheduling, VLIW, EPIC & Speculation Today’s topics: HW support for better compiler scheduling VLIW/EPIC idea & IPF example School of Computing 1 University of Utah CS6810 Beating the IPC=1 Asymptote • Superscalar . static/compiler scheduled » common in embedded space MIPS & ARM . dynamic scheduled » HW scheduling via scoreboard/Tomasulo approach • VLIW . long instruction word contains set of independent ops . key – compiler schedule and hazard detection (εδ adv.) » each slot goes to a particular type of XU • similar to reservation station role . problem in high performance practice » need to be conservative w.r.t. run time activities • data dependent branch predicate » fix – add some HW to make less conservative but probable choice School of Computing 2 University of Utah CS6810 Page 1 VLIW History • As usual it’s not new . late 60’s early 70’s – microcode » same idea, different granularity . 80’s (textbook inaccurate on this) » Cydrome Cydra-5 (Rau/UIUC) & Multiflow (Fisher/Yale) • mini-super segment (Cray like performance on a budget) • killer micro ate them and the companies cratered • both Rau and Fisher go to HP to develop PA-WW – note both were compiler types (Fisher inspired by dataflow geeks) . 90’s » HP wants out of process business, Intel wants a server line » HP & Intel jointly develop and produce Itanium • 2001 first release of “Merced” & IA-64 . Now » AMD shocks x86 land w/ 64-bit architecture at MPF 2000 » poor IA-64 integer performance forces Intel to follow suit » IA-64 IPF still happening • now all Intel but “Itanic” problems persist School of Computing 3 University of Utah CS6810 “Itanic” • Interesting quotes: .
    [Show full text]
  • Intel's Core 2 Family
    Intel’s Core 2 family - TOCK lines II Nehalem to Haswell Dezső Sima Vers. 3.11 August 2018 Contents • 1. Introduction • 2. The Core 2 line • 3. The Nehalem line • 4. The Sandy Bridge line • 5. The Haswell line • 6. The Skylake line • 7. The Kaby Lake line • 8. The Kaby Lake Refresh line • 9. The Coffee Lake line • 10. The Cannon Lake line 3. The Nehalem line 3.1 Introduction to the 1. generation Nehalem line • (Bloomfield) • 3.2 Major innovations of the 1. gen. Nehalem line 3.3 Major innovations of the 2. gen. Nehalem line • (Lynnfield) 3.1 Introduction to the 1. generation Nehalem line (Bloomfield) 3.1 Introduction to the 1. generation Nehalem line (Bloomfield) (1) 3.1 Introduction to the 1. generation Nehalem line (Bloomfield) Developed at Hillsboro, Oregon, at the site where the Pentium 4 was designed. Experiences with HT Nehalem became a multithreaded design. The design effort took about five years and required thousands of engineers (Ronak Singhal, lead architect of Nehalem) [37]. The 1. gen. Nehalem line targets DP servers, yet its first implementation appeared in the desktop segment (Core i7-9xx (Bloomfield)) 4C in 11/2008 1. gen. 2. gen. 3. gen. 4. gen. 5. gen. West- Core 2 Penryn Nehalem Sandy Ivy Haswell Broad- mere Bridge Bridge well New New New New New New New New Microarch. Process Microarchi. Microarch. Process Microarch. Process Process 45 nm 65 nm 45 nm 32 nm 32 nm 22 nm 22 nm 14 nm TOCK TICK TOCK TICK TOCK TICK TOCK TICK (2006) (2007) (2008) (2010) (2011) (2012) (2013) (2014) Figure : Intel’s Tick-Tock development model (Based on [1]) * 3.1 Introduction to the 1.
    [Show full text]
  • Montecito Overview
    Tukwila – a Quad-Core Intel® Itanium® Processor Eric DeLano Intel® Corporation 1 26 August 2008– HotChips 20, Copyright 2008 Intel Corporation Agenda • Tukwila Overview • Exploiting Thread Level Parallelism • Improving Instruction Level Parallelism • Scalability and Headroom • Power and Frequency management • Enterprise RAS and Manageability • Conclusion 26 August 2008 – HotChips 20, Copyright 2008 Intel Corporation 2 Intel® Itanium® Processor Family Roadmap Intel® Itanium® Processor Tukwila Poulson Kittson Generation Processor 9000, 9100 Series Quad Core (2 Ultra Parallel Highlights Dual Core Billion Transistors) Micro-architecture • 30MB On-Die Cache, Hyper- • 24MB L3 cache • Advanced multi-core Threading Technology architecture • Hyper-Threading • QuickPath Interconnect 9th Technology • Hyper-threading Itanium® • Dual Integrated Memory • Intel® Virtualization enhancements Product Controllers, 4 Channels New Technology • Instruction-level Technologies • Mainframe-Class RAS • Intel® Cache Safe advancements • Enhanced Virtualization Technology • 32nm process technology • Common chipset w/ Next • Lock-step data integrity • Large On-Die Cache Gen Xeon® processor MP technologies (9100 series) • New RAS features • Voltage Frequency Mgmt • DBS Power Management • Up to 2x Perf Vs 9100 • Compatible with Tukwila Technology (9100 series) Series* platforms Targeted Enterprise Business (Database, Business Intelligence, ERP, HPC, …) Segments Availability 2006-07 End 2008 Future Future Intel and the Intel logo are trademarks or registered trademarks
    [Show full text]
  • DCG) Platform Roadmap Data Center Group Marketing (DCGM
    NDA Data Center Group (DCG) Platform Roadmap Data Center Group Marketing (DCGM) WW32 2010 Intel Confidential—NDA Platform Roadmap 11 Legal Information • All products, computer systems, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. This document contains information on products in the design phase of development. • Results have been estimated based on internal Intel analysis and are provided for informational purposes only. Any difference in system hardware or software design or configuration may affect actual performance. • Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Click here for details • Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which processors support HT Technology, see here • Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/technology/turboboost. • No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application.
    [Show full text]
  • How Intel® Itanium®-Based Servers Are Changing the Economics of Mission-Critical Computing
    Mainframe Reliability on Industry-Standard Servers : How Intel® Itanium®-based Servers are Changing the Economics of Mission-Critical Computing Michael EISA Intel Strategic Initiatives Manager Europe, Middle East & Africa HP EMEA TSG 16th October, 2008 11 Business Challenges Mainframe Environment Costs – Lack of agility incurs cost in lost opportunity and business responsiveness – High cost levels for maintenance and support – Poor price/performance – Poor choice of software, high proprietary licensing cost – Lack of Open Systems severely restricts options – Limited skills availability with an ever shrinking pool of talent – Big server footprint with high power and cooling costs Recession fears hit IT budgets* CIO Agenda 2008: The challenges for the year ahead... “The state of the economy and its potential impact on IT budgets will be the key challenge for IT chiefs this year along with the ongoing war for tech talent, according to silicon.com's exclusive CIO Agenda 2008 survey” For notes and disclaimers, see legal information slide at end of this presentation. Source: (1) IDC QST Analysis, October 2006. (2,3) Supporting Performance Benchmarks, System Configurations, and System Pricing in backup. (4) IDC WW Unix Migration Model, 2006. (5) IDC Server Tracker Q4’07 022608. *http://www.silicon.com/research/specialreports/cio-agenda-2008/0,3800014530,39182131,00.htm 2 * Other names and brands may be claimed as the property of others. Copyright © 2008, Intel Corporation. Mainframe customers are moving to Itanium® HPHP AnnouncesAnnounces OverOver
    [Show full text]