Impact of the New Generation of X86 on the Server Market
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Introduction to the Poulson (Intel 9500 Series) Processor Openvms Advanced Technical Boot Camp 2015 Keith Parris / September 29, 2015
Introduction to the Poulson (Intel 9500 Series) Processor OpenVMS Advanced Technical Boot Camp 2015 Keith Parris / September 29, 2015 © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Information on Poulson from Intel’s ISSCC Paper © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Poulson information from Intel’s ISSCC Paper http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-poulson-isscc-paper.pdf 3 © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Poulson information from Intel’s ISSCC Paper http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-poulson-isscc-paper.pdf 4 © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Poulson information from Intel’s ISSCC Paper http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-poulson-isscc-paper.pdf 5 © Copyright 2015 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Poulson information from Intel’s ISSCC Paper • Intel presented a paper on Poulson at the International Solid-State Chips Conference (ISSCC) in July 2011. From this, we learned: • Poulson would be in a 32 nm process (2 process generations ahead from Tukwila, which was at 65 nm, skipping the 45 nm process) • The socket would be compatible with Tukwila • Poulson would have 8 cores, of a brand new core design • The front end (instruction fetch) would be decoupled from the back end (instruction execution) • Poulson could execute and retire as many as 12 instructions per cycle, double Tukwila’s 6 instructions http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-poulson-isscc-paper.pdf 6 © Copyright 2015 Hewlett-Packard Development Company, L.P. -
Multiprocessing Contents
Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References ............................................. -
A 65 Nm 2-Billion Transistor Quad-Core Itanium Processor
18 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 A 65 nm 2-Billion Transistor Quad-Core Itanium Processor Blaine Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul Gronowski, Dan Krueger, Charles Morganti, and Steve Troyer Abstract—This paper describes an Itanium processor imple- mented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105 C. High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s. Index Terms—65-nm process technology, circuit design, clock distribution, computer architecture, microprocessor, on-die cache, voltage domains. I. OVERVIEW Fig. 1. Die photo. HE next generation in the Intel Itanium processor family T code named Tukwila is described. The 21.5 mm by 32.5 mm die contains 2.05 billion transistors, making it the first two billion transistor microprocessor ever reported. Tukwila combines four ported Itanium cores with a new system interface and high speed serial interconnects to deliver greater than 2X performance relative to the Montecito and Montvale family of processors [1], [2]. Tukwila is manufactured in a 65 nm process with 8 layers of copper interconnect as shown in the die photo in Fig. 1. The Tukwila die is enclosed in a 66 mm 66 mm FR4 laminate package with 1248 total landed pins as shown in Fig. -
Poulson: an 8 Core 32 Nm Next Generation Intel* Itanium* Processor
Poulson: An 8 Core 32 nm Next Generation Intel® Itanium® Processor Steve Undy Intel® 1 I NTEL CONFIDENTIAL This slide MUST be used with any slides removed from this presentation Legal Disclaimer • INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLI ED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR I MPLI ED WARRANTY, RELATING TO SALE AND/ OR USE OF INTEL® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTI CULAR PURPOSE, MERCHANTABI LI TY, OR I NFRI NGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RI GHT. I NTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. • Intel may make changes to specifications and product descriptions at any time, without notice. • Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. • Configurations: [describe config + what test used + who did testing]. For more information go to http://www.intel.com/performance • Intel does not control or audit the design or implementation of third party benchmarks or Web sites referenced in this document. -
Intel Developer Forum Day 1 News Disclosures from Shanghai
Intel Corporation 2200 Mission College Blvd. P.O. Box 58119 Santa Clara, CA 95052-8119 News Fact Sheet CONTACTS: Claudine Mangano George Alfs Connie Brown 408-765-0146 408-219-7588 503-791-2367 [email protected] [email protected] [email protected] INTEL DEVELOPER FORUM DAY 1 NEWS DISCLOSURES FROM SHANGHAI April 2, 2008: Intel Corporation is holding its Intel Developer Forum in Shanghai on April 2-3. Below are brief summaries of each executive’s Day 1 keynote speech and news highlights. Anand Chandrasekher, “The Heart of a New Generation” Intel Senior Vice President and General Manager, Ultra Mobility Group Describing how the Internet continues to grow and flourish globally, Chandrasekher said that personal mobility is a key catalyst driving people to embrace the Internet in new places and ways. Chandrasekher formally introduced five Intel® Atom™ processors (formerly codenamed “Silverthorne”) and Intel Centrino® Atom™ processor technology for Mobile Internet Devices (MIDs), outlined a series of innovations in the new platform and highlighted the growing momentum in the MID software and device ecosystem. Also covered were the benefits of the new Atom Microarchitecture, including performance features, Internet and software compatibility, and the drastic reductions that Intel has made in power and packaging to achieve this new technology platform. Chandrasekher also offered insight into the company’s future silicon roadmap. Intel Launches Centrino Atom Processor Technology – Chandrasekher introduced Intel Centrino Atom Processor Technology, the company’s first-generation low-power platform for MIDs designed to enable the best Internet experience in a device that fits in your pocket. -
Intel® Processor Architecture
Intel® Processor Architecture January 2013 Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Agenda •Overview Intel® processor architecture •Intel x86 ISA (instruction set architecture) •Micro-architecture of processor core •Uncore structure •Additional processor features – Hyper-threading – Turbo mode •Summary Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. 2 Intel® Processor Segments Today Architecture Target ISA Specific Platforms Features Intel® phone, tablet, x86 up to optimized for ATOM™ netbook, low- SSSE-3, 32 low-power, in- Architecture power server and 64 bit order Intel® mainstream x86 up to flexible Core™ notebook, Intel® AVX, feature set Architecture desktop, server 32 and 64bit covering all needs Intel® high end server IA64, x86 by RAS, large Itanium® emulation address space Architecture Intel® MIC accelerator for x86 and +60 cores, Architecture HPC Intel® MIC optimized for Instruction Floating-Point Set performance Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. 3 Itanium® 9500 (Poulson) New Itanium Processor Poulson Processor • Compatible with Itanium® 9300 processors (Tukwila) Core Core 32MB Core Shared Core • New micro-architecture with 8 Last Core Level Core Cores Cache Core Core • 54 MB on-die cache Memory Link • Improved RAS and power Controllers Controllers management capabilities • Doubles execution width from 6 to 12 instructions/cycle 4 Intel 4 Full + 2 Half Scalable Width Intel • 32nm process technology Memory QuickPath Interface Interconnect • Launched in November 2012 (SMI) Compatibility provides protection for today’s Itanium® investment Software & Services Group, Developer Products Division Copyright © 2013, Intel Corporation. -
Cisco Systems, Inc. 2014 Annual Report
Cisco Systems, Inc. 2014 Annual Report Annual Report 2014 Letter to Shareholders To Our Shareholders, When we look back on fiscal 2014, we could describe to capture this opportunity. With this robust foundation, it as one of the most innovative years in Cisco’s history. we are able to provide our customers with an integrated, Through our innovation strategy of build, buy, partner, and network-centric architectural solution that not only solves integrate, we brought new architectures to market for the their IT challenges but also helps them achieve their desired next generation of networking, security, data center, and business outcomes. collaboration products and solutions, and we made bold Our vision is clear, and our strategy is working and has moves to help our customers capitalize on the changes in largely played out as we expected. In 2011, I said that the market. customers will view the network as the most strategic We managed our business well amid a great deal of change asset, not just in communications but also in IT and that this and a tough market. Our fiscal year began with several would enable us to become the number-one IT company. external headwinds, including the U.S. federal government I am more confident than ever that we can make that shutdown and the possibility of a U.S. default, combined aspiration a reality. with a significant slowdown in emerging countries. Even Innovation, Disruption, and Transformation with this backdrop, we ended fiscal 2014 with revenue of $47.1 billion, making it the second strongest year in our The pace of change being experienced in almost every history. -
1 Cloud Computing the Present of Cloud Computing
Outlines Cloud Computing: Past, Present, Introduction and Future The Past of Cloud Computing The Present of Cloud Computing The Future of Cloud Computing Ruay-Shiung Chang (張瑞雄) Department of Computer Science and Information Engineering Conclusions National Dong Hwa University (國立東華大學) November 4, 2010 “The distinction between past, present, and future is only a stubbornly persistent illusion” Albert Einstein 1 2 Introduction 3 4 1 Introduction Introduction Cloud computing in everything! Cloud computing=cloud+computing? There are many types of clouds! 5 6 Introduction Introduction Different angles have different opinions! The computer industry is the only industry that is more fashion-driven than women's fashion. ---Larry Ellision (Oracle CEO) Grid computing Cloud computing Utility computing Elastic comppguting Fabric computing Reconfigurable computing Social computing Volunteer computing SaaS (Software as a Service), PaaS, IaaS, … ASP (Application Service Provision) Data Center Co-location … 7 8 2 Introduction Introduction Oracle CEO talks about cloud computing Computer manufacturer Dell even tried to trademark the term "cloud computing", although its application was refused. But Dell got the domain name cloudcomputing.com, cloud-computing.com cloudcomputing.org (.net) is registered by r4l.com (待價而沽) cloud-computing.org (.net) (not used) thecloudcomputing.org (IEEE CC conference) 9 10 Introduction Introduction Who coined the phrase Cloud Computing? Who coined the phrase Cloud Computing? 11 12 3 Introduction Introduction 台灣翻譯成「雲端計算」 中華文化「雲端」的起源 大陸翻譯成「雲計算」 李白的詩「長相思二首之一」 那個高明? 長相思,在長安。絡緯秋啼金井闌, 有雲(servers)有端(access devices) 微霜淒淒簟色寒。孤燈不明思欲絕, 卷帷望月空長歎。美人如花隔雲端, 上有青冥之長天,下有淥水之波瀾。 天長地遠魂飛苦,夢魂不到關山難。 長相思,摧心肝。 We can’t see the cloud computing clearly yet. We can’t reach the cloud computing yet. -
Static Scheduling, VLIW, EPIC & Speculation Beating the IPC=1
Static Scheduling, VLIW, EPIC & Speculation Today’s topics: HW support for better compiler scheduling VLIW/EPIC idea & IPF example School of Computing 1 University of Utah CS6810 Beating the IPC=1 Asymptote • Superscalar . static/compiler scheduled » common in embedded space MIPS & ARM . dynamic scheduled » HW scheduling via scoreboard/Tomasulo approach • VLIW . long instruction word contains set of independent ops . key – compiler schedule and hazard detection (εδ adv.) » each slot goes to a particular type of XU • similar to reservation station role . problem in high performance practice » need to be conservative w.r.t. run time activities • data dependent branch predicate » fix – add some HW to make less conservative but probable choice School of Computing 2 University of Utah CS6810 Page 1 VLIW History • As usual it’s not new . late 60’s early 70’s – microcode » same idea, different granularity . 80’s (textbook inaccurate on this) » Cydrome Cydra-5 (Rau/UIUC) & Multiflow (Fisher/Yale) • mini-super segment (Cray like performance on a budget) • killer micro ate them and the companies cratered • both Rau and Fisher go to HP to develop PA-WW – note both were compiler types (Fisher inspired by dataflow geeks) . 90’s » HP wants out of process business, Intel wants a server line » HP & Intel jointly develop and produce Itanium • 2001 first release of “Merced” & IA-64 . Now » AMD shocks x86 land w/ 64-bit architecture at MPF 2000 » poor IA-64 integer performance forces Intel to follow suit » IA-64 IPF still happening • now all Intel but “Itanic” problems persist School of Computing 3 University of Utah CS6810 “Itanic” • Interesting quotes: . -
Intel's Core 2 Family
Intel’s Core 2 family - TOCK lines II Nehalem to Haswell Dezső Sima Vers. 3.11 August 2018 Contents • 1. Introduction • 2. The Core 2 line • 3. The Nehalem line • 4. The Sandy Bridge line • 5. The Haswell line • 6. The Skylake line • 7. The Kaby Lake line • 8. The Kaby Lake Refresh line • 9. The Coffee Lake line • 10. The Cannon Lake line 3. The Nehalem line 3.1 Introduction to the 1. generation Nehalem line • (Bloomfield) • 3.2 Major innovations of the 1. gen. Nehalem line 3.3 Major innovations of the 2. gen. Nehalem line • (Lynnfield) 3.1 Introduction to the 1. generation Nehalem line (Bloomfield) 3.1 Introduction to the 1. generation Nehalem line (Bloomfield) (1) 3.1 Introduction to the 1. generation Nehalem line (Bloomfield) Developed at Hillsboro, Oregon, at the site where the Pentium 4 was designed. Experiences with HT Nehalem became a multithreaded design. The design effort took about five years and required thousands of engineers (Ronak Singhal, lead architect of Nehalem) [37]. The 1. gen. Nehalem line targets DP servers, yet its first implementation appeared in the desktop segment (Core i7-9xx (Bloomfield)) 4C in 11/2008 1. gen. 2. gen. 3. gen. 4. gen. 5. gen. West- Core 2 Penryn Nehalem Sandy Ivy Haswell Broad- mere Bridge Bridge well New New New New New New New New Microarch. Process Microarchi. Microarch. Process Microarch. Process Process 45 nm 65 nm 45 nm 32 nm 32 nm 22 nm 22 nm 14 nm TOCK TICK TOCK TICK TOCK TICK TOCK TICK (2006) (2007) (2008) (2010) (2011) (2012) (2013) (2014) Figure : Intel’s Tick-Tock development model (Based on [1]) * 3.1 Introduction to the 1. -
Mellanox Technologies, Arista Networks, Lawrence Livermore National Laboratory, Sun Microsystems and System Fabric Works Demonst
Mellanox Technologies, Arista Networks, Lawrence Livermore National Laboratory, Sun Microsystems and System Fabric Works Demonstrate Lustre File System using Low Latency 10 Gigabit Ethernet at SC08 11/18/2008 Austin, Texas, Nov 18, 2008 - Mellanox® Technologies, Ltd. (NASDAQ: MLNX; TASE: MLNX), a leading supplier of semiconductor-based, server and storage interconnect products, today announced a multi-vendor 10 Gigabit Ethernet file system and storage infrastructure demonstration using a 10Gb/s Low Latency Ethernet (LLE) cluster network using Lustre™ technology for computational checkpointing and persistent visualization data storage. The demonstration includes the following vendor components: Mellanox - ConnectX EN 10 Gigabit Ethernet Adapters, Arista Networks - 7124 10 Gigabit Switches, Sun Microsystems - Lustre file system and Sun Fire™ X4540 storage server, System Fabric Works – software integration and demonstration deployment. “To maintain the cutting-edge R&D computing capabilities our scientists need to fulfill their national security missions, we look for the cost-effective technology solutions that best suit our unique computing environment,” said Mark Seager, Assistant Department Head for Advanced Technology of LLNL’s Computation Directorate. “Employing this kind of technology allows us to explore and develop the petascale computing capabilities vital to our future research endeavors and advances high performance computing.” “End-users are looking for improved application latency and performance for their compute intensive applications, -
Montecito Overview
Tukwila – a Quad-Core Intel® Itanium® Processor Eric DeLano Intel® Corporation 1 26 August 2008– HotChips 20, Copyright 2008 Intel Corporation Agenda • Tukwila Overview • Exploiting Thread Level Parallelism • Improving Instruction Level Parallelism • Scalability and Headroom • Power and Frequency management • Enterprise RAS and Manageability • Conclusion 26 August 2008 – HotChips 20, Copyright 2008 Intel Corporation 2 Intel® Itanium® Processor Family Roadmap Intel® Itanium® Processor Tukwila Poulson Kittson Generation Processor 9000, 9100 Series Quad Core (2 Ultra Parallel Highlights Dual Core Billion Transistors) Micro-architecture • 30MB On-Die Cache, Hyper- • 24MB L3 cache • Advanced multi-core Threading Technology architecture • Hyper-Threading • QuickPath Interconnect 9th Technology • Hyper-threading Itanium® • Dual Integrated Memory • Intel® Virtualization enhancements Product Controllers, 4 Channels New Technology • Instruction-level Technologies • Mainframe-Class RAS • Intel® Cache Safe advancements • Enhanced Virtualization Technology • 32nm process technology • Common chipset w/ Next • Lock-step data integrity • Large On-Die Cache Gen Xeon® processor MP technologies (9100 series) • New RAS features • Voltage Frequency Mgmt • DBS Power Management • Up to 2x Perf Vs 9100 • Compatible with Tukwila Technology (9100 series) Series* platforms Targeted Enterprise Business (Database, Business Intelligence, ERP, HPC, …) Segments Availability 2006-07 End 2008 Future Future Intel and the Intel logo are trademarks or registered trademarks