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PA-RISC 2.0 the Information Contained in This Document Is Subject to Change Without Notice PA-RISC 2.0 The information contained in this document is subject to change without notice. HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with furnishing, performance, or use of this material. Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is not furnished by Hewlett-Packard. This document contains proprietary information which is protected by copyright. All rights are reserved. No part of this document may be photocopied, reproduced, or translated to another language without the prior written consent of Hewlett-Packard Company. Copyright © 1995 by HEWLETT-PACKARD COMPANY Published by Prentice-Hall, Inc. A Simon & Schuster Company Englewood Cliffs, New Jersey 07632 Book Design: Suzanne Hayes Acknowledgements Special thanks to Martin Whittaker who was the impetus behind this book and provided leadership and direction at every turn and to Dale Morris and Jim Hall who contributed key sections. Many other folks at Hewlett-Packard provided critical information: among them Ruby Lee, and Jerry Huck. Personal thanks go to the usual suspects: Sean, Kyle, Ambrose, Marcella. Foreword “Everything should be made as simple as possible, but not simpler.” A. Einstein When the first PA-RISC systems were shipped in 1986, the architecture was clearly recognized as a break with the past, with regular, hardware-inspired instructions rather than variable, interpretive forms. But its simple instructions were somewhat richer than other RISC designs, providing basic support for operations on strings and other data types prevalent in commercial applications. This semantic richness, unusual in the RISC designs of the time, was a direct result of the breadth of markets for HP computers and the decision to optimize PA-RISC for the full range of technical and commercial applications. In the intervening years, PA-RISC has become the basis of a large family of computer systems, currently spanning a capacity range of over two orders of magnitude. As the product family has grown, the range of applications has also expanded geometrically. PA-RISC workstations now host applications which were once the province of supercomputers. Database servers now supply realtime streams of compressed video and audio. And PA-RISC has evolved to meet the demands for leadership performance in these emerging application domains. The purpose of a processor architecture is to define a stable interface which can efficiently couple multiple generations of software investment to successive generations of hardware technology. Stability and efficiency are the goals, and the range of software and hardware technologies expected during the architecture’s life determine the scope for which the goals must be achieved. The desired stability does not rule out change, but it does require that any evolution of the architecture contain the prior definition as a subset. This is the principle of “forward compatibility” which ensures that all prior software will continue to work on all later machinesa straightforward idea whose value to users is obvious. Over the last decade, PA-RISC has evolved in response both to significant changes in the nature of customer applications and to rapid advances in technology, particularly chip fabrication technology and compiler technology. Efficiency also has evident value to users, but there is no simple recipe for achieving it. Optimizing architectural efficiency is a complex search in a multidimensional space, involving disciplines ranging from device physics and circuit design at the lower levels of abstraction, to compiler optimizations and application structure at the upper levels. Because of the inherent complexity of the problem, the design of processor architecture is an iterative, heuristic process which depends upon methodical comparison of alternatives (“hill climbing”) and upon creative flashes of insight (“peak jumping”), guided by engineering judgement and good taste. To design an efficient processor architecture, then, one needs excellent tools and measurements for accurate comparisons when “hill climbing,” and the most creative and experienced designers for superior “peak jumping.” At HP, this need is met within a cross-functional team of about twenty designers, each with depth in one or more technologies, all guided by a broad vision of the system as a whole. Since the inception of PA-RISC, nearly fifty people have contributed directly to its definition as PA-RISC 2.0 Architecture iii members of the architecture team. With the generous support of colleagues and managers in their respective organizations, they have made careful measurements of application workloads, designed ingenious tools and methods to analyze data, created novel semantics and encodings, deliberated intently to hone the best cost-performance design, and crafted clear, unambiguous descriptions. It was my great privilege and pleasure to lead this team of talented designers, and it is their achievement which is documented in this book. Michael Mahon Principal Architect Hewlett-Packard August, 1995 iv PA-RISC 2.0 Architecture Contents Figures. ix Tables . xi Preface. xv Compatibility with PA-RISC 1 . xv PA-RISC 2.0 Enhancements . xv How This Book is Organized . xvii Conventions Used in This Book . xvii Instruction Notations . .xviii 1 Overview. .1-1 Traditional RISC Characteristics of PA-RISC . .1-1 PA-RISC - The Genius is in the Details . .1-2 A Critical Calculus: Instruction Pathlength. .1-2 Multimedia Support: The Precision Process Illustrated . .1-6 Integrated CPU . .1-7 Extensibility and Longevity. .1-9 System Organization . .1-10 2 Processing Resources . .2-1 Non-Privileged Software-Accessible Registers. .2-2 Privileged Software-Accessible Registers. .2-7 Unused Registers and Bits. .2-17 Data Types. .2-18 Byte Ordering (Big Endian/Little Endian) . .2-19 3 Addressing and Access Control . .3-1 Physical and Absolute Addressing . .3-1 Virtual Addressing. .3-5 Pointers and Address Specification . .3-6 Address Resolution and the TLB. .3-9 Access Control. .3-11 Page Table Structure . .3-15 Caches . .3-16 4 Control Flow . .4-1 Branching. .4-1 Nullification. .4-7 Instruction Execution. .4-7 Instruction Pipelining. .4-9 5 Interruptions . .5-1 Interrupt Classes . .5-1 Interruption Handling . .5-2 Instruction Recoverability . .5-3 Masking and Nesting of Interruptions . .5-4 Interruption Priorities. .5-4 Return from Interruption . .5-4 PA-RISC 2.0 Architecture v Interruption Descriptions . 5-5 6 Instruction Set Overview . 6-1 Computation Instructions . 6-1 Multimedia Instructions . 6-3 Memory Reference Instructions . 6-6 Long Immediate Instructions . 6-12 Branch Instructions . 6-13 System Control Instructions . ..
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