DOCSLIB.ORG

Uma Abordagem De Escalonamento Heterogêneo Preemptivo E Não Preemptivo Para Sistemas De Tempo Real Com Garantia Em Multiprocessadores

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Uma Abordagem De Escalonamento Heterogêneo Preemptivo E Não Preemptivo Para Sistemas De Tempo Real Com Garantia Em Multiprocessadores View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Repositório Institucional da UFSC UNIVERSIDADE FEDERAL DE SANTA CATARINA DEPARTAMENTO DE AUTOMAÇÃO E SISTEMAS Renan Augusto Starke UMA ABORDAGEM DE ESCALONAMENTO HETEROGÊNEO PREEMPTIVO E NÃO PREEMPTIVO PARA SISTEMAS DE TEMPO REAL COM GARANTIA EM MULTIPROCESSADORES Florianópolis 2012 Renan Augusto Starke UMA ABORDAGEM DE ESCALONAMENTO HETEROGÊNEO PREEMPTIVO E NÃO PREEMPTIVO PARA SISTEMAS DE TEMPO REAL COM GARANTIA EM MULTIPROCESSADORES Dissertação submetida ao programa de Pós- Graduação em Engenharia de Automação e Sistemas para a obtenção do Grau de Mestre em Engenharia de Automação e Sis- temas. Orientador: Rômulo Silva de Oliveira, Dr. Florianópolis 2012 Catalogação na fonte pela Biblioteca Universitária da Universidade Federal de Santa Catarina S795a Starke, Renan Augusto Uma abordagem de escalonamento heterogêneo preemptivo e não preemptivo para sistemas de tempo real com garantia em multiprocessadores [dissertação] / Renan Augusto Starke ; orientador, Rômulo Silva de Oliveira. - Florianópolis, SC, 2012. 200 p.: il., grafs., tabs. Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia de Automação e Sistemas. Inclui referências 1. Engenharia. de sistemas. 2. Automação. 3. Multiprocessadores. 4. Escalonamento. 5. Memória cache. I. Oliveira, Rômulo Silva de. II. Universidade Federal de Santa Catarina. Programa de Pós-Graduação em Engenharia de Automação e Sistemas. III. Título. CDU 621.3-231.2(021) Renan Augusto Starke UMA ABORDAGEM DE ESCALONAMENTO HETEROGÊNEO PREEMPTIVO E NÃO PREEMPTIVO PARA SISTEMAS DE TEMPO REAL COM GARANTIA EM MULTIPROCESSADORES Esta Dissertação foi julgada aprovada para a obtenção do Título de “Mestre em Engenharia de Automação e Sistemas”, e aprovada em sua forma final pelo programa de Pós-Graduação em Engenharia de Automação e Siste- mas. Florianópolis, 10 de fevereiro 2012. José Eduardo Ribeiro Cury, Dr. Coordenador Banca Examinadora: Rômulo Silva de Oliveira, Dr Presidente Alexandre José da Silva, MSc Carlos Barros Montez, Dr George Marconi de Araújo Lima, Ph.D AGRADECIMENTOS Agradeço ao meu orientador Rômulo Silva de Oliveira pela dedica- ção, incentivo, paciência e pelas ótimas sugestões quando o caminho parecia obscuro. Agradeço à minha família pela confiança e apoio dado no decorrer do curso. Em especial agradeço aos meus pais pelo acesso à uma educação de boa qualidade e íntegra. Agradeço também aos amigos do LTIC pela amizade, ajuda em corre- ções, compartilhamento e aprimoramento das ideias. Por fim agradeço a CAPES pelo apoio financeiro que tornou possível a realização deste trabalho. Aprender é a única coisa de que a mente nunca se cansa, nunca tem medo e nunca se arre- pende. Leonardo da Vinci RESUMO Sistemas de tempo real são sistemas onde o correto funcionamento não de- pende somente da resposta lógica correta, mas também do tempo no qual ela foi dada. Igualmente do ponto de vista lógico, a viabilidade temporal da aplicação deve ser determinada através de técnicas, como por exemplo análise do tempo de reposta. Este tipo de aplicação está cada vez mais pre- sente atualmente e a demanda de processamento é tamanha que necessita-se de processadores com múltiplos núcleos complexos. É perceptível que o de- senvolvimento dos multiprocessadores está muito mais avançado em relação às técnicas de análise de tais sistemas e, portanto, é evidente a necessidade de pesquisa com objetivo de promover maior confiabilidade e redução de su- perdimensionamentos. O objetivo deste trabalho é promover uma solução de escalonamento que considere a escalonabilidade em conjunto com a anali- sabilidade do código da aplicação. Atualmente, a pesquisa de sistemas de tempo real trata o problema do escalonamento isolado do problema de obten- ção do parâmetro do tempo de computação da tarefas (WCET – Worst Case Execution Time). Dependendo da arquitetura do processador, as premissas adotadas no cálculo do WCET são incompatíveis com as premissas de escalo- namento, o que gera uma contradição fundamental entre o cálculo do WCET e os algoritmos de escalonamento. A incompatibilidade das premissas pode ser ilustrada pela preempção em arquiteturas com memória cache, onde o cál- culo de WCET assume execução contínua da tarefa, o que não é verdade em grande parte dos algoritmos de escalonamento. Este trabalho propõe o uso de uma abordagem heterogênea em multiprocessadores onde parte dos nú- cleos operam em regime preemptivo e parte em regime não preemptivo para tentar lidar com as diferentes considerações sobre preempção. As análises realizadas mostram que existe vantagem em usar a abordagem heterogênea. Palavras-chave: tempo real, Worst Case Execution Time, multiprocessado- res, escalonamento. ABSTRACT Real-time systems are systems where the correct functioning depends not only on the logically correct response, but also the time when it was given. As the the logic functionality, the application response time could be analy- zed to determine the viability of a real-time system. This type of application is increasingly present today and the processing demand is such that complex multi-core processors are needed. It is noticeable that the development of multiprocessor is a long way ahead compared with the techniques of analy- sis of such systems and is therefore necessary researches to promote more reliability and to reduce over-specified systems. The objective of this work is to promote a solution that considers scheduling in conjunction with the analyzability of the application code. Currently, the real-time research consi- ders the scheduling problem isolated from the WCET (Worst Case Execution Time) problem. Depending on the processor architecture, the values obtai- ned by computing WCET are incompatible with the scheduling model which creates a fundamental contradiction between the assumptions of calculation of WCET and scheduling algorithms. This work proposes the use of a he- terogeneous approach where part of the multiprocessor cores operate under preemptive and part on a non-preemptive scheduling. The analysis shows that there are advantages using the heterogeneous approach. Keywords: real-time, Worst Case Execution Time, multiprocessors, schedu- ling. LISTA DE FIGURAS Figura 1 Técnicas de balanceamento de pipeline..................... 38 Figura 2 Exemplo de unificação de recursos de um pipeline.. 41 Figura 3 Exemplo de pipeline diversificado. 43 Figura 4 Exemplo de pipeline dinâmico.. 44 Figura 5 Relação e hierarquia de memória. 45 Figura 6 Interação entre cache e TLB. 50 Figura 7 Modelo padrão desenvolvido para análise estática de código (CULLMANN et al., 2010). 57 Figura 8 Exemplo de grafo de controle fluxo . 63 Figura 9 Exemplo de grafo de análise de pilha . 63 Figura 10 Exemplo de grafo de análise de tempo . 64 Figura 11 Grafo de fluxo de controle para o exemplo da tabela hash. 66 Figura 12 Grafo de pior tempo de execução da tabela hash.. 68 Figura 13 Grafo de utilização de pilha para exemplo da tabela hash. 69 Figura 14 Exemplo de anomalia temporal. 89 Figura 15 Exemplo de atrasos de cache direto e indireto. 96 Figura 16 Atraso de preempção da tarefa 1 sobre a tarefa 2. 98 Figura 17 Resumo das técnicas de inclusão de efeitos na cache no teste de escalonabilidade . 103 Figura 18 Diagrama de blocos do processador FreeScale MPC5668G (CULLMANN et al., 2010) . 106 Figura 19 Particionamento de um conjunto de tarefas T sob o mesmo regime de preempção. 112 Figura 20 Particionamento de um conjunto de tarefas T sob diferentes regimes de preempção. 112 Figura 21 Resultados do escalonamento não preemptivo. 128 Figura 22 Resultados do escalonamento preemptivo, g = 20% de Ci . 130 Figura 23 Resultados do escalonamento heterogêneo para 4 processado- res, g = 20% de Ci .................................................133 Figura 24 Resultados do escalonamento heterogêneo para 16 processa- dores, g = 20% de Ci .............................................. 134 Figura 25 Comparação entre particionamento homogêneo e heterogêneo para 4 processadores com g = 20% de Ci .............................135 Figura 26 Comparação entre particionamento homogêneo e heterogêneo para 16 processadores com g = 20% de Ci ........................... 136 Figura 27 Técnicas de balanceamento de pipeline (Apêndice). 155 Figura 28 Exemplo de unificação de recursos de um pipeline (Apêndice).159 Figura 29 Pipeline com inclusão de atalhos (Apêndice).. 163 Figura 30 Pipeline do i486 (a) e Pentium (b) (Apêndice). 165 Figura 31 Exemplo de pipeline diversificado (Apêndice).. 166 Figura 32 Exemplo de pipeline dinâmico (Apêndice). 167 Figura 33 Exemplo de pipeline superescalar (SEHN; LIPASTI, 2005) (Apêndice). 170 Figura 34 Exemplo de máquina de estados finitos para previsão de con- trole de fluxo (Apêndice). 172 Figura 35 Relação e hierarquia de memória (Apêndice).. 173 Figura 36 Propriedades da memória cache (Apêndice). 179 Figura 37 Interação entre cache e TLB (Apêndice). 185 Figura 38 Processamento escalar e vetorial de um supercomputador (Apên- dice). 192 Figura 39 Porções de trabalho vetorizado e sequencial (Apêndice). 193 Figura 40 Perfil de execução de um pipeline de N estágios (Apêndice). 194 Figura 41 Perfil de execução de um pipeline com flutuação (Apêndice). 194 Figura 42 Modelo de um pipeline com flutuação (Apêndice). 196 LISTA DE TABELAS Tabela 1 Especificação das instruções aritméticas/ponto flutuante.. 39 Tabela 2 Especificação das instruções de acesso a memória. 40 Tabela 3 Especificação das instruções controle
Load more

Recommended publications
  • Computing :: Operatingsystems :: DOS Beyond 640K 2Nd
    DOS® Beyond 640K 2nd Edition DOS® Beyond 640K 2nd Edition James S. Forney Windcrest®/McGraw-Hill SECOND EDITION FIRST PRINTING © 1992 by James S. Forney. First Edition © 1989 by James S. Forney. Published by Windcrest Books, an imprint of TAB Books. TAB Books is a division of McGraw-Hill, Inc. The name "Windcrest" is a registered trademark of TAB Books. Printed in the United States of America. All rights reserved. The publisher takes no responsibility for the use of any of the materials or methods described in this book, nor for the products thereof. Library of Congress Cataloging-in-Publication Data Forney, James. DOS beyond 640K / by James S. Forney. - 2nd ed. p. cm. Rev. ed. of: MS-DOS beyond 640K. Includes index. ISBN 0-8306-9717-9 ISBN 0-8306-3744-3 (pbk.) 1. Operating systems (Computers) 2. MS-DOS (Computer file) 3. PC -DOS (Computer file) 4. Random access memory. I. Forney, James. MS-DOS beyond 640K. II. Title. QA76.76.063F644 1991 0058.4'3--dc20 91-24629 CIP TAB Books offers software for sale. For information and a catalog, please contact TAB Software Department, Blue Ridge Summit, PA 17294-0850. Acquisitions Editor: Stephen Moore Production: Katherine G. Brown Book Design: Jaclyn J. Boone Cover: Sandra Blair Design, Harrisburg, PA WTl To Sheila Contents Preface Xlll Acknowledgments xv Introduction xvii Chapter 1. The unexpanded system 1 Physical limits of the system 2 The physical machine 5 Life beyond 640K 7 The operating system 10 Evolution: a two-way street 12 What else is in there? 13 Out of hiding 13 Chapter 2.
    [Show full text]
  • Communication Theory II
    Microprocessor (COM 9323) Lecture 2: Review on Intel Family Ahmed Elnakib, PhD Assistant Professor, Mansoura University, Egypt Feb 17th, 2016 1 Text Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey, Prentice Hall, 2009 2. Assembly Language for x86 processors, 6th edition, K. R. Irvine, Prentice Hall, 2011 References: 1. Computer Architecture: A Quantitative Approach, 5th edition, J. Hennessy, D. Patterson, Elsevier, 2012. 2. The 80x86 Family, Design, Programming and Interfacing, 3rd edition, Prentice Hall, 2002 3. The 80x86 IBM PC and Compatible Computers, Assembly Language, Design, and Interfacing, 4th edition, M.A. Mazidi and J.G. Mazidi, Prentice Hall, 2003 2 Lecture Objectives 1. Provide an overview of the various 80X86 and Pentium family members 2. Define the contents of the memory system in the personal computer 3. Convert between binary, decimal, and hexadecimal numbers 4. Differentiate and represent numeric and alphabetic information as integers, floating-point, BCD, and ASCII data 5. Understand basic computer terminology (bit, byte, data, real memory system, protected mode memory system, Windows, DOS, I/O) 3 Brief History of the Computers o1946 The first generation of Computer ENIAC (Electrical and Numerical Integrator and Calculator) was started to be used based on the vacuum tube technology, University of Pennsylvania o1970s entire CPU was put in a single chip. (1971 the first microprocessor of Intel 4004 (4-bit data bus and 2300 transistors and 45 instructions) 4 Brief History of the Computers (cont’d) oLate 1970s Intel 8080/85 appeared with 8-bit data bus and 16-bit address bus and used from traffic light controllers to homemade computers (8085: 246 instruction set, RISC*) o1981 First PC was introduced by IBM with Intel 8088 (CISC**: over 20,000 instructions) microprocessor oMotorola emerged with 6800.
    [Show full text]
  • Intel: 3002, 4004, 4040, 8008, 8080, 8085, MCS48, MCS51, 80X86 up To
    Intel: 3002, 4004, 4040, 8008, 8080, 8085, MCS-48, MCS-51, 80x86 up to 80386, 80860, 80960, SA-110 Intel 80486: 80486, 80486 overdrive Intel Pentium: Pentium, Pentium MMX, Pentium Overdrive, Mobile Pentium Intel Pentium II: Boxed Pentium II, Boxed Pentium Pro, Mobile Pentium II and Celeron modules Intel Pentium III: Pentium III markings, Mobile Pentium III and Celeron modules Intel modern CPUs: Pentium II, Pentium III, Pentium 4, Core Duo, Core Solo, Core 2 Duo, Core 2 Quad, Core 2 Extreme, Xeon, Pentium Dual Core, Celeron, Celeron D, Celeron Dual Core Intel 287 adapter Intel 3002 Intel 478-pin FC-PGA Thermal Sample Intel 80188 Intel 80486 Mech sample Intel 8080A Intel 80P23T-25 Intel A100 UM80536UC600512 Intel A110 UM80536UC800512 Intel A80186 Intel A80186-10 Intel A80188 Intel A80188-10 Intel A80286-10 Intel A80286-12 Intel A80286-8 Intel A80376-16 Intel A80376-20 Intel A80386-16 Intel A80386-20 Intel A80386-25 Intel A80386DX-16 Intel A80386DX-16 IV Intel A80386DX-20 Intel A80386DX-20 IV Intel A80386DX-25 Intel A80386DX-25 IV Intel A80386DX-33 IV Intel A80386DX16 Intel A80386EXI Intel A80387-16 Intel A80387-20 Intel A80387-20B Intel A80387-25 Intel A80387DX-16 (with logo) Intel A80387DX-16-33 Intel A80387DX-20 Intel A80387DX-25 Intel A80387DX-33 Intel A80486DX-33 Intel A80486DX-50 Intel A80486DX2-50 Intel A80486DX2-66 Intel A80486DX4-100 Intel A80486DX4-75 Intel A80486SX-16 Intel A80486SX-20 Intel A80486SX-25 Intel A80486SX-33 Intel A80486SX2-50 Intel A80487SX Intel A80860XP-40 Intel A80860XP-50 Intel A80860XR-25 Intel A80860XR-33 Intel
    [Show full text]
  • Mikroişlemcilerin Tarihi
    D9 Mikroişlemcilerin Tarihi 1 D9 Mikroişlemcilerin Tarihi Mikroişlemcili sistemlerin kalbi olarak kabul edilen mikroişlemciler, genel amaçlı elemanlardır ve farklı uygulamalarda amaca uygun olarak kullanılırlar. Kullandığımız bilgisayarlar ister masaüstü, ister sunucu isterse de dizüstü bilgisayar olsun tüm cihazlarda temel eleman mikroişlemcidir. 2 D9 Mikroişlemcilerin Tarihi Diğer taraftan kullandığımız mikroişlemci bir Pentium, Athlon, PowerPC, SPARC veya Alpha yada herhangi bir marka olabilir, ancak tüm işlemciler benzer yöntemlerle benzer işler gerçekleştirir. İşlemleri yerine getirmede mantıksal devreleri kullanan mikroişlemcilerde temel elektronik eleman olarak transistörler kullanılır. 3 D9 Mikroişlemcilerin Tarihi Mikroişlemcili sistemlerin ve bilgisayarların en önemli parçası olan bu eleman başlangıçtan günümüze kadar hızlı bir gelişim süreci sergilemiştir. 8086 işlemcisiyle beraber Intel ailesinin mikroişlemcilerde kullandığı mimariye Intel Mimarisi (Intel Architecture-IA) denilmiştir. 4 D9 Mikroişlemcilerin Tarihi Mikroişlemcileri bir kerede işleyebildikleri bit sayısına göre sınıflandırmaya tabi tutarsak; – 8 bitlik mikroişlemciler – 16 bitlik mikroişlemciler – 32 bitlik mikroişlemciler – 64 bitlik mikroişlemciler Şeklinde sınıflama yapabiliriz. 5 D9 Birinci Kuşak Mikroişlemciler Bu kuşak mikroişlemciler eski orijinal IBM PC, XT tipi ve benzer makinalarda kullanılmıştır. O günlerin şartlarına göre mükemmel fakat günümüze göre oldukça sınırlı yeteneklere sahip bu makinelerle günümüz makineleri kıyaslanırsa çok ilkel
    [Show full text]
  • Prozessorenliste
    Fach Bezeichnung Stepping Taktfrequenz Anmerkung 1A Intel C4001 7347 0,74 MHz ROM Intel P4002-1 0488D RAM Intel D4002-2 X1191128 RAM Intel P4003 F8956 Shift Register Intel P4004 5199W Prozessor Intel P1101A 7485 MOS SRAM 1B Intel D8008 I1220098 Intel P4040 5869W 1C Intel D3001 I3320035 Intel D3002 I3370036 1D Intel P8259A-2 L8360894 10 MHz PIC Intel P8254-2 L0421586 10 MHz PIT 1E Intel P8080A 2194B 2 MHz Intel P8086-2 L4151756B 5 MHz 1F Intel P8088 L5500345 5 MHz Intel C8087 L5380043 Math. CP 1G Intel P8031 L61100346 12 MHz Intel P8085 L5500055 3 MHz 1H Intel 8237A L0311554 5 MHz DMA Contr. Intel P8274 L7440107 MPSC Intel D8742 U2420277 12 MHz 8 Bit SMC 2A AMD N80186, N80186 91939DFE7 10 MHz, 12 MHz 335BCWD AMD 80286, Intel 80188 918KPSC L5322539 2B Intel 80286, 80286 L8500401 6, 12 MHz L9080860 2C Intel 80287 L9190444 10 MHz Math. CP 2D Intel 80286 L2140286 6 MHz Harris 80286 F3360 16MHz 2E Intel NG80386SX L1121576 16 MHz 2F Intel A82596SX SZ649 20 MHz 2G Intel 80486SX SX676 25 MHz 2H Intel A80501 SX835 60 MHz FDIV Bug 3A Intel Pentium II SL357 400 MHz Deschutes 3B Intel 80386DX SX366 33 MHz IIT 3C87 KY9220 40 MHz Math. CP 3C IT´s ST 80486DX4 100 MHz 3D UMC GREEN CPU U5S 9439K 33 MHz Not for US Sale 3E Intel 80386DX/DXL SX218 25 MHz IIT 3C87 ID9143.8 33MHz Math. CP 3F M27128AFI 88723S EPROM 3G Intel Pentium 4 SL79L 3,0 GHz Prescott Intel Pentium 4 SL6RZ 2,4 GHz Nortwood 3H Intel Celeron SL2WM 300 MHz Mendocino 4A Intel Pentium II SL357 400 MHz Deschutes 4B Intel i80960 L8373305B0 33 MHz RISC 4C Intel i80860XR SX438 40 MHz RISC 4D Intel
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • CPU History [Tualatin] [Banias] [Dothan] [Yonah (Jonah)] [Conroe] [Allendale] [Yorkfield XE] Intel Created Pentium (From Quad-Core CPU
    2nd Generation 4th Generation 5th Generation 6th Generation 7th Generation 3rd Generation Intel Pentium III-S Intel Pentium-M (Centrino) Intel Pentium-M (Centrino) Intel Core Duo (Viiv) Intel Core 2 Duo (Viiv)/Xeon Intel Core 2 Duo (Viiv) Intel Core 2 Extreme (Viiv) Intel had the first consumer CPU History [Tualatin] [Banias] [Dothan] [Yonah (Jonah)] [Conroe] [Allendale] [Yorkfield XE] Intel created Pentium (from quad-core CPU. x86/CISC Microprocessors Greek penta which means (2001) (2003) (2004) (2006) (2006) (2007) (2007) 1st Generation Intel Pentium II Xeon Intel Pentium III Xeon Centrino is not a CPU; it is Begin Core five) to distinguish the Intel [P6] [Tanner] a mobile Intel CPU paired nomeclature brand from clones. Names (1998) (1999) Intel Celeron with an Intel Wi-Fi adapter. Intel Celeron Intel Core Solo can be copyrighted, product [Tualeron] [Dothan-1024] Intel Xeon LV Intel Celeron Intel Celeron [Yonah] ID's cannot. (2001) (2004) [Sossaman] [Banias-512] [Shelton (Banias-0)] (2006) (2006) Intel Core 2 Duo Intel Core 2 Extreme Intel Celeron Intel 80386 DX Intel 80486 DX Intel Pentium Intel Pentium Pro Intel Pentium II Intel Pentium II Intel Pentium III Intel Pentium III Intel Pentium 4 Intel Pentium 4 (2004) (2004) Intel Pentium 4 Intel Pentium 4 Intel 4004 Intel 8008 Intel 8086 Intel 80286 [Conroe XE] [Conroe-L] [P3] [P4] [P5/P54/P54C] [P6] [Klamath] [Deuschutes] [Katmai] [Coppermine] [Williamette] [Northwood] [Prescott] [Cedar Mill] END-OF-LINE (Centrino Duo) (1971) (1972) (1978) (1982) (2006) (2007) (1985) (1989) (1993) (1995) (1997) (1998) (1999) (1999) (2000) (2002) (2004) (2006) [Merom] (2006) Yonah is Hebrew for Jonah.
    [Show full text]
  • ABSOLVENTSKÁ PRÁCE Historie Počítačů
    Vyšší odborná škola a St řední pr ůmyslová škola elektrotechnická Olomouc, Božet ěchova 3 ABSOLVENTSKÁ PRÁCE Historie po číta čů 2006 Jaromír MATUCHA Absolventská práce – Historie po číta čů Zde bude vloženo oficiální zadání (ve 2. výtisku jeho kopie). Absolventská práce – Historie po číta čů Prohlašuji, že jsem vypracoval absolventskou práci, Historii po číta čů , samostatn ě pod vedením ing. Ji řího Rudolfa a ing. Josefa Kolá ře. ………….……………….. Jaromír Matucha Prohlašuji, že lze používat tuto absolventskou práci k dalšímu studiu tj. je možné si ji p ůjčovat a používat p ři výuce na škole. ………….……………….. Jaromír Matucha 5. kv ětna 2006 Absolventská práce – Historie po číta čů OBSAH Úvod..................................................................................................................................6 1. Po četní pomůcky.......................................................................................................7 1.1 Kosti (p řed 25 000 lety) ....................................................................................7 1.2 Po čítání na prstech (5. století p ř.n.l.) ................................................................7 1.3 Abakus (kolem roku 5 000 p řed n.l.) ................................................................8 1.3.1 Salamínská deska (300 p ř.n.l.) ..................................................................9 1.3.2 Liny (15. století)........................................................................................9 1.3.3 Suan-pan (13. století)..............................................................................10
    [Show full text]
  • Historie Procesorů Od Počátku Až Do Dnešní Doby
    Jiří Marchalín Historie procesorů od počátku až po současnost 2004 1 Mikroprocesor, srdce počítače, prošel od svého prvního uvedení na trh, bouřlivým vývojem. V průběhu vývoje od počátku k dnešním procesorům kráčely nohy vývojářů po různých cestách, ne všechny však vedly k cíli. Některé vývojové větve zanikly, jiné nesplnily účel, ke kterému byly vytvořeny a jiné se neopomenutelně zapsaly do počítačové historie. Toto je skromný výtah nejslavnějších procesorů z jejich nepřeberného množství. Záznamy o mikroprocesorech jsou řazeny chronologicky, tak jak byly postupně uváděny na trh. V průběhu vývoje mikroprocesorů výrobci postupně opouštěli staré technologie a přecházeli k novým, aby se krátce poté jiní výrobci vrátili k těmto opuštěným technologiím zpět. Mikroprocesory se dají jednoduše rozdělit do dvou základních skupin podle navržené architektury a to RISC a CISC. Jedná se víceméně o soubor pravidel a parametrů, které musí mikroprocesor splňovat, tedy o strategii a návrh. V poslední době se objevuje ještě určitá kombinace těchto architektur nazvaná "post-RISC" a také architektura EPIC. První z těchto architektur je tzv. Complex Instruction Set Computer (CISC). Základní charakteristikou je poměrně rozsáhlá instrukční sada stroje a její komplexnost. Na každý obtížnější problém, jako je například násobení dvou čísel, existuje zvláštní instrukce. Dalšími specifiky jsou vysoký počet adresovacích módů a proměnná délka instrukcí. Zastánci ostatních architektur považují tuto vlastnost za hlavní nevýhodu celé architektury. V současné době používá architekturu CISC pouze řada mikroprocesorů x86 firmy Intel. V minulých letech to byly mikroprocesory použité v platformách Amiga a Atari. Postupný úpadek architektury CISC způsobil hlavně výrazný pokles pamětí RAM z 5000USD za 1 MB v roce 1977 na nepatrný zlomek v současné době.
    [Show full text]
  • Emulator Including Prototype Control Probes
    INSTRUCTION Part No. 061-2918-00 T EK MANUAL Product Group 61 8500 Modular MOL Series 80186/80188 Emulator Including Prototype Control Probes This manual supports the Users and Installation following TEKTRONIX products: 8300E38 Manual 8300P45 8300P46 8300P45 Option 01 8300P46 Option 01 Please check for change information a t the rear of this manual First Printing FEB 1984 Tektronix~ COMMITTED TO EXCELLENCE Copyright ® 1984 by Tektronix, Inc. All rights reserved. Contents of this publication may not be reproduced in any form without the permission of Tektronix, Inc. Products of Tektronix, Inc. and its subsidiaries are covered by U.S. and foreign patents and/or pending patents. TEKTRONIX, TEK, SCOPE-MOBILE, and i! are regis­ tered trademarks of Tektronix, Inc. TELEQUIPMENT is a registered trademark of Tektronix U.K. Limited. There is no implied warranty of fitness for a particular purpose. Tektronix, Inc. is not liable for consequential damages. Specification and price change privileges are reserved. Printed in U.S.A. 80186/80188 Emulator Instruction PREFACE ABOUT THIS MANUAL This manual tells how to operate and install the 80186/80188 Emulator in an 8500 Series Tektronix development system. In addition, this manual explains the features of the 8550 and 8540 development systems unique to the 80186 Emulator and 80188 Emulator. DEFINITION OF TERMS Throughout this manual, the following terms are used to enhance readability: • All references to a "development system" refer to: • 8550 Microcomputer Development Lab which consists of the 8301 Microprocessor Development Unit, and the 8501 Data Management Unit • 8540 Integration Unit • The term "emulator boards" refers to the 80186/80188 Emulator boards (Board I, Board II, and Board III).
    [Show full text]
  • Datasheet Search Site
    80186/80188 HIGH-INTEGRATION 16-BIT MICROPROCESSORS Y Integrated Feature Set Y Direct Addressing Capability to 1 Mbyte Ð Enhanced 8086-2 CPU of Memory and 64 Kbyte I/O Ð Clock Generator Y Completely Object Code Compatible Ð 2 Independent DMA Channels with All Existing 8086, 8088 Software Ð Programmable Interrupt Controller Ð 10 New Instruction Types Ð 3 Programmable 16-bit Timers Ð Programmable Memory and Y Numerics Coprocessing Capability Peripheral Chip-Select Logic Through 8087 Interface Ð Programmable Wait State Generator Y Available in 68 Pin: Ð Local Bus Controller Ð Plastic Leaded Chip Carrier (PLCC) Y Available in 10 MHz and 8 MHz Ð Ceramic Pin Grid Array (PGA) Versions Ð Ceramic Leadless Chip Carrier (LCC) Y High-Performance Processor Y Available in EXPRESS Ð 4 Mbyte/Sec Bus Bandwidth Ð Standard Temperature with Burn-In Interface @ 8 MHz (80186) Ð Extended Temperature Range Ð 5 Mbyte/Sec Bus Bandwidth (b40§Ctoa85§C) Interface @ 10 MHz (80186) 272430±1 Figure 1. Block Diagram *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. November 1994 Order Number: 272430-002 © COPYRIGHT INTEL CORPORATION, 1995 1 80186/80188 High-Integration 16-Bit Microprocessors CONTENTS PAGE CONTENTS PAGE FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 ABSOLUTE MAXIMUM RATINGS ÀÀÀÀÀÀÀÀ 15 Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 D.C.
    [Show full text]
  • Evaluating Vista and Epics with Regard to Future Control Systems Development at Isis I
    17th Int. Conf. on Acc. and Large Exp. Physics Control Systems ICALEPCS2019, New York, NY, USA JACoW Publishing ISBN: 978-3-95450-209-7 ISSN: 2226-0358 doi:10.18429/JACoW-ICALEPCS2019-MOPHA042 EVALUATING VISTA AND EPICS WITH REGARD TO FUTURE CONTROL SYSTEMS DEVELOPMENT AT ISIS I. Finch, ISIS, Rutherford Appleton Laboratory, United Kingdom Abstract Vsystem is the more centralised of the two with data- bases existing on central servers, and the expectation that The ISIS accelerators currently use the Vista Controls input and output to the hardware will be performed by System software Vsystem for machine control purposes. In readers and handlers respectively running on the same this paper we describe our preliminary work in evaluating servers. In EPICS Input/Output Controllers (IOCs), the a possible migration to the EPICS control system, with em- equivalent of Vsystem’s readers and handlers, are expected phasis on lessons learned in our previous software migra- to be distributed and localised to the controlled hardware tion. We outline a Vsystem/EPICS bridge that has been de- along with the databases. veloped to facilitate the trial and any migration following on from that evaluation. FRONT END TEST STAND A HISTORY OF CHANGE The EPICS evaluation will be conducted on the ISIS Front End Test Stand (FETS) [7], a hardware development The ISIS spallation neutron source saw first beam in system separate from the main ISIS accelerators. FETS 1984 and was formally opened in 1985, with a second tar- consists of a Penning ion source, a magnetic low energy get station commissioned in 2008 [1].
    [Show full text]