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INFORMATION to USERS the Most Advanced Technology Has Been Used to Photo­ Graph and Reproduce This Manuscript from the Microfilm Master Expandable multiprocessor using low cost microprocessors Item Type text; Thesis-Reproduction (electronic) Authors Olson, Joseph Augustine, 1959- Publisher The University of Arizona. Rights Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. Download date 25/09/2021 12:03:00 Link to Item http://hdl.handle.net/10150/277133 INFORMATION TO USERS The most advanced technology has been used to photo­ graph and reproduce this manuscript from the microfilm master. UMI films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margins, and improper alignment can adversely affect reproduction. In the unlikely event that the author did not send UMI a complete manuscript and there are missing pages, these will be noted. Also, if unauthorized copyright material had to be removed, a note will indicate the deletion. Oversize materials (e.g., maps, drawings, charts) are re­ produced by sectioning the original, beginning at the upper left-hand corner and continuing from left to right in equal sections with small overlaps. Each original is also photographed in one exposure and is included in reduced form at the back of the book. These are also available as one exposure on a standard 35mm slide or as a 17" x 23" black and white photographic print for an additional charge. Photographs included in the original manuscript have been reproduced xerographically in this copy. Higher quality 6" x 9" black and white photographic prints are available for any photographs or illustrations appearing in this copy for an additional charge. Contact UMI directly to order. University Microfilms International A Bell & Howell Information Company 300 North Zeeb Road, Ann Arbor, Ml 48106-1346 USA 313/761-4700 800/521-0600 Order Number 13S8526 Expandable multiprocessor using low cost microprocessors Olson, Joseph Augustine, M.S. The University of Arizona, 1989 U MI 300 N. Zeeb Rd. Ann Aibor, MI 48106 EXPANDABLE MULTIPROCESSOR USING LOW COST MICROPROCESSORS by Joseph Augustine Olson A Thesis Submitted to the Faculty of the DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING In Partial Fulfillment of the the Requirements For the Degree of MASTER OF SCIENCE WITH A MAJOR IN ELECTRICAL ENGINEERING In the Graduate College THE UNIVERSITY OF ARIZONA 19 8 9 STATEMENT BY AUTHOR This thesis has been submitted in pactial fulfillment of requirements for an advanced degree at The University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the Library. Brief quotations from this thesis are allowable with­ out special permission, provided that accurate acknowledge­ ment of source is made. Requests for permission for ex­ tended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his or her judgement the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author. SIGNED :< APPROVAL BY THESIS DIRECTOR This thesis has been approved on the date shown below: Frederick/y. Hil'l Professor of ^Electrical and Computer Engineering 3 TABLE OF CONTENTS LIST OF ILLUSTRATIONS 5 ABSTRACT 8 1. INTRODUCTION 9 1.0 The LAN Multiprocessor Alternative 1.1 System Overview 2. HARDWARE DESIGN 19 2.0 Hardware Overview 2.1 Basic Multiprocessor Element (MPE) 2.1.0 INTEL 80188 CPU 2.1.1 Memory Systems 2.1.2 IP Communications Subnetwork 2.1.2.0 Z8530 SCC 2.1.2.1 Z8530 CPU Interface 2.1.2.2 IP Interface 2.1.2.3 Analysis of Coaxial Medium 2.2 IBM PC Interface Card 2.2.0 Basic MPE 2.2.1 PC Shared Memory Interface 2.3 Quad Processor Card 2.4 IBM PC Development Card 3. SYSTEM SOFTWARE 72 3.0 System Software Overview 3.1 80188 Initialization 4 3.2 80188 Timer Routines 3.3 Z8530 SCC Routines 3.4 Data Link Control 3.4.0 DLC Overview 3.4.1 XDLC Frame Format 3.4.2 DLC Finite State Machine 3.5 Network Control 3.6 Application and Network Services 4. APPLICATIONS DEVELOPMENT 117 4.0 Loading the Pseudo Rom 4.1 Developing an 80188 Application 4.2 Summary of Application Service Requests 4.3 IBM PC Application Interface 4.4 Communications Subnetwork Performance 5. CONCLUSION 138 REFERENCES 142 5 ILLUSTRATIONS FIGURES 1-1 DMPS Expansion Using LAN Technology 10 2-1 Basic Multiprocessing Element Block Diagram 20 2-2 IBM PC Interface Card Block Diagram 32 2-3 IBM PC Interface Card - MPE Memory Map 35 2-4 IBM PC Interface Card - MPE I/O Map 36 2-5 IBM PC Interface Card - Schematic 1 80188 CPU 37 2-6 IBM PC Interface Card - Schematic 2 80188 Memory Systems 38 2-7 IBM PC Interface Card - Schematic 3 Z8530 SCC 39 2-8 IBM PC Interface Card - Schematic 4 Z8530 SCC Interface 40 2-9 IBM PC Interface Card - Schematic 5 MPE Shared Memory Interface 41 2-10 IBM PC Interface Card - Schematic 6 Shared Memory & Flip Flops. 42 2-11 IBM PC Interface Card - Schematic 7 IBM PC Shared Memory Interface 43 2-12 IBM PC Interface Card - Schematic 8 IBM PC Address Selection 44 2-13 IBM PC Interface Card - Schematic 9 IBM PC I/O Channel Interface 45 2-14 IBM PC Interface Card - Schematic 10 IBM PC I/O Channel 46 2-15 Quad Card Block Diagram 49 6 2-16 Quad Card - MPE Memory Map.- 50 2-17 Quad Card - MPE I/O Map 51 2-18 Quad Card - Schematic 1 80188 CPU * 52 2-19 Quad Card - Schematic 2 80188 Memory Systems 53 2-20 Quad Card - Schematic 3 Z8530 SCC 54 2-21 Quad Card - Schematic 4 Z8530 SCC Interface 55 2-22 Quad Card - Schematic 5 Clock Generator, IBM PC I/O Channel 56 2-23 IBM PC Development Card Block Diagram 58 2-24 IBM PC Development Card - MPE Memory Map 59 2-25 IBM PC Development Card - MPE I/O Map 60 2-26 IBM PC Development Card - Schematic 1 80188 CPU 61 2-27 IBM PC Development Card - Schematic 2 80188 Memory Systems 62 2-28 IBM PC Development Card - Schematic 3 Z8530 SCC 63 2-29 IBM PC Development Card - Schematic 4 Z8530 SCC Interface 64 2-30 IBM PC Development Card - Schematic 5 MPE Memory Interface 65 2-31 IBM PC Development Card - Schematic 6 Shared Memory & Flip Flops 66 2-32 IBM PC Development Card - Schematic 7 IBM PC Shared Memory Interface 67 2-33 IBM PC Development Card - Schematic 8 IBM PC - MPE Interface 68 7 2-34 IBM PC Development Card - Schematic 9 IBM PC System Memory Interface 69 2-35 IBM PC Development Card - Schematic 10 IBM PC I/O Channel Interface 70 2-36 IBM PC Development Card - Schematic 11 IBM PC I/O Channel 71 3-1 DLC Finite State Machine Diagram 81 3-2 XLDC Frame Format 82 3-3 Control Field Formats 83 3-4 Network Control Frame Control Field Format....113 4-1 Channel Utilization and Application Frame Size 134 4-2 Channel Utilization and Token Hold Time 135 4-3 Channel Utilization and Search Successor Period 136 4-4 Channel Utilization and Maximum Possible Nodes 137 5-1 Performance/Cost Relationship 140 8 ABSTRACT This paper presents an expandable multiprocessor system design based on: a) an INTEL 80188 based microcomputer as the basic processing element b) a multi-channel, multi-access, processor independent interprocessor communications subnetwork with data transfer rates of 250 Kbps or 1 Mbps per channel The basic system design consists of two IBM PC expansion cards - a single processor IBM PC Interface Card, and a Quad Processor Card containing four 80188 CPUs. Bach processor has access to two separate Interprocessor (IP) serial data channels. An IP channel supports as many as 16 processors using a token bus data link control. IP communications is either direct or routed via intervening processors to sup­ port an unlimited number of processors in a given system. 9 CHAPTER 1 INTRODUCTION 1.1 The LAN Multiprocessor Alternative The availability of a large variety of microprocessor and microelectronic components at very low prices allows de­ sign engineers to develop large multimicroprocessor systems that not long ago were economically impractical. Although the topologies of such systems can be as different as the myriad of microprocessor components, one approach to multi- microprocessor design is to take advantage of available microcommunication devices that support Local Area Network technology. By designing interprocessor communications sub­ networks using LAN technology, multimicroprocessor systems can be developed that are both easily expandable and non-CPU specific. A multimicroprocessor system that provides LAN based interprocessor (IP) communications can be easily expanded by ensuring that at least one node on each LAN in the system has the potential to access at least one other LAN. Figure 0-1 illustrates this concept of multiprocessor expansion. This idea is not unique in that many computer networks are multiple LANs coupled by inter-LAN "gateways". As fi­ gure 1-1 indicates, each LAN is not necessarily implemented the same. Many different LAN strategies (i.e., CSMA/CD, Token Passing Bus, Token Ring,...) can be used in the same TOKEN LAN(n-1) BUS PE(i) PE(i+p) TOKEN LAN(n) BUS PE( j) PE(j+q) TOKEN BUS STAR NETWORK LAN(n+2) PE(k) (NET HUB) PE(k+r) (NET HUB) m s Figure 1-1.
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