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Bicmos TECHNOLOGY and APPLICATIONS the KLUWER INTERNATIONAL SERIES in ENGINEERING and COMPUTER SCIENCE BiCMOS TECHNOLOGY AND APPLICATIONS THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING Corisulting Editor Jonathan Allen Otber booklJ In tbe serIes: Logie Minimization Aigorithms for VLSI Synthesis. R.K. Brayton, G.D. Hacbtel, C.T. McMullen, and A1berto Sangiovanni-Vincentelli. ISBN 0-89838-164-9. Adaptive Filters: Struetures, Aigorithms, and Applieations. M.L. Honig and D.G. Messerschmitt. ISBN 0-89838-163-0. Introduetion to VLSI Silicon Deviees: Physies, Technology and Charaeterization. B. EI-Kareh and R.J. Bombard. ISBN 0-89838-210-6. Latehup in CMOS Teehnology: The Problem and Its Cure. R.R. Troutman. ISBN 0-89838-215-7. Digital CMOS Circuit Design. M. Annaratone. ISBN 0-89838-224-6. The Bounding Approach to VLSI Circuit Simulation. C.A. Zukowski. ISBN 0-89838-176-2. Multi-Level Simulation for VLSI Design. D.D. Hili and D.R. Coelho. ISBN 0-89838-184-3. Relaxation Teehniquesfor the Simulation of VLSI Cireuits. J. White and A. Sangiovanni-Vincentelli. ISBN 0-89838-186-X. VLSI CAD Tools and Applieations. W. Fichtner and M. Morf, Editors. ISBN 0-89838-193-2. A VLSI Arehiteeture for Concurrent Data Struetures. W.J. DaIly. ISBN 0-89838-235-1. Yield Simulation for Integrated Circuits. D.M.H. Walker. ISBN 0-89838-244-0. VLSI Speei.J;eation, Verification and Synthesis. G. Birtwistle and P.A. Subrahmanyam. ISBN 0-89838-246-7. Fundamentals ofComputer-Aided Circuit Simulation. W.J. McCalla. ISBN 0-89838-248-3. Serial Data Computation. S.G. Smith and P.B. Denyer. ISBN 0-89838-253-X. Phonologie Parsing in Speech Recognition. K.W. Church. ISBN 0-89838-250-5. Simulated Annealingfor VLSI Design. D.F. Wong, H.W. Leong, and C.L. Liu. ISBN 0-89838-256-4. Polycrystalline Silicon for Integrated Circuit Applications. T. Kamins. ISBN 0-89838-259-9. FET Modeling for Circuit Simulation. D. Divekar. ISBN 0-89838-264-5. VLSI Placement and Global Routing Using Simulated Annealing. C. Sechen. ISBN 0-89838-281-5. Adaptive Filters and Equalisers. B. Mulgrew, C.F.N. Cowan. ISBN 0-89838-285-8. Computer-Aided Design and VLSI Device Development, Second Edition. K.M. Cham, S-Y. Oh, J.L. Moll, K. Lee, P. Vande Voorde, D. Chin. ISBN: 0-89838-277-7. Automatie Speech Reeognition. K-F. Lee. ISBN 0-89838-296-3. Speech Time-Frequency Representations. M.D. Riley. ISBN 0-89838-298-X A Systolic A"ay Optimizing Compiler. M.S, Lam. ISBN: 0-89838-300-5. Aigorithms and Techniquesfor VLSI Layout Synthesis. D. Hili, D. Shugard, J. Fishburn, K. Keutzer. ISBN: 0-89838-301-3. Switch-Level Timing Simulation of MOS VLSI Circuits. V.B. Rao, D.V. Overhauser, T.N. Trick, I.N. Hajj. ISBN 0-89838-302-1 VLSI for Artijiciallntel/igence. J.G. Delgado-Frias, W.R. Moore (Editors). ISBN 0-7923-9000-8. Wtifer Levellntegrated Systems: Implementation lssues. S.K. Tewksbury. ISBN 0-7923-9006-7 The Annealing Aigorithm. R.H.J.M. Otten & L.P.P.P. van Ginneken. ISBN 0-7923-9022-9. VHDL: Hardware Description and Design. R. Lipsett, C. Schaefer and C. Ussery. ISBN 0-7923-9030-X. The VHDL Handbook. Dr. Coelho. ISBN 0-7923-9031-8. Unijied Methodsfor VLSI Simulation and Test Generation. K.T. Cheng and V.D. Agrawal. ISBN 0-7923-9025-3 ASIC System Design with VHDL: A Paradigm. S.S. Leung and M.A. Shanblatt. ISBN 0-7923-9032-6. BiCMOS TECHNOLOGY AND APPLICATIONS edited by A.R. Alvarez Aspen Semiconductor Corporation (A Cypress Semiconductor Company) ..... Springer Science+Business" Media, LLC Library of Congress Cataloging-in-Publicatlon Data BiCMOS technology and applications. (The Kluwer international series in engineering and computer science ; #76. VLSI, computer architecture, and digital signal processing) Inc1udes bibliographies and index. 1. Metal oxide semiconductors, Complementary. 2. Bipolar intellrated circuits. I. Alvarez, A. R. (Antonio R.) 11. Series: Kluwer international series in engineering and computer science ; SECS #76. III. Series: Kluwer international series in engineering and computer science. VLSI, computer architecture, and digital signal processing. TK7871.99.M44B53 1989 621.381 '5 89-15310 ISBN 978-1-4757-2031-0 ISBN 978-1-4757-2029-7 (eBook) DOI 10.1007/978-1-4757-2029-7 This reprint edition has been published by KALA CORPORATION under copyright arrangements with KLUWER ACADEMIC PUBLISHERS. Copyright © 1990 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1990 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photocopying, recording, or other­ wise, without the prior written permission of the publisher, Springer Science+Business Media, LLC. Contents Foreword xi Preface xiii Chapter 1. Introduction to BiCMOS A.R. Alvarez (Aspen Semiconductor corp.) 1.0 Introduction 1 1.1 BiCMOS Historical Perspective 2 1.2 BiCMOS Device Technology 4 1.3 BiCMOS Process Technology 7 1.4 BiCMOS Costs 9 1.5 Applications 10 1.5.1 Memories 12 1.5.2 Semi-Custom 13 1.5.3 Microprocessors 14 1.5.4 Analog/Digital Systems 15 1.6 Projections 16 1.7 Summary 17 1.8 References 17 Chapter 2. Device Design J. Teplik (Motorola Inc.) 2.0 Introduction 21 2.1 Device Issues 22 2.1.1 MOS Devices 22 2.1.2 Bipolar Devices 30 2.2 BiCMOS Device Synthesis 42 2.2.1 Front-end Design 42 2.2.2 BiCMOS Device Compromises 43 2.3 Design Methodology 46 2.3.1 Synthesis versus Analysis 46 2.3.2 Response Surface Methodology 49 2.3.3 Circuit Design Considerations 53 2.4 Device Scaling 54 2.4.1 MOS Scaling 54 2.4.2 Bipolar Scaling 56 2.4.3 BiCMOS Scaling Considerations 58 2.5 References 59 vi Chapter 3. BiCMOS Process Technology R.A. Haken, R.H. Havemann, R.H. Eklund, L.N. Hutter (Texas Instruments, Ine.) 3.0 Introduetion 63 3.1 Evolution of BiCMOS From a CMOS Perspective 65 3.2 BiCMOS Isolation Considerations 69 3.2.1 Latchup 69 3.2.2 Buried Layers 70 3.2.3 Epitaxy and Autodoping 71 3.2.4 Parasitie Junetion Capacitance 72 3.2.5 Trench Isolation 72 3.2.6 Aetive Device Isolation 73 3.3 CMOS WeIl and Bipolar Collector Process Tradeoffs 75 3.4 CMOS Processing Considerations 79 3.4.1 CMOS Threshold Voltage Considerations and Adjustments 80 3.4.2 Source/Drain Processing and Channel Profiles 80 3.4.3 Relationship Between Transistor Performance and Manufacturing Control 85 3.5 Bipolar Process Options and Tradeoffs 86 3.5.1 Base Design Options 88 3.5.2 Emitter Design Options 88 3.5.3 Collector Design Options 89 3.6 Interconnect Processes for Submicron BiCMOS 91 3.6.1 Silicidation 91 3.6.2 Local Interconnect 94 3.6.3 Planarization and Metallization 97 3.7 Example of Submicrometer BiCMOS Process Flow for 5V Digital Applications 100 3.7.1 Starting Wafer and N+ Buried Layer Formation 101 3.7.2 Epitaxial Layer Deposition 102 3.7.3 Twin-Well Formation 102 3.7.4 Active Region and Channel Stop Formation 103 3.7.5 Deep N+ Collector and Base Formation 103 3.7.6 Polysilicon Emitter Formation 104 3.7.7 Gate and LDD Formation 105 3.7.8 Sidewall Oxide and Final Junction Formation 105 3.7.9 Silicide and Local Intereonnect 106 3.7.10 Multilevel Metal (MLM) Processing 107 3.8 Analog BiCMOS Process Technology 108 3.8.1 Analog BiCMOS Evolution 108 3.8.2 Analog BiCMOS Process Design Considerations 109 3.8.3 Analog BiCMOS Process Integration Discussion 112 3.8.4 Sampie Analog BiCMOS Process 115 vii 3.8.5 Future Process Issues in Analog BiCMOS 119 3.9 References 120 Chapter 4. Process Reliability R. Lahri, S.P. Joshi, B. Bastani (National Semiconductor Corporation) 4.1 Introduction 125 4.2 Reliability by Design 126 4.2.1 Reliabi~ty and Performance Tradeoffs 126 4.2.2 Monitoring Reliability 128 4.3 Built-in Immunity to Soft Errors 131 4.3.1 Alpha Particle Inducted Charge Collection 132 4.3.2 Role ofEpitaxiallayer and Buried Layer 133 4~3.3 Soft Errors in BiCMOS SRAMs 135 4.3.4 Other Protection Techniques 136 4.4 Gate Oxide Integrity and Hot Electron Degradation in MOSFETs 137 4.4.1 Gate Oxide Integrity 138 4.4.2 oe Hot Electron Characteristics 139 4.4.3 Role of Backend Processing 141 4.4.4 AC Hot Electron Degradation Characteristics 142 4.5 Hot Carrier Effects in Bipolar Devices 144 4.5.1 Device Instability Due to High Injection Forward Bias 145 4.5.2 Device Instability Due to Reverse Biasing of E-B Junction 145 4.5.3 Charge to Degradation Model 147 4.5.4 AC vs oe Stressing 149 4.6 E1ectromigration 149 4.6.1 Multilayer Interconnect Systems 150 4.6.2 E1ectromigration in Multilayer Interconnect Systems 150 4.6.3 Role of Passivation Films 152 4.7 Latchup in BiCMOS Circuits 152 4.7.1 Latchup Phenomenon 153 4.7.2 Latchup in Merged Devices 155 4.8 ESD Protection 156 4.8.1 ESD Failure Models 157 4.8.2 ESD Protection in BiCMOS Circuits 160 4.9 Summary 160 4.10 References 162 viii Chapter 5. Digital Design K. Deirling, (Dallas Semieonduetor) 5.0 Introduetion 165 5.1 CMOS vs BiCMOS 166 5.1.1 Statie Characteristies 166 5.1.2 Dynamie Charaeteristies 170 5.1.3 CMOS Delay Analysis 176 5.1.4 Staged Buffer Delay Analysis 177 5.1.5 BiCMOS Delay Analysis 180 5.2 Basic BiCMOS Cireuit Design 182 5.3 BiCMOS ASIC Applieations 186 5.4 Conclusion 198 5.5 References 198 Chapter 6.
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