Conference paper -Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides

International Electron Devices Meeting 2003

A novel Diode‐Triggered SCR (DTSCR) ESD protection element is introduced for low‐voltage application (signal, supply voltage ≤1.8V) and extremely narrow ESD design margins. Trigger voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultra‐sensitive circuit nodes, such as SiGe HBT bases (e.g. fTmax=45GHz in BiCMOS‐0.35u LNA input) and thin gate‐oxides (e.g. tox=1.7nm in CMOS‐ 0.09u input). SCR integration is possible based on CMOS devices or can alternatively be formed by high‐speed SiGe HBT’s. Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides Markus P.J. Mergens, Christian C. Russ**, Koen G. Verhaege, John Armer*, Phillip C. Jozwiak*, Russ Mohn*, Bart Keppens, Con Son Trinh* Sarnoff Europe, Brugse Baan 188A, B-8470 Gistel, Belgium, Europe Phone: ++49-751-3525633 - Fax: ++49-751-3525962, e-mail: [email protected] *) Sarnoff Corporation, 201 Washington Road, Princeton, NJ-08543, USA **) formerly with Sarnoff Corp., now with Infineon Technologies, Munich, Germany, Europe

Abstract – A novel Diode-Triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application (signal, supply voltage ≤ 1.8V) and extremely narrow ESD design margins. Trigger voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultra-sensitive circuit nodes, such as SiGe HBT bases (e.g. fTmax=45GHz in BiCMOS-0.35u LNA input) and thin gate-oxides (e.g. tox=1.7nm in CMOS-0.09u input). SCR integration is possible based on CMOS devices or can alternatively be formed by high-speed SiGe HBT’s.

I. INTRODUCTION This paper focuses on various implementations of a novel Due to their excellent clamping capabilities (low holding Diode Triggered SCR (DTSCR), which can be implemented voltage and low dynamic on-resistance), SCR’s represent ideal based on CMOS or SiGe HBTs, respectively. In addition, two ESD protection elements to operate within very narrow ESD narrow design window applications will be discussed, which design window applications, cf. Figure 1, where (GGNMOS) represent two common key issues for ESD protection design in NPN bipolar-based protection is not feasible anymore. advanced technologies: 1. SiGe HBT RF-ESD protection in However, a suitable trigger element needs to be incorporated to BiCMOS, cf. Figure 1 (top). 2. Ultra-thin GOX protection in latch the SCR sufficiently fast during ESD events and below CMOS-0.09u, cf. Figure 1 (bottom). the critical voltage limits of IC damage. II. DTSCR PROTECTION DESIGN Vin Vmax t

n »0.7V »6V II.1. SCR Trigger Voltage Engineering e r r ESD Design u The DTSCR uses a trigger diode chain to latch the SCR during C Window ESD stress conditions, when the diode string injects enough n o

i GGNMOS t ESD HBT current into the SCR gates (“trigger taps”) G1 or/and G2. a

r in BiCMOS

e IN (SiGe) p (a) G1 trigger (b) G2 trigger (c) G2 trigg, Vhold diode

o SiGe HBT

l

a BE m

r junction VEE o

n damage GND Vhold diode Rpn A for LU A n trigg (n-1) immunity Vt1»10V (n-2) trigger during IC trigger G 2 diodes operation G2 diodes G V »6V 2 hold Voltage Vin BVox t

n 1.2V »5.2V

e G1 G1 G1 r

r ESD Design u Window C Rpp Rsub

n GGNMOS C C o

i ESD t CMOS-0.09u a r IN NMOS Figure 2 G1-triggered DTSCR (a): forward bias of SCR e

p Thin-Oxide

o G1-Cathode junction. In CMOS-SCR an intrinsic connection to the substrate

l damage a (Rsub) is present. G2-triggered DTSCR (b/c): forward bias of G2-Anode m

r VSS

o junction. Vhold diode for LU immunity allows removing one diode (c).

n GND Triggering can either be accomplished by forward biasing the inherent SCR G1-Cathode junction, cf. Figure 2 (a), or V »5.4V t1 alternatively the G2-Anode diode, cf. Figure 2 (b), or both V »3.7V hold Voltage simultaneously. The number of trigger diodes (n) must be Figure 1 Narrow ESD design window IC applications. Top: SiGe HBT base chosen sufficiently high so that the chain does neither leak nor protection in BiCMOS-0.35u: GGNMOS snapback trigger Vt1 and holding trigger the SCR during normal circuit operation. On the other voltages Vhold are far above or too close to the damage level of the sensitive base-emitter junctions. Bottom: Ultra-Thin GOX input protection in CMOS- hand, the SCR ESD trigger voltage is also defined by n. 0.09u: GGNMOS trigger Vt1 and holding voltage Vhold are above / too close Obviously there is an important design trade-off between to the transient breakdown voltage of the ultra-thin gate oxide (tox=1.7nm). leakage during normal operation (“maximize n”) and ESD

trigger voltage (“minimize n”). A reasonable design bipolar device options. The implementation of both compromise can be achieved for low-voltage applications, configurations is discussed in the next two chapters. where the supply or signal voltage does not exceed 1.8V. For higher VDD (e.g. if the DTSCR is used as a 1.8V supply leakage current [A] @ 1.0V clamp), a series diode is needed to increase the holding voltage -10 -8 -6 -4 -2 0 Vhold above VDD to ensure latch-up immunity during normal 10 10 10 10 10 10 operation [1], cf. Figure 2 (c). This holding diode can also 5 become part of the trigger chain in a G2-triggered scheme DTSCR 2 trigg dio W=50um replacing one trigger diode. 4 G1 triggered 3 trigg dio Figure 4 shows the IV characteristics of two G2 triggered SCR 8 trigg dio

] demonstrating a holding voltage shift by approximately 1V to A [

3 latch above VDD(=1.8V) using a series diode (P+/Nwell) to t n

e achieve latch-up immunity. The substitution of a trigger diode r r

u by a holding diode, does not alter the trigger voltage.

c 2 8d 3d 2d 2.4V Moreover, an increased maximum stress current can be (2d) trigger Vt1 observed when using a holding diode. This is due to the 1 3.3V 7.5V parasitic Darlington formed by the vertical PNPs in the device (3d) (8d) forming an additional ESD current path to GND. 0 An important option with a diode trigger chain, apart from -4 -2 0 2 4 6 8 10 triggering the SCR, is that the diodes can serve as an ESD voltage [V] backup path for slower SCRs by clipping possible transient Figure 3 DTSCR Vt1 engineering: TLP-IV characteristic of DTSCR (CMOS- trigger voltage overshoots during very fast ESD transients, SCR) for three G1 trigger diode schemes: Vt1 » (n+1)×0.8V (n trigger diodes + such as CDM (Charged Device Model). Careful design of the intrinsic SCR G1/Cdiode). trigger diodes and trigger current injection point (G1 or G2) is For CMOS-based SCRs, G2-triggered devices bear an required to form a sufficiently strong initial ESD current path important advantage: the SCR G2 (Nwell)-Anode diode can be through the diodes until efficient SCR clamping sets in. exploited as a trigger diode within the trigger chain due to the Anode LnLp Cathode isolation of the Nwell from the P-substrate. In contrast, in G1(Pwell)-triggered elements the diode chain sees an intrinsic Pwell-substrate connection with a leakage path to ground, cf. P+ N+ Rsub in Figure 2 (a). As such, G2-triggering allows for the same diode-chain leakage during normal operation while using one trigger diode less, which is substituted by the inherent NWell PWell P+/Nwell (A/G2) SCR diode. Consequently, G2-triggered SCRs can be activated at an approximately 0.8V lower trigger e e voltage. d d o o h

Vhold t

3 n a

extra It2 due to diode A C vertical PNP SCR 2.5 of Vh-diode

diode D a r l i 2 6 trigg dio G2 n ] g G2 G1 t A o [ b

n t

Vdd =1.8V u

e s n s 1.5 5 trigg diode S R e e d e u r d b d o r + 1 hold diode o s u i o h t t c d r n a 1 r a t e A e C g

C

g i u DTSCR r t y r 0.5 l Figure 5 Cross-section / layout of a CMOS based SCR. The local G1/G2 r o b

G2-triggered n e u p n

s trigger taps can be inserted between the interrupted cathode / anode diffusion,

W=40um R t R + 0 ` respectively [1]. In the DTSCR, a diode chain is applied to bias the wells 0 1 2 3 4 5 6 7 through the gates G1/G2. voltage [V] II.2. SCR integration in CMOS Figure 4 DTSCR latch-up engineering: TLP-IV characteristic of a G2- triggered DTSCR (CMOS-SCR) for 1.8V application with 6 trigger diodes / no Conventional CMOS design integrates SCRs purely based on holding diode compared to 5 trigger diodes / 1 holding diode. Result: CMOS layers [1], [2]. A schematic example layout and a cross- approximately 1V difference in Vh, approximately same Vt1, but higher It2 section of the SCR kernel including gate / trigger tap with series diode due to parasitic darlington current into the substrate. implementation are depicted in Figure 5. Figure 3 illustrates the Vt1 engineering technique by showing II.3. SCR integration in SiGe HBT TLP-IV characteristics of various DTSCRs with different diode-chains. In this example, the SCR design is based on A schematic layout and cross-section of a SiGe HBT based CMOS layers only as will be explained in the next paragraph. SCR are shown in Figure 6. Due to the vertical current flow Alternatively, the SCR can be realized solely using SiGe from the SiGe HBT emitter to collector, the SCR will benefit from the high currents that can flow in a vertical bipolar

structure in contrast to lateral bipolar conduction in a lateral discussion above: G1-trigger vs. G2-trigger). This allows SCR. As demonstrated in Figure 7, the ESD performance in simultaneous G1/G2 triggering with identical diode chains on terms of maximum current It2 and HBM level drastically both gates. Dual-gate triggering enhances the SCR speed [3] increases implementing more contact rows in anode and and thus helps to avoid transient trigger voltage over-shoots cathode, respectively, due to the reinforced vertical junction during the device turn-on time. area. Moreover, due to the complete device isolation from the N+ emitter poly substrate, DTSCRs can also be applied as local protection P+ base poly with polycide N+ diffusion with polycide SiGe p-base element between IO and supply. A further benefit is the device Cathode G2 Anode G1 G1 immunity to latch-up induced by substrate current injection. III. DTSCR RF-ESD APPLICATION STI STI STI STI N+ N-epi sinker III.1. Input SiGe HBT Base in BiCMOS-0.35u I T

D SiGe HBT (fTmax=45GHz) emitter-base protection applying the N-Buried Layer conventional dual-diode protection approach in conjunction P- substrate with an NMOS-triggered SCR power clamp, see Figure 8, is ineffective. Reason is the very low base-emitter failure voltage (~6V), which is already exceeded by the power-clamp trigger voltage as defined by the NMOS holding voltage (Vhold~6V). This situation is illustrated in the ESD design window in Figure 1 (top). Diodes up: Diodes down: RF SiGe diodes N+/Pwell diodes VCC G2 3.3V D2 A G1 C G1 Modified <150fF SiGe LV-trigger Low-Volt 50fF HBT OUT ggNMOS triggered 59fF (Vt1»Vh»6V) GGSCR 3.3V D6 D1 Maximum permissible <120fF voltage across 24fF BE junction IN Figure 6 Cross-section and layout of SiGe-HBT based SCR (not shown: 78fF Vbe±0.1V c

external diode-chain trigger scheme that can be integrated through G1, or G2, r i

D4 FW: +6.0V t D5 i or G1 and G2). The symmetrical SCR device is formed by a vertical NPN HBT c REV: -7.5V a Rpol (emitter/SiGe-base/N-epi) in conjunction with a distributed PNP bipolar l <150fF 17fF (Anode/N-epi/SiGe-base). Note: alternatively the same intermittent trigger taps VEE as shown in Figure 4 could be used replacing the solid G1/G2 stripes. 0V±0.05V 104fF Furthermore, the SCR holding voltage is relatively small D3 (Vhold~1.1V) as compared to regular CMOS implementations GND 0V standard dual diode GGSCR power clamp reflecting the high current gain of the SiGe HBT part protection including low-voltage trigger of the SCR. Figure 8 LNA including conventional dual-diode protection approach for output, input, and emitter pad. ESD protection scheme fulfills the capacitance leakage current [A] @ 1.0V specs at each pin (C(V) numbers calculated by SPICE parameters). Serious 10-12 10-10 10-8 10-6 10-4 10-2 100 ESD issues occur since the NMOS-triggered power clamp has a higher Vt1 10 Symmetrical than failure voltage of forward biased SiGe HBT base-emitter (BE) junction. It2=83mA/um (HBM>8kV) 4 CT rows 2-sided The most critical ESD current path is indicated. SCR design 8 Moreover, a direct local diode chain protection between Input 2CT 2CT 2CT 2CT

] and VEE (for both pins a capacitance spec is defined) A [

6 t 47mA/um (> 8kV) 2 CT rows compromises the RF performance because of a too high diode n e r r cathode capacitance (also increased by the forward bias). u

c 4 25mA/um (4.4kV) 1 CT row Introducing a diode chain between Input and GND violates the ESD design window: for worst-case stress between IN and 2 DTSCR W=2x50um VEE, 4 width-limited RF diodes (high series R!) would G1 triggered compete with the parasitic HBT BE diode in forward 0 A C A -4 -2 0 2 4 6 8 10 conduction. voltage [V] Local DTSCR protection as shown in Figure 9 succeeds for Figure 7 HBT-based DTSCR (W=2x50u; 2-sided) TLP-IV for three different three reasons: 1. By applying three small trigger diodes in variations of number of contact rows in anode and cathode, respectively. The performance boost with larger number of contact rows reflects the predominant series, the SCR Vt1 can be reduced sufficiently below the vertical current flow in HBT based SCRs. critical HBT failure voltage at 6V with an acceptably low input An interesting benefit of the described SiGe HBT-SCR is the leakage during normal RF operation. 2. The SCR clamps the fact that the SCR is fully isolated from the substrate. As a IN-VEE voltage below the HBT damage, thus enabling the consequence, the gate G1 can be treated the same as G2 (see challenging 200V-MM spec (roughly corresponds to 4kV-

HBM). 3. To meet the input RF capacitance spec Cin<120fF, essentially results in the same leakage current as compared to the SCR-Nwell can be pulled high to VCC through G2, thus, the G1-triggered SCR. However, the G2-triggered SCR reveals reverse biasing the SCR Anode-Nwell junction minimizing the a lower trigger voltage Vt1, since one trigger diode less can be parasitic capacitance of the Anode at IN. used as explained above. The leakage increase at It2 indicates The TLP characteristic in Figure 10 corroborates the gate-oxide failure occurring within the high-resistive roll-off functionality of the DTSCR ESD protection revealing the regime of the SCR IV curve. So, almost the intrinsic failure following IV regimes: HBT BE diode conduction, DTSCR current of the stand alone SCR is achieved. This experiment triggering, joined HBT/DTSCR conduction (see inset including proves that the SCR can successfully protect a thin input gate ESD current path for most critical stress case), HBT failure oxide. The large margin of Vt1 and clamping voltage with after input voltage exceeds the critical HBT failure limit of 6V. regard to BVox provides a large IC ESD design window for ESD protection on IC level, where additional voltage drops VCC occur in the ESD discharge path e.g. across bus resistance and diodes. The experiment with parallel gate monitor demonstrates D2 50fF that the DTSCR structure is able to protect ultra-thin gate OUT oxides. 59fF reverse biased P+/Nwell junct. Vt1=6V leakage current [A] @ 1.32V for minimum S P

C -9 -7 -5 -3 -1

SCR anode D o R

D1 10 10 10 10 10 G

w T capacitance w M S i t e h O

3.5 C

r R N pn R N

42fF M 78fF c

O DTSCR in CMOS-

l 4 trig dio a

IN S m - W=40um

t @ G1

r 3 i g p Parallel thin GOX monitor g 3 trig dio e local r @ G2 tox=1.7nm (electr.) trigger D4 2.5

diodes DTSCR ] A

G [ 2 32fF t 2 leakage VEE n

e mainly from

104fF r G1 r gate monitor BVox

D3 u 1.5 Rpol c GND 1 trigger Vt1 Figure 9 LNA including local DTSCR protection of HBT in conjunction with 3.4V 4.0V application of capacitance reduction scheme for the anode by reverse biasing 0.5 (G2) (G1) the P+/Nwell junction. All pin combinations exceed ESD spec of 2kV-HBM and 200V-MM spec (latter corresponds to approx 4kV-HBM), whereas RF 0 capacitance spec is also met. -1 0 1 2 3 4 5 6 voltage [V] leakage current [A] @ -0.5V 10-9 10-7 10-5 10-3 10VCC-1 Figure 11 CMOS-0.09u: TLP-IV characteristic of DTSCR including a parallel 3.5 gate-oxide (tox=1.7nm) monitor to emulate IC input protection. The thin GOX HBT BE junction IN can be successfully protected! 3 Local DTSCR protection D4 Pos. stress: IN vs. GND VEE IV. CONCLUSION 2.5 This paper presents a novel diode-chain triggered SCR ESD ] D3 A GND [ protection element for low voltage applications (signal, supply

t 2 n ≤ 1.8V). The DTSCR enables ESD protection design of ultra- e

r DTSCR & BE junction r sensitive IC nodes within extremely narrow ESD design u 1.5 HBT BE failure c DTSCR & D3 on windows, such as SiGe HBT emmitter-base junctions 1 at Vt1 + V(1 dio) = (advanced BiCMOS) or ultra-thin gate oxides (sub-0.25u 3.3V + 0.8V = 4.1V CMOS). Conventional CMOS-integrated DTSCRs as well as HBT BE below failure! 0.5 SCR-based on high-speed SiGe HBT elements were 0 successfully proven in product ICs. 0 2 4 6 8 10 voltage [V] REFERENCES Figure 10 LNA TLP-IV characteristic: worst-case stress (positive on Input vs. VEE on ground) protected by local DTSCR, cf. Figure 9: the DTSCR triggers [1] C. Russ, M. Mergens, K. Verhaege, J. Armer, P. Jozwiak, G. Kolluri, L. and clamps the voltage below HBT base damage. The ESD spec of 2kV-HBM Avery. GGSCRs: GGNMOS Triggered Silicon Controlled for and 200V-MM can easily be achieved within the RF capacitance constraints. ESD Protection in Deep Sub-Micron CMOS Processes. EOS/ESD 2001, pp. 22. III.2. Input Ultra-Thin GOX in CMOS-0.09u [2] M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, R. Mohn. High Figure 11 depicts the TLP-IV characteristics of two DTSCRs Holding Current SCR (HHI-SCR) for ESD Protection and Latch-up in a G1- and G2-triggered configuration, respectively. Both Immune IC Operation. EOS/ESD 2002, pp. 10. structures have the thinnest NMOS gate oxide (tox=1.7nm) as a [3] K-C Hsu, M-D. Ker. Double-Triggered SCR Devices for On-Chip ESD protection monitor in parallel to emulate an RF IC input Protection in Sub-Quarter-Micron CMOS Processes. EOS/ESD 2003, in configuration, see figure inset. Note that the G2-trigger scheme press at time of submission.

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