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MOS CAPACITOR – MOSFET – MOS INVERTERS

Prof. Philippe LORENZINI Polytech-Nice Sophia Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 2

Outline

• Metal Oxyde Structure • MOS Transistor • MOS Inverters • NMOS • CMOS Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 3

Metal Oxyde Semiconductor Structure band diagram of the three components that make up MOS system

 MOS capacitor  E   g   SC SC 2e fi Pr. Ph.Lorenzini  From MOS Capacitor to CMOS inverter 4  Equilibrium of MOS structure

dV d 2V  (x) Vd  M  SC , E   , 2   dx dx  SC

Metal SC(n) Metal SC(n)

e SC eSC eVd e E M C e e M SC e E SC F EC EF E F EF E V EV dx Independant system Equilibrium state Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 5

Ox The five regimes : a function of function

(a) Accumulation

(b) Flat band

(c) Desertion / depletion

(d) Weak inversion

(e) Strong inversion Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 6 Energy band diagram for ideal n and p type MOS capacitors under different bias conditions Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 7 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 8

Field, potential and charges in Silicon

We suppose we deal with a p type semiconductor:

warning: in few books, e  E  E  0 absolute value is not Fi F Fi present!!!!

V (x  )  0, V (x  0) Vs, Vg Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 9

Field, potential and charges in Silicon

d2V  (x)  Poisson’s Equation: 2  dx SC

  (x)  ep(x)  n(x)  N D (x)  N A (x)

e   e Fi Fi p  n  N  N n  n exp( ) p0  ni exp( ) 0 0 A D 0 i kT kT eV(x) e(V (x)  ) n(x)  n exp( )  n exp( Fi ) 0 kT i kT

e(V (x)  ) p(x)  n exp( Fi ) i kT Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 10

Field, potential and charges in Silicon

eV ( x) eV ( x)    kT kT (x)  en0  p0  p0e  n0e   

2 eV (x) eV (x)     d V (x) e kT kT 2    p0 (e 1)  n0 (e 1) dx  SC  

d 2V (x) d  dV (x)  d  dV (x)  dV (x)       dx 2 dx  dx  dV  dx  dx

eV ( x) eV ( x)     dV (x)  dV (x)  e kT kT d     p0 (e 1)  n0 (e 1)dV (x) dx  dx   SC   Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 11

Field, potential and charges in Silicon •We compute the from bulk to a point x in SC

dV ( x ) MO S V(x=« bulk »)=0 et  0 Vg dx bulk

eV (x) eV (x) dV (x) V ( x)     dx dV (x)  dV (x)  e kT kT d    p0 (e 1)  n0 (e 1) dV (x) 0 0   dx  dx   SC   dV (x) As the is given by: E(x)   dx

2 eV (x) eV (x) 2  dV (x)  2kTp0   eV (x)  n0  eV (x)  E (x)     e kT  1  e kT  1  dx   SC  kT  p0  kT  Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 12

Field, potential and charges in Silicon

2 2 eV (x) eV (x) 2  dV (x)   kT  2  kT eV (x)  n0  kT eV (x)  E (x)       2 e  1  e  1  dx   e  LD  kT  p0  kT 

 SC kT With the Debye length: LD  2 e po Q If we use the Gauss’s theorem: SC E(x  0)  ES    SC

1 eV e(V 2 ) 2  S S FI  kT   SC 2  kT eVS kT n0  eVS  QSC    e  1 e   1  Qmetal  e  LD  kT p0  kT  Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 13

Field, potential and charges in Silicon Allways negligible

1 eV e(V 2 ) 2  S S FI  kT   SC 2  kT eVS kT n0  eVS  QSC    e  1 e   1  Qmetal  e  LD  kT p0  kT 

For Vs (and so Vg) negative (accumulation)

For Vs (and Vg) positive but Less than 2fi (depletion – weak inversion)

For Vs (and Vg) > 2fi (strong inversion) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 14

Weak / Strong Inversion 2kT  N   A  VS  2 Fi  ln  e  ni 

eFI

ns=p0=NA

This condition will define a very important parameter of the struture: the threshold or the required gate voltage to be in strong inversion Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 15

Measurement of in Ideal MOS Structure

The C-V curve is usually measured with a CV meter: • We apply a DC bias voltage Vg + small sinusoidal (100 Hz to 10 MHz) • We measure the capacitive current with an AC meter (90 degree phase shift)

=> icap/vac =C Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 16

Measurement of capacitance in Ideal MOS Structure

When a voltage Vg is applied to the MOS Gate, part of it appears as a potential drop across oxyde and the rest of it appears as a band bending Vs in silicon:

 QSC Vg  Vox VS  VS Cox

V(X) MO S VOX Vg VG V Vox VSC S Oxyde and Silicon have -t 0 X capacitor behavior OX Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 17

Measurement of capacitance in Ideal MOS Structure

• Oxide capacitance: as a ‐plate capacitor

 ox 2 Cox  F/cm dox • We can also write :

QM QM dQM Cox    VOX (VG VS ) d(VG VS ) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 18

Measurement of capacitance in Ideal MOS Structure

• Semiconductor (silicon) capacitance

 (charge in SC) d(QSC ) d(QM ) CSC     (voltage across SC) dVS dVS Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 19

Measurement of capacitance in Ideal MOS Structure

M O S Vg • Global capacitance of the structure: Vox VSC dQM dQSC CMOS    dVG dVG • If we combine the 3 relations above :

1 1 1    2 connected in series CMOS Cox CSC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 20

Measurement of capacitance in Ideal MOS Structure

• Total charge in SC depends on different regimes  2 types of charges, fixed and mobile/free:

QSC  free carriers charges  fixed charges  QS  Qdep

Semiconductor capacitance can be written as:

 dQsc  (dQS  dQdep ) dQS dQdep CSC      dVS dVS dVS dVS Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 21

Measurement of capacitance in Ideal MOS Structure

• Total charge in SC depends on different regimes  2 types of charges, fixed and mobile/free:

QSC  free carriers charges  fixed charges  QS  Qdep

Semiconductor capacitance can be written as:

 dQ sc C SC   C S  C dep dV S Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 22

Measurement of capacitance in Ideal MOS Structure

• Summary: MOS capacitor is equivalent : - of 2 capacitors series connected, COX and CSC - CSC equivalent of two capacitors - either of the two is variable and be view as 2 capacitors in //

C ox Cox

Csc Cs Cdep

Conclusion: the whole capacitance of MOS structure is function of bias conditions or operating regime through

CSC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 23

Capacitance of MOS structure

• Accumulation Regime: VS<0 ie VG<0 1 eV e(V 2 ) 2  S S FI  kT   SC 2  kT eVS kT n0  eVS  QSC    e  1 e   1  Qmetal  e  LD  kT p0  kT 

eV  S  SC 2 kT 2 kT Q SC  e  0 eL D

 dQSC e e CSC   QSC  Cox Vg VS dVs 2kT 2kT Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 24

Capacitance of MOS structure

• Accumulation Regime: VS<0 ie VG<0

1 eV eV 2  S S  kT   SC 2  kT eVS n0  kT eVS  QSC    e  1 e  1  Qmetal  e  LD  kT p0  kT 

C  2kT  ox 1 1  1 e  Csc C C  V V  MOS ox  g S  Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 25

Capacitance of MOS structure

• Accumulation Regime: VS<0 ie VG<0

1 eV eV 2  S S  kT   SC 2  kT eVS n0  kT eVS  QSC    e  1 e  1  Qmetal  e  LD  kT p0  kT 

 kT=26 meV, VS:‐0,3 V to ‐0,4 V in acc,  as soon as VG>‐1 to ‐2 V, CMOS = Cox

2 kT 1 1   1   1  e   C C  V  V  C MOS ox  g S  ox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 26

Capacitance of MOS structure

• Flat Band: VS =0 V ie VG=0 V (warning : ideal structure!!!!!)

 SC Analytical compute: CSC ( fb)  LD

  C ( fb)  ox   ox MOS  ox ox kT  SC dox  LD d   ox SC SC e eN A Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 27

Capacitance of MOS structure

• Depletion regime and weak inversion

0  VS  2 Fi

1 2 1 2εSC kT  eVS  2 QSC      2eN AεSCVS  Qdep  0 eLD  kT  1  dQ  eN ε  2 ε SC  A SC  SC CSC       dVS  2VS  Wdep

Wdep Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 28

Capacitance of MOS structure

• Depletion regime and weak inversion

0  VS  2 Fi  1 dQ  eN  2  C   SC   A SC   SC SC dV  2V  W S   S  dep   C C (depletion)  ox  ox MOS 2 ox 1 (2C V /  eN ) dox  Wdep ox g SC A SC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 29

Capacitance of MOS structure

• Strong inversion VS  2Fi

1 eV e(V 2 ) 2   S S FI  kT   SC 2  kT eV S kT n0  eVS  QSC    e  1 e   1  Qmetal  e  LD  kT p0  kT 

 e (V  2 )  e (V  2 ) S FI S  FI SC 2 kT 2 kT  2 kT Q SC   e   2 SC kTNa e  0 eL D  eV S  2 e FI  2 e  FI 2 kT 2 kT n 0 2 kT n 0 Q SC   2 SC kTNa e e et  e  p 0 Na

eV S 2 kT Q SC   2 SC kT n 0 e   2  SC kTn S Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 30

Capacitance of MOS structure

• Strong inversion VS  2Fi

1 eV e(V 2 ) 2  S S FI  kT   SC 2  kT eVS kT n0  eVS  QSC    e  1 e   1  Qmetal  e  LD  kT p0  kT 

e (V S  2  FI )  SC 2 kT 2 kT Q SC   e  0 eL D

 dQ  e(Vs 2FI ) 1 1 1 1 C  SC  SC e 2kT    SC C C C C dVs 2LD MOS ox SC ox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 31

Capacitance of MOS structure Strong inversion accumulation dep

???

p type SC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 32

Capacitance of MOS structure

• Strong inversion:

Which mechanism governs the onset of strong inversion layer?

 P type SC : we must create electrons at oxide/SC interface. Where they come from?  Metal : NO because oxide barrier  SC (neutral region) : NO minority carriers (e‐)

Only one solution: thermal (or optical) generation Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 33

Capacitance of MOS structure

• Strong inversion: • Thermal generation? • N°1 :In the space charge + of charge by electric field E F • N°2 : In the neutral region (a) recombination + + p ++ 0W + + + space charge diffusion zone zone semitransparent metal contact (b) metal p+ SiO 2 n n+

First mechanism dominates but it’s a slow (c) one. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 34

Capacitance of MOS structure

• Strong inversion • Which Delay time to create strong inversion layer ?

Shockley-Read equation n g  i Strong inversion limit: n = N th 2 S A m  N g   N   2 A  th S A S n m  i N Si: A 10 -3 More realistics S 1- 10  m ni=10 cm 15 -3 ni NA=10 cm s=1s !! -5 m=10 s Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 35

Capacitance of MOS structure

• When we measure C(V) , results depend on YES or NO, time is allowed to create this layer • YES: we measure capacitance du to inversion layer • NO : Depletion layer preserves the neutrality of the system with an increase of its width .

Results are dependant Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 36

Capacitance of MOS structure: strong inversion

3 cases :

Low frequency High frequency High frequency + + + Slow ramp Vg Slow ramp Vg High ramp Vg

Q Q Q

x x x Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 37 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 38

Capacitance of MOS structure: strong inversion

• minimum capacitance (HF):

BF   2 sc 4 sckT Wmax  2 Fi  2 ln(N A / ni ) eN A e N A HF

1 1 4kT ln(N A / ni )   2 Cmin Cox  sce N A Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 39

MOS capacitor : parasitic effects

• 2 factors modify « ideal » structure of MOS capacitor. • Charges in oxide and/or Charges at interface Oxide – SC. • Difference between work function of Metal and SC

Influence on the threshold voltage VT of the structure. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 40

MOS capacitor :oxide charge

• Distribution of charges in the oxide : K+ Na+ Ionic mobiles • Mobile ionic charge SiO2 • Oxide traped charge ----- traped • Fixed oxide charge + + + +

• Traped charge at Si-SiO2 interface + + + + + SiOx x x x x Si

Depending on their position in the oxide, the charges will influence more or less on the electron population below the gate. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 41

MOS capacitor :oxide charge

• Effect of a sheet charge of areal density Q within the oxide layer of an MOS capacitor: Q V =0V (x) Oxide charge are g compensated with a charge Metal Oxyde Si in Metal AND SC.

0 x1 x

Q Vg=Vfb (x) If Vg=Vfb, charge in SC must be zero. Only Metal « DO the job »

d x  ox xQox x Qox -Q Vg      ox d ox Cox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 42

MOS capacitor :oxide charge

• The effect is maximum when the charges are located at the interface oxide - SC, ie Qox=QSS (and zero effect if Qox close to Metal)

Qss x  d ox Vg   Cox It is a common practice to define an equivalent

oxide charge per unit area Qox located at the oxide – silicon interface:

Qox (VS ) Vg (VS )   VFB Cox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 43 Work function difference

• Work function difference  non zero oxide field.

• Even when Vg = 0 V, structure show a band bending

e

Depletion zone

A gate voltage must be applied to restore the flat band

condition  VFB = M – S = MS : this voltage is called Flat Band voltage VFB Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 44 Work function difference

• Work function difference. • Example: polysilicon n+ gate on p-MOS

 poly  e silicium  n  E   g  SC Silicium 2e fi

poly Eg kT Na MS    fi  0.56  ln( ) 2e e ni Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 45

Non ideal MOS capacitor

• Taking into account both Oxide charges and work- function difference, the global flat band voltage can be written as:

Qox VFB  MS  Cox

Warning: this is the voltage we have to apply on the gate to restore de flat band condition. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 46 Threshold voltage

• Key parameter for behavior understanding of transistor

• Many definitions (same results!):

• nS = NA

• Vs = 2 fi • … Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 47 Threshold voltage

VT is simply the gate voltage when the surface potential or band bending reaches 2FI and the silicon charge is equal to the bulk depletion charge for that potential

4 SCeN A Fi VT  Vg (VS  2 Fi )   2 Fi VFB (from slide 16) COX

V(X) (we suppose here that no bias of bulk is present  no V OX (V  0) body effect) FB VT VS=2FI

-tOX 0 X Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 48 Threshold voltage

• Substrate sensitivity - Body Effect

• In general the MOS devices have a common silicon substrate  substrate voltage is equal for all transistor.

• BUT when multiple NFETs (or PFETs) are connected in series in a circuit, they share a common body (the silicon substrate) but their sources do not have the same voltage. We introduce a coefficient that accounts for this effect : Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 49 Threshold voltage

>0 >0 +++++++ + +++++++++

-- - + + +

=0 <0 One part of Gate voltage is no more used to create inversion layer but just to

compensate the extra depletion width  VT will increase Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 50 Threshold voltage

• The new threshold voltage taking account the body effect can be written as:  2eN   A SC VT VT 0    2Fi VSB  2Fi  Cox • The substrate sensitivity as:

dVT 1 dQ  sceNa / 2(2 Fi VSB ) Q    et VT   dVSB Cox dVSB Cox Cox

• Of course substrate bias have to be reverse to prevent current flow Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 51 Threshold voltage

1,8 Na = 1E16 cm-3 Na = 3E15 cm-3 1,6 

(V) d  200 A ox

VFB  0V

T 1,4

1,2

1,0

Threshold voltage 0,8

0 2 4 6 8 10

Substrate bias voltage VSB (V) The effect of (reverse) substrate bias is to widen the bulk and raise the threshold voltage: • The back contact acts as a back Gate

• We can tune VT ! MOS-FET TRANSISTOR Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 53

MOS-FET transistor Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 54 Graphical summary of the major processing steps in the formation of a MOSFET Transistor

http://www.youtube.com/watch?v=dR-Qtv-7uWI Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 55

MOS-FET transistor

Stockage time ? Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 56 Linear regime Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 57 Saturation / linear limit Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 58

Saturation regime

Effective length of canal decreases from L to L’ Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 59

Basic MOSFET IV Model

• L, canal length( y oriented) • W, canal width(z oriented) • V, voltage in the canal (f(y))

• V(y=0) = V(source) = Vs = 0 V • V(y=L) = V (drain) = Vds • Vg, gate voltage

• -VBS, body voltage Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 60

Schematic MOSFET cross section (Taur) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 61

Charge sheet approximation

• Analytical solution  we simplify the model:

• Charge sheet approximation (xi=0): • We assume all the inversion charges are located at the silicon interface without any thickness • No potentiel drop across this layer • No band bending across this layer Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 62

Charge sheet approximation

First step: calculation of inversion layer charge function of Vg

Q dep  eN AW M   2eN A SC V S ( y)   2eN A SC (2 Fi  V ( y) )

Qsc (y)  Qmétal (y)  Cox (Vg VFB VS (y))  Cox (Vg VFB  2 Fi V (y))

Qinv  Qsc  Qdep  Cox (Vg VFB  2 Fi V (y))  2eN A SC (2 Fi V (y))

1 Q 2 Qinv Qsc dep Cox (Vg VFB  2 Fi V (y)) 2N A SC (2 Fi V (y)) nS (y)        e e e e  e  Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 63

Charge sheet approximation

• Using Ohm’s law:

Jn(z,y) = charge density X mobility X electric field

 dV I (y)  Q  W I dy  Q  dVW DS inv n dy Ds inv n

Integration from y = 0 to y = L, (source to drain) yield

L VDS I DS dy  nW  Qinv dV 0 0 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 64

Charge sheet approximation

After few simple steps:

W V I  C (V V  2  DS )V DS n L ox g FB Fi 2 DS 2 2 eN  3 3   sc A (2 V ) 2  (2 ) 2  Fi DS Fi  3 Cox  

‐2 ‐2 !! Cox is the oxide capacitance per surface unit (Fm ou Fcm )!! Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 65

Characteristics in the linear () region

When VDS is small (VDS << 2Fi) , one can expand the previous equation into power series in VDS and keep only first order term:

   W 4 sceN A Fi I DS  nCox (VGS V fb  2 Fi  )VDS L  Cox  W I   C (V V )V  DS n ox L GS T DS

We recognize threshold voltage VT. In the linear region, the MOSFET simply acts like a modulated by the gate voltage Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 66

Characteristics in the linear (triode) region

• For larger values of VDS we have to keep second order term (quadratic term) and a good approximation of current is:

W  m 2  I DS   nCox (Vgs VT )VDS  VDS  L  2 

 eN / 4 C 3d with m  1 sc A Fi  1 dm  1 ox Cox Cox Wm

Cdm is the bulk depletion capacitance in limit of strong inversion Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 67

Characteristics in the saturation region

• Previous equation is a parabole. Ids follows a parabolic curve with VDS until a maximun (or saturation) value is reached when VDS = Vdsat. (V V ) V  V  gs T D Dsat m

W (V V ) 2 I  I   C gs T DS Dsat n ox L 2m

In the case of thin oxide and low doping m can be reduced to 1 and Drain current yield the well known expression:

W 2 VDS I  I   C (V V ) DS Dsat n ox 2L gs T Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 68

Characteristics in the saturation region • Without any approximation (series expand,…), complete

expressions for IDSAT can be expressed as:   1  W 4 (eN   ) 2 I  µ C (V  2 )(V  2  2V  2V ) 12 (V V    A sc Fi ) dsat n 6L ox  Dsat Fi Dsat Fi gs FB Fi gs Fb Fi 3 C   ox 

sceN A 2 sceN A  sc eN A VDsat  Vgs VFB  2 Fi  2  2 (Vgs VFB  2 ) Cox Cox 2Cox

If we suppose high value for Cox (thin oxyde) and low doping level,

threshold voltage can be simplified as VT  2Fi VFB, and at the

same time we can rewrite Vdsat  Vgs VT  Vgs  2Fi VFB

VDsat  Vgs VT W W I  µ C (V V ) 2  µ C V 2 Dsat n 2L ox gs T n 2L ox Dsat Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 69

Subthreshold characteristics – weak inversion region

• Three regimes: • Triode (Linear) • Saturation

• OFF state (if Vg < VT for nMOS) • Transition ON /OFF is not so sharp

• Weak inversion for fi

MOSFET basics

• Subthreshold current : « OFF » is not totally « OFF »

• Previous analysis  VGS

∞ 0

with , a ideality (or nonideality) factor (≥1) • Remember that changes by 10 for every x60 mV change in VGS. • Typically, if IDS decreases for one decade , then VGS must decrease by at least x60 mV (in fact around 80 mV, ) (at 300K!). Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 71

MOSFET basics

• For example: Subthreshold current : 0 (for VGS

log IDS Exponential Quadratic

• 0,3V/80 mV=3,75 ION

1 decade IOFF

~80 mV 3,75 •ION/IOFF = 10 ~ 5600 V VT3 T1 V 7 GS • If VT=0,6V, ION/IOFF >10 !! VT2 OF COURSE WE WANT  CLOSE TO UNITY Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 72

Short channel

• Threshold voltage reduction • Drain Induced Barrier Lowering (DIBL) • Channel length modulation • MOSFETs breakdown • … Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 73

Threshold voltage reduction: short channel effect (Kang et al)

• Origin:

• Previous VT expression supposes channel depletion region comes only from gate • In fact one part is created by depletion region associated by source/channel and drain/channel pn junctions • Overestimation of charge induced by

gate  overestimation of VT

• This reduction more prominent for MOSFET with shorter channel length

VT (shortchannel)  VT 0 (longchannel)  VT 0 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 74

Threshold voltage reduction: short channel effect (Kang et al)

• Origin:

• Previous VT expression supposes channel depletion region comes only from gate • In fact one part is created by depletion region associated by source/channel and drain/channel pn junctions • Overestimation of charge induced by

gate  overestimation of VT

• This reduction more prominent for MOSFET with shorter channel length

VT (shortchannel)  VT 0 (longchannel)  VT 0 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 75

Threshold voltage reduction: short channel effect (Kang et al)

2 Si 2 Si xdS  Vbi xdD  (Vbi VDS ) eN A eN A

 2x  L  x . 1 dS ,D 1 S ,D j  x   j 

1  x  2x   2x  V  4e N  j  1 dS 1   1 dD 1 T 0 C Si A Fi 2L  x   x  ox  j   j  Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 76

Threshold voltage reduction: short channel effect (Kang et al)

0,9 VT0 0,8 • Threshold voltage is (V) 0,7 function of: • Channel length 0,6 • Drain –Source voltageVds 0,5 through xdD 0,4 Threshold voltage

0,3 0 1 2 3 4 5 6 Channel Length (µm) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 77

Drain Induced Barrier Lowering (DIBL) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 78

Channel length modulation (saturation operation)

• At the onset of -off (VDS>VDSAT), the effective channel length (the length of inversion layer) is reduced.

L L I  I 1  1 VDS D Dsat L L  L(VDS )

If VDS 1

µ C W I (sat)  n ox (V V )2 (1 V ) D 2 L GS T DS Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 79

MOSFET Breakdown

• 2 main effects: • punchthrough breakdown • Punch through in a MOSFET is an extreme case of channel length modulation where the depletion layers around the drain and source regions merge into a single depletion region. • Punch through causes a rapidly increasing current with increasing drain‐source voltage • No current saturation • Impact ionisation at the drain: • Electron acceleration in the channel • Impact ionisation  holes electrons pairs generated • Holes collected by substrate  substrate current  in the channel • Reduction of VT ( body effect) • Increase of current and so on ! • Permanent dammage Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 80

MOSFET capacitances

• Difficulties: • In general, capacitances associated with MOS circuits are complicated function of geometries and process • Not lumped capacitances but distributed capacitances

• In the following, first approximation model • Sufficiently accurate to represent main characteristics of MOSFET charge voltage behavior • All the capacitances are lumped • Three differents physical origins • Overlay capacitance • Oxyde capacitance • Junction capacitance

Important point : capacitances are dependent of bias voltage / working point. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 81

MOSFET capacitances

• Overlay capacitances:

• LD, gate – drain and gate – source overlay

• LM, mask length

L=LM ‐ 2.LD gate

LD LD W (n+)(nL +) CGS (overlap) = Cox .W.LD

CGD (overlap) = Cox .W.LD LM εox Cox = dox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 82

MOSFET capacitances

Lumped representation of Equivalent model (with overlap parasistics capacitances capacitances)

Cgb D

Cdb Cgd MOSFET GB(DC Model)

Cgs Csb Cd b S Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 83 Gate – Channel capacitances

• Cut off mode:

Cgs = Cgd = 0 Cgb = CoxWL • Linear mode = =1 Cgs Cgd CoxWL = 2 Cgb 0 (chanel shields substrate) canal • Saturation mode 2 C  C WL,C  0 gs 3 ox gd

Cgb  0 (chanel shields substrate) canal Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 84

Oxyde capacitance

Capacitance Cut off Linear saturation

Cgb(total) CoxWL 00

1 Cgd(total) CoxWLD C WL  C WL C WL 2 ox ox D ox D C (total) C WL 1 2 gs ox D C WL  C WL C WL  C WL 2 ox ox D 3 ox ox D Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 85

Dynamic characteristics (1)

• Conductance:   I D W 2 sc Na gD   µn Cox Vgs VFB  2 Fi VDS  VDS  2 Fi  VD L Cox Vg cte   • Linear mode

µnW • Saturation mode g  C (V V ) Dlin L ox gs T

µ C W  g  0 ou g  n ox (V V )²  I Dsat Dsat 2L gs T D Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 86

Dynamic characteristics (2)

 transconductance: device speed  linear

µ W g  n C V mlin L ox DS

 « active region »

µnW W 2I Dsat gmsat  Cox (Vgs VT )  2µnCox I Dsat  L L (Vgs VT ) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 87 HF Caracteristics

• Cut off frequency current gain = 1

Iin  jωCGSVg  jωCGD (VG VD )

VD  gmVg  jωCGD (VD VG )  0 RL   1 g R   m L  Iin  jωCGS  CGD  VG  1 jωRLCGD 

If we neglect jRLCgd (small)

Iin  jωCGS  CGD (1 gm RL ) VG

Iin  jωCGS  CM VG

CM : Miller capacitance Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 88 HF Caracteristics

I = I = g V out D m gs Iin = Iout

gm fT  2π(CGS  CM )

If CM = 0  cut off frequency is maximum (saturation mode):

µn (VG -VT ) vs f  or (if short chanel and/or vsat ) f  T max 2πL2 T max 2πL Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 89 HF Caracteristics

• An other figure of merit : power gain =1  oscillation frequency

fT fmax  4Rg (gd  ωT Cgd )

Rg: gate resistance Rs : negligeable

Ref: (Tsividis) MOS INVERTERS

Statics characteristics Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 91 ideal Inverter : definition

• Input voltage: Vin

• Output voltage: Vout • Inverter threshold Vertical drop in voltage:Vth=VDD/2 ideal case • Logic « 1 » output :

• 0

• Vth

NMOS Inverter: general circuit structure

• Load: active (MOS) or passive

(resistor) I DS (Vin ,Vout )  I L (VL ) • «driver»

• Cload :lumped capacitance • Input Voltage: Vin=Vgs • Output Voltage: Vout=Vds

• DC domain: no input current neither output current

• Kirchoff’s current law: ILOAD(VL) = IDS(Vin, Vout) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 93

Inverter: voltage transfer characteristics

• With analytical solving

IDS ( Vin ,Vout )=IL( VL ) we found the VTC characteristics:

Vout = f ( Vin ) • Keys :

• VIL : maximum input voltage wich can be interpreted as a « 0 » logic input

• VIH : minimum input voltage wich can be interpreted as a « 1 » logic input

• VOL : minimun ouput voltage when the output level is logic « 0 »

• VOH : maximum ouput voltage when the output level is logic « 1 » Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 94

Inverters: noise margins

• Interconnexions and gate noise can add parasitics voltage  logic faults . We introduce for quantify the noise immunity of the circuit the «noise margins ». • The noise immunity increases with the noise margins Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 95

Inverters: noise margins

’ NM H  VOH VIH VOH

NM L  VIL VOL

Uncertainty region must be

’ reduce if we have VIL~VIH VOL  VTC close to ideal inverter Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 96

Inverters: brief summary

• Preceding discussions of inverter static (DC) characteristics shows: • Shape of the VTC in general • Noise immunity are very important criteria for design priorities.

For any inverter circuit five critical points (VIL, VIH,…) fully determine these properties

Accurate estimation of these voltage points have to be determined. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 97

Resistive-load Inverter

• Vin=VGS

• Vin=« 1 »: n-MOS is ON  at first order, Drain grounded V = «0» out RL

• Vin=« 0 »: n-MOS is OFF  open circuit  IL = IDS = 0  Vout= VDD= «1»

CL Input Voltage Operating Range Mode

Vin

VT0

Vin>Vout+VT0 Linear Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 98

Resistive-load Inverter : VTC

10

RL=36 k 8 RL=50 k

6

4

2

0 -4 -3 -2 -1 0 1

VDD Vout I L   I DS RL Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 99

Resistive-load Inverter : VTC

VOH  VDD

1 1 2 2VDD VOL  VDD VTn   (VDD VTn  )  kn RL kn RL kn RL 1 VIL  VTn  kn RL

8 VDD 1 VIH  VTn   3 kn RL kn RL

( good exercise ! ) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 100

Saturated enhancement-type nMOS Inverters :

• VGS = VDS  VGS ‐VT < VDS  saturation mode

• Warning : if Vout>VDD‐VT  cut‐off VOH=VDD‐VT Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 101 Saturated enhancement-type nMOS Inverters : graphic analysis

VGS The representative Non linear points of the load line resistance are given by :

VGS = VDS

The load NMOS is equivalent to a non linear resistance

VDS Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 102 Saturated enhancement-type nMOS Inverters : graphic analysis

ID2, µA Load VDS1=VDD -VDS2 = 6 - VDS2

Driver

75

VDS2 4

75

VDS1 = 6 – 4 = 2 V 2 ID2 = 75 µA = ID1 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 103 Saturated enhancement-type nMOS Inverters : graphic analysis

B 75

2

NMH = VOH ‐VIH = ‐0.2 V <0 By changing the ratio W/L, we can improve NM. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 104 Inverter with linear enhancement type load Load transistor never in saturation mode:

 VGS,load –VT,load >VDS,load (1)

VGS,load –VDS,load = VGG –VDD

 (1) OK  VGG –VDD >VT,load

non saturated load

drawback : 2 separate voltage !! Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 105 Inverter with linear enhancement type load

VGG = +9V VDD = +6V

T2

Load resistance

VDS1 T1

VGS1

VGS2 -VDS2 =VGG –VDD = 3V

V = V –3V Load DS2 GS2 resistance Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 106 Inverter with linear enhancement type load

VDS1 = 6 – VDS2 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 107

Depletion Load NMOS inverter

VDD = +6V Vin Vout Driver load

VOL VOH Cut off Linear

VIL ~VOH Saturation Linear

VIH small Linear Saturation

VOH VOL linear saturation

Driver : enhancement  VT,Driver >0 Load : depletion  VT,load <0  VGS,load =0 >VT,load

VSB,load = VDS,pilote = Vout  VT,load sensitive to body effect

VT ,load (Vout ) VT 0    2 Fi Vout  2 Fi  Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 108

Depletion Load NMOS inverter

VDS2 = 0 V, IDS2 = 0 µA

VDS1 = 6 – 0 = 6 V

VDS2 = 3 V, IDS2 = 22 µA

VDS1 = 6 – 3 = 3 V Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 109

Depletion Load NMOS inverter

VOH  VDD )

2 2 kload VOL  VOH VTO,driver  (VOH VTO,driver )  VT ,load (VOL ) kdriver

exercise! kload

VIL  VT ,driver  Vout VDD  VT ,load (Vout ) kdriver good kload dVT ,load ( VIH  VT ,driver  2Vout   VT ,load (Vout ) kdriver dVout

Drawback (compare to enhancement load Inverter):

• Additional processing step (VT adjust for load)

Advantages (compare to enhancement load Inverter): • Sharp VTC transition • Better noise margins • Single power supply • Smaller layout area Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 110 Depletion Load NMOS inverter: power considerations

• Vin = 0 et Vout = VOH  driver is cut off  IDS=0. No power

• Vin= VDD et Vout = VOL  both transistors ON  large current

I DC (Vin  VDD )  I load (sat)  I driver (lin) 50% of time logic« 1 » V k P  DD load V (V ) 2 unacceptable DC 2 2 T ,load OL Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 111

C-MOS inverter

• All previous Inverters are based on : • enhancement driver NMOS • a load wich can be a resitor, an enhancement or depletion NMOS.

• Major drawback: in one state (output level « 0 ») DC comsuption or power dissipation nonzero

• New concept /design :

• One enhancement NMOS and one enhancement PMOS (Complementary MOS or CMOS). • Depending on input Voltage, NMOS is the load and PMOS the driver and vice versa.

• Advantages: • No DC ( steady state) power dissipation ( except current)

• Full output voltage swing between VDD and 0 • Very sharp VTC transition : very close to ideal inverter Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 112 C-MOS inverter

S

D

D

S

VGS,p ‐(VDD –Vin)

VDS,p ‐(VDD –Vout)

VGS,n Vin

VDS,n Vout Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 113 C-MOS inverter

The structure complexity of CMOS is the price to be paid for the improvements achieved in power consumption and the noise margins Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 114 C-MOS inverter

• careful! VTn > 0 et VTp < 0 st • 1 case: Vin < VTn

• VGS,n < VTn  nMOS cut off zero current

• VGS,p < VTp  pMOS ‘ON ‘ Vout = VDD = VOH

nd • 2 case: Vin > VDD + VTp

• VGS,n > VTn  nMOS ‘ON ’ zero current

• VGS,p > VTp  pMOS cutoff Vout = VOL  0 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 115 C-MOS inverter Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 116 C-MOS inverter

Region Vin Vout nMOS pMOS

A < VTn VOH Cut off linear

B VIL «1» VOH Saturation linear

C Vth Vth Saturation Saturation

D VIH «0» VOL linear Saturation

E > (VDD + VT,p )VOL linear Cut off

Consumption zone when switching Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 117 C-MOS inverter

V OH  V DD

V OL  0 2V  V  V  k V out T , p DD R T , n V IL  1  k R

V DD  V T , p  k R .( 2V out  V T , n ) V IH  1  k R 1 V  (V  V ) T ,n k DD T , p V  r th 1 (1  ) k r

k n W k R  k  µC ox k p L Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 118 C-MOS inverter: switching characteristics Interconnect effects

Cint represents the between the two inverters Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 119 C-MOS inverter: switching characteristics

• To simplify the problem, all the capacitances are combined into a unique lumped linear capacitance Cload

• The question of inverter transient response is reduced to finding the charge‐up and charge‐down time of a Cload single capacitance which is charged and discharged through a transistor (NMOS or PMOS).

Cload  Cgd ,n  Cgd , p  Cdb,n  Cdb, p  Cint  Cg Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 120 C-MOS inverter: switching characteristics

• Delay-time or Propagation-time:

PLH : delay time from « 0 » to «1».

PHL : delay time from « 1 » to «0».

The average propagation delay time :     PHL PLH P 2 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 121 C-MOS inverter: switching characteristics

• Output voltage Rise and Fall time:

VOH

V10% VOL  0.1(VO H VOL )

VOL V90% VOL  0.9(VOH VO L )  fall  tB  tA

 rise  tD  tC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 122 C-MOS inverter: switching characteristics Calculation of delay times:

dV C out  i  i  i load dt C D, p D,n Fall time calculation:

•Vin from VOL to VOH • nMOS is turned ‘ON’ and it

starts to discharge Cload •pMOS is switched off ID,p 0

dV C out  i load dt D,n Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 123 C-MOS inverter: switching characteristics

Be carefull : during the switching, operating mode of MOS changes !!

In our case , we have to decompose the calcul in two delay‐times

NMOS in saturation ?

VGSn –VTN < VDS  Vin-VTN

• After few steps

C  2V  4(V V )  load T ,n  OH T ,n   PHL    ln 1 kn (VOH VT ,n ) VOH VT ,n  VOH VOL 

 2V  2(V V  V )  Cload T , p  OH OL T , p   PLH    ln 1  k (V V  V ) V V  V  V V  p OH OL T , p  OH OL T , p  OH 50%  Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 125 C-MOS inverter: switching characteristics

Power dissipation for a gate CMOS during switching : this is the power used to charge and discharge the capacitance

Cload.

1 T P  v(t).i(t)dt avg  T 0

2 Pavg  CloadVDD f Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 126 C-MOS inverter: switching characteristics

Another source of power consumption: the short‐circuit current, ie a direct pathway from power supply to through PMOS and NMOS, both of them being in ON state. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 127

bibliographic references

• S.M. Sze « Physics of devices », 2° edition, Wiley and Sons, New York, 1981 • H.Mathieu, « Physique des semi-conducteurs et des composants électroniques », 4° edition, Masson 1998. • J. Singh, « semiconductors devices : an introduction », McGraw-Hill, Inc 1994 • Y.Taur et T.H. Ning, « Fundamentals of Modern VLSI devices », Cambridge University Press, 1998. • K.K. Ng, « complete guide to semiconductor devices », McGraw-Hill, Inc, 1995 • E. H. Nicollian et J. R. Brews, « MOS Physics and », John Wiley and Sons, 1982 • S.M. Kang et Y. Leblebici, « CMOS Digital Integrated Circuits : analysis and design », Mc Graw Hill, 2° edition., 1999 • J. Millman et A. Grabel, « microelectronique », Mc Graw Hill, 1995 • Chenming C. Hu “ Modern Semiconductor Devices for Integrated Circuits”, Prentice Hall, 2009

Figures and tables mainly from these references MERCI! THANK YOU FOR YOUR ATTENTION! 感谢您的关注