Élan™SC520 Microcontroller Register Set Manual
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Élan™SC520 Microcontroller Register Set Manual Order #22005B © 2001 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci- fications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any in- tellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. 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Élan™SC520 Microcontroller Register Set Manual iii iv Élan™SC520 Microcontroller Register Set Manual TABLE OF CONTENTS PREFACE INTRODUCTION XV Élan™SC520 Microcontroller. .xv Purpose of this Manual . .xv Intended Audience . .xv Overview of this Manual . .xv Related Documents . xvi AMD Documentation . xvi Additional Information . xvii Documentation Conventions . xviii CHAPTER 1 CONFIGURATION REGISTER OVERVIEW 1-1 1.1 Memory-Mapped Configuration Region (MMCR) Registers. 1-1 1.2 Direct-Mapped I/O Registers . 1-7 1.3 PCI Host Bridge Indexed Configuration Registers . 1-10 1.4 RTC and CMOS RAM Indexed Registers. 1-11 CHAPTER 2 SYSTEM ADDRESS MAPPING REGISTERS 2-1 2.1 Overview. 2-1 2.2 Registers . 2-1 Address Decode Control (ADDDECCTL). 2-2 Write-Protect Violation Status (WPVSTA) . 2-4 Programmable Address Region 0 (PAR0) . 2-5 Programmable Address Region 1 (PAR1) . 2-5 Programmable Address Region 2 (PAR2) . 2-5 Programmable Address Region 3 (PAR3) . 2-5 Programmable Address Region 4 (PAR4) . 2-5 Programmable Address Region 5 (PAR5) . 2-5 Programmable Address Region 6 (PAR6) . 2-5 Programmable Address Region 7 (PAR7) . 2-5 Programmable Address Region 8 (PAR8) . 2-5 Programmable Address Region 9 (PAR9) . 2-5 Programmable Address Region 10 (PAR10) . 2-5 Programmable Address Region 11 (PAR11) . 2-5 Programmable Address Region 12 (PAR12) . 2-5 Programmable Address Region 13 (PAR13) . 2-5 Programmable Address Region 14 (PAR14) . 2-5 Programmable Address Region 15 (PAR15) . 2-5 Configuration Base Address (CBAR) . 2-9 CHAPTER 3 RESET GENERATION REGISTERS 3-1 3.1 Overview. 3-1 3.2 Registers . 3-1 System Board Information (SYSINFO). 3-2 Reset Configuration (RESCFG) . 3-3 Reset Status (RESSTA) . 3-5 SCP Data Port (SCPDATA). 3-7 SCP Command Port (SCPCMD) . 3-8 System Control Port A (SYSCTLA) . 3-9 Élan™SC520 Microcontroller Register Set Manual v Table of Contents ® CHAPTER 4 Am5X86 CPU REGISTERS 4-1 4.1 Overview. 4-1 4.2 Registers . 4-1 Élan™SC520 Microcontroller Revision ID (REVID) . 4-2 Am5x86® CPU Control (CPUCTL) . 4-3 CHAPTER 5 SYSTEM ARBITRATION REGISTERS 5-1 5.1 Overview. 5-1 5.2 Registers . 5-1 System Arbiter Control (SYSARBCTL) . 5-2 PCI Bus Arbiter Status (PCIARBSTA) . 5-3 System Arbiter Master Enable (SYSARBMENB) . 5-4 Arbiter Priority Control (ARBPRICTL) . 5-6 CHAPTER 6 PCI BUS HOST BRIDGE REGISTERS 6-1 6.1 Overview. 6-1 6.2 Registers . 6-1 Host Bridge Control (HBCTL). 6-3 Host Bridge Target Interrupt Control (HBTGTIRQCTL) . 6-5 Host Bridge Target Interrupt Status (HBTGTIRQSTA) . 6-7 Host Bridge Master Interrupt Control (HBMSTIRQCTL) . 6-9 Host Bridge Master Interrupt Status (HBMSTIRQSTA) . 6-12 Host Bridge Master Interrupt Address (MSTINTADD) . 6-14 PCI Configuration Address (PCICFGADR) . 6-15 PCI Configuration Data (PCICFGDATA). 6-17 Device/Vendor ID (PCIDEVID) . 6-18 Status/Command (PCISTACMD) . 6-19 Class Code/Revision ID (PCICCREVID) . 6-22 Header Type (PCIHEADTYPE) . 6-23 Master Retry Time-Out (PCIMRETRYTO) . 6-24 CHAPTER 7 SDRAM CONTROLLER REGISTERS 7-1 7.1 Overview. 7-1 7.2 Registers . 7-1 SDRAM Control (DRCCTL) . 7-2 SDRAM Timing Control (DRCTMCTL). 7-4 SDRAM Bank Configuration (DRCCFG) . 7-5 SDRAM Bank 0–3 Ending Address (DRCBENDADR) . 7-7 ECC Control (ECCCTL) . 7-9 ECC Status (ECCSTA) . 7-10 ECC Check Bit Position (ECCCKBPOS) . 7-11 ECC Check Code Test (ECCCKTEST) . 7-12 ECC Single-Bit Error Address (ECCSBADD). 7-14 ECC Multi-Bit Error Address (ECCMBADD). 7-15 CHAPTER 8 WRITE BUFFER AND READ BUFFER REGISTER 8-1 8.1 Overview. 8-1 8.2 Register . ..