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Am5 86™ Microprocessor Family

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Am5 86™ Microprocessor Family PRELIMINARY Am5 86™ Advanced X Micro Microprocessor Family Devices DISTINCTIVE CHARACTERISTICS ■ High-Performance Design ■ Complete 32-Bit Architecture — Industry-standard write-back cache support — Address and data buses — Frequent instructions execute in one clock — All registers — 105.6-million bytes/second burst bus at 33 MHz — 8-, 16-, and 32-bit data types — Flexible write-through and write-back address ■ Standard Features control — 3-V core with 5-V tolerant I/O µ — Advanced 0.35- CMOS-process technology — Available in a 133-MHz version — Dynamic bus sizing for 8-, 16-, and 32-bit buses — Binary compatible with all Am486®DX, — Supports “soft reset” capability Am486DX2, and Am486DX4 microprocessors ■ High On-Chip Integration — Wide range of chipsets and support available — 16-Kbyte unified code and data cache through the AMD FusionPCSM Program ■ — Floating-point unit 168-pin PGA package or 208-pin SQFP package — Paged, virtual memory management ■ IEEE 1149.1 JTAG Boundary-Scan Compatibility ■ Enhanced System and Power Management ■ Supports Environmental Protection Agency's — Stop clock control for reduced power Energy Star program consumption — 3-V operation reduces power consumption up to — Industry-standard two-pin System Management 40% Interrupt (SMI) for power management indepen- — Energy management capability provides excel- dent of processor operating mode and operating lent base for energy-efficient design system — Works with a variety of energy-efficient, power- — Static design with Auto Halt power-down support managed devices — Wide range of chipsets supporting SMM avail- able to allow product differentiation GENERAL DESCRIPTION Table 1. Clocking Options The Am5X86™ microprocessor is an addition to the AMD microprocessor product family. The new processor en- Operating Input Clock Available Package hances system performance by raising the microproces- Frequency sor operating frequency to the highest levels allowed by 133 MHz 33 MHz 168-pin PGA current manufacturing technology, while maintaining complete compatibility with the standard Am486 proces- 133 MHz 33 MHz 208-pin SQFP sor architecture and Microsoft® Windows®. The CPUs The Am5X86 microprocessor family allows write-back incorporate write-back cache, flexible clock control, and configuration through software and cacheable access enhanced SMM. Table 1 shows available processors control. On-chip cache lines are configurable as either in the Am5X86 microprocessor family. write-through or write-back. The CPU clock control fea- ture permits the CPU clock to be stopped under con- trolled conditions, allowing reduced power consumption during system inactivity. The SMM function is implement- ed with an industry standard two-pin interface. This document contains information on a product under development at Advanced Micro Devices. The information is Publication # 19751 Rev: C Amendment/0 intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Issue Date: March 1996 AMD PRELIMINARY BLOCK DIAGRAM 2Am5X86 Microprocessor PRELIMINARY AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AMD-X5 – 133 A D W Case Temperature W= 55° C Z = 85° C Operating Voltage D= 3.45 V F= 3.3 V Package Type A =168-pin PGA S = 208-pin SQFP Clock Speed 133 = 133 MHz Family/Core AMD-X5 Valid Combinations Case Temperature Valid Combinations OPN Package Type Operating Voltage (Max) Valid Combinations list configura- tions planned to be supported in vol- AMD-X5-133ADW PGA 3.45 V 55° C ume for this device. Consult the local AMD-X5-133ADZ PGA 3.45 V 85° C AMD sales office to confirm avail- ability of specific valid combinations AMD-X5-133SFZ SQFP 3.3 V 85° C and to check on newly released AMD-X5-133SDZ SQFP 3.45 V 85° C combinations. Am5X86 Microprocessor 3 AMD PRELIMINARY Table of Contents 1 Connection Diagrams and Pin Designations ......................................................................................... 8 1.1 168-Pin PGA (Pin Grid Array) Package .......................................................................................... 8 1.2 168-Pin PGA Designations (Functional Grouping) ......................................................................... 9 1.3 208-Pin SQFP (Shrink Quad Flat Pack) Package ........................................................................ 10 1.4 208-Pin SQFP Designations (Functional Grouping) ..................................................................... 11 2 Logic Symbol ...................................................................................................................................... 12 3 Pin Description .................................................................................................................................... 13 4 Functional Description ........................................................................................................................ 18 4.1 Overview ....................................................................................................................................... 18 4.2 Memory ......................................................................................................................................... 18 4.3 Modes of Operation ...................................................................................................................... 18 4.3.1 Real mode ........................................................................................................................... 18 4.3.2 Virtual mode ........................................................................................................................ 18 4.3.3 Protected mode ................................................................................................................... 18 4.3.4 System Management mode ................................................................................................ 18 4.4 Cache Architecture ....................................................................................................................... 18 4.4.1 Write-Through Cache .......................................................................................................... 18 4.4.2 Write-Back Cache ............................................................................................................... 18 4.5 Write-Back Cache Protocol ........................................................................................................... 19 4.5.1 Cache Line Overview .......................................................................................................... 19 4.5.2 Line Status and Line State .................................................................................................. 19 4.5.2.1 Invalid ......................................................................................................................... 19 4.5.2.2 Exclusive .................................................................................................................... 19 4.5.2.3 Shared ....................................................................................................................... 19 4.5.2.4 Modified ..................................................................................................................... 19 4.6 Cache Replacement Description .................................................................................................. 20 4.7 Memory Configuration ................................................................................................................... 20 4.7.1 Cacheability ......................................................................................................................... 20 4.7.2 Write-Through/Write-Back ................................................................................................... 20 4.8 Cache Functionality in Write-Back mode ...................................................................................... 20 4.8.1 Processor-Initiated Cache Functions and State Transitions ............................................... 20 4.8.2 Snooping Actions and State Transitions ............................................................................. 21 4.8.2.1 Difference between Snooping Access Cases ............................................................ 21 4.8.2.2 HOLD Bus Arbitration Implementation ....................................................................... 22 4.8.2.2.1 Processor-Induced Bus Cycles ........................................................................ 22 4.8.2.2.2 External Read ................................................................................................... 22 4.8.2.2.3 External Write ................................................................................................... 22 4.8.2.2.4 HOLD/HLDA External Access TIming .............................................................. 22 4.8.3 External Bus Master Snooping Actions ............................................................................... 25 4.8.3.1 Snoop Miss ................................................................................................................. 25 4.8.3.2 Snoop Hit to a Non-Modified Line .............................................................................. 25 4.8.4 Write-Back Case ................................................................................................................
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