Elansc520 Microcontroller User's Manual
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Élan™SC520 Microcontroller User’s Manual Order #22004A © 1999 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci- fications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any in- tellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. 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Élan™SC520 Microcontroller User’s Manual iii iv Élan™SC520 Microcontroller User’s Manual TABLE OF CONTENTS PREFACE INTRODUCTION xxiii Élan™SC520 Microcontroller. xxiii Purpose of this Manual . xxiii Intended Audience . xxiii Overview of this Manual . xxiii Related Documents . xxiv AMD Documentation . xxiv Additional Information . .xxv Documentation Conventions . .xxv CHAPTER 1 ARCHITECTURAL OVERVIEW 1-1 1.1 ÉlanSC520 Microcontroller. 1-1 1.1.1 Distinctive Characteristics . 1-1 1.2 Block Diagram . 1-2 1.3 Architectural Overview . 1-4 1.3.1 Industry-Standard x86 Architecture . 1-4 1.3.2 AMDebug™ Technology for Advanced Debugging . 1-4 1.3.3 Industry-Standard PCI Bus Interface. 1-5 1.3.4 High-Performance SDRAM Controller . 1-5 1.3.5 ROM/Flash Controller . 1-5 1.3.6 Flexible Address-Mapping . 1-5 1.3.7 Easy-to-Use General-Purpose (GP) Bus Interface . 1-6 1.3.8 Clock Generation . 1-6 1.3.9 Integrated Peripherals . 1-7 1.3.10 JTAG Boundary Scan Test Interface . 1-7 1.3.11 System Testing and Debugging Features . 1-8 1.4 Applications . 1-8 1.4.1 Smart Residential Gateway . 1-8 1.4.2 Thin Client . 1-8 1.4.3 Digital Set Top Box . 1-9 1.4.4 Telephone Line Concentrator . 1-9 CHAPTER 2 PIN INFORMATION 2-1 2.1 Overview . 2-1 2.2 Logic Symbols . 2-1 2.3 Signal Descriptions. 2-4 CHAPTER 3 SYSTEM INITIALIZATION 3-1 3.1 Overview . 3-1 3.1.1 Native Embedded Initialization Sequence . 3-1 3.1.2 BIOS Initialization Sequence . 3-3 3.1.3 Memory-Mapped Configuration Region (MMCR) . 3-3 3.1.4 Reset Event . 3-4 3.1.5 Reset Vector and Reset Segment . 3-5 3.2 Configuring the SDRAM Controller . 3-6 3.3 Identifying the CPU Core . 3-7 3.4 Setting the CPU Speed . 3-7 3.5 Configuring External GP Bus Devices . 3-7 3.6 Configuring the Pin Multiplexing. 3-8 3.7 Configuring the Programmable Address Region (PAR) Registers . 3-8 3.7.1 Specifying Pages and Regions . 3-9 Élan™SC520 Microcontroller User’s Manual v Table of Contents 3.7.2 Address Region Attributes. 3-12 3.7.2.1 Write-Protect Attribute . 3-12 3.7.2.2 Cacheability Control Attribute . 3-12 3.7.2.3 Code Execution Attribute . 3-12 3.7.2.4 Performance Considerations . 3-12 3.7.3 PAR Register Priority. 3-13 3.7.4 External GP Bus Devices . 3-13 3.7.4.1 Single Device (an A/D Converter) Using One Chip Select. 3-14 3.7.4.2 Single Device That Performs Its Own Decode. 3-14 3.7.4.3 Multiple Devices On One Chip Select . 3-14 3.7.5 PCI Bus Devices . 3-15 3.7.5.1 VGA Controller on the PCI Bus . 3-15 3.7.5.2 Network Adapter for Remote Program Loading. 3-16 3.7.6 External ROM Devices . 3-17 3.7.6.1 Boot ROM Device Mapping for BIOS Shadowing . 3-17 3.7.6.2 Two Banks of Flash for an Execute-In-Place (XIP) Operating System . 3-17 3.7.7 SDRAM Regions . 3-18 3.7.7.1 Setting Up DMA Buffers. 3-18 3.7.7.2 Write-Protected Code Segments . 3-18 3.8 Configuring the Interrupt Mapping . 3-19 3.8.1 Edge-Sensitive or Level-Triggered Interrupts . 3-19 3.8.2 Interrupt Mapping . 3-19 3.8.3 Interrupt Polarity . 3-20 3.9 Configuring the Programmable I/O Pins. 3-20 3.10 Configuring the PCI Host Bridge and Arbitration . 3-20 3.11 Disabling Internal Peripherals . 3-21 CHAPTER 4 SYSTEM ADDRESS MAPPING 4-1 4.1 Overview . 4-1 4.2 Registers . 4-2 4.3 Operation . 4-3 4.3.1 Programming External Memory, Buses, and Chip Selects . 4-4 4.3.2 Programmable Address Region (PAR) Registers . 4-5 4.3.3 Memory Space . 4-7 4.3.3.1 SDRAM Space. 4-8 4.3.3.2 ROM/Flash Space . 4-8 4.3.3.3 GP Bus Memory Space . 4-9 4.3.3.4 PCI Bus Memory Space. 4-9 4.3.3.5 Memory-Mapped Configuration Region (MMCR) Registers Space. 4-9 4.3.4 I/O Space . 4-10 4.3.4.1 Configuration Base Address (CBAR) Register . 4-11 4.3.4.2 PCI Configuration Space . ..