Am486 Microprocessor PCI Customer Development Platform User's Manual

Am486® Microprocessor PCI Customer Development Platform User’s Manual

Order #22408A

Am486® Microprocessor PCI Customer Development Platform User’s Manual

© 1998 by Advanced Micro Devices, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Advanced Micro Devices, Inc.

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AMD, the AMD logo, and combinations thereof, Comm86, E86, E86MON, and PCnet are trademarks of, Am486, MACH, and PAL are registered trademarks of, and FusionE86 is a service mark of Advanced Micro Devices, Inc. Vantis is a trademark of Vantis Corporation. Microsoft and Windows are registered trademarks of Microsoft Corp. Other product or brand names are used solely for identification and may be the trademarks or registered trademarks of their respective companies. IF YOU HAVE QUESTIONS, WE’RE HERE TO HELP YOU. The AMD customer service network includes U.S. offices, international offices, and a customer training center. Technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86™ and Comm86™ microcontroller family hardware and software development questions. Frequently accessed numbers are listed below. Additional contact information is listed on the back of this manual. AMD’s WWW site lists the latest phone numbers.

Technical Support Answers to technical questions are available online, through e-mail, and by telephone. Go to AMD’s home page at www.amd.com and follow the Service link for the latest AMD technical support phone numbers, software, and Frequently Asked Questions. For technical support questions on all E86 and Comm86 products, send e-mail to [email protected] (in the US and Canada) or [email protected] (in Europe and the UK). You can also call the AMD Corporate Applications Hotline at: (800) 222-9323 Toll-free for U.S. and Canada 44-(0) 1276-803-299 U.K. and Europe hotline

WWW Support For specific information on E86 and Comm86 products, access the AMD home page at www.amd.com and follow the Embedded Processors link. These pages provide information on upcoming product releases, overviews of existing products, information on product support and tools, and a list of technical documentation. Support tools include online benchmarking tools and CodeKit™ software—tested source code example applications. Many of the technical documents are available online in PDF form. Questions, requests, and input concerning AMD’s WWW pages can be sent via e-mail to [email protected].

Documentation and Literature Support Data books, user’s manuals, data sheets, application notes, and product CDs are free with a simple phone call. Internationally, contact your local AMD sales office for product literature. To order literature, call: (800) 222-9323 Toll-free for U.S. and Canada (512) 602-5651 Direct dial worldwide (512) 602-7639 Fax

Third-Party Support AMD FusionE86SM program partners provide an array of products designed to meet critical time-to-market needs. Products and solutions available include emulators, hardware and software debuggers, board-level products, and software development tools, among others. The WWW site and the E86 Family Products Development Tools CD, order #21058, describe these solutions. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.

iv Am486® Microprocessor PCI Customer Development Platform v Microprocessor ...... xiii ® Microprocessor PCI Customer Development Platform Platform Development Customer PCI Microprocessor ® Am486 Core Logic Chipset Logic Core ...... xiii DRAM Main Memory...... xiv Memory...... Flash and ROM Boot xiv Cache L2 Onboard ...... xiv and DOS Compatibility...... xv PC Super PC-Style I/O...... xv Controller...... xv Mouse and Keyboard Ethernet 10/100-Mbit/s Onboard ...... xvi Support...... Bus Expansion xvi Support...... Development xvi Factor...... Form xvi BIOS and Software ...... xvi Manual This About ...... xvii Material...... Reference Suggested xviii Conventions...... Documentation xix Am486 Evaluation Board Features Board Evaluation ...... xiii Customer Development Platform Documentation Platform Development Customer ...... xvii Contents About Customer the Development Platform

Chapter 1 Quick Start Setting Up the PCI CDP ...... 1-2 Installation Requirements...... 1-3 Board Installation ...... 1-4 Starting from Diskette ...... 1-6 Starting from an IDE Hard Drive...... 1-7 Installation Troubleshooting...... 1-8

Chapter 2 Board Functional Description Feature and Layout Diagrams...... 2-2 Jumper Functions...... 2-6

Board Restrictions ...... 2-7 Board Features...... 2-7 Am486 Microprocessor (M14)...... 2-8 Core Logic Chipset (M8, I13, D15) ...... 2-11 Onboard Ethernet Controller (F7) ...... 2-13 4-Kbyte Serial EEPROM (C4)...... 2-14 Development Support...... 2-15 PCI Bus (I7)...... 2-19 Level-2 Cache Memory (K19–N19 and N11)...... 2-20 DRAM Main Memory (P7)...... 2-20 Boot ROM (C16)...... 2-21 ISA Flash Memory (F20) ...... 2-23 EIP Flash Memory (L21) ...... 2-25 Real-Time Clock (G17)...... 2-27 ISA Bus Interface (A7)...... 2-28

vi Am486® Microprocessor PCI Customer Development Platform Super I/O (C19)...... 2-28 IDE Hard Drive (L4 and M4)...... 2-31 Keyboard (O1) ...... 2-31 Mouse (M1)...... 2-31 CPU Voltage Adjustment (Q15–Q16)...... 2-32 Power Supply Connectors (N2 and P2) ...... 2-33 Reset and Interrupt Switches and Headers...... 2-34 Resistor Options...... 2-35

Appendix A Default Settings

Appendix B

Bill of Materials and Schematics Board Bill of Materials (BOM) ...... B-2 Schematics...... B-10

Index

Am486® Microprocessor PCI Customer Development Platform vii List of Figures Figure 0-1. PCI CDP Overview...... xii Figure 2-1. PCI CDP Overview (Same as Figure 0-1)...... 2-3 Figure 2-2. PCI CDP Block Diagram...... 2-4 Figure 2-3. PCI CDP Layout...... 2-5 Figure 2-4. Am486 Microprocessor Block Diagram...... 2-10 Figure 2-5. JP32 and JP33 Jumper Configuration (B14–C14)...... 2-22 Figure 2-6. Typical Memory Map With ISA and EIP Flash Memory ...... 2-24 Figure 2-7. Serial Port Connector Pins (J8, J9)...... 2-29 Figure 2-8. Parallel Port Socket (J4) ...... 2-30 Figure 2-9. Voltage Jumper Default Configuration (Q15–Q16)...... 2-32 Figure 2-10. Ground Wire Connections ...... 2-33

viii Am486® Microprocessor PCI Customer Development Platform List of Tables Table 0-1. Notational Conventions ...... xix Table 1-1. Installation Troubleshooting ...... 1-8 Table 2-1. Board Jumper Summary ...... 2-6 Table 2-2. PCI Configuration Addressing ...... 2-11 Table 2-3. Analyzer Headers ...... 2-16 Table 2-4. PCI Bus Master Test Points ...... 2-17 Table 2-5. TIP Interrupt Usage ...... 2-18 Table 2-6. PCI Bus Interrupt Routing...... 2-19 Table 2-7. SIMM Socket Population Chart ...... 2-21 Table 2-8. Serial Port Pin/Signal Table ...... 2-29 Table 2-9. Parallel Port Pin/Signal Table ...... 2-30 Table 2-10. Switch Summary ...... 2-34 Table 2-11. Resistor Options ...... 2-35 Table A-1. Default Jumper Settings ...... A-1

Am486® Microprocessor PCI Customer Development Platform ix

x Am486® Microprocessor PCI Customer Development Platform About the Customer Development Platform

Congratulations on your decision to design with the Am486® microprocessor. The Am486 microprocessor PCI customer development platform (CDP) provides a reference design for embedded Am486 microprocessor-based systems using the Peripheral Component Interconnect (PCI) bus with an onboard 10- or 100-Mbit/s Ethernet connection.

The PCI CDP includes 9 Mbytes of Flash memory, PCI and ISA expansion connectors, and standard PC peripherals to allow customers to develop and benchmark network-ready firmware and applications for their embedded products. In addition, the platform’s use of low cost, off-the-shelf components makes it a suitable example for use in training or as a reference for customer hardware designs.

The PCI CDP demonstrates that a fifth-generation x86 microprocessor is not required to include a PCI bus in customer designs.

Note: Advanced Micro Devices does not assume any responsibility for the maintenance of this evaluation tool. Changes to the schematics will be made only if the board is required to go back through a CAD layout. Refer to the Am486 microprocessor documentation (listed on page xviii) for detailed information on the Am486 microprocessor.

Figure 0-1 on page xii provides an overview of the PCI CDP’s features.

Am486® Microprocessor PCI Customer Development Platform xi Level-2 Cache DRAM ® Three 72-pin SIMM Sockets Am486 512 Kbyte Supports 48 Mbytes of EDO or FPM DRAM Write-Back Policy Microprocessor 48 Mbytes of 60-ns DRAM Installed JTAG Port CPU Logic Analyzer Headers In-Circuit Emulator Support Zero-Insertion-Force Socket Fan/Heat Sink Included

EIP Flash Memory CPU Bus Addressed as fourth DRAM bank 8-Mbyte Flash Memory Faster than ISA Bus Flash Memory Coexists with up to 48 Mbyte of DRAM ALi M1489 Cache, Memory, and DRAM Controller (Northbridge Chip) PCI Bus Logic Analyzer Headers NMI, SMI, Reset Switches Ethernet Controller PCI Bus Am79C972 Device 10/100Base-T Port Three Connection Status LEDs Extra EEPROM for User Data

IDE Interface Supports up to Four Devices Two Connector Status LEDs

PCI Expansion Two PCI Bus Connectors

ALi M1487 ISA Bridge (Southbridge Chip) PCI Bus Arbiter

ISA Bus Boot ROM Socket 8 Bits Wide BIOS Included

ISA Expansion Two ISA Bus Connectors RTC DS1685 Real-Time Clock Year-2000 Compliant ISA Flash Memory 242 Bytes Nonvolatile RAM 1 Mbyte, 16 Bits Wide Super I/O IrDA Module 2 Serial Ports with Hex Display Status LEDs M5042 Keyboard I/O Port 80h, 8 Bits Wide 1 Parallel Port Controller I/O Port 680h, 8 Bits Wide Floppy Disk Interface AT Keyboard Controller PS/2 Mouse Controller

Test Interface Port

Figure 0-1. PCI CDP Overview

xii Am486® Microprocessor PCI Customer Development Platform User’s Manual Evaluation Board Features

This section describes the following features of the PCI CDP: • Am486® Microprocessor, page xiii • Core Logic Chipset, page xiii • DRAM Main Memory, page xiv • Boot ROM and Flash Memory, page xiv • Onboard L2 Cache, page xiv • PC and DOS Compatibility, page xv • PC-Style Super I/O, page xv • Keyboard and Mouse Controller, page xv • Onboard 10/100-Mbit/s Ethernet, page xvi • Expansion Bus Support, page xvi • Development Support, page xvi • Form Factor, page xvi • BIOS and Software, page xvi

Am486® Microprocessor

• AMD Am486 DX5 microprocessor is included. Supports Am486 DX2, DX4, and DX5 microprocessors (168-pin pin-grid array (PGA), 3.3 V or 3.45 V). • Zero insertion force (ZIF) PGA microprocessor socket for emulator support. • CPU voltage is jumper selectable. Core Logic Chipset

• Acer Labs FINALi 486 PCI chipset – M1489 Cache, Memory, and PCI Controller – M1487 ISA Bridge Controller – M5402 Mouse/Keyboard Controller

Am486® Microprocessor PCI Customer Development Platform xiii DRAM Main Memory

• 48 Mbyte of 60-ns EDO DRAM installed. • Supports one, two, or three banks of 32- or 36-bit-wide DRAM using industry standard 5-V 72-pin SIMMs. DRAM can be fast page mode (FPM) or extended data out (EDO). • Supports 1-, 4-, or 16-Mbit technology DRAMs. • Three SIMM sockets. One or two banks per socket. Three banks DRAM maximum. • DRAM is accessible by CPU and PCI bus masters. • L1/L2 cache snoop cycles are generated for PCI master memory accesses. • Wait-state timing is configurable through chipset registers. Boot ROM and Flash Memory

• Dip socket provided for one 8-bit-wide boot ROM, logically on the ISA bus.

• 1 Mbyte of 16-bit-wide Flash memory soldered to the board, logically on ISA bus. • 8-Mbyte Flash memory for execute-in-place (EIP) applications, located on the memory bus in place of one DRAM bank. EIP Flash is implemented using an AMD 22V10 PAL® device for glue logic. Onboard L2 Cache

• 512-Kbyte cache size, configured as 32-bit-wide memory. • Write-back or write-through protocol configurable through chipset registers. • One 32-Kbyte x8 SRAM for cache tag space, soldered to board. • Four 128-Kbyte x8 SRAMs for cache data space, soldered to board. • 2-1-1-1 (read) and 2-2-2-2 (write) burst timing with 15-ns data and 10-ns tag SRAMs.

xiv Am486® Microprocessor PCI Customer Development Platform User’s Manual PC and DOS Compatibility

• IDE interface in chipset. • Standard chipset configuration registers, known to BIOS and DOS. • Off-the-shelf PC chipset provides common I/O functions found in a PC: - Two 82C59 interrupt controllers (SMI, NMI, and INT support) - One 82C54 programmable interval timer - Two 82C37 DMA controllers (seven channels) - External boot ROM chip-select signal - PC-style real-time clock (RTC) (non-Y2K-compliant, disabled by default) • DS1285 Y2K-compliant RTC chip. The DS1285 RTC can be disabled, and the non-Y2K RTC enabled, by removing one resistor and populating another. PC-Style Super I/O

• DOS and PC-AT compatible I/O.

• Two 16550-compatible serial ports. • One parallel port. Supports enhanced parallel port (EPP) and extended capabilities port (ECP) modes. • Floppy disk interface. • IrDA port with external transceiver (115 Kbyte/s). Keyboard and Mouse Controller

• 8042-compatible controller chip (included in chipset). • AT keyboard interface. • PS/2 Mouse interface.

Am486® Microprocessor PCI Customer Development Platform xv Onboard 10/100-Mbit/s Ethernet

• AMD PCnet™-Fast+ Ethernet Controller Chip, Am79C972. • 32-bit PCI bus interface with bus mastering capability. • Integrated 12-Kbyte buffer. • External PHY transceiver for full duplex operation at 10 or 100 Mbit/s. • IEEE802.3, PC97, PC98, and NetPC compliance. • Preprogrammed 1-Kbyte serial EEPROM included for Ethernet configuration. • Extra 4-Kbyte serial EEPROM included for user nonvolatile data. Expansion Bus Support

• Two PCI 2.0 expansion connectors, desktop PC style. • Two ISA 16-bit expansion connectors, desktop PC style. Development Support

• In-circuit emulator (ICE) support with socketed microprocessor in PGA package. • Logic analyzer headers for all CPU and PCI bus signals. • Switches (push-button) for NMI, SMI, and RESET. • LEDs for IDE, serial port, Ethernet activity, and Ethernet link speed. • I/O port 80h and 680h hexadecimal displays. • Am486 microprocessor JTAG support. • Connector for AMD embedded systems Test Interface Port (TIP) board. Form Factor

• Baby-AT motherboard form factor. • Fits standard desktop-PC-style chassis. BIOS and Software

The included diskette contains information about the included BIOS and any additional utility and demonstration software for the PCI CDP.

xvi Am486® Microprocessor PCI Customer Development Platform User’s Manual Customer Development Platform Documentation

The Am486® Microprocessor PCI Customer Development Platform User’s Manual provides information on the design and function of the development platform. The software shipped with the board is described in the README files and online BIOS manual included with your kit.

The included online documentation is in text or Adobe Acrobat (PDF) format. The latest Acrobat Reader is available from Adobe’s site on the World Wide Web (currently at www.adobe.com).

About This Manual

Chapter 1, “Quick Start” helps you quickly set up and start using the PCI CDP.

Chapter 2, “Board Functional Description” contains descriptions of the basic

sections of the evaluation board: layout, microprocessor, core logic chipset, Ethernet controller, DRAM, boot ROM and Flash memory, PCI bus and ISA bus interfaces, super I/O, keyboard and mouse, drives, and interrupt switches.

Appendix A, “Default Settings” summarizes the jumper and configuration resistor positions on the PCI CDP when it is shipped.

Appendix B, “Bill of Materials and Schematics” shows the bill of materials for the evaluation board, and the actual CAD schematics used to build the board.

Am486® Microprocessor PCI Customer Development Platform xvii Suggested Reference Material

The following AMD documentation may be of interest to the PCI CDP user. For information on ordering literature, see page iii.

• Enhanced Am486®DX Microprocessor Family Data Sheet, order #20736

• Am486®DX/DX2 Microprocessor Hardware Reference Manual, order #17965

• Am486® Microprocessor Software User's Manual, order #18497 • Am79C972 PCnetTM-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support Data Sheet, order #21485 • E86 Family Products Development Tools CD, order #21058 • Flash Memory Products Data Book, order # 11796 • For current application notes and technical bulletins, see our World Wide Web page at www.amd.com.

The following non-AMD documents are also recommended:

• Application Note 77: DS1585/87, DS1685/87, and DS17x85/87 Accessing Extended User RAM via Software Dallas Semiconductor, www.dalsemi.com. • DS1685/DS1687 3 Volt/5 Volt Real Time Clock Data Sheet Dallas Semiconductor, www.dalsemi.com. • FINALi 486 M1489/1487 PCI Chip Set Preliminary Data Sheet Acer Laboratories Inc., see www.acerlabs.com for contact information. Related BIOS guidelines, errata, and application documents are also available. • M5113: Enhanced Super I/O Controller Data Sheet Acer Laboratories Inc., see www.acerlabs.com for contact information.

xviii Am486® Microprocessor PCI Customer Development Platform User’s Manual Documentation Conventions

The Advanced Micro Devices Am486® Microprocessor PCI Customer Development Platform User’s Manual uses the conventions shown in Table 0-1 (unless otherwise noted). These same conventions are used in all the E86 family support product manuals.

Table 0-1. Notational Conventions

Symbol Usage Boldface Indicates that characters must be entered exactly as shown, except that the alphabetic case is only significant when indicated. Italic Indicates a descriptive term to be replaced with a user-specified term. Typewriter face Indicates computer text input or output in an example or listing. [ ] Encloses an optional argument. To include the

information described within the brackets, type only the arguments, not the brackets themselves. { } Encloses a required argument. To include the information described within the braces, type only the arguments, not the braces themselves. .. Indicates an inclusive range. ... Indicates that a term can be repeated. | Separates alternate choices in a list — only one of the choices can be entered. := Indicates that the terms on either side of the sign are equivalent.

Am486® Microprocessor PCI Customer Development Platform xix

xx Am486® Microprocessor PCI Customer Development Platform User’s Manual 1-1 Microprocessor PCI Customer Development Platform Platform Development Customer PCI Microprocessor microprocessor PCI customer development platform (CDP). (CDP). platform development PCI customer microprocessor ® ® Am486 This chapter provides information that helps you quickly set up andstart using the Am486 The PCI CDP is shipped with a BIOS that has been configured specifically for the for specifically configured that has been with a BIOS is shipped PCI CDP The the PCI that enables code the BIOS contains The platform. this on chipset used displays, PC, using AT-compatible CDP to function as a standard AT-compatible BIOS the in found be can BIOS the on Details and keyboards. adapters, display documentation shipped on diskette with your kit. can start the You system software. operating CDP The PCI run AT-compatible can that already drive disk hard (IDE) ATA an diskette or a bootable system with either has the operating system installed. Flash onboard of configuration the supports typically software BIOS Embedded flash a resident as memory that can also disk (RFD) Seebe set up as a device. boot onlinetheBIOS manual included with your kit. to: on how information For • 1-2. page see CDP, PCI the up Set • 1-6. page see a diskette, from CDP PCI the Boot • 1-7. see page drive, disk a hard from PCI CDP the Boot • 1-8. page see problems, installation Troubleshoot Chapter 1 Chapter Quick Start

Setting Up the PCI CDP

CAUTION: As with all computer equipment, the PCI CDP may be damaged by electrostatic discharge (ESD). Please take proper ! ESD precautions when handling any board.

Warning: Read before using this development platform Before applying power, the following precautions should be taken to avoid damage or misuse of the board: • Make sure power supply connectors (from a standard AT system power supply) are plugged onto the board correctly. The grounds (usually black wires) must meet at the center of the two power supply connectors on the board. See “Power Supply Connectors (N2 and P2)” on page 2-33. • See Figure 2-3 on page 2-5 for connector positions.

• Check the diskette that was shipped with your kit for README or errata documentation. Read all the information carefully before continuing.

For current application notes and technical bulletins, see the AMD World Wide Web page at www.amd.com and follow the link to Embedded Systems.

1-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual Installation Requirements

You need to provide the following items (in addition to the PCI CDP from the kit).

Required for all setups: • A VGA-compatible monitor • A PCI- or ISA-bus video card that supports VGA • A cable to connect the monitor to the video card • An AT-compatible keyboard • A PS/2-style mouse (if needed for your operating system) • A standard AT-style power supply

To boot from a floppy diskette: • An AT-compatible 3.5-inch or 5.25-inch diskette drive • A bootable DOS diskette • A standard 34-wire AT diskette drive cable

To boot from a hard disk drive: • An ATA-compatible hard disk drive • AT-compatible operating system (preinstalled on the hard disk drive) • A standard 40-pin ATA HDD cable

If you install both a floppy diskette drive and a hard disk drive, you can boot from either device. Only one boot disk image (floppy or hard disk) is required. For example, you can boot from the floppy and then install the operating system on a blank hard disk drive.

CAUTION: Use the configuration described here when you first start the PCI CDP. Before using other features, read the appropriate sections in Chapter 2, “Board Functional ! Description.”

Am486® Microprocessor PCI Customer Development Platform 1-3 Board Installation

Note: See Figure 2-2 on page 2-4 for a block diagram of the board. See Figure 2-3 on page 2-5 for a layout diagram of the board, including connector locations referenced in this section.

DANGER: Make sure the power supply and the VGA monitor are not plugged into an electrical outlet during ! the following steps.

1. Remove the board from the shipping carton. Visually inspect the board to verify that it was not damaged during shipment. The board contains several jumpers. The following steps assume all jumpers are in the factory default configuration (settings are listed in Appendix A, “Default Settings”). 2. If you are installing a diskette drive, perform the following steps: a. Inspect the 34-wire, diskette-drive cable that you are providing. The red wire along one edge of the ribbon cable indicates wire 1. Most cables have a connector for the board at one end and two or more connectors along the length. There may be two different drive connectors at each location to accommodate different drive types. b. Connect one end of the diskette-drive cable to the 34-pin connector (connector J6 at location E20) on the PCI CDP (with wire 1 oriented towards the middle of the board). If there is a twist in one span of the cable, connect the opposite end to the board. c. Connect another connector on the diskette-drive cable to the diskette drive, just as you would for a standard PC installation. If there is a twist in the cable, the position you use determines whether the drive responds as A or B (typically drive A connects to the end of the cable, beyond the twist). The connector’s orientation should be indicated in the drive documentation, or marked near the connector on the drive. Usually wire 1 is oriented towards the drive’s power cable connector. d. Find one of the 4-wire power connectors from the PC power supply and attach it to the 4-pin connector on the diskette drive just as you would for a standard PC installation.

1-4 Am486® Microprocessor PCI Customer Development Platform User’s Manual 3. If you are installing a hard disk drive, perform the following steps: a. Inspect the 40-wire IDE cable that you are providing. The red wire along one edge of the ribbon cable indicates wire 1. b. Connect one end of the 40-wire IDE cable to the hard drive just as you would for a standard PC installation. The connector’s orientation should be indicated in the drive documentation, or marked near the connector on the drive. Usually wire 1 is oriented towards the drive’s power cable connector. c. Connect the other end of the 40-wire IDE cable to the first 40-pin connector (connector J5 at location L4) on the PCI CDP (with wire 1 oriented towards the edge of the board, near the power supply connector). d. Find one of the 4-wire power connectors from the PC power supply and attach it to the 4-pin connector on the hard drive just as you would for a standard PC installation. 4. Make sure the CPU heat sink is securely attached to the microprocessor and connect the heat sink fan power wires to a spare disk drive power connector. Fan power supply connectors are not all the same. Check the voltage printed on the fan and connect its wires to the correct voltage pins on the appropriate power supply connector. 5. Insert a PCI- or ISA-bus VGA-compatible video card into an appropriate slot on the PCI CDP. The PCI slots are labeled SLT1 and SLT2. The ISA slots are labeled SL1 and SL2. 6. Connect the monitor cable from the monitor to the D-connector on the video card just as you would for a standard PC. 7. Connect the AT keyboard to the keyboard connector (connector J1 at location O1). 8. Connect the PS/2 mouse (if used) to the mouse connector (connector J11 at location M1). 9. Connect the connectors (usually marked P8 and P9) from the standard PC power supply into the board’s power connectors J2 (at location Q2) and J3 (at location N2). P8 connects to J2 (the six pins closest to the corner of the board); P9 connects to the other six pins. Make sure the black ground wires from P8 and P9 meet in the middle of the board’s J2 and J3 connectors.

CAUTION: Failure to verify the power supply connections can ! result in total destruction of the PCI CDP.

Am486® Microprocessor PCI Customer Development Platform 1-5 Starting from Diskette

Use the following steps to start the PCI CDP from a bootable diskette:

1. Make sure you have installed the PCI CDP correctly as described in “Setting Up the PCI CDP” on page 1-2.

CAUTION: Failure to verify the power supply connections can ! result in total destruction of the PCI CDP.

2. Plug the VGA monitor into an electrical outlet and turn it on. 3. Insert a bootable DOS diskette (not included) in the disk drive. 4. Apply power to the PCI CDP by connecting the PC power supply to an electrical outlet. If the power supply is equipped with a switch, turn it on. The power supply fan should start running, and the port 80h LEDs should start to display power-on self-test (POST) status codes. Then the speaker should

beep and the monitor should start displaying startup information. Make sure the CPU heat sink fan is running. Do not operate the microprocessor without a functioning heat sink fan.

6. Save and exit the setup utility. 7. The system should now boot from the DOS diskette just like a standard PC. If you encounter any problems, see “Installation Troubleshooting” on page 1-8.

1-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual Starting from an IDE Hard Drive

Use the following steps to start up the PCI CDP from an IDE hard drive on which you have preinstalled an operating system (while it was connected to another PC):

1. Make sure you have installed the PCI CDP correctly as described in “Setting Up the PCI CDP” on page 1-2.

CAUTION: Failure to verify the power supply connections can ! result in total destruction of the PCI CDP.

2. Plug the VGA monitor into an electrical outlet and turn it on. 3. If a diskette drive is installed, make sure it is empty. 4. Apply power to the PCI CDP by connecting the PC power supply to an electrical outlet. If the power supply is equipped with a switch, turn it on. The power supply fan and hard disk should start running, and the port 80h LEDs

should start to display power-on self-test (POST) status codes. Then the speaker should beep and the monitor should start displaying startup information. Make sure the CPU heat sink fan is running. Do not operate the microprocessor without a functioning heat sink fan.

5. The first time you start the system, the BIOS might display a message reporting a CMOS error or some other BIOS configuration problem. Follow the instructions shown on the screen to enter the Setup utility. Once you are in the Setup utility, you can set the system’s date, time, startup drive, and other options. 6. In the BIOS setup utility, use the automatic configuration option to set up Drive C. Select either physical addressing or logical block addressing (LBA) as appropriate for your hard disk drive. For more information on the included BIOS, see the online BIOS manual included with your kit.

7. Save and exit the setup utility. 8. The system should now boot using the operating system on the hard disk. If you encounter any problems, see “Installation Troubleshooting” on page 1-8.

Am486® Microprocessor PCI Customer Development Platform 1-7 Installation Troubleshooting

Table 1-1. Installation Troubleshooting

Problem Solution The Port 80h LED readout is blank Check power supply connectors J2 and J3. after I turn on the power supply. The Port 80h LED readout is stuck Ensure processor reset by pressing the Reset button, SW1 at 00. I see nothing on the VGA at location N5. monitor and do not hear any beeps from the speaker. I do not hear the Check that the BIOS ROM and the microprocessor are head synchronization on the correctly installed, and that jumpers JP32 and JP33 are diskette drive (if attached). both off. The Port 80h LED readout Make sure all cables are connected properly, all adapters displayed some power-on-self- are seated firmly in their slots, and the CMOS battery is test (POST) numbers, but then correctly installed. stopped at one number before the system finished starting. See the online BIOS documentation included with your kit for a list of POST numbers and meanings. I hear a beep on the speaker but see Check that the monitor is plugged in and turned on. nothing on the VGA monitor. Check that the monitor is correctly connected to the video card.

Check that the video card is correctly seated in the appropriate slot.

Check that the video card supports VGA. I see the startup information on the Make sure the SIMMs that came with the kit are securely monitor but the memory test stops installed in the SIMM sockets. at an incorrect memory size. (1 Mbyte equals 1024 Kbyte.) I see the startup information on the Follow the BIOS instructions to run the Setup utility to monitor but it says there’s a battery configure the CMOS RAM and save settings. problem or CMOS checksum error and the system doesn’t finish booting.

1-8 Am486® Microprocessor PCI Customer Development Platform User’s Manual Table 1-1. Installation Troubleshooting (Continued)

Problem Solution I configured the CMOS RAM and Make sure a fresh 3.0-V 20-mm coin cell is installed saved my settings, but settings are correctly (“+” side facing up) in the BT1 battery holder lost the next time I turn on the PCI at location E12. CDP. I don’t hear any sound from the Check that the 34-wire cable to the diskette drive is diskette drive and the system does properly connected at both the drive end and the board not boot from a diskette. end (board connector J6 at location E20). The red wire should be oriented towards pin 1 on both the drive and the board.

Check that the CMOS setup indicates that drive A is the correct size and capacity for your diskette drive. I hear the diskette being accessed Check that the diskette in the drive is bootable, just as you but get an error message “Non would on a standard PC. System disk” or “Drive A not found.” Make sure the diskette drive is connected properly to the

last connector on the cable.

In the BIOS setup utility, make sure the BIOS is configured to boot from diskette, and that the diskette size and density is configured properly. I get a “Missing Keyboard” error Check that an AT-style keyboard is properly connected. message on the monitor during boot-up. The BIOS debugging monitor Make sure the NMI switch is not pressed. prompt is displayed. Check that the DRAM and any PCI or ISA-bus devices are installed correctly and known to be functional.

Am486® Microprocessor PCI Customer Development Platform 1-9 Table 1-1. Installation Troubleshooting (Continued)

Problem Solution I have installed a hard disk with a Check that the 40-wire IDE cable is properly connected preinstalled operating system, but at both the drive end and the board end (board connector the PCI CDP won’t access the hard J5 at location L4). Check that the CMOS setup is disk. configured correctly for your drive.

Make sure the board will start from a bootable diskette in drive A. Then try to do a directory listing of drive C. If the directory listing of C works, the drive is functioning and there is a problem with the drive’s boot block or system image. (Note that some operating systems will display an error if you list an empty directory. If this happens, try copying a file to the drive; then do a directory listing again. If this fails, check the drive for boot block viruses.)

Make sure the drive functions properly on a different system.

There is a problem you cannot Check that the board is set to its default settings (see resolve. Appendix A, “Default Settings”).

Contact the AMD Technical Support Hotline (see page iii).

1-10 Am486® Microprocessor PCI Customer Development Platform User’s Manual 2-1 microprocessor PCI customer development platform (CDP) provides (CDP) provides platform customerdevelopment PCI microprocessor ® Microprocessor PCI Customer Development Platform Platform Development Customer PCI Microprocessor ® -page 2-15 D17), and (Q14 Ports JTAG - 2-15 page Headers, Analyzer Logic - In-Circuit Emulator Compatibility (M14,Q15–Q16), page2-17 -2-17 page J23), (H23, Display Hexadecimal -2-18 page (A16), Port (TIP) Interface Test - 2-29 page C23), and (E23 Ports Serial - 2-29 page (A19), Interface IrDA -2-30 page (A22), Port Parallel - 2-30 page (E20), Drive Disk Floppy – 2-8 page (M14), Microprocessor Am486 – 2-11 page D15), I13, (M8, Chipset Logic Core –2-13 page (F7), Controller Ethernet Onboard – 2-14 page (C4), EEPROM Serial 4-Kbyte – 2-15 page Support, Development – 2-19 page (I7), Bus PCI – 2-20 page N11), and (K19–N19 Memory Cache Level-2 – 2-20 page (P7), Memory Main DRAM – 2-21 page (C16), ROM Boot – ISA Flash Memory (F20), page 2-23 – 2-25 page (L21), Memory Flash EIP –2-27 page (G17), Clock Real-Time – 2-28 page (A7), Interface ISA Bus –2-28 page (C19), I/O Super Am486 The Am486 The a test and development platform for Am486 microprocessor-based designs. Read Read designs. microprocessor-based Am486 for platform development and a test followingthe sections to learn more about the board: • 2-2 page Diagrams, and Layout Feature • Jumper Functions, page 2-6 • 2-7 page Restrictions, Board • 2-7 page Features, Board Chapter 2 Chapter Description Board Functional

– IDE Hard Drive (L4 and M4), page 2-31 – Keyboard (O1), page 2-31 – Mouse (M1), page 2-31 – CPU Voltage Adjustment (Q15–Q16), page 2-32 – Power Supply Connectors (N2 and P2), page 2-33 – Reset and Interrupt Switches and Headers, page 2-34 – Resistor Options, page 2-35

See the appendices for information about default board settings, bill of materials, and schematics.

Feature and Layout Diagrams

The following figures summarize the features and layout of the PCI CDP. • Figure 2-1 on page 2-3 provides an overview of the platform’s features. • Figure 2-2 on page 2-4 is the block diagram for the platform. • Figure 2-3 on page 2-5 shows the platform layout and component locations.

2-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual Level-2 Cache DRAM ® Three 72-pin SIMM Sockets Am486 512 Kbyte Supports 48 Mbytes of EDO or FPM DRAM Write-Back Policy Microprocessor 48 Mbytes of 60-ns DRAM Installed JTAG Port CPU Logic Analyzer Headers In-Circuit Emulator Support Zero-Insertion-Force Socket Fan/Heat Sink Included

IDE Interface Supports up to Four Devices Two Connector Status LEDs

PCI Expansion Two PCI Bus Connectors

ALi M1487 ISA Bridge (Southbridge Chip) PCI Bus Arbiter

ISA Bus Boot ROM Socket 8 Bits Wide BIOS Included

Test Interface Port

Figure 2-1. PCI CDP Overview (Same as Figure 0-1)

Am486® Microprocessor PCI Customer Development Platform 2-3 CPU CPU Jumpers EDO DRAM

JTAG Power 72-pin SIMM Socket 1

Logic Analyzer Header(s): CPU Signals EDO DRAM 72-pin SIMM Socket 2 Am486® CPU Address Onboard Microprocessor EDO DRAM 512K L2 Cache 72-pin SIMM Socket 3 Pin Grid Array (ZIF Socket) CPU Data DRAM-to-Flash 8-Mbyte Flash Memory Interface For Execute-In-Place CPU Control Cache Control Memory Address ALi M1489 & Control Cache, Memory, and PCI Controller Logic Analyzer Header(s): PCI Signals IDE Connector PCI Bus (33 MHz, 5 V) AMD Am79C972 PHY IDE Connector PCNet Fast+ Ethernet CPU Interface

ALi M1487 1-Kbyte Config SEEPROM ISA Bridge Controller 4-Kbyte User SEEPROM

ISA Bus PCI Expansion Connector ISA Expansion Connector DS1685 PCI Expansion Connector ISA Expansion Connector Y2K RTC

Boot ROM Socket (x8) M5113A IrDA Super I/O Chip

1-Mbyte FLASH Memory (x16)

Floppy Disk Connector MACH® Logic Serial Port1 Connector M5042 HEX LEDs for Debug Keyboard Serial Port2 Connector Controller TIP Board Interface Parallel Port Connector E/net SIO1 SIO2 IDE0 IDE1 SMI

AT Keyboard Connector NMI Reset System System PS/2 Mouse Connector LEDs Switches Clocks Power

Figure 2-2. PCI CDP Block Diagram

2-4 Am486® Microprocessor PCI Customer Development Platform User’s Manual A B C D E F G H I J K L M N O P Q

1 1 Ethernet KBD Conn. Mouse 2 2 Power Conn.

3 1 Pin 1 Pin 3

4 4

5 5

6 6 IDE Hard Disk Conn. IDE Hard Disk Conn. Am79C972 7 Ethernet DRAM 7 ISA Controller PCI Slots SIMM 8 Slots 8 M1489 Slots Northbridge 9 9

10 10

11 11

12 Battery 12

M1487 13 Southbridge 13 Pin A1 14 Speaker 14 Am486® 15 M5042 15 Kbd/ Microprocessor TIP Mouse Conn. Boot 16 ROM 16 DS MACH® 17 Logic Chip 1685 17 RTC 18 18

19 M5113 19

Super 1 Pin I/O 20 20 ISA 21 Flash 21 EIP Flash Memory Floppy Conn. 22 22 Parallel Port Parallel 23 23 COM 1 COM 2 24 24

A B C D E F G H I J K L M N O P Q Figure 2-3. PCI CDP Layout

Am486® Microprocessor PCI Customer Development Platform 2-5 Jumper Functions

Table 2-1 describes the configuration jumpers on the PCI CDP.

Table 2-1. Board Jumper Summary

Part Signal Description Location in See App. B For More Figure 2-3 Schematics Info., See: on Page 2-5 on:

JP2 CPUVCC3 Used with JP3 to select Q15 Sheet 3 page 2-32 either 5-V CPU voltage or the adjustable voltage set by jumper JP4. Both JP2 and JP3 must be positioned the same.

JP3 CPUVCC3 Used with JP2 to select Q16 Sheet 3 page 2-32 either 5-V CPU voltage or the adjustable voltage set by

jumper JP4. Both JP2 and JP3 must be positioned the same. JP4 CPUV1, Selects the CPU voltage R15 Sheet 3 page 2-32 CPUV2, used when JP2 and JP3 are CPUV3 set to “ADJ.” The selectable voltages are 3.45 V, 3.3 V, and 2.5 V. JP32 Boot ROM Used to configure boot C14 Sheet 17 page 2-21 A17 ROM address signal A17. JP33 Boot ROM Used to configure boot B14 Sheet 17 page 2-21 A18 ROM address signal A18.

2-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual Board Restrictions

• Using a PCI chipset with the Am486 microprocessor is a fast and effective way to design a working system, but the system’s features can be limited by the chipset’s capabilities. • The chipset used in the PCI CDP supports 5-V PCI 2.0 devices only. Three devices are supported: the onboard Ethernet controller and two PCI slots. • Except for the adjustable CPU supply voltage and 3.3-V Ethernet controller, the PCI CDP uses 5-V power throughout. (The Am486 microprocessor provides 5- V-tolerant I/O.) • The chipset does not directly support ROM or Flash memory devices except for the boot ROM. It is possible to implement Flash memory on the DRAM, PCI or ISA bus, but the chipset only allows booting from the boot ROM. ISA-bus Flash memory is limited to 1 Mbyte because of addressing considerations. • The PCI CDP implements two banks of execute-in-place (EIP) Flash memory in place of one DRAM bank. Flash memory timing requirements limit the chipset’s DRAM interface to its Fast (not Fastest) speed when the Flash memory

is used. This is equivalent to using 70-ns fast-page-mode (FPM) DRAM. • The chipset allows only three banks of DRAM to be attached without external buffers. Buffering the DRAM adds one wait state and reduces the available performance. “DRAM Main Memory (P7)” on page 2-20 describes additional DRAM device and configuration limits. • The ISA peripherals provided by the M1487 chip are configured for standard PC-AT compatibility, so there is not much flexibility in assigning interrupts and DMA channels. • The PCI CDP does not implement OnNow or Advanced Configuration and Power Interface (ACPI) power management. Board Features

The remainder of this chapter describes the features of the PCI CDP. The number in parentheses following each heading indicates the part’s location in Figure 2-3 on page 2-5. In addition, other locations referenced can be found in the figure.

Am486® Microprocessor PCI Customer Development Platform 2-7 Am486 Microprocessor (M14)

The PCI CDP includes an Am486 microprocessor in a 168-pin, pin-grid-array package (part U25). The microprocessor is zero-insertion-force (ZIF) socketed and a CPU fan heat sink is provided for cooling. For debugging and analysis, access is provided to the Am486 microprocessor’s JTAG debugging port and to all of the microprocessor signals, and support is provided for Intel-compatible in-circuit emulators. See “Development Support” on page 2-15.

The Enhanced Am486DX Microprocessor Family boosts system performance by incorporating a 16-Kbyte cache to the existing flexible clock control and enhanced System Management mode (SMM) features of a 486 CPU. The Enhanced Am486DX Microprocessor Family has the following characteristics:

• Industry-standard write-back cache support • Frequent instructions execute in one clock • 105.6-million bytes/second burst bus at 33 MHz • Flexible write-through and write-back address control

• Advanced 0.35-µ CMOS-process technology • 3.3-V or 3.45-V core with 5-V tolerant I/O • Dynamic data bus sizing for 8-, 16-, and 32-bit buses (the PCI CDP uses a 32- bit data bus) • 32-bit address bus • 32-bit registers • Supports “soft reset” capability • 16-Kbyte unified code and data cache – Four-way set-associative – Write-through or write-back policy (the PCI CDP uses write-back policy) • Floating-point unit • Paged, virtual memory management • Stop clock control for reduced power consumption • Industry-standard two-pin System Management Interrupt (SMI) for power management independent of processor operating mode and operating system

2-8 Am486® Microprocessor PCI Customer Development Platform User’s Manual • Static design with Auto Halt power-down support • Wide range of chipsets supporting SMM available to allow product differentiation (the PCI CDP uses the Acer Laboratories Inc. FINALi 486 chipset) • Support available through the AMD FusionE86 Program

Am486® Microprocessor PCI Customer Development Platform 2-9 VOLDET Power Plane VCC, VSS

32-Bit Data Bus Clock Interface 32-Bit Data Bus CLK Clock CLKMUL Generator STPCLK 32-Bit Linear Address Bus Interface PCD, PWT A31–A2 Segmentation Address Barrel Shifter Cache Unit 32 BE3–BE0 Unit 2 Drivers Paging Unit Descriptor Write Register File Buffers 24 Registers 24 16-Kbyte 4x32 Cache Physical Limit and Translation Physical Copyback ALU Address Attribute Lookaside Address Buffers Buffer PLA 4x32 Writeback Buffers 128 4x32 Data Bus D31–D0 Displacement Bus Prefetcher Transceivers 32 32 Micro-instruction Code 32-Byte Stream Code Queue ADS, W/R, D/C, 2x16 Bytes M/IO, PCD, PWT, Floating Central and RDY, LOCK, Bus Control Point Protection Instruction 24 PLOCK, BOFF, Unit Request A20M, BREQ, Test Unit Decode Sequencer HOLD, HLDA, Decoded RESET, INTR, Floating Instruction NMI, FERR, UP, Point Control Path IGNNE, SMI, Register ROM SMIACT, SRESET File

Burst Bus BRDY, BLAST Control Bus Size BS16, BS8 Control

KEN, FLUSH, Cache AHOLD, CACHE, Control EADS, INV, WB/WT, HITM

Parity PCHK, Generation DP3–DP0 and Control TDI, TCK, JTAG TDO, TMS

Figure 2-4. Am486 Microprocessor Block Diagram

2-10 Am486® Microprocessor PCI Customer Development Platform User’s Manual Core Logic Chipset (M8, I13, D15)

The PCI CDP uses the Acer Laboratories Inc. FINALi 486 chipset. The chipset consists of two very-large-scale-integration (VLSI) devices that provide bus interface and peripheral functions used in the system, plus an M5042 keyboard and mouse controller. See “Keyboard (O1)” on page 2-31.

The M1489 Cache, Memory, and PCI Controller (often called a northbridge chip) interfaces the Am486 microprocessor to the memory and PCI bus. The M1489 (part U5 at location M8) performs the following functions:

• Controls DRAM accesses and refresh cycles. See “DRAM Main Memory (P7)” on page 2-20 • Provides a 33-MHz, PCI 2.0-compliant interface with 5-V signalling. See “PCI Bus (I7)” on page 2-19 • Maintains Level-1 and Level-2 cache coherency for PCI-master-initiated memory cycles. See “Level-2 Cache Memory (K19–N19 and N11)” on page 2-20

• Provides an IDE controller for a hard disk drive. See “IDE Hard Drive (L4 and M4)” on page 2-31 The PCI CDP routes three PCI address signals via series resistors to the IDSEL pins on the two PCI slots and the onboard Ethernet controller. The chipset asserts one of these signals to configure each device according to the device number written to the chipset’s configuration address register. Table 2-2 relates each device to its device number and signal routing.

Table 2-2. PCI Configuration Addressing

PCI Device Device PCI Address PCI ID Select See App. B Number Signal Signal schematics on: Slot SLT1 Device 3 PAD19 PCIID1 Sheet 11 Slot SLT2 Device 4 PAD20 PCIID2 Sheet 11 Ethernet Device 5 PAD21 PCIID3 Sheet 11, Sheet 13 Controller

Am486® Microprocessor PCI Customer Development Platform 2-11 All PCI bus signals are routed to logic analyzer headers. See “Development Support” on page 2-15.

The M1487 ISA Bridge Controller (often called a southbridge chip) interfaces the ISA bus to the PCI bus and provides standard, PC-compatible peripherals devices common to desktop computers. The M1487 (Part U21 at location I13) provides the following peripheral functions:

• Two 82C59 interrupt controllers • One 82C54 programmable interval timer • Two 82C37 DMA controllers • A real-time clock (RTC) (optional on the CDP, see “Real-Time Clock (G17)” on page 2-27) • External boot ROM decoding The M1487’s integrated peripherals are configured for standard PC-AT compatibility, so there is not much flexibility in assigning interrupts and DMA channels.

The M1487 also contains the PCI bus arbiter, which allows three additional masters. The PCI CDP board uses one master request/grant interface for the onboard Am79C972 Ethernet controller. The other two master interfaces are routed to the PCI expansion slots.

The M1489 and M1487 communicate with each other across their proprietary LinkBus. The LinkBus has no separate pins, but instead uses the CPU address pins A2 to A17. The LinkBus handles the RTC, keyboard controller, and boot ROM transactions as well; this is why CPU address pins are routed to these devices in the schematics. The chipset asserts the Am486 microprocessor’s AHOLD input to three-state its address pins when the LinkBus is in use.

2-12 Am486® Microprocessor PCI Customer Development Platform User’s Manual Onboard Ethernet Controller (F7)

The PCI CDP includes an onboard, full-duplex 10/100BaseT Ethernet port based on the AMD Am79C972 PCnet™-FA S T+ Ethernet Controller (part U51). A separate voltage regulator provides 3.3-V power for the Ethernet controller. The Ethernet port is part J10 at location E1 on the board. Three LEDs near the port indicate transmit and receive activity and link speed. The link LED lights if 100 Mbit/s operation is established.

The Ethernet controller’s interrupt output (INTA) is routed to the chipset’s PCI INT2 signal. The initialization code dynamically assigns INT2 to an interrupt request (IRQ) in the chipset’s PCI INTx routing table mapping registers. See the chipset documentation for details on the mapping registers.

The Am79C972 PCnet-FA S T+ device is a highly integrated 10/100 Mbps PCI Ethernet controller. It includes an IEEE 802.3-compliant Ethernet Media Access Controller (MAC) with Auto-Negotiation of 10 or 100 Mbps and half- or full- duplex operation, and a Media Independent Interface (MII) for connection to any standard IEEE 802.3 compliant 10/100 Mbps physical layer (PHY) device.

The Am79C972 contains a high performance 32-bit PCI bus master interface, as well as large, flexible internal memory buffers, to provide high-speed data throughput and low CPU and system bus utilization. For PCI configuration, the Ethernet controller is accessed as device number 5.

The Am79C972 can be configured by the PCI configuration space mechanism or it can download its configuration from a 1-Kbyte serial EEPROM (part U54 at location D6). The PCI CDP uses the serial EEPROM interface to configure the Am79C972 device. The EEPROM is preprogrammed with an Ethernet configuration suitable for the PCI CDP.

In addition to the Ethernet configuration EEPROM, a 4-Kbyte serial EEPROM is provided for user nonvolatile data. See “4-Kbyte Serial EEPROM (C4)” on page 2-14.

For customer designs, the PCnet-FA S T+ controller is offered with AMD’s extensive suite of industry-proven PCnet software drivers, remote boot ROM firmware (not supported by the PCI CDP), and a complete set of supporting utilities and design tools. Follow the Networking link at www.amd.com for information about networking software, support, and tools.

Am486® Microprocessor PCI Customer Development Platform 2-13 The PCnet-FA S T+ device supports the industry's Net PC specification. The PCnet- FA ST + device also complies with Microsoft’s PC97 and PC98 requirements by fully supporting the OnNow and ACPI power management initiatives; however, the PCI CDP does not implement OnNow or ACPI. A customer design could support these technologies by using an ATX-style power supply and motherboard design.

4-Kbyte Serial EEPROM (C4)

An extra NM93C66M8 4-Kbyte serial EEPROM (part U81) is connected to the Am79C972 Ethernet controller’s serial EEPROM interface. This provides additional EEPROM space for storing user nonvolatile data.

The M1487 device’s CLKCTL signal (controlled via chipset register 40h) is used to multiplex the Ethernet controller’s EEPROM chip select between the 1-Kbyte EEPROM and the 4-Kbyte EEPROM. When CLKCTL is asserted (the default), the Ethernet controller’s 1-Kbyte configuration EEPROM (part U54) is accessed normally. When CLKCTL is deasserted, the Ethernet controller’s EEPROM interface registers can be used to access the 4-Kbyte EEPROM to store or retrieve user data. See Sheet 13 of the schematics in Appendix B.

Software for using the 4-Kbyte EEPROM is provided with the PCI CDP. See the readme file on the diskette that came with your kit for information about available utilities.

2-14 Am486® Microprocessor PCI Customer Development Platform User’s Manual Development Support

The PCI CDP includes the following facilities for development support: •JTAG port • CPU-bus and PCI-bus logic analyzer headers • Port 80 and Port 680 hexadecimal displays • TIP board interface

These features are described in the following paragraphs.

JTAG Ports (Q14 and D17) The Am486 microprocessor provides an IEEE Standard 1149.1-1990 (JTAG) compliant test access port and boundary-scan architecture. The JTAG port provides a scan interface for testing the microprocessor in a production environment. The microprocessor’s JTAG port is available on connector J35 at location Q14.

Do not attempt use the second JTAG port (part P48 at location D17). This port is used at AMD to program the Vantis™ MACH® programmable logic device.

Reprogramming of the MACH device can cause improper system operation. The MACH device controls the ISA Flash memory space and the Port 80h and 680h hexadecimal displays. See “ISA Flash Memory (F20)” on page 2-23 and “Hexadecimal Display (H23, J23)” on page 2-17.

Logic Analyzer Headers The CPU interface signals are buffered and routed to headers for a logic analyzer. The signals on the CPU bus logic analyzer headers are arranged to be compatible with the disassembler for the HP 16500 Logic Analyzer, but any analyzer can be used. Table 2-3 lists the available headers, their locations in Figure 2-3, and the Appendix B schematics sheet on which they appear. Sheet 4 of the schematics includes usage notes.

Am486® Microprocessor PCI Customer Development Platform 2-15 Table 2-3. Analyzer Headers

Part Description Location in See App. B Figure 2-3 on Schematics Page 2-5 on: P36 POD 4, Microprocessor data (GD) P24 Sheet 4 signals P38 POD 3, Microprocessor data (GD) M24 Sheet 4 signals P39 POD 2, Microprocessor control L11 Sheet 5 signals, plus LA qualifier (see note on schematics Sheet 4) P40 POD 6, Microprocessor address I17 Sheet 5 (GA) signals P41 POD 1, Microprocessor control K16 Sheet 5 signals P42 POD 5, Microprocessor address I20 Sheet 5

(GA) signals, including logic- derived GA0 and GA1 signals P43 PCI Address and Data (PAD) signals F11 Sheet 12 P44 PCI Address and Data (PAD) signals H9 Sheet 12 P45 PCI control signals C12–D13 Sheet 12 P46 PCI control signals C9–D10 Sheet 12 P47 POD 7, Miscellaneous K10 Sheet 4 microprocessor control signals

2-16 Am486® Microprocessor PCI Customer Development Platform User’s Manual In addition to the logic analyzer headers, separate three-pin headers are provided for each PCI device’s bus request and bus grant signals. These headers are listed in Table 2-4:

Table 2-4. PCI Bus Master Test Points

Part Signal Location in See App. B Figure 2-3 on Schematics Page 2-5 on: JP29 PREQJ0 I6 Sheet 12 PGNTJ0 GND JP30 PREQJ1 K5 Sheet 12 PGNTJ1 GND JP31 PREQJ2 E7 Sheet 12 PGNTJ2 GND

In-Circuit Emulator Compatibility (M14, Q15–Q16) The PCI CDP can be used with an in-circuit emulator that mates to the pin-grid- array (PGA) zero-insertion-force (ZIF) socket in place of the Am486 microprocessor. To support emulators that use an Intel microprocessor, the necessary CPU power-supply jumpers are provided so the board will work with Intel 486 DX2 and DX4 chips. See “CPU Voltage Adjustment (Q15–Q16)” on page 2-32.

When connecting an in-circuit emulator, risers might be required to allow proper placement relative to the microprocessor socket and the ISA slots.

Hexadecimal Display (H23, J23) The PCI CDP includes 2-digit hexadecimal displays for port 80h and port 680h debugging messages. To change the display value, perform an 8-bit write to I/O port 80h or 680h, respectively. The value written is latched by the display and cannot be read back by software.

Am486® Microprocessor PCI Customer Development Platform 2-17 Test Interface Port (TIP) (A16) The PCI CDP includes a connector for the AMD Test Interface Port (TIP) board. The TIP board is used for testing and debugging AMD embedded product customer development platforms. It connects through a ribbon cable to the TIP connector on the platform.

The TIP board provides a collection of peripherals, such as LEDs, hexadecimal displays, an LCD display, two serial ports, a parallel port, an Ethernet controller, and Flash memory, that can be convenient in system development.

The PCI CDP’s TIP connector resides on the ISA bus and can use the ISA interrupt request (IRQ) signals if a TIP board is connected. Individual TIP connector IRQ signals are listed in Table 2-5. See the TIP board documentation for I/O addressing information.

Table 2-5. TIP Interrupt Usage

TIP Function Interrupt TIP Ethernet IRQ15

TIP parallel port IRQ12 TIP serial port 1 IRQ11 TIP test function IRQ14 TIP serial port 2 IRQ10

NOTE: The TIP board’s IRQ usage can conflict with the PCI CDP’s onboard PC peripherals. Some TIP or CDP peripherals may not operate correctly when the TIP board is in use.

2-18 Am486® Microprocessor PCI Customer Development Platform User’s Manual PCI Bus (I7)

The PCI CDP has two desktop-PC-style PCI expansion connectors (parts SLT1 and SLT2) to allow the installation of a wide array of off-the-shelf 5-V PCI devices. These include standard devices such as video, sound, SCSI, or PCMCIA adapters, or diagnostic devices such as PCI bus analyzers, extender cards, and other diagnostic hardware. The slots do not support 3.3-V PCI peripherals. The PCI bus is implemented via the chipset’s M1489 northbridge chip except for bus arbitration, which is handled by the M1487.

For PCI bus configuration, connector SLT1 is addressed as Device 3 and SLT2 is addressed as Device 4. See Table 2-2, “PCI Configuration Addressing,” on page 2-11.

The PCI bus connector’s interrupt signals are routed as shown in Table 2-6. (The Ethernet interrupt signal is also shown for reference.) The initialization code dynamically assigns PCI interrupts to an interrupt request (IRQ) in the chipset’s PCI INTx routing table mapping registers. See the chipset documentation for details on the mapping registers.

Table 2-6. PCI Bus Interrupt Routing

PCI Bus Interrupt PCI Slot 1 Signal PCI Slot 2 Signal Ethernet Signal INT0 INTA INTD — INT1 INTB INTA — INT2 INTC INTB INTA INT3 INTD INTC —

Am486® Microprocessor PCI Customer Development Platform 2-19 Level-2 Cache Memory (K19–N19 and N11)

The PCI CDP includes an onboard 512-Kbyte, single-bank, direct-mapped, unified Level-2 cache. This is the largest single-bank cache allowed by the chipset. The cache tag and data static RAM (SRAM) devices are soldered onto the PCI CDP board. A 10-ns tag SRAM device and 15-ns data SRAM devices are used to achieve 2-1-1-1 timing on reads and 2-2-2-2 on writes.

The tag SRAM is a single 32-K by 8-bit device, part U11, and the data SRAMs are 128-K by 8-bit devices, parts U7, U8, U9, and U10.

Chipset registers allow the level-2 cache to be disabled or enabled. The level-2 cache can be configured for either write-back or write-through operation.

NOTE: The benefit of level-2 cache varies, depending on the software being used.

DRAM Main Memory (P7)

The PCI CDP comes with three standard, 5-V, 72-pin single inline memory module (SIMM) sockets, populated with three 16-Mbyte, 60-ns, extended data out (EDO) SIMMs.

The included SIMMs provide the largest and fastest DRAM configuration allowed in this design. For customer designs, the SIMM configurations supported depend upon the chipset and the initialization or BIOS code used to configure the chipset’s registers. See the chipset documentation for information about detecting and configuring DRAM. The BIOS provided will automatically detect the amount of DRAM installed.

The chipset used in this design supports 2-, 4-, 8-, 16-, or 32-Mbyte SIMMS using 4- or 16-Mbit technology DRAM chips. Either fast page mode (FPM) or EDO SIMMs can be used, and the sockets can be filled with a combination of FPM or EDO SIMMs. All installed SIMMs must be run at the same speed, however.

The chipset allows either 1, 2, or 3 DRAM banks. Single- and double-bank SIMMs can be combined as shown in Table 2-7 on page 2-21.

2-20 Am486® Microprocessor PCI Customer Development Platform User’s Manual Table 2-7. SIMM Socket Population Chart

SIMM 0 SIMM 1 SIMM 2 Single Bank SIMM Single Bank SIMM Single Bank SIMM Double Bank SIMM Single Bank SIMM —

NOTE: 32- or 36-bit-wide memory can be used. However, 36-bit EDO SIMMs are accessed as only 32 bits wide because the FINALi chipset does not support EDO SIMMs’ 32-bit data plus 4-bit error correction code (ECC) format. Only traditional byte-wide parity is supported.

Boot ROM (C16)

The PCI CDP provides a 0.5-inch wide 32-pin DIP socket (part U14) for an initialization or BIOS ROM device. The boot ROM is implemented on the M1487 chip’s LinkBus.

The boot ROM socket is populated with a BIOS that allows the PCI CDP to boot

and run DOS, Windows, or a real-time operating system (RTOS) immediately.

The platform must always boot from the boot ROM because of chipset limitations. The chipset does not allow booting from another source such as DRAM-bus, ISA- bus, or PCI-bus memory.

The boot ROM address space size defaults to 128 Kbytes, using ROM device address bits A0–A16, but the board design provides jumpers JP32 and JP33 (at locations C14 and B14) for configuring the ROM device’s A17 and A18 address signals. The jumpers allow these address bits to be left High, tied Low, or connected to their corresponding ISA bus signal. This provides flexibility in addressing various sized Flash memory or ROM devices. See Figure 2-5 on page 2-22

Am486® Microprocessor PCI Customer Development Platform 2-21 JP33 (SA18)JP32 (SA17) 5 V

12 3 12 3 ISA Signal 12 3 (SA17 or SA18)

Boot ROM ROM Pin (A17 or A18)

ROM Jumper Locations Individual Jumper Schematic

Figure 2-5. JP32 and JP33 Jumper Configuration (B14–C14)

By default, jumpers JP32 and JP33 are not connected, so ROM device pins A17 and A18 are tied High to address the 128-Kbyte BIOS range, E0000h–FFFFFh. If these jumpers are changed to select ISA addressing for addresses C0000h–DFFFFh, software must enable ROM addressing for this space via chipset register index 12h, bits 2–1, and index 44h, bits 7–6.

For software compatibility, the boot ROM image appears from E0000h to FFFFFh

in the Am486 microprocessor’s lower 1-Mbyte address space. (This assumes that a 128-Kbyte boot ROM is used.) At reset, however, the microprocessor is in a special state that causes it to fetch its first instruction from FFFFFFF0h, at the top of its extended memory range. To provide the first instruction, the boot ROM is aliased to begin at FFFE0000h. One of the first instructions is typically a far jump, which ends the special state and causes the microprocessor to continue execution in the lower 1-Mbyte space.

Because boot ROM accesses are relatively slow, subsequent initialization code typically copies the boot ROM contents into DRAM space and configures the chipset’s Shadow Region Register to direct all boot ROM accesses to this shadow image of the boot ROM.

2-22 Am486® Microprocessor PCI Customer Development Platform User’s Manual ISA Flash Memory (F20)

The PCI CDP includes 1 Mbyte of 16-bit wide AMD Flash memory soldered onto the board and located logically on the ISA Bus. A Vantis MACH programmable logic device is used to control the interface between the ISA bus and the Flash device. This provides an example of how a small amount of ISA Flash memory might be implemented in customer designs.

The ISA Flash memory employs one Am29F800 top-sector boot block Flash memory chip (part U58). This device occupies ISA memory space from address F00000h to FFFFFFh. See Figure 2-6 on page 2-24. Software should access this space in 16-bit words on even addresses.

Software can enable this ISA memory space by setting bit 3 of the chipset’s ROM Function Register, index 12h. This disables DRAM access in the 1-Mbyte range from F00000h to FFFFFFh, allowing access to the ISA memory space instead. If bit 3 of index 12h is clear, access to the ISA Flash memory space is allowed only if 15 Mbytes or less of DRAM is installed.

The Flash device is configured in word mode, so only 16-bit access is allowed. The ISA address signals are routed so that ISA address bit A1 is routed to bit A0 on the Flash device, so it can only be addressed on even word boundaries. When generating Flash command sequences, multiply the Flash address by two to generate the correct ISA address. For example, writing address F00AAAh asserts 555h (AAAh ÷ 2) on the Flash device’s address pins.

The Am29F800 can be programmed using the JDEC single-power-supply Flash standard command set. See the Am29F800 documentation for details. Software for using Flash memory is provided with the PCI CDP. See the readme file on the diskette that came with your kit for information about available utilities.

ISA space is limited to 16 Mbytes, and because the chipset provides limited support for mapping ISA memory windows over DRAM, only 1 Mbyte of Flash memory is provided. However, in a customer design with a small amount of DRAM, a larger ISA Flash memory space can be situated between the top of DRAM and the 16 Mbyte ISA address limit. Note that access to memory on the ISA bus is relatively slow when compared to DRAM or PCI bus transactions. See “EIP Flash Memory (L21)” on page 2-25 for another approach.

Am486® Microprocessor PCI Customer Development Platform 2-23 (56 Mbyte) 37FFFFFh EIP Flash Bank 1 Accessed as 3400000h Fourth DRAM (52 Mbyte) 33FFFFFh Bank (Bank 3) EIP Flash Bank 0 } EIP Location 3000000h Depends on (48 Mbyte) 2FFFFFFh DRAM Size DRAM

1000000h (16 Mbyte) FFFFFFh ISA Flash Enabled Via Memory Chipset Register F00000h } 12h, Bit 3 (15 Mbyte) EFFFFFh

DRAM

100000h 128 Kbyte (1 Mbyte) 0FFFFFh Boot ROM DRAM 000000h

Figure 2-6. Typical Memory Map With ISA and EIP Flash Memory

2-24 Am486® Microprocessor PCI Customer Development Platform User’s Manual EIP Flash Memory (L21)

The PCI CDP includes 8 Mbytes of Flash memory for execute-in-place (EIP) applications. The EIP Flash memory is implemented in the fourth bank (bank 3) of the DRAM controller’s address space. This memory consists of eight 29F800B top-sector boot block Flash memory devices (parts U61, U62, U63, U64, U65, U66, U67, and U68), soldered to the board and organized as two 32-bit wide Flash memory banks.

The EIP Flash memory is controlled by an AMD 22V10 PAL® device programmed to act as a simple DRAM-to-Flash interface that makes the Flash memory appear to the M1489 DRAM controller as a single bank of 32-bit-wide EDO DRAM.

The provided BIOS enables the EIP Flash memory and configures the other DRAM banks accordingly. To enable the EIP Flash memory, the BIOS programs the chipset’s DRAM Configuration Register 2 (index 11h, bits 4–7) so the fourth DRAM bank is accessed as 2-Mbyte by 8 (11 row, 10 column) DRAM chips. The DRAM-to-Flash interface uses CPU address bit A22 for Flash memory bank switching (A22 is routed to DRAM address bit 8 in the selected configuration). Because of timing requirements, it is also necessary to program the chipset’s

DRAM Configuration and Timing Control registers (index 1Ah and 1Bh) to disable hidden refresh, disable RAS-only refresh, select Fast access mode (not Fastest), and select CAS before RAS refresh. This affects all four DRAM banks.

The EIP Flash memory can be accessed only by the CPU (no PCI bus-master access to the EIP Flash is allowed), and all accesses are 32 bits wide. During normal operation, the EIP Flash memory can be read like other DRAM memory, but data cannot be written directly. Instead, the Am29F800 devices are programmed using the JDEC single-power-supply Flash standard command set. See the Am29F800 documentation for details. Software for using Flash memory is provided with the PCI CDP. See the readme file on the diskette that came with your kit for information about available utilities.

Software that writes to the EIP Flash memory must make sure that accesses to the Flash memory are not cached. This can be done by disabling Level-1 and Level-2 memory caching, or by appropriate programming of the page tables if paging is enabled in the microprocessor.

Am486® Microprocessor PCI Customer Development Platform 2-25 Software that writes to the EIP Flash memory must also avoid any back-to-back write cycles (including back-to-back non-burst cycles) to the EIP Flash memory space. For reliable writes, always read or write a different DRAM bank (0, 1 or 2) before and after writes to the EIP space. For example, read location 00000h, write a value to Flash memory, and then read location 00000h again. (Simply running the Flash programming software in the normal DRAM space does not ensure reliable Flash programming, even though caching is disabled.)

Reading the EIP Flash memory does not entail any of the timing restrictions that apply to writes. The microprocessor can read EIP Flash memory with any combination of single-beat or burst read cycles.

The EIP Flash memory itself is organized in two banks. The base address of each EIP bank depends on how much DRAM is installed in DRAM banks 0–2. The board is shipped with 48 Mbytes installed, so by default the EIP first bank base address is 3000000h (48 Mbytes + 1 byte), and the EIP second bank base address is 3400000. See Figure 2-6 on page 2-24. Software can query the chipset’s DRAM Configuration Registers (index 10h and 11h) to determine the size of banks 0–2. See the chipset documentation for a description of these registers.

Each Flash device is configured in byte mode, with four devices in each EIP bank.

The CPU address signals are routed so that CPU address bit A2 is routed to bit A0 on the Flash devices, so the EIP space can only be addressed on even 4-byte (32- bit double-word) boundaries. When writing to the devices’ control registers, multiply the byte-mode register offset by four to generate the correct CPU address. For example, if the bank base address is 3000000h, writing address 3002AA8h asserts AAAh (2AA8h ÷ 4) on each Flash device’s address pins.

2-26 Am486® Microprocessor PCI Customer Development Platform User’s Manual Real-Time Clock (G17)

The real-time clock (RTC) function in the chipset’s 1487 chip is initially disabled on the PCI CDP. Instead, a separate DS1685 year-2000 (Y2K)-compliant RTC is enabled.

The DS1685 provides the features of widely-used, non-Y2K-compliant RTCs such as the DS1287. In addition, the DS1685 provides a byte for storing century information, plus other registers and features not found in older RTC chips.

Because of its extra features, the DS1685 RTC is not completely compatible with the DS1287. The provided BIOS operates correctly with the DS1685 RTC, but the extra RTC features can cause unexpected behavior if a customer-supplied BIOS is used in PC-AT compatible systems. One example is that the DS1685 provides some interrupt sources that are not present in the DS1287 RTC. Customer-written initialization software can take the following steps to disable the extended RTC interrupts:

1. Set the DV0 bit in CMOS register A to enable access to the extended register bank in the DS1685.

2. Write a value of 60h to CMOS address 4Bh to disable the extended interrupt addresses. 3. Clear the Dv0 bit in CMOS register a to disable access to the extended register bank (so that legacy software behaves as expected). 4. Read CMOS register C to clear any pending interrupts that were triggered while the extended interrupts were enabled. For DS1685 RTC programming details, see the DS1685/DS1687 3 Volt/5 Volt Real Time Clock Data Sheet, and Application Note 77: DS1585/87, DS1685/87, and DS17x85/87 Accessing Extended User RAM via Software, available from Dallas Semiconductor, www.dalsemi.com.

If desired, the M1487’s internal RTC can be enabled instead of the DS1685 by removing resistor part R58 from the back side of the board, beneath location I14. (See Sheet 16 of the schematics in Appendix B.)

Am486® Microprocessor PCI Customer Development Platform 2-27 ISA Bus Interface (A7)

The PCI CDP is populated with two standard ISA bus connectors (parts SL1 and SL2) for developers who need to use ISA devices in their development systems. The ISA bus interface is provided by the chipset’s M1497 southbridge.

ISA devices that use the F00000h to FFFFFFh address space cannot be used on the PCI CDP, because this area is used by the ISA Flash memory bank. See “ISA Flash Memory (F20)” on page 2-23.

ISA devices that use the C0000h to DFFFFh address space cannot be used if this space is enabled for boot ROM addressing. See “Boot ROM (C16)” on page 2-21. Boot ROM addressing in this range might also cause conflicts with devices using the D0000h to DFFFF address space.

Super I/O (C19)

The PCI CDP uses an M5113 Super I/O chip to provide standard PC input/output functions. The Super I/O chip provides:

• Two 16450/16550-compatible serial ports • IrDA 1.0 infrared interface • AT-compatible parallel port • 82077-compatible floppy disk interface

The BIOS supplied with the platform configures these peripherals to operate as they would on a standard PC. See the Acer Laboratories Inc. M5113 data sheet for detailed configuration information.

2-28 Am486® Microprocessor PCI Customer Development Platform User’s Manual Serial Ports (E23 and C23) The platform’s Super I/O device includes two 16550-compatible serial ports. These are routed to two 9-pin D-shell connectors, J8 and J9. See Figure 2-7 and Table 2- 8. Light-emitting diodes (LEDs) are provided near each serial port to indicate transmit and receive activity.

Notes: 6 9 See Figure 2-3 on page 2-5 for connector locations. Figure 2-7. Serial Port Connector Pins (J8, J9)

Table 2-8. Serial Port Pin/Signal Table

Pin Signal 1DCD 2RXD

3TXD 4DTR 5 GND 6DSR 7RTS 8CTS 9RIN

IrDA Interface (A19) The Super I/O device is configured to support infrared data transfers via an IrDA LED module, part U44. The serial data transmission rates include all of the UART bit rates (up to 115 Kbps).

The IrDA LED module is connected to dedicated pins on the M5113 Super I/O chip. The IrDA interface shares one UART with serial port COM2. A control bit in the M5113 chip controls whether the UART communicates over the COM2 port or the IrDA port. See the M5113: Enhanced Super I/O Controller Data Sheet, available from Acer Laboratories Inc. See www.acerlabs.com for contact information.

Am486® Microprocessor PCI Customer Development Platform 2-29 Parallel Port (A22) Figure 2-8 and Table 2-9 show the parallel port pinouts.

13 1

Notes: 25 14 See Figure 2-3 on page 2-5 for connector locations. Figure 2-8. Parallel Port Socket (J4)

Table 2-9. Parallel Port Pin/Signal Table

Pin Signal 1STRB 2–9 PD0–PD7 10 ACK 11 BUSY

12 PE 13 SLCT 14 AFDT 15 ERROR 16 INIT 17 SLCTIN 18–25 GND

Floppy Disk Drive (E20) The PCI CDP’s Super I/O chip provides a floppy disk controller to support the system’s floppy disk drive connector (part J6). Either a 5.25-inch or 3.5-inch floppy disk drive can be installed with a standard 34-pin connector. For details, see “Board Installation” on page 1-4.

2-30 Am486® Microprocessor PCI Customer Development Platform User’s Manual IDE Hard Drive (L4 and M4)

The PCI CDP contains two standard 40-pin IDE connectors (parts J5 and J7). The M1498 chip provides the IDE hard drive controller. For details on how to connect a single IDE hard drive to the PCI CDP, see “Board Installation” on page 1-4.

An LED is located next to each IDE connector to indicate IDE activity. IDE devices on connector J5 can generate interrupts on IRQ14, and devices on connector J7 can generate interrupts on IRQ15. This interrupt mapping can be changed by reprogramming the chipset configuration registers.

Each connector supports one master and one slave device. If only one device is attached to an IDE connector, that device must be configured as an IDE master. If a two-position cable is used to attach two devices to a single IDE connector on the board, one of the devices must be configured as an IDE master and the other as an IDE slave. See each IDE device’s documentation for configuration details.

Keyboard (O1)

The PCI CDP provides a standard AT-compatible keyboard connector (part J1) implemented via the chipset’s M5402 mouse/keyboard controller chip (part U79 at location D15).

Mouse (M1)

A port is provided for a PS/2-style mouse (connector J11). This device is driven by the M5402 mouse/keyboard controller chip.

Am486® Microprocessor PCI Customer Development Platform 2-31 CPU Voltage Adjustment (Q15–Q16)

The CPU power supply voltage can be adjusted by moving jumper JP4 or both jumpers JP2 and JP3 on the PCI CDP. Selectable voltages are 2.5 V, 3.3 V, 3.45 V, or 5 V. Figure 2-9 shows the default configuration of the CPU voltage jumpers (set for 3.45 V).

To select either 3.3-V or 2.5-V CPU voltage, leave JP2 and JP3 set to “ADJ” and move jumper JP4 to the desired voltage.

To select 5-V operation, move both jumpers JP2 and JP3 to their “5 V” position.

JP2 JP3 ADJ ADJ JP4 3.45 V

3.3 V

5 V 5 V 2.5 V

Figure 2-9. Voltage Jumper Default Configuration (Q15–Q16)

CAUTION: Jumpers JP2 and JP3 must both be placed in the same position. Positioning JP2 and JP3 differently can damage ! the PCI CDP.

2-32 Am486® Microprocessor PCI Customer Development Platform User’s Manual Power Supply Connectors (N2 and P2)

The PCI CDP accepts standard PC-style motherboard power connectors to supply power to the CPU and all onboard components. To ensure proper functionality of the power module, the board’s PC power supply sockets must be inserted correctly onto the board.

CAUTION: It is important that the ground wires of one connector are adjacent to the ground wires of the other. ! See Figure 2-10.

PS2 Power Conn

-5 GND GND +12 Back of +5 -12 +5 PWG IDE Connector Power Supply Conn.

Edge of Board

Figure 2-10. Ground Wire Connections

Am486® Microprocessor PCI Customer Development Platform 2-33 Reset and Interrupt Switches and Headers

Three push-button switches are provided so the user can generate RESET, SMI, and NMI events. In addition, a two-pin header is provided for the RESET signal so that an external pushbutton switch can be attached. These switches and headers are routed to the appropriate chipset signals as listed in Table 2-10.

Table 2-10. Switch Summary

Part Signal Description Location in See App. B Figure 2-3 Schematics on Page 2-5 on: SW1, PWG Used to reset the system. N5, K23 Sheet 17 JP34 SW2 NMI Used to generate an NMI K6 Sheet 17 event. SW3 EXTSMI Used to generate an SMI H11 Sheet 17 event.

Embedded BIOS software typically enters its debugging monitor when an NMI event is generated. In addition to pressing the NMI switch, an NMI event can be caused by a PCI-bus parity error, a DRAM parity error, or an ISA-bus IOCHCK error.

2-34 Am486® Microprocessor PCI Customer Development Platform User’s Manual Resistor Options

The PCI CDP includes a number of resistor populate/depopulate options, which are listed in Table 2-11. Many are used only as manufacturing options, but some may be useful for exploring design options or better emulating a target design.

Table 2-11. Resistor Options

Part Signal Description Location in See App. B Figure 2-3 Schematics on Page 2-5 on: R11 CLKMUL When R11 is populated and R148 is M17 Sheet 2 removed, the clock multiplier for an Am486DX2-66 microprocessor is selected. R58 ENRTC When populated (the default), the I14 (back Sheet 16 M1487 chip’s internal RTC is disabled side) and the DS1685 Y2K-compliant RTC

is enabled. R59 CMPSTJ When removed (the default), the 1X I14 (back Sheet 16 CPU-to-PCI bus frequency multiplier side) is selected. (1X is the only multiplier supported in this design.) R70 TURBO When R70 is removed and R71 is I14 (back Sheet 17 populated (the default), the M1487’s side) TURBO signal is High (asserted). This input must be enabled by software to have any effect. R71 TURBO When R71 is populated and R70 is I14 (back Sheet 17 removed (the default), the M1487’s side) TURBO signal is asserted. This input must be enabled by software to have any effect. R93 CLKPU2 When R93 is populated and R176 is J3 (back Sheet 18 removed, the system clock speed is 25 side) MHz.

Am486® Microprocessor PCI Customer Development Platform 2-35 Table 2-11. Resistor Options (Continued)

Part Signal Description Location in See App. B Figure 2-3 Schematics on Page 2-5 on: R145 KBINHIBIT When R145 is populated and R146 is D15 (back Sheet 25 removed (the default), the M5042 side) keyboard controller is enabled. R146 KBINHIBIT When R145 is populated and R146 is D15 (back Sheet 25 removed (the default), the M5042 side) keyboard controller is enabled. R148 CLKMUL When R148 is populated and R11 is M17 Sheet 2 removed (the default) the clock multiplier for an Am486DX4-100 or Am486DX5-133 microprocessor is selected. R170 IBCSTJ When populated (the default), the I14 (back Sheet 16 M1487’s internal keyboard controller is side) disabled. (The M1487 internal keyboard controller function is discontinued. The M5042 is provided instead.) R176 CLKPU2 When R176 is populated and R93 is J3 Sheet 18 removed (the default), the system clock speed is 33 MHz.

2-36 Am486® Microprocessor PCI Customer Development Platform User’s Manual A-1 Default PositionDefault Marking Position Pins 2–3 “ADJ” Figure 2-3 Pageon 2-5 R15 Pins 1–2 “3.45 V” C14 No connection (No marking) B14 No connection (No marking) 3 Q15 3 Q162–3 Pins “ADJ” CC CC CPUV2, CPUV3 A17 A17 A18 A18 Microprocessor PCI Customer Development Platform Platform Development Customer PCI Microprocessor ® JP2 CPUV Part Signal in Location JP4 CPUV1, JP3 CPUV JP32 ROM Boot JP33 ROM Boot Am486 This chapter lists the default settings of the Am486 microprocessor PCI customer development platform whenshipped. it is A-1.Table Settings Default Jumper Appendix A Appendix Settings Default

A-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual B-1 Microprocessor PCI Customer Development Platform Platform Development Customer PCI Microprocessor ® Am486 The billthe materials of Am486for microprocessor customer PCI development B-2. page on begins (CDP) platform B-10. page on begin CDP PCI the build to used schematics actual The Appendix B Appendix Schematics and Bill of Materials

Board Bill of Materials (BOM)

Item Qty. Reference Part Package Description

1 119 C1, BC1, BC2, C3, BC3, C4, 0.1 µF 805 RC0805, X7R, ±10%, BC4, C5, BC5, C6, BC6, C7, 50 V BC7, C8, BC8, BC9, BC10, BC11, BC12, BC13, BC14, BC15, BC16, BC17, BC18, BC19, BC20, BC21, BC22, BC23, BC24, BC25, BC26, BC27, BC28, BC29, BC30, BC31, BC32, BC33, BC34, BC35, C36, BC36, C37, BC37, C38, BC38, C39, BC39, BC40, BC41, BC42, BC43, BC44, BC45, BC46, C47, BC47, C48, C50, C52, C65, C67, C69, C70, C71, C72, C73, C74, C75, C76, C77, C79, C80, C81, C82, C88, C89, C90, C91, C92, C93, C94,

C95, C100, C105, C111, C112, C114, C115, C122, C123, C124, C125, C126, C127, C128, C129, C130, C131, C132, C133, C134, C135, C136, C137, C156, C157, C160, C166, C167, C168, C169, C170, C171, C172, C173, C174

2 1 BT1 3 V Coin cell (socket) KEYSTONE 103 or 106

3 14 C9, C10, C11, C12, C13, C34, 0.01 µF 805 RC0805, X7R, ±10%, C35, C83, C96, C97, C102, 50 V C103, C104, C109

4 6 C14, C28, C58, C64, C158, 47 pF 805 RC0805, NPO, ±5%, C159 50 V

5 33 C15, C16, C17, C18, C19, C20, 180 pF 805 RC0805, NPO, ±10%, C21, C22, C23, C24, C25, C26, 50 V C27, C29, C30, C31, C32, C138, C139, C140, C141, C142, C143, C144, C145, C146, C147, C148, C149, C150, C151, C152, C153 Notes: An asterisk (*) indicates parts that are not populated.

B-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual Item Qty. Reference Part Package Description

6 10 C33, C41, C42, C43, C46, C56, 15 pF 805 RC0805, NPO, ±5%, C57, C60, C66, C154 50 V

7 1 C40 1000 pF 805 RC0805, 1/8 W, ±5%, 50 V

8 2 C44, C45 39 pF 805 RC0805, NPO, ±5%, 50 V

9 4 C53, C54, C155, C161 10 pF 805 RC0805, NPO, ±5%, 50 V

10 1 C55 22 pF 805 RC0805, NPO, ±5%, 50 V

11 1 C68 6.8 µF C-CASE TANTALUM, C-CASE, 16 V, ±20%

12 2 C86, C78 2.2 µF B-CASE TANTALUM, B-CASE, 20 V, ±20%

13 23 TC2, TC3, TC9, TC11, TC12, 10 µF C-CASE TANTALUM, C-CASE, TC13, TC14, TC15, TC16, 16 V, ±20% TC17, TC18, TC19, TC22, TC23, TC24, TC25, C84, C87, C106, C107, C108, C110, C113

14 1 C85 1 µF A-CASE TANTALUM, A-CASE, 16 V, ±20%

15 2 C98, C99 33 pF 805 RC0805, NPO, ±5%, 50 V

16 1 C101 0.001 µF, 2 KV TH SPRAGUE 30GAD10 (MIN.)

17 4 C162, C163, C164, C165 0.015 µF 805 RC0805, X7R, ±10%, 50 V

18 6 D1, D5, D6, D7, D8, D9 MMBD4148 (SOT23) SOT-23 VISHAY MMBD4148

19 1 D10 LED (SOT23) SURSOT- LUMEX 23 SSL-LX15IC-RP

20 4 D11, D12, D13, D14 LED (SOT23) SURSOT- LUMEX 23 SSL-LX15GC-RP

21 2 D15, D17 LED (2mA, SOT23) SOT-23 KINGBRIGHT KM-23LSGC Notes: An asterisk (*) indicates parts that are not populated.

Am486® Microprocessor PCI Customer Development Platform B-3 Item Qty. Reference Part Package Description

22 2 D16, D18 LED (2mA, SOT23) SOT-23 KINGBRIGHT KM-23LEC

23 2 F1, F2 FUSE, 0.5A 1206 BUSSMAN 3216FF-500mA

24 1 HS1 HEATSINK (TO-220) THERMALLOY ML32

25 7 JP2, JP3, JP29, JP30, JP31, HEADER 3X1 TH-1X3 1X3 HEADER; 0.025” JP32, JP33 SQ. POST AMP 87224-3

26 1 JP4 HEADER 3X2 TH-2X3 1X3 HEADER; 0.025” SQ. POST AMP 103186-3

27 1 JP34 HEADER 2X1 TH-1X2 1X2 HEADER; 0.025” SQ. POST AMP 87224-2

28 1 J1 KYBD CONN TH AMP 212044-1

29 2 J2, J3 PWR-CN6 TH MOLEX 15-48-0106

30 1 J4 Parallel Port DB25 AMP 745967-7

31 2 J7, J5 CNN-40C TH-2X20- 2X20 HEADER; SHRD

SHRD AMP 103308-8

32 1 J6 CNN-34C TH-2X17- 2X17 HEADER; SHRD SHRD AMP 103308-7

33 2 J8, J9 SERIAL PORT DB9 AMP 745410-1

34 1 J10 AMP RJ45A TH AMP 555153-1

35 1 J11 MOUSE_CON TH AMP 750329-2

36 1 LS1 SPEAKER ISL PROD. INTL. ISL-8032VT

37 9 L1, L2, L3, L4, L5, L6, L7, L8, FB RC1206 MURATA ERIE L9 BLM32A07

38 10 MT1, MT2, MT3, MT4, MT5, Mounting Hole MT6, MT7, MT8, MT9, MT10

39 1 P31 COND60 AMPMOD AMP 104069-7 50, 1X30, R-ANG

40 2 P35, P48 HEADER2X5; SHRD TH-1X5- 2X5 HEADER; SHRD SHRD AMP 103308-1 Notes: An asterisk (*) indicates parts that are not populated.

B-4 Am486® Microprocessor PCI Customer Development Platform User’s Manual Item Qty. Reference Part Package Description

41 11 P36, P38, P39, P40, P41, P42, HP CONN TH-1X10- 3M:2520-6003UB or P43, P44, P45, P46, P47 SHRD AMP 103308-5

42 1 Q1 MMBT3906 (SOT23) SOT-23 VISHAY MMBT3906

43 2 Q4, Q2 MMBT3904 (SOT23) SOT-23 VISHAY MMBT3904

44 1 Q5 TIP127 TO-220 MOTOROLA TIP127

45 9 RN1, RN2, RN3, RN4, RN8, 33-8B CTS 743 08-3 330 J TR RN9, RN10, RN11, RN12

46 7 RN5, RN6, RN7, RN13, RN14, 22-8B CTS 743 08-3 220 J TR RN15, RN16

47 12 RP1, RP2, RP5, RP6, RP7, 10 K-10P SIP10 CTS 770 10 1 103 SP RP12, RP14, RP16, RP17, RP18, RP19, RP20

48 2 RP4, RP3 1 K-10P SIP10 CTS 770 10 1 102 SP

49 6 RP8, RP9, RP10, RP11, RP15, 4.7 K-10P SIP10 CTS 770 10 1 472 SP RP21

50 1 RP13 330-8P SIP8 CTS 770 8 1 331 SP

51 19 R3, R4, R5, R13, R19, R49, 10 K 805 RC0805, 1/8 W, ±5%, R50, R52, R61, R64, R68, R76, 50 V R77, R91, R104, R131, R141, R142, R175

52 17 R6, R20, R21, R34, R58, R78, 1K 805 RC0805, 1/8 W, ±5%, R85, R103, R105, R118, R130, 50 V R134, R170, R173, R174, R177, R178

53 5 R7, R8, R27, R81, R124 33 805 RC0805, 1/8 W, ±5%, 50 V

54 1 R11 *10 K 805 RC0805, 1/8 W, ±5%, 50 V

55 6 R14, R15, R16, R17, R18, R147 22 805 RC0805, 1/8 W, ±5%, 50 V

56 11 R22, R31, R35, R36, R38, R41, 10 805 RC0805, 1/8 W, ±5%, R42, R54, R99, R100, R101 50 V

57 1 R23 27.4 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V Notes: An asterisk (*) indicates parts that are not populated.

Am486® Microprocessor PCI Customer Development Platform B-5 Item Qty. Reference Part Package Description

58 1 R25 25.5 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

59 1 R26 15.8 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

60 10 R28, R94, R97, R135, R136, 330 805 RC0805, 1/8 W, ±5%, R137, R138, R156, R158, R160 50 V

61 1 R29 15.0 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

62 4 R30, R65, R139, R140 100 805 RC0805, 1/8 W, ±5%, 50 V

63 15 R33, R47, R57, R119, R120, 0 805 RC0805, 1/8 W, ±5%, R121, R122, R123, R127, R148, 50 V R163, R165, R167, R169, R176

64 9 R39, R44, R45, R75, R90, R92, 4.7 K 805 RC0805, 1/8 W, ±5%, R106, R171, R172 50 V

65 1 R48 51 K 805 RC0805, 1/8 W, ±5%, 50 V

66 1 R59 *1 K 805 RC0805, 1/8 W, ±5%, 50 V

67 5 R62, R63, R149, R150, R151 270 805 RC0805, 1/8 W, ±5%, 50 V

68 2 R70, R146 *2.2 K 805 RC0805, 1/8 W, ±5%, 50 V

69 9 R71, R80, R95, R96, R98, 470 805 RC0805, 1/8 W, ±5%, R145, R157, R159, R161 50 V

70 1 R79 10M 805 RC0805, 1/8 W, ±5%, 50 V

71 1 R93 *4.7 K 805 RC0805, 1/8 W, ±5%, 50 V

72 1 R102 47 805 RC0805, 1/8 W, ±5%, 50 V

73 1 R107 100, 1% 805 RC0805, 1/8 W, ±1%, 50 V

74 2 R108, R109 49.9, 1% 805 RC0805, 1/8 W, ±1%, 50 V Notes: An asterisk (*) indicates parts that are not populated.

B-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual Item Qty. Reference Part Package Description

75 4 R110, R111, R112, R113 75, 1% 805 RC0805, 1/8 W, ±1%, 50 V

76 3 R114, R115, R117 1.00 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

77 1 R116 22 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

78 4 R152, R153, R154, R155 1.5 K 805 RC0805, 1/8 W, ±5%, 50 V

79 4 R162, R164, R166, R168 *0 805 RC0805, 1/8 W, ±5%, 50 V

80 3 SIMM1, SIMM2, SIMM0 SIMM72 AMP 822030-3

81 2 SLT1, SLT2 PCI Slot AMP 145154-4

82 2 SL1, SL2 ISA AT Connector AMP 645169-3

83 3 SW1, SW2, SW3 PBNO C&K KT11P2SM

84 4 TC1, TC4, TC7, TC10 47 µF D-CASE TANTALUM, D-CASE, 16 V, ±20%

85 4 TC5, TC6, TC20, TC21 10 µF D-CASE TANTALUM, D-CASE, 25 V, ±20%

86 1 TC8 100 µF E-CASE TANTALUM, E-CASE, 16 V, ±20%

87 1 T1 PE68515 PULSE ENGR. PE-68515

88 1 U1 74F245 SOL20 SIGNETICS 74F245D

89 1 U5 M1489 PQFP208 ALi M1489

90 1 U6 LP2951 SO8 NATIONAL LP2951CM

91 4 U7, U8, U9, U10 128 Kx8-15 SOJ32(0.3” 128 Kx8, 15 ns, Corner /0.4”) Vcc/GND Pins, SOJ32

92 1 U11 32 Kx8-15 SOJ28(.3”) 32 Kx8, 15 ns, Corner Vcc/GND Pins, 0.3”SOJ28

93 1 U14 Am29F010-90 DIP32(0.6” AMD )(SOCKET Am29F010-90PC )

94 1 U15 74F04 SO14 SIGNETICS 74F04D Notes: An asterisk (*) indicates parts that are not populated.

Am486® Microprocessor PCI Customer Development Platform B-7 Item Qty. Reference Part Package Description

95 1 U17 IMI SC464 SSOP28 INTL. MICROCKTS. INC. IMISC464AYB

96 1 U21 M1487 PQFP160 ALi M1487

97 1 U22 DS1685-5 DIP24(0.65 DALLAS SEMI. 0”) DS1685-5

98 2 U24, U82 74F08 SO14 SIGNETICS 74F08D

99 1 U25 Am486 PGA169 AMD (AMP SOCKET1 Microprocessor, PGA 916504-2)

100 11 U26, U28, U30, U31, U32, U36, 74ABT16244 SSOP48 SIGNETICS U38, U40, U47, U49, U70 74ABT16244ADL

101 1 U42 74ABT244 SOL20 SIGNETICS 74ABT244D

102 1 U43 M5113A PQFP100 ALi M5113A

103 1 U44 TFDS6000 SMT TEMIC TFDS6000D

104 2 U46, U45 RS232-5V SSOP28 LINEAR TECH LTC1349CG

105 1 U51 Am79C972 PQR160 AMD Am79C972KC (PQR160)

106 1 U52 LXT970QC MQFP64 LEVEL ONE LXT970QC

107 1 U53 MC33269DT-3.3 DPAK MOTOROLA MC33269DT-3.3

108 1 U54 NM93C46N DIP8 NATIONAL NM93C46N

109 1 U55 MACH221 PQFP-100 AMD MACH221SP-7

110 9 U56, U61, U62, U63, U64, U65, 29F800-55 TSOP48 TSOP48 AMD U66, U67, U68 AM29F800BT-55EC

111 2 U60, U80 PALCE22V10_PLCC PLCC28 AMD (5ns) PALCE22V10H-5JC

112 1 U69 74ABT373 SOL20 SIGNETICS 74ABT373AD

113 1 U71 74ABT16245 SSOP48 SIGNETICS 74ABT16245BDL

114 4 U72, U73, U74, U75 Hex Display TH TI TIL311 Notes: An asterisk (*) indicates parts that are not populated.

B-8 Am486® Microprocessor PCI Customer Development Platform User’s Manual Item Qty. Reference Part Package Description

115 1 U77 74F32 SO14 SIGNETICS 74F032D

116 1 U78 74F06 SO14 SIGNETICS 74F06D

117 1 U79 M5042 PLCC44 ALi M5042

118 1 U81 NM93C66M8 SO8 NATIONAL NM93C66M8

119 1 U83 74F14 SO14 SIGNETICS 74F14D

120 1 U84 74ABT125 SO14 Signetics 74ABT125D

121 1 Y1 24 MHz_SMD ECLIPTEK ECSMA-24.00MTR

122 1 Y2 14.318 MHz_SMD ECLIPTEK ECSMAT-14.318MTR

123 2 Y4, Y6 32.768 KHz_SMD ECLIPTEK ECPSM29T-32.768KTR

124 1 Y5 25 MHz_SMD ECLIPTEK ECSMA-25.000MTR

127 1 XU14 DIP32(0.6”) SAMTEC ICA-632-SGG SOCKET

128 1 XBT1 3.3 V LITHIUM TOSHIBA CR2032 COINCELL

129 1 U25-HS FANSINK FOR CPU THERMALLOY 2321B- TCM-42S-PF17

130 5 XXX JUMPERS (0.1”) FOR 0.025” SQ. POSTS Notes: An asterisk (*) indicates parts that are not populated.

Am486® Microprocessor PCI Customer Development Platform B-9 Schematics

The schematics that follow are the actual CAD schematics used to build the PCI CDP. These schematics are useful for understanding and modifying the PCI CDP. Because the development platform is based on a particular chipset and incorporates many different possible design options, actual Am486 microprocessor-based designs might be considerably different.

B-10 Am486® Microprocessor PCI Customer Development Platform User’s Manual 1 2 3 4 5

Table of Contents Page 1: COVER.SCH Page 2: CPU.SCH Page 3: CPU_POWER.SCH Page 4: CPU_VIS1.SCH Page 5: CPU_VIS2.SCH Page 6: M1489.SCH Page 7: L2_CACHE.SCH Page 8: SIMM_SKTS.SCH A Page 9: EIP_MEM1.SCH A Page 10: EIP_MEM2.SCH Page 11: PCI_CONN.SCH Page 12: PCI_VIS.SCH Page 13: ENET1.SCH Page 14: ENET2.SCH Page 15: IDE.SCH Am486 Microprocessor Page 16: M1487.SCH Page 17: ROM_MISC.SCH Page 18: CLOCK.SCH Page 19: ISA_CONN.SCH Page 20: SUPER_I/O.SCH Page 21: SERIAL_PARALLEL.SCH Page 22: ISA_MEM1.SCH Page 23: ISA_MEM2.SCH Page 24: RTC_TIP.SCH PCI Customer Page 25: KEYBOARD.SCH Page 26: CPU_PINOUT.SCH

B Development Platform B Am486 Microprocessor Development System With PCI Expansion and On-Board Am79C972 100MB/s Ethernet Controller

Rev 2.0 (continued):

Rev 1.0: Original design SH17: Added jumpers to allow mulitple BIOS images in a single Flash ROM device Removed 1 diode from VBAT generation circuit Rev 1.1: Minor modifications after Design Review Added new NMI generation circuit and spare 'F14 gates Rev 1.2: Added External 8042 Style Keyboard Controller (SH24) Added jumper for external RESET# pushbutton Removed Support for M1487 Internal KBC (SH15) SH18: Fixed wiring error on crystal Removed Keyboard Interface From Clock Page (SH17) Removed MCLK1 net (16MHz) and rewired MCLK2 to drive all 33MHz clock nets Changed design name to Am486PCI C.D.P. Removed CLKCNTL signal from DOZE# pin of U17 C Rev 1.3: Added Extra Bypass Capacitors (SH5 & SH14 & SH15 & SH17) C Swapped Around Some Signals Within Resistor Networks (SH6 & SH20) SH20: Removed unneeded 0-ohm resistors from Super I/O chip Renamed MCLK1 net to M_CLK1 (SH24) Fixed wiring error on crystal Added 0-ohm resistor to make pin 10 & 11 pullup work (SH17) Added 'ABT125 buffer to drive serial port LEDs Added Pin to HS1 for NetLister (SH3) SH22: MACH device outputs changed for new ISA Flash support Fixed Error in 3.3V Regulator Circuit (SH12) SH23: Changed ISA Flash to 1MByte (512Kx16) Rev 1.4: Rearranged Clock Nets to Facilitate Routing (SH17) Changed Some Components to Standard Values SH24: Removed unneeded logic from RTC interface (50ohm to 49.9ohm, 1% on SH 13 and 40pF to 39pF, Added inverter to generate proper CS# for RTC chip Fixed wiring error on crystal Rev 2.0: Changed 5%SIP on reSH19)sistor packs to 10-pin (SH2, SH3, SH11, SH15, SH16, SH17, SH19, SH20 & SH21) Grounded U22-pin 22 Changed 330ohm SIP Resistor Pack to 8-pin (SH19) Removed 1 unused OR gate for use on SH17 SH3: Added diagram to correct Power Connector Footprint SH4 & 5: Broke CPU Logic Analyzer Headers into 2 pages SH25: Switched mouse connector to verticle type Added PAL to gnerate CPU A0 and A1 and also generate a Logic Analyzer Qualify signal Changed 'F06 symbol to show o/c Buffered BE[0..3], RDY#, BRDY#, and ADS# through the new PAL

D SH9: Added better explanation of EIP Flash memory operation D SH11: Added configuration information for PCI slots Rev 2.1: Updated revision level and prototype warning on all sheets Removed circuit to generate PCI PERR# to cause SH17: Modified ROM jumpers to allow mulitple BIOS images in a single Flash ROM M1487 to assert NMI to Am486 microprocessor device and support 256K or 512K BIOS for non-PC applications SH13: Added a 4K serial EEPROM for user parameters and mux. circuit to daisy chain it off the 1K device. SH22: Added XBUSCSJ signal to Mach device so it does not respond when Am486 '972 E/net device loads its configuration from 1K SEEPROM. fetches the reset vector at FFFF FFF0 CLKCNTL signal from M1487 used to select 1K or 4K SEEPROM. SH14 &15 &20: Connected pins 1 and 2 on all LEDs for greater purchasing/manufacturing flexibility SH14: Swapped R107 and R109; R109 is 49.9ohm, 1% Fixed wiring error on crystal SH15: Added 5 more 0.1uF bypass capacitors for new chips ('F14, 'ABT125, 22V10, 'F08, 'C66) SH16: Fixed wiring error on crystal Fixed wiring error in generation of low-active reset signal RSTDRV# Removed unused inverter (used on SH24) Changed net on NMI pin to 1487NMI for use in new circuit Changed R58 to be a populated component (C) Advanced Micro Devices, Inc. (800) 222-9323 E 5204 E. Ben White Blvd. E Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Am486 MICROPROCESSOR Note: Unless otherwise noted all logic operates off a 5V power supply PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev COVER.SCH 2.1

Date:Friday, December 04, 1998 Sheet 1of 26 Note: Unless otherwise stated the resistors are a 0805 package and 5% Tol. 1 2 3 4 5 Note: Unless otherwise stated the capacitors are a 0805 package and 10% Tol. 1 2 3 4 5 Am486 MICROPROCESSOR, PULLUPS, AND JTAG INTERFACE

STPCLKJ PCD_CACH

CPURST HITMJ INV

K2VCC A A

VCC RP1 1 C O2 2 O3 3 O4 4 O5 5 K2VCC O6 6 O7 7 CPUVCC3 O8 8 HITMJ O9 9 PULLHI1 10 CLK U25 O10 RESET 24 26 28 38 39 60 63 72 75 81 90 93 99 102 105 117 138 141 143 144 145 146 149 83 13 47 10 12 44 29 74 INTR 10K-10P NMI CPUCLK 37 111 MIOJ VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC M/IO# ZRSTDRV 50 HOLD 104 INTR D/C# DCJ 16 BOFF# 112 WRJ NMI 32 AHOLD W/R# 110 LOCK# LOCKJ INC 62 EADS# INC(DX2NC) 134 PLOCK#

BOFFJ 58 INC(DX4VCC5) PLOCK# 169 C40 KEN# ADSJ

AHOLD 17 SRESET ADS# 151 FLUSH# STPCLK# BLAST# 1000pF EADSJ 34 BLAST# 133 B IGNNE# BREQ B KENOJ INV(DX2INC) 68 BS16# BEJ3BREQ 116 HDLA

FLUSHJ 49 HITM#(DX2INC) HLDA 98 BS8# BEJ2 PWT IGNNEJ CACHE#(DX2INC) 15 A20M# PWT 88 PCD BS16J 51 BEJ1 48 RDY# PCD FERRJ BS8J GD31 57 BEJ0 BRDY# FERR# A20MJ GD30 56 RDYOJ GD29 69 BE3# 70 BEJ[0..3] BRDYOJ 80 BE2# 86 GD28 GA31 BE1# 87 GD27 GA30 25 D31 BE0# 92 GD26 43 GA29 8 D30 GD25 D29 GA28 BEJ[0..3] GD24 42 GA27A31 119 40 D28 115 GD23 41 D27 GA26A30 114 GD22 23 D26 GA25A29 136 GD21 6 D25 GA24A28 153 A27 GD20 4 D24 GA23 154 A26 GD19 2 D23 GA22 137 GA[2..31] 19 D22 Enhanced Am486 A25 124 GD18 1 D21 Microprocessor GA21A24 155 GD17 18 D20 GA20A23 125 GA[2..31] GD16 36 D19 (SOCKET1-PGA169) GA19A22 123 GA31 RP8 GD15 54 D18 GA18A21 126 GA30 85 122 1 C O2 2 C GD14 D17 GA17A20 GA29 C 67 A19 140 O3 3 GD13 D16 GA16 GA28 91 A18 121 O4 4 GD12 53 D15 GA15 127 GA27 5 D14 A17 O5 GD11 73 GA14A16 142 GA26 O6 6 35 D13 157 7 GD10 GA13A15 GA25 O7 61 D12 128 8 GD9 D11 GA12A14 GA24 O8 52 159 O9 9 GD8 66 D10 GA11A13 147 10 O10 GD7 97 D9 GA10A12 165 GD6 96 D8 GA9 A11 129 A10 4.7K-10P GD5 84 D7 GA8 148 103 D6 A9 131 GD4 GA7 78 D5 A8 167 GD3 107 D4 GA6 A7 130 VCC GD2 108 D3 GA5 A6 168 GD1 113 D2 GA4 A5 150 A4 132 GD0 D1 DP0 GA3 109 A3 D0 DP1 GA2 R91 65 A2 DP0 79 DP2 135 PCHKJ 10K DP1 5 DP3 27 SMIJ DP2 30 WB-WT# PCHK# PULLHI1 DP3 45 SMI# 46 SMIACKJ D GD[0..31] WB/WT#(DX2INC) D GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 152 UP# VCC GD[0..31] SMIACT# CLKMUL(DX2INC) 55 TMS DP[0..3] TCK TDI TDO VOLDET(DX2NC) R11

3 14 33 31 7 9 11 20 21 22 59 64 71 76 77 82 89 94 95 100 101 106 118 120 139 158 160 161 162 163 164 166 156 SKT1_NC *10K DP[0..3] Tie CLKMUL pin to GND for AMD DX2-66 and AMD DX5-133; use 10K pullup for Am486-PGA VCC AMD DX4-100

R148 CLKMUL 0 R13 10K

P24T5

P35 JTAG Connector 12 (C) Advanced Micro Devices, Inc. (800) 222-9323 34 1 2 E 56 5204 E. Ben White Blvd. E 78 Austin, TX 78741 910 AMD Proprietary/All Rights Reserved HEADER2X5; SHRD Title Am486 MICROPROCESSOR JTAG Connector TDO 9 10 Size DocumentPCI CUSTOMER Number DEVELOPMENT PLATFORM Rev TDI 2.1 TMS Top View CPU.SCH TCK Date:Friday, December 04, 1998 Sheet 226 of

1 2 3 4 5 1 2 3 4 5 POWER CONNECTOR, CPU PULLUPS, CPU POWER SUPPLY, CPU BYPASS CAPACITORS K2VCC VCC CPUVCC3 HS1

C162 C163 C164 C165 C166 C167 C168 C169 R30 K2VCC VCC 1 1 0.015uF 0.015uF 0.015uF 0.015uF 0.1uF 0.1uF 0.1uF 0.1uF 100 TC9 A + C39 A 10uF 0.1uF HEATSINK (TO-220) THERMALLOY ML32

VCC Q5 VCC TIP127 JP2 3 2 E C 1 1-2: 5V CPU CPUVCC3 R28 2 2-3: OTHERS 330 B 3 DP[0..3] DP[0..3] HEADER 3X1 1 JP3 RP2 1 10 O10 BASE CPUVCC3 DP1 9 2 O9 3 DP2 8 U6 C37 B DP3 7 O8 U6O/P 1 8 COLLECTOR B O/P VIN U6VIN HEADER 3X1 DP0 6 O7 2 7 SEN FB U6FB 5 O6 VCC 3 6 0.1uF R23 R25 R26 MIOJ O5 SD TAP 4 4 5 27.4K, 1% 15.8K, 1% RDYOJ O4 GND ERR 25.5K, 1% BRDYOJ 3 1/8W 2 O3 1 1/8W 1/8W BOFFJ LP2951 1% O2 C 1% 1% + TC8 JP4 100uF 10K-10P CPUV1 R27 12 34 CPUV2 33 CPUV3 VCC 56 HEADER 3X2 R29 15.0K, 1% 1-2: 3.45V 1/8W 3-4: 3.3V V(out)= 1.235(1+ R/15.0K) R3 R5 R4 R61 1% 5-6: 2.5V 10K 10K 10K 10K

FLUSHJ C BS16J C BS8J IGNNEJ

+ TC4 + TC7 + TC1 + TC10 47uF 47uF 47uF 47uF

PWG -12V +12V VCC -5V J2 C7 C5

1 0.1uF 0.1uF 2 3 4 -5V -12V +12V 5 CPUVCC3

6 TC5 TC6 + + 10uF 10uF MT1 MT8 C6 C4 C36 C3 C8

J3PWR-CN6 TC19 TC20 TC21 + + + 1 1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF 10uF D 1 D 2 MountingHole MountingHole 3 4 MT2 MT7 5 6 1 1 C11 C34 C9

TC18 TC3 0.01uF 0.01uF 0.01uF 10uF + 10uF PWR-CN6 + MountingHole MountingHole

MT3 MT6 MT9 1 1 C35 C12 C10 C13 1 0.01uF 0.01uF 0.01uF 0.01uF

MountingHole MountingHole MountingHole MT4 MT5 MT10 J3 J2 1 1 1 (C) Advanced Micro Devices, Inc. (800) 222-9323 MountingHole MountingHole MountingHole E 5204 E. Ben White Blvd. E 6 514 3 2 1 625 4 3 Overlap To Make An Oval Austin, TX 78741 AMD Proprietary/All Rights Reserved Power Connector(s) Title = Connector Polarizing Key Am486 MICROPROCESSOR Size Document Number Rev PCI CUSTOMER DEVELOPMENT PLATFORM 2.1

Date:Friday, December 04,CPU_POWER.SCH 1998 Sheet 326 of

1 2 3 4 5 1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR CPU SIGNALS

POD 4 A A

VCC U261OE# VCC P36 1 2OE# VCC 7 1 2 +5V CLK2 48 3OE# VCC 18 3 VGD314 25 4OE# VCC 31 VGD30 5 CLK1 D15 VGD296 D14 D13 24 42 VGD28 7 VGD278 1A1 1Y1 9 D12 D11 10 VGD26 D10 D9 VGD25 47 1A2 1Y2 2 VGD31 11 12 GD31 VGD24 D8 D7 VGD23 46 1A3 1Y3 3 VGD30 13 14 GD30 VGD22 VGD21 44 1A4 1Y4 5 VGD29 15 D6 D5 16 GD2943 2A1 2Y1 6 VGD20 17 D4 D3 VGD1918 41 8 VGD28 19 20 GD28 2A2 2Y2 VGD18 D2 D1 VGD17 40 9 VGD27 GD27 VGD16 D0 GND 38 2A3 2Y3 11 VGD26 POD 3 GD26 2A4 2Y4 HP CONN 37 12 VGD25 GD25 3A1 3Y1 36 13 VGD24 3M:2520-6003UB GD2435 3A2 3Y2 14 3A3 3Y3 VGD23 P38 GD2333 16 32 3A4 3Y4 17 VGD22 1 2 GD22 +5V CLK2 30 4A1 4Y1 19 VGD21 3 4 GD21 CLK1 D15 29 4A2 4Y2 20 VGD20 5 6 GD20 D14 D13 27 4A3 4Y3 22 VGD19 7 8 GD1926 4A4 4Y4 23 9 D12 D11 VGD1510 B VGD18 D10 D9 B GD18 VGD14 11 VGD1312 21 28 VGD17 13 D8 D7 14 GD17 GND GND VGD12 VGD11 4 34 VGD16 15 D6 D5 16 GD16 GND GND VGD10 VGD9 10 GND GND 39 17 D4 D3 18 15 45 VGD8 19 VGD720 GND GND D2 D1 VGD6 D0 GND VGD5 VCC VGD4 HP CONN VGD3 VGD2 VGD1 U281OE#74ABT16244VCC 3M:2520-6003UB 1 2OE# VCC 7 VGD0VGD[0..31] 48 3OE# VCC 18 25 4OE# VCC 31 24 42 1A1 1Y1 47 1A2 1Y2 2 46 1A3 1Y3 3 44 1A4 1Y4 5 43 2A1 2Y1 6 41 8 2A2 2Y2 40 9 2A3 2Y3 38 11 VGD15 SIGNALS NOT NEEDED BY HP DISASSEMBLER GD15 2A4 2Y4 VCC 37 12 VGD14 GD1436 3A1 3Y1 13 U471OE# VCC POD 7 3A2 3Y2 VGD13 GD1335 14 1 2OE# VCC 7 33 3A3 3Y3 16 VGD12 48 3OE# VCC 18 C GD12 P47 C 32 3A4 3Y4 17 VGD11 25 4OE# VCC 31 GD1130 4A1 4Y1 19 24 42 1 2 VGD10 +5V CLK2 GD1029 4A2 4Y2 20 VPCHKJ 3 4 VGD9 1A1 1Y1 CLK1 D15 GD927 4A3 4Y3 22 PCHKJ 47 2 VSMIJ 5 6 VGD8 1A2 1Y2 D14 D13 26 4A4 4Y4 23 VGD0 SMIJ 46 3 VWB-WT# 7 8 GD8 1A3 1Y3 D12 D11 VGD7 WB-WT# 44 5 VSMIACKJ 9 10 GD7 SMIACKJ 1A4 1Y4 D10 D9 21 GND GND 28 VGD6 43 2A1 2Y1 6 VFERRJ 11 12 GD64 34 FERRJ 41 8 13 D8 D7 14 GND GND VGD5 2A2 2Y2 VAHOLD GD510 39 AHOLD 40 9 15 D6 D5 16 GND GND VGD4 2A3 2Y3 VNMI GD415 45 NMI 38 11 17 D4 D3 18 GD[0..31] GND GND VGD3 IGNNEJ 2A4 2Y4 VIGNNEJ GD3 37 12 19 D2 D1 20 VGD2 36 3A1 3Y1 13 GD2 D0 GND VGD1 35 3A2 3Y2 14 GD1 74ABT16244 STPCLKJ 33 3A3 3Y3 16 HP CONN GD0 PCD_CACH 32 3A4 3Y4 17 VSTPCLKJ 3M:2520-6003UB CPURST 30 4A1 4Y1 19 VCACHE# HITMJ 29 4A2 4Y2 20 VSRESET INV 27 4A3 4Y3 22 VHITMJ PLOCK# 26 4A4 4Y4 23 VINV GD[0..31] VPLOCK# 21 GND GND 28 4 GND GND 34 10 GND GND 39 15 45 D GND GND D

74ABT16244

HP Conn. Using Logic Analyzer Headers: 12 Clock the analyzer off the clock signal on P41 (POD1) Qualify the clock using the LA_QUAL signal on P39 (POD2) This qualification signal is asserted (1) when ADS#, RDY# or BRDY# is asserted on the Am486 Microprocessor bus. Thus cycles where valid address or data information is not transferred can be filtered out when needed Signals are arranged on the LA Headers to work with the HP Disassembler for the 16500 analyzer

E 5204 E. Ben White Blvd. E 19 20 Austin, TX 78741 AMD Proprietary/All Rights Reserved Top View Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev CPU_VIS1.SCH 2.1 Date:Friday, December 04, 1998 Sheet 426 of

1 2 3 4 5 1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR CPU SIGNALS, AND PAL TO AID LOGIC ANALYZER USE

POD 2 VBRDYOJ VCC VRDYOJ VADSJ U491OE# VCC VPWT P39 1 2OE# VCC 7 VA20MJ VHOLD 48 3OE# VCC 18LA_QUAL 1 2 VBREQ +5V CLK2 VFLUSHJ 25 31 3 4 4OE# VCC VZRSTDRV CLK1 D15 VINTR A 24 42 5 6 A D14 D13 1A1 1Y1 7 8 D12 D11 BEJ[0..3] 47 1A2 1Y2 2 9 10 D10 D9 BEJ[0..3] PWT 46 1A3 1Y3 3 11 12 A20MJ 44 5 13 D8 D7 14 BREQ 1A4 1Y4 D6 D5 43 2A1 2Y1 6 15 16 U80 ZRSTDRV 41 8 17 D4 D3 18 VBRDYOJ 2A2 2Y2 40 9 19 D2 D1 20 BEJ0 VADSJ 3 I1 38 2A3 2Y3 11 BEJ1 D0 GND 4 I2 I/O9 27 VRDYOJ VCC 37 2A4 2Y4 12 BEJ2 5 I3 I/O8 26 36 3A1 3Y1 13 VCPUCLK1 HP CONN BEJ3 6 I4 I/O7 25 INTR 35 3A2 3Y2 14 VCPUCLK 3M:2520-6003UB ADSJ 7 I5 I/O6 24 LA_QUAL FLUSHJ 33 3A3 3Y3 16 BRDYOJ 9 I6 I/O5 23 VGA0 R94 32 3A4 3Y4 17 RDYOJ 10 I7 I/O4 21 VGA1 330 30 4A1 4Y1 19 11 I8 I/O3 20 VBEJ0 29 4A2 4Y2 20 12 19 VBEJ1 27 4A3 4Y3 22 I9 I/O2 CPUCLK3 VCPUCLK1 13 I10 I/O1 18 VBEJ2 PLACE THEVENIN 26 4A4 4Y4 23 16 17 I11 I/O0 VBEJ3 TERMINATOR NEAR 21 GND GND 28 R95 VCC 2 'ABT16244 4 GND GND 34 CLK/I0 470 BUFFER 10 GND GND 39 15 45 GND GND PLACE THEVENIN TERMINATOR R156 NEAR HP LOGIC ANALYZER B PALCE22V10_PLCC5nsec (5ns) B LACNTL.JED 330 74ABT16244 CONNECTOR

R157 470

VCC U311OE# VCC POD 1 1 2OE# VCC 7 VCPUCLK 48 3OE# VCC 18 VMIOJ P41 25 4OE# VCC 31 VWRJ 24 42 VBEJ2 1 2 +5V CLK2 3 4 VGA31 1A1 1Y1 VCC MIOJ 47 2 VLOCKJ 5 CLK1 D15 6 U30 VGA30 1A2 1Y2 D14 D13 1OE# VCC WRJ 46 1A3 1Y3 3 VKENOJ 7 8 1 2OE# VCC 7 VGA29 44 5 VBS16J 9 D12 D11 10 1A4 1Y4 VBEJ0 D10 D9 48 3OE# VCC 18 VGA28 43 2A1 2Y1 6 VBLAST# 11 12 25 31 LOCKJ 41 8 13 D8 D7 14 4OE# VCC VGA27 2A2 2Y2 24 42 KENOJ 40 9 15 D6 D5 16 GA31 VGA26 2A3 2Y3 1A1 1Y1 BS16J 38 11 17 D4 D3 18 GA30 VGA25 BLAST# 2A4 2Y4 C 47 1A2 1Y2 2 37 12 VHLDA19 D2 D1 20 C GA29 VGA24 HDLA 3A1 3Y1 46 1A3 1Y3 3 36 13 VBS8J D0 GND GA28 44 5 VGA23 BS8J 35 3A2 3Y2 14 1A4 1Y4 PCD 3A3 3Y3 VPCD HP CONN GA27 43 2A1 2Y1 6 VGA22 33 16 41 8 BOFFJ 32 3A4 3Y4 17 VBOFFJ 2A2 2Y2 3M:2520-6003UB GA26 40 9 VGA21 30 4A1 4Y1 19 VBEJ1 GA25 38 2A3 2Y3 11 VGA20 29 4A2 4Y2 20 VBEJ3 GA24 37 2A4 2Y4 12 VGA19 DCJ 27 4A3 4Y3 22 VDCJ 3A1 3Y1 GA23 36 13 VGA18 EADSJ 26 4A4 4Y4 23 VEADSJ 3A2 3Y2 GA22 35 14 VGA17 33 3A3 3Y3 16 21 GND GND 28 GA21 32 3A4 3Y4 17 VGA16 4 34 GA20 POD 6 VGA31 GND GND 30 4A1 4Y1 19 10 GND GND 39 GA19 29 4A2 4Y2 20 VGA30 VGA29 15 45 P40 GND GND GA18 27 4A3 4Y3 22 VGA28 VGA27 26 23 1 2 GA17 4A4 4Y4 VGA26 +5V CLK2 VGA25 3 4 GA16 VGA24 CLK1 D15 VGA23 74ABT16244 21 GND GND 28 5 6 4 34 VGA227 D14 D13 8 VGA21 GND GND D12 D11 HP Conn. 10 GND GND 39 VGA209 10 VGA19 15 45 11 D10 D9 12 GND GND VGA18 VGA17 13 D8 D7 14 1 2 VGA16 15 D6 D5 16 VCC 17 D4 D3 18 U321OE#74ABT16244VCC 19 D2 D1 20 D 1 2OE# VCC 7 D0 GND D 48 3OE# VCC 18 25 4OE# VCC 31 HP CONN 24 42 3M:2520-6003UBPOD 5 VGA15 1A1 1Y1 P42 47 1A2 1Y2 2 VGA14 46 3 1 2 1A3 1Y3 VGA13 +5V CLK2 VGA15 44 5 3 4 1A4 1Y4 VGA12 VGA14 CLK1 D15 VGA13 43 2A1 2Y1 6 5 6 41 8 VGA11 VGA127 D14 D13 8 VGA11 2A2 2Y2 GA15 40 9 VGA10 VGA109 D12 D11 10 VGA9 GA14 38 2A3 2Y3 11 VGA9 VGA811 D10 D9 12 VGA7 2A4 2Y4 GA13 37 12 VGA8 VGA613 D8 D7 14 VGA5 3A1 3Y1 D6 D5 GA12 36 13 VGA7 VGA415 16 VGA3 35 3A2 3Y2 14 17 D4 D3 18 19 20 GA11 33 3A3 3Y3 16 VGA6 VGA219 D2 D1 20 VGA1 GA10 32 3A4 3Y4 17 VGA5 VGA0 D0 GND GA9 30 4A1 4Y1 19 VGA4 Top View GA8 29 4A2 4Y2 20 VGA3 HP CONN 27 22 GA7 4A3 4Y3 VGA2 3M:2520-6003UB 26 4A4 4Y4 23 GA6 GA5 21 28 VGA[2..31] GND GND (C) Advanced Micro Devices, Inc. (800) 222-9323 GA4 4 GND GND 34 10 39 E GA3 GND GND VGA[2..31] E 15 45 5204 E. Ben White Blvd. GA[2..31] GA2 GND GND Austin, TX 78741 AMD Proprietary/All Rights Reserved VADSJ Title 74ABT16244 VRDYOJ VADSJ Am486 MICROPROCESSOR VRDYOJ VBRDYOJ PCI CUSTOMER DEVELOPMENT PLATFORM VWRJ VBRDYOJ VWRJ Size Document Number Rev CPU_VIS2.SCH 2.1 GA[2..31] Date:Friday, December 04, 1998 Sheet 526 of

1 2 3 4 5 1 2 3 4 5 FINALiPARITY M1489 INTERFACE

HDCSJ3 HDCSJ2 HDRQ1 R162 *0 PD0 R163 0 HDRQ1 MDP0 HDCSJ1 DEVSELJ HDACK1 HDACK1 R164 *0 PD1 R165 0 MDP1 HDCSJ0 PAR HDRQ0 HDRQ0 R166 *0 PD2 R167 0 MDP2 HDIO16J HDACK0 R168 *0 R169 0 HDIORDY STOPJ HDACK0 PD3 MDP3 IRDYJ HDA2 FOR IDE MASTER: DO A TRDYJ A HDA1 C_BEJ0 NOT POPULATE HDA0 C_BEJ1 HDIORJ HDIOWJ C_BEJ2 C_BEJ3 FRAMEJ VCC HDD[0..15] HDD[0..15] HDD0 HDD1 HDD2 HDD3 HDD4 HDD5 HDD6 HDD7 HDD8 HDD9 HDD10 HDD11 HDD12 HDD13 HDD14 HDD15 TC11 + C38 C171 C172 10uF 0.1uF 0.1uF 0.1uF U5 87 89 92 94 96 98 100 101 99 97 95 93 91 88 86 85 84 83 77 80 79 82 81 74 73 76 75 139 114 113 140 112 123 137 141 147 111 22 52 78 130 144 182 34 53 72 90 104 128 156 168 208 PAR VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND HDA0 HDA1 HDA2 HDD0 HDD1 HDD2 HDD3 HDD4 HDD5 HDD6 HDD7 HDD8 HDD9 IRDYJ STOPJ TRDYJ HDD10 HDD11 HDD12 HDD13 HDD14 HDD15 C/BEJ0 C/BEJ1 C/BEJ2 C/BEJ3 HDIORJ

GA[2..31] HDCSJ0 HDCSJ1 HDCSJ2 HDCSJ3 PAD[0..31] HDIOWJ FRAMEJ PAD0 HDIO16J PAD[0..31]

GA[2..31] DEVSELJ HDIORDY PAD1 PAD2 157 GA2 PAD3 122 GA2 158 PAD0 132 B GA3 GA3 PAD1 PAD4 B 173 PAD5 120 GA4 172 GA4 PAD2 133 GA5 PAD6 GA5 171 PAD3 119 170 GA6 PAD7 125 GA6 PAD4 167 GA7 PAD8 121 GA7 165 GA8 PAD5 PAD9 124 GA8 163 GA9 PAD6 PAD10 126 GA9 162 GA10 PAD7 PAD11 118 GA10 164 GA11 PAD8 PAD12 134 169 PAD13 117 GA11 GA12 PAD9 166 GA13 PAD14 135 GA12 PAD10 161 GA14 PAD15 116 GA13 160 GA15 PAD11 PAD16 136 GA14 159 GA16 PAD12 PAD17 115 GA15 174 GA17 PAD13 PAD18 110 175 142 GA16 GA18 PAD14 PAD19 176 PAD20 109 GA17 177 GA19 PAD15 143 PAD21 GA18 178 GA20 PAD16 108 PAD22 GA19 179 GA21 PAD17 145 GA22 PAD23 GA20 180 PAD18 107 183 GA23 PAD24 146 GA21 184 GA24 PAD19 PAD25 106 GA22 181 GA25 PAD20 PAD26 148 C GA23BEJ0 47 GA26 PAD21 PAD27 105 C GA24BEJ1 46 GA31 PAD22 PAD28 149 BEJ2 GA25 48 BEJ0 PAD23 PAD29 103 BEJ3 45 BEJ1 PAD30 150 GA26ADSJ PAD24 186 BEJ2 PAD31 102 GA31MIOJ 187 PAD25 COEJ0 151 DCJ BEJ3 188 PAD26 COEJ1 201 COEJ0 WRJ ADSJ 189 PAD27 CWEJ0 194 RDYOJ MIOJ 39 PAD28 CWEJ1 200 CWEJ0 BRDYOJ 40 DCJ 196 LOCKJ WRJ PAD29 CCSJ0 185 193 PD0 PCD_CACH 190 RDYOJ PAD30 CCSJ1 195 BRDYJ CCSJ2 PD1 TAG[0..7] HITMJ 191 PAD31 198 PD2 LOCKJ CCSJ3 AHOLD 42 202 PD3 BOFFJ 41 PCD TAG0 203 KENOJ 44 HITMJ TAG1 204 EADSJ 43 AHOLD TAG2 205 RSTDRV 131 BOFFJ TAG3 3 PCICLK 127 KENOJ TAG4 2 CPUCLK1 129 EADSJ TAG5 1 TAG[0..7] SMIACKJ 192 RSTDRV TAG6 207 IBCSTJ 155 PCICLK TAG7 206 CMPSTJ 152 PERRJ 138 PERRJ CMPGNTJ CPUCLK1 154 TAG0 TAGWEJ 4 TAGWEJ CLEAROKJ SMIACKJ 153 TAG1 CA2 197 A3II D IBCSTJ 199 D CMPSTJ TAG2 CA3 A3I R85 CMPGNTJ TAG3

1K CLEAROKJ TAG4 WEJ TAG5 TAG6

GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 GD16 GD17 GD18 GD19 GD20 GD21 GD22 GD23 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 CASJ0 TAG7CASJ1 CASJ2 CASJ3 RASJ0 RASJ1 RASJ2 RASJ3 5 6 7 8 9 10 12 11 13 14 15 16 17 18 20 19 21 23 24 25 26 27 29 28 30 31 32 33 35 36 37 38 58 57 56 55 54 51 50 49 62 61 60 59 66 65 64 63 71 70 69 68 67

M1489

WEJ GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 GD10 GD11 GD12 GD13 GD14 GD15 GD16 GD17 GD18 GD19 GD20 GD21 GD22 GD23 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 MA10 MA11 RASJ3 RASJ2 RASJ1 RASJ0 CASJ3 GD[0..31] CASJ2 CASJ1 CASJ0 (C) Advanced Micro Devices, Inc. (800) 222-9323

E 5204 E. Ben White Blvd. E MA[0..11] Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev M1489.SCH 2.1 Date:Friday, December 04, 1998 Sheet 626 of GD[0..31]

1 2 3 4 5

MA[0..11] GD[0..31]

GA[4..18]

A3II

A3I

1 2 3 4 5 L2 CACHE TAG AND DATA SRAMS AND BYTE CONTROL; DRAM SERIES TERMINATION AND WE* FANOUT

GD[0..31] GA4 GD0 GA4 GD8 GA4 GD16 GA4 GD24 GA5 GD1 GA5 GD9 GA5 GD17 GA5 GD25 GA[4..18] GA6 GD2 GA6 GD10 GA6 GD18 GA6 GD26 GA7 GD3 GA7 GD11 GA7 GD19 GA7 GD27 A3II GA8 GD4 GA8 GD12 GA8 GD20 GA8 GD28 GA9 GD5 GA9 GD13 GA9 GD21 GA9 GD29 GA10 GD6 GA10 GD14 GA10 GD22 GA10 GD30 A3I A GA11 GD7 GA11 GD15 GA11 GD23 GA11 GD31 A GA12 VCC GA12 GA12 VCC GA12 VCC U10 GA13 U9 GA13 VCC GA13 U8 GA13 U7 VCC GA14 GA14VCC GA14 VCC GA14 VCC 32 32 32 32 GA15 GA15 GA15 GA15 A0 A0 A0 A0 GA16 GA16 GA16 GA16 12 A1 DQ1 12 A1 DQ1 12 A1 DQ1 12 A1 DQ1 11 13 11 13 11 13 11 13 A2 DQ2 A2 DQ2 A2 DQ2 A2 DQ2 10 14GA17 10 GA17 14 10GA17 14 GA17 10 14 9 A3 DQ3 15 9 A3 DQ3 15 9 A3 DQ3 15 9 A3 DQ3 15 GA18 GA18 GA18 GA18 8 A4 DQ4 17 8 A4 DQ4 17 8 A4 DQ4 17 8 A4 DQ4 17 7 A5 DQ5 18 7 A5 DQ5 18 7 A5 DQ5 18 7 A5 DQ5 18 6 A6 DQ6 19 6 A6 DQ6 19 6 A6 DQ6 19 6 A6 DQ6 19 5 A7 DQ7 20 5 A7 DQ7 20 5 A7 DQ7 20 5 A7 DQ7 20 27 A8 DQ8 21 27 A8 DQ8 21 27 A8 DQ8 21 27 A8 DQ8 21 26 A9 26 A9 26 A9 26 A9 23 A10 23 A10 23 A10 23 A10 25 A11 25 A11 25 A11 25 A11 4 A12 4 A12 4 A12 4 A12 28 A13 CE2 30 28 A13 CE2 30 28 A13 CE2 30 28 A13 CE2 30 3 A14 CE1# 22 3 A14 CE1# 22 3 A14 CE1# 22 3 A14 CE1# 22 31 A15 WE# 29 31 A15 WE# 29 31 A15 WE# 29 31 A15 WE# 29 2 A16 OE# 24 2 A16 OE# 24 2 A16 OE# 24 2 A16 OE# 24 1 1 1 1 VCC NC VCC NC VCC NC VCC NC B 16 16 16 16 B GND GND GND GND COEJ0 CWEJ0128Kx8-15 128Kx8-15 128Kx8-15 128Kx8-15 COEJ0 CWEJ0

CSJ0 CSJ1 CSJ2 CSJ3

GA[2..19]

MA[0..11] MA[0..11] AMA[0..11] AMA[0..11] GA4 GA5 TAG[0..7] TAG[0..7] GA6 RN4 C GA[2..19] GA7 2 1 C VCC MA0 4 3 AMA0 U11 GA8 MA2 6 5 AMA2 A0 VCC GA9 RN2 10 28 MA4 8 7 AMA4 9 A1 GA10 2 1 RASJ0 MRASJ0 MA6 AMA6 8 A2 GA11 4 3 33-8B RASJ1 MRASJ1 RN3 7 A3 DQ1 GA1211 RASJ2 6 5 MRASJ2 6 12 8 7 2 1 A4 DQ2 GA13 RASJ3 MRASJ3 5 A5 DQ3 13 TAG0 4 3 GA14 4 A6 DQ4 15 TAG1 33-8B MA1 6 5 AMA1 3 A7 DQ5 GA1516 8 7 TAG2 RN9 MA3 AMA3 25 A8 DQ6 GA1617 TAG3 MA5 AMA5 24 A9 DQ7 GA1718 CASJ0 2 1 MCASJ0 33-8B 21 19 TAG4 4 3 MCASJ1 MA7 AMA7 A10 DQ8 GA18 CASJ1 RN1 23 TAG5 CASJ2 6 5 MCASJ2 2 A11 8 7 2 1 TAG6 CASJ3 MCASJ3 26 A12 4 3 A13 TAG7 1 33-8B 6 5 A14 8 7 MA8 AMA8 TAGWEJ 27 MA9 33-8B AMA9 20 WE# MA10 AMA10 22 CE# 14 OE# GND MA11 AMA11

D D 32Kx8-15 U1 VCC U1PD 2 A1 B1 18 U24A 3 A2 B2 17 WRJ 1 4 A3 B3 16 3 CSJ3 R19 5 A4 B4 15 BEJ3 2 10K 6 A5 B5 14 7 A6 B6 13 ZMWEJ2 R124 33 MWEJ2 74F08 8 A7 B7 12 R8 33 MWEJ1 R7 33 MWEJ0 U24B WEJ 9 A8 B8 11 4 6 CSJ2 19 G 5 1 BEJ2 DIR VCC 74F08 R96 U24C 470 74F245 9 ZMWEJ1 8 CSJ1 ZMWEJ0 BEJ1 10

74F08 U24D 12 (C) Advanced Micro Devices, Inc. (800) 222-9323 E 11 CSJ0 E 13 5204 E. Ben White Blvd. BEJ0 Austin, TX 78741 AMD Proprietary/All Rights Reserved 74F08 Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev L2_CACHE.SCH 2.1 Date:Friday, December 04, 1998 Sheet 726 of

1 2 3 4 5 AMA[0..11] AMA[0..11] GD[0..31] GD[0..31] GD31 1 2 GD31 3 AMA11 4 GD30 5 AMA11 GD30 AMA10 GD29 AMA10 GD29 AMA9 VCCGD28 DRAM 72-PIN SIMM SOCKETS AMA9 VCC GD28 AMA8 GD27 AMA8 GD27 AMA7 GD26 AMA7 GD26 AMA6 GD25 AMA6 GD25 AMA5 SIMM2 GD24 AMA5 SIMM0 GD24 AMA4 GD2310 30 59

10 30 59 AMA[0..11] AMA[0..11] AMA4 GD23 AMA3 GD22 GD[0..31] AMA3 GD22 GD[0..31] AMA2 A12 GD21 VCC VCC VCC IO34 A12 71 A11 64 AMA2 VCC VCC VCC IO34 GD21 AMA1 GD20 A 71 A11 64 29 A10 IO33 62 A AMA1 IO33 GD20 AMA0 GD19 29 A10 62 19 A9 IO32 60 AMA0 IO32 GD19 GD18 19 A9 60 32 A8 IO31 58 IO31 32 A8 58 GD18 31 A7 GD17 IO30 56 31 IO30 56 28 IO29 54 A7 GD17 A6 GD16 28 IO29 54 18 52 A6 GD16 A5 GD15 IO28 18 IO28 52 17 50 A5 GD15 A4 GD14 IO27 17 IO27 50 16 27 A4 A3 IO25 16 IO25 27 GD14 15 GD13 25 A3 A2 IO24 15 IO24 25 GD13 14 GD12 IO23 23 A2 A1 14 IO23 23 GD12 13 GD11 IO22 21 13 A1 21 12 A0 9 IO22 GD11 GD10 IO21 12 A0 9 7 IO21 7 GD10 GD9 IO20 5 IO20 5 GD9 66 GD8 IO19 3 IO19 66 3 GD8 48 NC4 GD7 IO18 65 NC4 IO18 NC3 IO16 48 65 GD7 46 GD6 63 46 NC3 IO16 63 11 NC2 IO15 61 GD6 GD5 11 NC2 IO15 61 NC1 IO14 57 NC1 IO14 57 GD5 GD4 IO13 55 IO13 GD4 GD3 IO12 55 70 PRD3 53 70 PRD3 IO12 53 GD3 MCASJ[0..3] 69 GD2 IO11 51 MCASJ[0..3] 69 IO11 51 GD2 68 PRD2 GD1 IO10 49 68 PRD2 IO10 49 MRASJ0 67 PRD1 IO9 26 MRASJ1 GD1 GD0 67 PRD1 IO9 26 PRD0 IO7 24 B GD0 MCASJ3 MRASJ2 B PRD0 IO7 24 22 MRASJ0 IO6 MCASJ3 IO6 22 MCASJ2 33 MDP3 IO5 20 33 20 34 RAS3 8 MCASJ2IO5 MDP3 MCASJ1 MDP2 IO4 34 RAS3 8 45 6 MCASJ1IO4 MDP2 MCASJ[0..3] MCASJ0 MDP1 45 6 44 RAS2 IO3 4 MCASJ[0..3] RAS2 IO3 MCASJ044 4 MDP1 RAS1 MDP0 IO2 2 RAS1 IO2 2 MDP0 42 RAS0 IO1 RAS0 IO1 42 41 CAS3 IO0MDP[0..3]38 41 CAS3 IO0 38 MDP[0..3] 43 35 43 35 40 CAS2 IO35 37 CAS2 IO35 40 37 CAS1 GND GND GND IO26 36

CAS1 GND GND GND IO26 36 MWEJ2 47 CAS0 IO17 47 CAS0 IO17 MWEJ0 WE IO8 MDP[0..3] WE IO8 MDP[0..3] 1 39 72 1 39 72 SIMM72 SIMM72

C C

VCC

SIMM1 10 30 59 GD[0..31] SIMM SOCKET POPULATION CHART GD[0..31] AMA[0..11] AMA[0..11] A12 71 A11 VCC VCC VCC IO34 64 GD31 SIMM0 SIMM1 SIMM2 AMA11 29 A10 IO33 62 GD30 IO32 AMA10 19 A9 60 GD29 IO31 32 A8 58 AMA9 31 IO30 56 GD28 SINGLE BANK SINGLE BANK SINGLE BANK AMA8 A7 GD27 28 A6 IO29 54 AMA7 18 IO28 52 GD26 17 A5 50 AMA6 A4 IO27 GD25 16 IO25 27 AMA5 A3 GD24 15 IO24 25 DOUBLE BANK SINGLE BANK AMA4 14 A2 23 GD23 AMA3 A1 IO23 GD22 13 IO22 21 12 A0 9 AMA2 IO21 GD21 D 7 D AMA1 IO20 GD20 5 AMA0 GD19 SIMMS CAN BE SINGLE BANK OR DOUBLE BANK, USING 66 IO19 3 48 NC4 IO18 65 GD18 1Mbit, 4Mbit, or 16Mbit DRAM CHIPS. POPULATE 46 NC3 IO16 63 GD17 SIMM SOCKETS AS SHOWN IN THIS CHART. 11 NC2 IO15 61 GD16 NC1 IO14 57 GD15 IO13 55 GD14 70 PRD3 IO12 53 69 IO11 51 GD13 68 PRD2 IO10 49 GD12 MRASJ2 67 PRD1 IO9 26 GD11 PRD0 IO7 24 GD10 MRASJ1 22 IO6 GD9 33 IO5 20 34 RAS3 8 GD8 IO4 45 6 GD7 MCASJ[0..3] RAS2 IO3 44 4 GD6 RAS1 IO2 2 GD5 42 RAS0 IO1 GD4 41 CAS3 IO0 38 43 35 GD3 MCASJ[0..3] 40 CAS2 IO35 37 GD2 (C) Advanced Micro Devices, Inc. (800) 222-9323

MCASJ11 39 72 MDP2 Title MCASJ0 MDP1 Am486 MICROPROCESSOR SIMM72 MDP0 PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev MDP[0..3] SIMM_SKTS.SCH 2.1 Date:Friday, December 04, 1998 Sheet 826 of

1 2 3 4 5 1 2 3 4 5 EIP FLASH MEMORY CONTROLLER

VA(2:21) A A

Am486 A(2:22) MICROPROCESSOR A(22)=0 U60 4 ea. 1Mx8 Bank1 Cntl. VA(22) Flash ROM Chips 3 I1 'ABT244 PAL A(22)=1 RSTDRV 4 I2 I/O9 27 Bank2 Cntl. 4 ea. 1Mx8 VGA22 5 I3 I/O8 26 EIPCE1# Flash ROM Chips VCC AMA8 6 I4 I/O7 25 EIPCE2# VWRJ 7 I5 I/O6 24 REFCIP MRASJ3 9 I6 I/O5 23 EIPOE1# MCASJ3 10 I7 I/O4 21 MCASJ2 EIPOE2# CPU Address Bit A(22) Used As Flash Bank Select R158 11 I8 I/O3 20 WRCIP 330 MCASJ1 12 19 EIPWE1# MCASJ0 I9 I/O2 13 I10 I/O1 18 EIPWE2# 16 17 I11 I/O0 VCPUCLK1 2 CLK/I0

R159 470 B EIPCNTL.JEDPALCE22V10_PLCC REV. (5ns) 0.9 B PLACE THEVENIN TERMINATOR NEAR 22V10 PAL

Makes 2 banks of 1Mx32 Flash ROM appear as 1 bank of 2Mx32 DRAM (70ns, FPM) to M1489 Memory Controller. Program M1489 for 2Mx8 (11/10) DRAM chips. MA8 (CPU A22) used as Flash ROM Bank Select when RAS3# asserted by M1489 Memory Controller.

Limitations and Operation of the EIP Interface: Access as 32-bits wide always Supports burst Read Cycles or single-beat Read Cycles Supports single-beat Write Cycles only; no back-to-back Write Cycles Compatible with CAS-before-RAS Refresh Cycles only C C Set M1489 Memory Controller to "Fast" for proper operation, even if installed DRAM is 60ns and can run at the "Fastest" setting Flash chip A0 pin tied to Am486 Microprocessor A2 pin, so multiply desired Flash chip address by 4h to find Am486 Microprocessor address needed to access the desired memory cell (ex: Flash Chip AAAh accessed by Am486 Microprocessor at 2AA8h) EIP Flash Array start address moves, depending on how much DRAM is installed (ex: 48MByte DRAM puts EIP start address at 48MB or 3000000h for first bank of Flash ROMs and 3400000h start address for second bank of Flash ROMs Uses 29F800T, 55ns devices in "Byte" mode Accessable from Am486 Microprocessor only; not accessable from PCI Bus Masters Uses fourth DRAM bank of M1489 Memory Controller

D D

E 5204 E. Ben White Blvd. E Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev EIP_MEM1.SCH 2.1 Date:Friday, December 04, 1998 Sheet 926 of

1 2 3 4 5 1 2 3 4 5 EIP FLASH MEMORY ARRAY

GD[0..31]

VGA[2..31] A A

U61 U62 U63 U64

GD0 GD8 GD16 GD24 DQ0 29 DQ0 29 DQ0 29 DQ0 29 VGA3 25 31 GD1 VGA3 25 31GD9 VGA3 25 GD1731 VGA3 25 GD25 31 A0 DQ1 A0 DQ1 A0 DQ1 A0 DQ1 VGA4 24 33 GD2 VGA4 24 33GD10 VGA4 24 GD1833 VGA4 24 GD26 33 VGA5 23 A1 DQ2 35 GD3 VGA5 23 A1 DQ2 35GD11 VGA5 23 A1 DQ2GD1935 VGA5 23 A1 GD27DQ2 35 VGA6 22 A2 DQ3 38 GD4 VGA6 22 A2 DQ3 38GD12 VGA6 22 A2 DQ3GD2038 VGA6 22 A2 GD28DQ3 38 VGA7 21 A3 DQ4 40 GD5 VGA7 21 A3 DQ4 40GD13 VGA7 21 A3 DQ4GD2140 VGA7 21 A3 GD29DQ4 40 VGA8 20 A4 DQ5 42 GD6 VGA8 20 A4 DQ5 42GD14 VGA8 20 A4 DQ5GD2242 VGA8 20 A4 GD30DQ5 42 VGA9 19 A5 DQ6 44 GD7 VGA9 19 A5 DQ6 44GD15 VGA9 19 A5 DQ6GD2344 VGA9 19 A5 GD31DQ6 44 VGA10 18 A6 DQ7 VGA10 18 A6 DQ7 VGA10 18 A6 DQ7 VGA10 18 A6 DQ7 VGA11 8 A7 30 VGA11 8 A7 30 VGA11 8 A7 30 VGA11 8 A7 30 VGA12 7 A8 DQ8 32 VGA12 7 A8 DQ8 32 VGA12 7 A8 DQ8 32 VGA12 7 A8 DQ8 32 6 34 6 34 6 34 6 34 VGA13 A9 DQ9 VGA13 A9 DQ9 VGA13 A9 DQ9 VGA13 A9 DQ9 5 A10 DQ10 36 5 A10 DQ10 36 5 A10 DQ10 36 5 A10 DQ10 36 VGA14 4 39 VGA14 4 39 VGA14 4 39 VGA14 4 39 VGA15 A11 DQ11 VGA15 A11 DQ11 VGA15 A11 DQ11 VGA15 A11 DQ11 3 A12 DQ12 41 3 A12 DQ12 41 3 A12 DQ12 41 3 A12 DQ12 41 VGA16 2 43 VGA16 2 43 VGA16 2 43 VGA16 2 43 VGA17 A13 DQ13 VGA17 A13 DQ13 VGA17 A13 DQ13 VGA17 A13 DQ13 1 A14 DQ14 45 1 A14 DQ14 45 1 A14 DQ14 45 1 A14 DQ14 45 VGA18 48 VGA2 VGA18 48 VGA2 VGA18 48 VGA2 VGA18 48 VGA2 A15 DQ15/A-1 A15 DQ15/A-1 A15 DQ15/A-1 A15 DQ15/A-1 VGA19 17 VGA19 17 VGA19 17 VGA19 17 VGA20 16 A16 15 VGA20 16 A16 15 VGA20 16 A16 15 VGA20 16 A16 15 B VGA21 A17 VGA21 A17 VGA21 A17 VGA21 A17 B A18 RY/BY# VCC A18 RY/BY# VCC A18 RY/BY# VCC A18 RY/BY# VCC 47 47 47 47 RSTDRV# 12 37 12 37 12 37 12 37 RSTDRV# BYTE# RSTDRV# BYTE# RSTDRV# BYTE# RSTDRV# BYTE# RESET# VCC C122 C123 RESET# VCC C124 C125 RESET# VCC C126 C127 RESET# VCC C128 C129 EIPCE1# 26 26 26 26 28 0.1uF 0.1uF 28 0.1uF 0.1uF 28 0.1uF 0.1uF 28 0.1uF 0.1uF EIPOE1# EIPCE1# EIPCE1# EIPCE1# EIPWE1# 11 CE# 46 11 CE# 46 11 CE# 46 11 CE# 46 27 EIPOE1# 27 EIPOE1# 27 EIPOE1# 27 OE# EIPWE1# OE# EIPWE1# OE# EIPWE1# OE# WE# GND WE# GND WE# GND WE# GND GND GND GND GND

29F800-55 TSOP48 29F800-55 TSOP48 29F800-55 TSOP48 29F800-55 TSOP48

GD[0..31]

C C VGA[2..31]

U65 U66 U67 U68

DQ0 29 DQ0 29 DQ0 29 DQ0 29 25 31 25 31 25 31 25 31 A0 DQ1 A0 DQ1 A0 DQ1 A0 DQ1 24 33 24 33 24 33 24 33 A1 DQ2 A1 DQ2 A1 DQ2 A1 DQ2 23 35 GD0 23 35GD8 23 GD1635 23 GD24 35 22 A2 DQ3 38 22 A2 DQ3 38 22 A2 DQ3 38 22 A2 DQ3 38 VGA3 A3 DQ4 GD1 VGA3 A3 DQ4 GD9 VGA3 A3 DQ4GD17 VGA3 A3 GD25DQ4 VGA4 21 40 GD2 VGA4 21 40GD10 VGA4 21 GD1840 VGA4 21 GD26 40 20 A4 DQ5 42 20 A4 DQ5 42 20 A4 DQ5 42 20 A4 DQ5 42 VGA5 A5 DQ6 GD3 VGA5 A5 DQ6 GD11 VGA5 A5 DQ6GD19 VGA5 A5 GD27DQ6 VGA6 19 44 GD4 VGA6 19 44GD12 VGA6 19 GD2044 VGA6 19 GD28 44 18 A6 DQ7 18 A6 DQ7 18 A6 DQ7 18 A6 DQ7 VGA7 GD5 VGA7 GD13 VGA7 GD21 VGA7 GD29 8 A7 30 8 A7 30 8 A7 30 8 A7 30 VGA8 7 A8 DQ8 32 GD6 VGA8 7 A8 DQ8 32GD14 VGA8 7 A8 DQ8GD2232 VGA8 7 A8 GD30DQ8 32 VGA9 6 A9 DQ9 34 GD7 VGA9 6 A9 DQ9 34GD15 VGA9 6 A9 DQ9GD2334 VGA9 6 A9 GD31DQ9 34 VGA10 5 A10 DQ10 36 VGA10 5 A10 DQ10 36 VGA10 5 A10 DQ10 36 VGA10 5 A10 DQ10 36 VGA11 4 A11 DQ11 39 VGA11 4 A11 DQ11 39 VGA11 4 A11 DQ11 39 VGA11 4 A11 DQ11 39 VGA12 3 A12 DQ12 41 VGA12 3 A12 DQ12 41 VGA12 3 A12 DQ12 41 VGA12 3 A12 DQ12 41 VGA13 2 A13 DQ13 43 VGA13 2 A13 DQ13 43 VGA13 2 A13 DQ13 43 VGA13 2 A13 DQ13 43 VGA14 1 A14 DQ14 45 VGA14 1 A14 DQ14 45 VGA14 1 A14 DQ14 45 VGA14 1 A14 DQ14 45 48 48 48 48 VGA15 A15 DQ15/A-1 VGA15 A15 DQ15/A-1 VGA15 A15 DQ15/A-1 VGA15 A15 DQ15/A-1 D 17 17 17 17 D VGA16 A16 VGA16 A16 VGA16 A16 VGA16 A16 16 15 16 15 16 15 16 15 VGA17 A17 VGA17 A17 VGA17 A17 VGA17 A17 VGA18 A18 RY/BY# VGA2 VGA18 A18 RY/BY# VGA2 VGA18 A18 RY/BY# VGA2 VGA18 A18 RY/BY#VGA2 VGA19 VCC VGA19 VCC VGA19 VCC VGA19 VCC VGA20 47 VGA20 47 VGA20 47 VGA20 47 12 37 12 37 12 37 12 37 VGA21 BYTE# VGA21 BYTE# VGA21 BYTE# VGA21 BYTE# RESET# VCC C130 C131 RESET# VCC C132 C133 RESET# VCC C134 C135 RESET# VCC C136 C137 EIPCE2# 26 26 26 26 28 0.1uF 0.1uF 28 0.1uF 0.1uF 28 0.1uF 0.1uF 28 0.1uF 0.1uF EIPOE2# RSTDRV# RSTDRV# RSTDRV# RSTDRV# EIPWE2# 11 CE# 46 11 CE# 46 11 CE# 46 11 CE# 46 OE# 27 OE# 27 OE# 27 OE# 27 WE# GND WE# GND WE# GND WE# GND GND EIPCE2# GND EIPCE2# GND EIPCE2# GND EIPOE2# EIPOE2# EIPOE2# EIPWE2# EIPWE2# EIPWE2# 29F800-55 TSOP48 29F800-55 TSOP48 29F800-55 TSOP48 29F800-55 TSOP48

E 5204 E. Ben White Blvd. E Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev EIP_MEM2.SCH 2.1 Date:Friday, December 04, 1998 Sheet 10 of 26

1 2 3 4 5 1 2 3 4 5 PCI PULLUPS AND SLOT CONNECTORS; PCI IDSEL GENERATION

VCC VCC VCC

RP10 RP11 RP9 2 O2 C 1 2 O2 C 1 2 O2 C 1 FRAMEJ INT0J RN8 A TRDYJ 3 O3 INT2J 3 O3 PGNTJ0 3 O3 A DEVSELJ 4 O4 INT1J 4 O4 PGNTJ1 4 O4 PCIID1 7 8 PAD19 STOPJ 5 O5 INT3J 5 O5 PREQJ0 5 O5 PCIID3 5 6 PAD21 PCIBus INT Slot1 Slot2 Ethernet PLOCKJ 6 O6 PREQJ1 6 O6 C_BEJ1 6 O6 PCIID2 3 4 PAD20 PAR 7 O7 PGNTJ2 7 O7 C_BEJ2 7 O7 1 2 INT0# INTA# INTD# SERRJ 8 O8 PREQJ2 8 O8 IRDYJ 8 O8 C_BEJ0 9 O9 9 O9 C_BEJ3 9 O9 33-8B INT1# INTB# INTA# 10 10 10 O10 O10 O10 INT2# INTC# INTB# INTA# C42 15pF 4.7K-10P 4.7K-10P 4.7K-10P INT3# INTC# INTC#

VCC VCC

B B -12V TRST# -12V TRST# -12V SLT1TCK +12V +12V -12V SLT2TCK +12V +12V GND TMS GND TMS 61 TDO TDI 1 61 TDO TDI 1 62 +5V +5V 2 62 +5V +5V 2 63 +5V INTA# 3 63 +5V INTA# 3 64 INTB# INTC# 4 64 INTB# INTC# 4 65 INTD# +5V 5 65 INTD# +5V 5 66 PRSNT1# RSRVD 6 INT0J 66 PRSNT1# RSRVD 6 INT1J INT1J 67 RSRVD +5V(I/O) 7 INT2J INT2J 67 RSRVD +5V(I/O) 7 INT3J INT3J 68 PRSNT2# RSRVD 8 INT0J 68 PRSNT2# RSRVD 8 69 GND GND 9 69 GND GND 9 70 GND GND 10 70 GND GND 10 71 RSRVD RSRVD 11 71 RSRVD RSRVD 11 72 GND RST# 12 72 GND RST# 12 73 CLK +5V(I/O) 13 73 CLK +5V(I/O) 13 74 14 74 14 75 GND GNT# 15 75 GND GNT# 15 REQ# GND PCIRSTJ REQ# GND PCIRSTJ PCICLK1 76 16 PCICLK2 76 16 77 +5V(I/O) RSVRD 17 77 +5V(I/O) RSVRD 17 AD31 AD30 PGNTJ0 AD31 AD30 PGNTJ1 PREQJ0 78 18 PREQJ1 78 18 79 AD29 +3.3V 19 79 AD29 +3.3V 19 GND AD28 GND AD28 PAD31 80 20 PAD30 PAD31 80 20 PAD30 AD27 AD26 AD27 AD26 C PAD29 81 21 PAD29 81 21 C 82 AD25 GND 22 PAD28 82 AD25 GND 22 PAD28 PAD27 83 +3.3V AD24 23 PAD26 PAD27 83 +3.3V AD24 23 PAD26 PAD25 84 C/BE3# IDSEL 24 PAD25 84 C/BE3# IDSEL 24 85 AD23 +3.3V 25 PAD24 85 AD23 +3.3V 25 PAD24 C_BEJ3 86 GND AD22 26 PCIID1 C_BEJ3 86 GND AD22 26 PCIID2 PAD23 87 AD21 AD20 27 PAD23 87 AD21 AD20 27 88 AD19 GND 28 PAD22 88 AD19 GND 28 PAD22 PAD21 89 +3.3V AD18 29 PAD20 PAD21 89 +3.3V AD18 29 PAD20 PAD19 90 30 PAD19 90 30 91 AD17 AD16 31 91 AD17 AD16 31 C/BE2# +3.3V PAD18 C/BE2# +3.3V PAD18 PAD17 92 32 PAD16 PAD17 92 32 PAD16 93 GND FRAME# 33 93 GND FRAME# 33 C_BEJ2 IRDY# GND C_BEJ2 IRDY# GND 94 34 FRAMEJ 94 34 FRAMEJ 95 +3.3V TRDY# 35 95 +3.3V TRDY# 35 IRDYJ GND IRDYJ GND 96 DEVSEL# 36 TRDYJ 96 DEVSEL# 36 TRDYJ GND STOP# GND STOP# DEVSELJ 97 37 DEVSELJ 97 37 98 LOCK# +3.3V 38 STOPJ 98 LOCK# +3.3V 38 STOPJ PLOCKJ 99 PERR# SDONE 39 PLOCKJ 99 PERR# SDONE 39 PERRJ 100 +3.3V SBO# 40 PERRJ 100 +3.3V SBO# 40 101 SERR# GND 41 101 SERR# GND 41 SERRJ 102 +3.3V PAR 42 SERRJ 102 +3.3V PAR 42 103 C/BE1# AD15 43 PAR 103 C/BE1# AD15 43 PAR C_BEJ1 104 AD14 +3.3V 44 PAD15 C_BEJ1 104 AD14 +3.3V 44 PAD15 PAD14 105 GND AD13 45 PAD14 105 GND AD13 45 D 106 46 106 46 D AD12 AD11 PAD13 AD12 AD11 PAD13 PAD12 107 47 PAD11 PAD12 107 47 PAD11 108 AD10 GND 48 108 AD10 GND 48 PAD10 GND AD9 PAD10 GND AD9 109 49 PAD9 109 49 PAD9

AD8 C/BE0# AD8 C/BE0# PAD8 110 50 C_BEJ0 PAD8 110 50 C_BEJ0 AD7 +3.3V AD7 +3.3V PAD7 111 51 PAD7 111 51 112 +3.3V AD6 52 PAD6 112 +3.3V AD6 52 PAD6 PAD5 113 AD5 AD4 53 PAD4 PAD5 113 AD5 AD4 53 PAD4 PAD3 114 AD3 GND 54 PAD3 114 AD3 GND 54 115 GND AD2 55 PAD2 115 GND AD2 55 PAD2 PAD1 116 AD1 AD0 56 PAD0 PAD1 116 AD1 AD0 56 PAD0 117 +5V(I/O) +5V(I/O) 57 117 +5V(I/O) +5V(I/O) 57 118 ACK64# REQ64# 58 118 ACK64# REQ64# 58 119 +5V +5V 59 119 +5V +5V 59 120 60 120 60 +5V +5V +5V +5V

IDSEL = AD19 IDSEL = AD20 Device #3 Device #4

PCI Slot PCI Slot (C) Advanced Micro Devices, Inc. (800) 222-9323

E 5204 E. Ben White Blvd. E Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev PCI_CONN.SCH 2.1 Date:Friday, December 04, 1998 Sheet 11 of 26

1 2 3 4 5 1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR PCI BUS PAD0 VPAD0VCC U36 PAD1 1OE# VCC VPAD1 VPAD[0..31] PAD[0..31] PAD2 1 2OE# VCC 7VPAD2 48 3OE# VCC 18 PAD3 VPAD3 25 4OE# VCC 31 PAD4 24 42VPAD4 PAD5 1A1 1Y1 VPAD5 PAD6 47 1A2 1Y2 2VPAD6 PLACE THEVENIN PAD7 46 1A3 1Y3 3VPAD7 A 44 5 TERMINATOR NEAR A PAD8 1A4 1Y4 VPAD8 VCC 43 2A1 2Y1 6 HP LOGIC ANALYZER PAD9 41 8VPAD9 2A2 2Y2 PAD10 40 9VPAD10 CONNECTOR 2A3 2Y3 PAD11 38 11VPAD11 VPAD31 2A4 2Y4 PAD12 37 12VPAD12 VPAD30 R160 VPAD29 36 3A1 3Y1 13 330 PAD13 35 3A2 3Y2 14VPAD13 VPAD28 VPAD27 P43 PAD14 33 3A3 3Y3 16VPAD14 VPAD26 VPAD251 2 +5V CLK2 PAD15 32 3A4 3Y4 17VPAD15 VPCICLKVPAD24 VPAD233 4 CLK1 D15 30 4A1 4Y1 19 5 6 VPAD22 VPAD21 D14 D13 29 4A2 4Y2 20 VPAD20 VPAD197 8 JP29 27 4A3 4Y3 22 R161 9 D12 D11 10 VPAD18 470 VPAD17 D10 D9 PREQJ0 1 26 4A4 4Y4 23 11 12 VPAD16 13 D8 D7 14 PGNTJ0 2 21 28 15 D6 D5 16 3 GND GND HP Conn. 4 GND GND 34 17 D4 D3 18 HEADER 3X1 10 GND GND 39 19 D2 D1 20 PLACE NEAR PCI0 CONNECTOR 15 45 12 GND GND D0 GND HP CONN 3M:2520-6003UB 74ABT16244 JP30 VCC U381OE# VCC PREQJ1 1 B 2OE# VCC B PGNTJ1 1 7 2 48 3OE# VCC 18 P44 3 25 4OE# VCC 31 24 42 1 2 HEADER 3X1 VPAD15 +5V CLK2 3 4 PLACE NEAR PCI1 CONNECTOR PAD16 1A1 1Y1 VPAD16 VPAD14 VPAD13 CLK1 D15 47 1A2 1Y2 2 5 6 PAD17 46 3VPAD17 VPAD12 VPAD117 D14 D13 8 1A3 1Y3 D12 D11 PAD18 44 1A4 1Y4 5VPAD18 VPAD10 VPAD9 9 10 PAD19 43 6VPAD19 VPAD8 VPAD711 D10 D9 12 2A1 2Y1 D8 D7 JP31 PAD20 41 8VPAD20 VPAD6 VPAD513 14 2A2 2Y2 D6 D5 PREQJ2 1 40 9 15 16 PAD21 38 2A3 2Y3 11VPAD21 VPAD4 VPAD317 D4 D3 18 PGNTJ2 2 19 20 PAD22 37 2A4 2Y4 12VPAD22 VPAD2 VPAD119 D2 D1 20 3 PAD23 36 3A1 3Y1 13VPAD23 VPAD0 D0 GND 3A2 3Y2 HEADER 3X1 PAD24 35 14VPAD24 Top View 3A3 3Y3 HP CONN PAD25 33 16VPAD25 PLACE NEAR Am79C972 E/NET 32 3A4 3Y4 17 3M:2520-6003UB CHIP PAD26 30 4A1 4Y1 19VPAD26 PAD27 29 4A2 4Y2 20VPAD27 PAD28 27 4A3 4Y3 22VPAD28 PAD29 26 4A4 4Y4 23VPAD29 PAD30 VPAD30 21 28 PAD31 GND GND VPAD31 4 GND GND 34 C 10 GND GND 39 C 15 45 GND GND P45 1 2 +5V CLK2 74ABT16244 3 4 CLK1 D15 VCC 5 6 U401OE# VCC 7 D14 D13 8 1 2OE# VCC 7 9 D12 D11 10 48 3OE# VCC 18 11 D10 D9 12 VC_BEJ3 25 4OE# VCC 31 13 D8 D7 14 24 42 VC_BEJ2 15 D6VC_BEJ1 D5 16 1A1 1Y1 VC_BEJ0 17 D4VFRAMEJ D3 18 VCC C_BEJ3 47 1A2 1Y2 2 VIRDYJ 19 D2VDEVSELJ D1 20 C_BEJ2 46 1A3 1Y3 3 VTRDYJ D0VSTOPJ GND 44 5 C_BEJ1 1A4 1Y4 HP CONN C_BEJ0 43 2A1 2Y1 6 R97 41 8 3M:2520-6003UB FRAMEJ 2A2 2Y2 330 40 9 IRDYJ 2A3 2Y3 TRDYJ 38 11 VC_BEJ3 37 2A4 2Y4 12 DEVSELJ 3A1 3Y1 VC_BEJ2 P46 PCICLK 36 13 35 3A2 3Y2 14 VC_BEJ1 1 2 INT0J 3A3 3Y3 VC_BEJ0 +5V CLK2 INT1J 33 16 3 4 R98 3A4 3Y4 CLK1 D15 INT2J 32 17 VFRAMEJ 5 6 D PLACE THEVENIN 470 30 4A1 4Y1 19 7 D14 D13 8 D INT3J VIRDYJ D12 D11 TERMINATOR NEAR PCIRSTJ 29 4A2 4Y2 20 VTRDYJ 9 10 27 4A3 4Y3 22 11 D10 D9 12 'ABT16244 BUFFER STOPJ VDEVSELJ D8 D7 PAR 26 4A4 4Y4 23 13 14 VPCICLK 15 D6 D5 16 21 GND GND 28 VINT0J 17 D4 D3 18 4 GND GND 34 VINT1J 19 D2VINT3J D1 20 10 39 GND GND VINT2J VINT2J D0VINT1J GND 15 45 GND GND VINT3J VINT0J HPVPCIRSTJ CONN VPCIRSTJ VPAR 3M:2520-6003UBVPERRJ VSTOPJ VSERRJ VPLOCKJ 74ABT16244 VPAR

U42 PLOCKJ 2 1A1 1Y1 18 PERRJ 4 1A2 1Y2 16 SERRJ 6 1A3 1Y3 14 8 1A4 1Y4 12 11 2A1 2Y1 9 13 2A2 2Y2 7 15 2A3 2Y3 5 17 3 (C) Advanced Micro Devices, Inc. (800) 222-9323 2A4 2Y4 E E 1 5204 E. Ben White Blvd. 19 1G Austin, TX 78741 2G AMD Proprietary/All Rights Reserved VPLOCKJ Title 74ABT244 VPERRJ VSERRJ Size DocumentAm486 Number MICROPROCESSOR Rev PCI CUSTOMER DEVELOPMENT PLATFORM 2.1 Date:Friday, December 04, 1998 Sheet 12 of 26 PCI_VIS.SCH 1 2 3 4 5 1 2 3 4 5 ETHERNET CONTROLLER, BYPASS CAPACITORS AND POWER SUPPLY FOR ETHERNET CONTROLLER, AND SERIAL EEPROMS

VCC3 VCC3 EECS_1K EECS_4K VCC VCC

VCC3 U54 U81 R103 R105 1 CS VCC 8 1 CS VCC 8 1K 1K 2 SK ORG 6 2 SK ORG 6

3 DI DO 4 3 DI DO 4 A A

ENETPG 7 5 7 5 NC GND NC GND For '972 E/net Config. For User NV Data

U51 8 24 48 64 100 140 5 13 21 29 38 45 53 147 155 65 77 88 101 113 124 136 131 132 133 141 PAD[0..31] VCC3 NM93C46N NM93C66M8 VCC3 PAD0 55 AD0 PAD1 54 AD1 PAD2 52 129 R104 AD2 EAR# PAD3 50 122 10K AD3 TBC_IN PAD4 49 PG 123 EEDI VDD VDD VDD VDD VDD VDD

AD4 RWU TBC_EN PME# PAD5 47 VDDB VDDB VDDB VDDB VDDB VDDB VDDB 125 EESK AD5 LED2#/SRDCLK/MIIRXFRTGEWUMI# PAD6 46 120 EEDO AD6 VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI EEDO/LED3#/SRD/MIIRXFRTGD PAD7 44 121 AD7 EEDI/LED0# PAD8 41 126 AD8 EESK/LED1#/SFBD EECS PAD9 40 128 39 AD9 EECS PAD10 37 AD10 PAD11 36 AD11 119 PAD12 PHY_RST 34 AD12 PHY_RST 118 PAD13 MDIO 33 AD13 MDIO 116 PAD14 MDC 31 AD14 MDC 115 ERXD3 PAD15 14 AD15 RXD3 114 ERXD2 PAD16 12 AD16 RXD2 112 ERXD1 PAD17 10 111 AD17 RXD1 ERXD0 B PAD18 9 109 B AD18 RXD0 RX_DV PAD19 7 108 AD19 RX_DV RX_CLK_RXCLK PAD20 6 107 AD20 RX_CLK/RXCLK RX_ER_RXDAT PAD21 4 105 AD21 RX_ER/RXDAT TX_ER PAD22 2 104 AD22 TX_ER TX_CLK_TXCLK PAD23 159 103 TX_EN_TXEN AD23 TX_CLK/TXCLK PAD24 158 97 ETXD3 156 AD24 TX_EN/TXEN 98 PAD25 ETXD2 154 AD25 TXD3 99 PAD26 ETXD1 153 AD26 TXD2 102 PAD27 ETXD0_TXDAT 152 AD27 TXD1 96 PAD28 COL_CLSN 151 AD28 TXD0/TXDAT 94 PAD29 CRS_RXEN 148 AD29 COL/CLSN PAD30 AD30 CRS/RXEN PAD31 AD31 71 C_BEJ0 42 70 C_BEJ1 30 EBUA_EBA7 69 C_BEJ2 15 68 EECS U82A C_BE0# EBUA_EBA6 C_BEJ3 160 67 1 EECS_1K C_BE1# EBUA_EBA5 66 3 C_BE2# EBUA_EBA4 63 2 PCIID3 1 C_BE3# EBUA_EBA3 61 EBUA_EBA2 FRAMEJ 17 74F08 IRDYJ 18 EBUA_EBA1 82 C TRDYJ 20 IDSEL EBUA_EBA0 81 C DEVSELJ 22 FRAME# 80 STOPJ 23 IRDY# EBDA15 79 U82B PERRJ 25 TRDY# EBDA14 78 U83A 4 EECS_4K SERRJ 26 DEVSEL# EBDA13 76 6 PAR 28 EBDA12 75 CLKCTRDefaults to "1" 1 2 CLKCTR# 5 INT2J STOP# 142 EBDA11 73 PCIRSTJ PERR# 143 SERR# EBDA10 74F08 PREQJ2 146 83 VCC3 PAR EBDA9 74F14 PGNTJ2 145 85 INTA# EBDA8 86 PCICLK3 144 PCIRST# 87 PCIREQ# EBD7 89 R106 PCIGNT# EBD6 91 4.7K EBD5 92 PCICLK EBD4 93 EBD3 EBD2 60 ENETEBCLK EBD1 59 EBD0 58 57 EBCLK TCK TMS TDI TDO VSS VSS VSS VSS VSS VSS VSS VSS VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB AS_EBOE# EBWE# 134 135 139 137 16 32 56 72 90 110 130 150 3 11 19 27 35 43 51 62 74 84 95 106 117 127 138 149 157 D EROMCS# D IDSEL = AD21 Device #5 Set CSR116 bit 0Am79C972 to "1" (PQR160) for proper PHY_RST operation Spare "AND" Gates

VCC3 U82C 9 8 10

74F08 VCC U53 VCC3 + C78 C79 C80 C81 C82 C83 VCC U82D 2.2uF 12 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 11 3 VIN VOUT 4 13 1 GND_ADJ 74F08 C85 + C84 10uF VCC3 1uF (C) Advanced Micro Devices, Inc. (800) 222-9323 MC33269DT-3.3 E 5204 E. Ben White Blvd. E PLACE INPUT AND OUTPUT FILTER CAPS Austin, TX 78741 AS CLOSE AS POSSIBLE TO REGULATOR + C86 + C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 AMD Proprietary/All Rights Reserved 2.2uF 10uF Title 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev ENET1.SCH 2.1 Date:Friday, December 04, 1998 Sheet 13 of 26

1 2 3 4 5 1 2 3 4 5 ETHERNET PHY CHIP, ETHERNET CONNECTOR, AND LEDS

Y5 A A 1 4 2 3 C98 C99

33pF 33pF 25MHz_SMD

PHY _XI PHY_ XO ECLIPTEK ECSMA-25.00MTR

U52 12 11

XI ENET_RD+

TX_ER XO 56 TX_ER TPIP 29 63 J10 ETXD3 62 TXD4 R107 ETXD2 61 TXD3 100, 1% T1 ENET_TX+ 1 1 ETXD1 60 TXD2 ENET_TX- 2 2 TXD1 ETXD0_TXDAT 59 1 RD+ RX+ 7 ENET_RX+ 3ENET_3 R1 TX_CLK_TXCLK TXD0 ENET_RD- 57 30 2 RD- RX- 6 ENET_RX- 4 4 TX_EN_TXEN TX_CLK TPIN 58 3 RD_CT RX_CT 5 RXCT 5 5 COL_CLSN 64 TX_EN 21 ENET_TD+ 6 ENET_6 R2 RX_DV 51 COL TPOP 14 12 7 TD_CT TX_CT TXCT 7 RX_ER_RXDAT 55 RX_DV R108 15 11 8 B TD+ TX+ 8 B RX_CLK_RXCLK 54 RX_ER 49.9, 1% 16 10 TD- TX- 46 RX_CLK RD_CT 11 GND1 ERXD3 47 RXD4 12 ERXD2 GND2 48 RXD3 ENET _RES ERXD1 49 ERXD0 RXD2 C100 PE68515 R110 R111 R112 R113 50 RXD1 AMP RJ45A CRS_RXEN 1 R109 0.1uF 75, 1% 75, 1% 75, 1% 75, 1% 555153-1 MDIO 44 RXD0 49.9, 1% 2 CRS ENET _CAP VCC MDC 45 MDIO 23 FDS/MDINT ENET_TD- 13 MDC TPON 20 ENET_TREF C101 15 VCCT R114 3 FDE TREF 1.00K, 1% 4 MDDIS 19 0.001uF, 2KV (MIN.) 5 TRSTE VCCA 6 MF4 24 7 MF3 MFV0 8 MF2 33 MF1 25 RBIAS C102 C103 14 MF0 0.01uF 0.01uF VCC 34 CFG1 RBIAS R115 16 R116 L4 PHY_RST CFG0 1.00K, 1% LEDS# 22K, 1% C104 C105 PWRDWN C 38 0.01uF 0.1uF AVCC 1 2 C 39 RESET# LEDT# 40 FB LEDS# C106 C107 LEDR# 41 GNDT + + 42 LEDC# 22 10uF L5 10uF LEDL# R117NET GNDA 32 LEDT# 26 AGND 1 2 35 LEDR# R117 36 FB 1.00K, 1% NC1 L6 NC2 AAVCC NC3 VCCR 37 1 2 VCC3 FB C109 + C108 53 VCCIO 0.01uF L7 10uF

GNDR 31 AAGND 1 2 + C110 C111 VCC 10uF 0.1uF FB 9 VCCD 17 C112 18 0.1uF

D FIBOP 27 12 D FIBON 28 10 8 VCC 7 GNDD GNDIO TEST FIBIP 6 FIBIN 5 43 52 10 4 LXT970QC 3 R149 R150 R151 2 EDGE OF BOARD 270 270 270 1 9 11 RLEDS# RLEDR# RLEDT#

RJ45 PINOUT, COMPONENT SIDE VIEW 2 1 2 1 2 1 PINS: 1-8 D10 D11 D12 NP MOUNTING HOLES: 9, 10 SHIELD MOUNTING HOLES: LED (SOT23) LED (SOT23) LED (SOT23) 12 12 11, 12

E 4 3 3 5204 E. Ben White Blvd. E ECLIPTEK ECSMA-25.00MTR Austin, TX 78741 LUMEX SOT23 LED AMD Proprietary/All Rights Reserved LINK SPEED TX DATA RX DATA Title LEDS#Red LEDT# Green LEDR# Green Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev ENET2.SCH 2.1 Date:Friday, December 04, 1998 Sheet 14 of 26

1 2 3 4 5 1 2 3 4 5 IDE INTERFACE AND BOARD BYPASS CAPACITORS

HDD[0..15] HDD[0..15]

VCC VCC Byass Capacitors For The Board

RP6 RP5 A 2 O2 C 1 1 C O2 2 A BC3 BC4 BC5 BC6 BC7 BC1 BC2 BC8 BC9 BC10 BC11 BC12 BC13 BC14 3 O3 O3 3 HDD7 HDD8 4 O4 O4 4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 5 O5HDD6 O5 5 HDD9 6 O6HDD5 O6 6 HDD10 7 O7HDD4 O7 7 HDD11 8 O8HDD3 O8 8 HDD12 9 O9 O9 9 VCC 10 HDD2 10 HDD15 O10HDD13 O10 HDD14 10K-10PHDD1 10K-10P HDD0 BC15 BC16 BC17 BC18 BC19 BC20 BC21 BC22 BC23 BC24 BC25 BC26 BC27 BC28

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF J5 SYSRSTJ 1 2 3 4 VCC 5 6 7 8 9 10 HDD7 11 12 HDD8 BC29 BC30 BC31 BC32 BC33 BC34 BC35 BC36 BC37 BC38 BC39 BC40 BC41 BC42 13 14 HDD6 HDD9 15 16 B 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF HDD5 17 18 HDD10 B HDD4 HDD11 HDRQ0 19 20 HDIOWJ HDD3 21 22 HDD12 HDIORJ HDD2 23 24 HDD13 HDIORDY HDD1 25 26 HDD14 Place one bypass capacitor near each chip Vcc pin, except: HDACK0 HDD0 27 28 HDD15 'ABT chips get one on each side near end Vcc pins IRQ14 29 30 HDIO16J VCC QFP chips get one on each side by central Vcc pin HDA1 31 32 HDA0 33 34 HDA2 HDCSJ0 35 36 HDCSJ1 VCC 37 38 39 40 + TC12 + TC2 + TC24 + TC25 10uF 10uF 10uF 10uF CNN-40C BC43 BC44 BC45 BC46 BC47 VCC HD ACTIVE LED J5LED J5LEDR R62 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1 3 2 270 D13 LED (SOT23) IDE HARD DISK 1 Distribute Tantalum capacitors around the board

C C

SYSRSTJ J7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RP7 17 18 10 O10 19 20 9 HDRQ1 O9 21 22 8 HDIOWJ O8 23 24 7 HDIORJ O7 25 26 6 HDIORDY O6 HDD7 27 28 HDD8 5 HDACK1 O5 VCC HDD6 29 30 HDIO16JHDD9 4 IRQ15 O4 HDA1 HDD5 31 32 HDD10 3 2 O3 1 HDA0 HDD4 33 34 HDA2HDD11 O2 C HDCSJ2 HDD3 35 36 HDCSJ3HDD12

J7LED HDD2 37 38 HDD13 10K-10P D HDD1 39 40 HDD14 R21 D HDD0 CNN-40C HDD15 VCC 1K HDCSJ1 R20 R63 HD ACTIVE LED HDCSJ0 J7LEDR 1 3 HDCSJ3 2 HDCSJ2 1K 270 D14 IDE HARD DISK 2 R90 LED (SOT23) HDA0 HDA2 HDA1 4.7k HDIO16J

HDIORJ

(C) Advanced Micro Devices, Inc. (800) 222-9323 HDIOWJ E LUMEX LED (SOT23) 5204 E. Ben White Blvd. E Austin, TX 78741 1 AMD Proprietary/All Rights Reserved 3 CATH Title HDIORDY 2 Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Top View Size Document Number Rev IDE.SCH 2.1 Date:Friday, December 04, 1998 Sheet 15 of 26

1 2 3 4 5 1 2 3 4 5 FINALi M1487 INTERFACE

DACK7 DRQ0 DACK6 DRQ1 DACK5 DRQ2 DACK3 DRQ3 DACK2 DRQ5 DACK1 DRQ6 DACK0 DRQ7 IRQ15 IRQ14 A VCC A RP12 IRQ12 IRQ11 1 C O2 2 XBUSCSJ IRQ10 O3 3 CLEAROKJ IRQ9 VCC O4 4 IRQ7 O5 5 CMPGNTJ IRQ6 O6 6 CMPSTJ IRQ5 O7 7 ENRTC IRQ4 O8 8 IRQ3 O9 9 IRQ1 10 O10 IRQ8J TC17 C50 C173 C174 + 10K-10P U21 10uF 0.1uF 0.1uF 0.1uF 3 11 93 92 90 89 88 83 96 97 99 101 100 102 86 94 84 104 106 108 103 87 91 85 105 107 109 1 40 60 80 120 144 10 41 62 98 128 138 160 VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ8J IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DREQ0 DREQ1 DREQ2 DREQ3 DREQ5 DREQ6 DREQ7 DACKJ0 DACKJ1 DACKJ2 DACKJ3 DACKJ5 DACKJ6 DACKJ7 SD[0..15] SD[0..15] CPUCLK SD0 CPURST SD1 U15A CPUCLK2 61 SYSRST SD2 137 SD0 CPURST 20 A20MJ SD3 136 2 1 SYSRST 63 135 SD1 B PCIRSTJ INTR SD4 B A20MJ 22 FERRJ SD5 134 SD2 74F04 INTR 23 IGNNEJ SD6 133 SD3 U15B FERRJ 16 NMI SD7 132 SD4 IGNNEJ 17 131 SMIJ SD8 4 3 M1487NMI 18 130 SD5 SYSRSTJ STPCLKJ SD9 SMIJ 19 119 SD6 PCICLK SD10 74F04 STPCLKJ 21 121 SD7 SYSRSTJ SD11 PCICLK 46 127 SD8 81 OSC SD12 126 U15D OSC ATCLK SD13 SD9 49 125 SA[0..19] JRESET ATCLK 70 PWG SD14 124 SD10 ZRSTDRV 8 9 PWG 13 PREQJ0 SD15 123 SD11 PREQJ0 50 PREQJ1 SA0 122 SD12 SA[0..19] 74F04 PREQJ1 53 PREQJ2 SA1 7 SD13 PREQJ2 54 4 SA2 SD14 PGNTJ0 52 PGNTJ1 SA3 157 PGNTJ0 SD15 PGNTJ1 51 PGNTJ2 SA4 156 U15C PGNTJ2 55 FARMEJ SA5 155 SA0 FRAMEJ R147 47 IRDYJ SA6 154 SA1 6 5 IRDYJ 48 152 RSTDRV# RRDRV# INT0J SA7 SA2 INT0J 57 151 INT1J SA8 SA3 22 74F04 INT1J 59 150 INT2J 56 INT2J SA9 149 SA4 INT3J 58 INT3J SA10 148 SA5 XBUSCSJ SA11 C XBUSCSJ 73 147 SA6 C RTCAS RTCAS SA12 78 146 SA7 14 OSC1 SA13 9 15 OSC2 SA14 8 SA8 R79 SPEAK 65 SPEAKER SA15 153 SA9 10M TURBO 64 TURBO SA16 145 SA10 EXTSMI 74 EXTSMI SA17 143 SA11 LA[17..23] Y4 75 SPLED SA18 142 SA12 CLKCTR 72 141 CLKCTR OSCI SA19 SA13 4 1 ENRTC 71 ENRTC LA17 118 3 2 5 OSCO LA18 117 SA14 6 116 SA15 KBCLK LA19 VBAT 12 115 SA16 C53 KBDATA LA20 114 SA17 LA[17..23] 10pF 32.768KHz_SMD C54 VBAT 113 ECLIPTEK 10pF LA21 112 SA18 ECPSM29T-32.768KTR LA22 SA19 LA23 LA17 LA18 CLEAROKJ CMPGNTJ CMPSTJ IBCSTJ HA2 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 IOCS16J MEMCS16J MEMRJ MEMWJ SMEMRJ SMEMWJ IOCHRDY OWAITJ BALE IORJ IOWJ MASTERJ TC IOCHCKJ REFRESHJ SBHEJ AEN LA19

44 43 45 42 39 38 24 25 26 27 29 31 33 34 32 28 30 35 36 37 110 111 67 79 66 76 139 2 68 69 77 82 95 129 158 159 140 LA20 LA21 R58 CLEAROKJ M1487 LA22 ENRTC ZAEN LA23 D CMPGNTJ D CMPSTJ ZSBHEJ 1K OFF: ENABLE INTERNAL RTC IBCSTJ ZREFSHJ ON: DISABLE INTERNAL RTC IOCHKJ GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GA17 TC MASTERJ ZIOWJ R59 ZIORJ CMPSTJ ZBALE N0WSJ *1K OFF: 1X CPU-TO-PCI BUS FREQUENCY IOCHRDYJ ON: 2X CPU-TO-PCI BUS FREQUENCY GA[2..17] ZSMEMWJ ZSMEMRJ ZMWJ R170 ZMRJ IBCSTJ MEM16J IO16J 1K DISABLES INTERNAL KBC

*=Do Not Populate

(C) Advanced Micro Devices, Inc. (800) 222-9323 GA[2..17] 12 E 5204 E. Ben White Blvd. E Austin, TX 78741 AMD Proprietary/All Rights Reserved Title 4 3 Am486 MICROPROCESSOR ECLIPTEK ECPSM29T-32.768KTR PCI CUSTOMER DEVELOPMENT PLATFORM (COMPONENT SIDE VIEW) Size Document Number Rev M1487.SCH 2.1 Date:Friday, December 04, 1998 Sheet 16 of 26

1 2 3 4 5 1 2 3 4 5 BIOS ROM, ISA SIGNAL SERIES TERMINATION; BATTERY AND SPEAKER CIRCUITS; RESET, SMI, AND NMI PUSHBUTTONS VCC

RP18 10K-10P 1

VCC VCC C O10 O9 O8 O7 O6 O5 O4 O3 O2

A R77 R76 10 9 8 7 6 5 4 3 2 A GA[2..9] 10K 10K VCC SA[0..19] SA[0..19] GA[2..9] U14 VCC 32 ROM Data RN12 A0 12 Transferred on AEN 1 2 ZAEN SA0 11 A1 3 4 SA1 A2 DQ0 FINALi LinkBus SBHEJ ZSBHEJ 10 13 GA2 5 6 ZRSTDRV A3 DQ1 RSTDRV SA2 9 14 GA3 7 8 BALE A4 DQ2 ZBALE SA3 8 15 GA4 7 A5 DQ3 17 SA4 GA5 33-8B 6 A6 DQ4 18 CTS 743 08-3 330 J TR SA5 5 A7 DQ5 19 GA6 VCC VCC SA6 27 A8 DQ6 20 GA7 RN10 SA7 26 A9 DQ7 21 GA8 1 2 R177 R178 SMEMWJ ZSMEMWJ SA8 23 A10 GA9 ZSMEMRJ 3 4 SMEMRJ 1K 1K SA9 25 A11 ZIORJ 5 6 IORJ 4 JP32 7 8 ZIOWJ VCC SA10 A12 ROM_A17 IOWJ 28 A13 A17 30 1 SA11 29 1 ROM_A18 SA17 VCC A14 A18 2 33-8B SA12 3 R71 A15 3 SA13 2 470 A16 R68 SA14 HEADER 3X1 XBUSCSJ 22 JP33 10K MRDJ SA15 24 OECE 16 1 B SMEMWJ SA16 31 GND RN11 TURBO SWITCH FUNCTION B WR SA18 2 1 2 3 REFRESHJ ZREFSHJ TURBO ZMRJ 3 4 MRDJ 5 6 Am29F010-90 HEADER 3X1 MWTJ ZMWJ ATCLKO 7 8 ATCLK R70 *2.2K FINALi only supports 1MBit Flash ROM chip Jumpers to allow multiple 128K BIOS 33-8B (128Kx8 worth of address space) for legacy, images in the same Flash ROM chip desktop PC applications and/or non-PC applications that can use more than 128Kx8 BIOS ROM VCC

D1 3 BT1P 1 3 VBAT D8 1 MMBD4148 (SOT23) MMBD4148 (SOT23) R34 BT1 1K Press Switch To Assert NMI R139 U83B 3V Coincell (socket) 100 1 U77A 2 KEYSTONE 103 or 106 1 3 SW2NET EXTNMI#3 4 EXTNMI 1 C 3 NMI C SW2 2 PBNO (TO Am486 CPU) VCC 74F14 Q1 + TC22 74F32 10uF MMBT3906 (SOT23) R47 M1487NMI 2 3 Q1R (FROM M1487) 0

1 VCC + TC13 10uF VCC 3 R48 R50 D5 51K 10K 3 MMBD4148 (SOT23) R64 D9 10K MMBD4148 (SOT23) R52 Press Switch To Assert RESET R65

10K 1 100

Q2RQ Q1RQ Press Switch To Assert SMI R140 1 3 RRPWG PWG 100 1 SW1 1 3 EXTSMI 3 PBNO JP34 Q2 SW3 RREXTSMI 1 1 2MMBT3904 (SOT23) PBNO + TC16 D Q2RR 2 10uF D R49 + TC23 HEADER 2X1 10K 10uF

Jumper for external RESET# pushbutton

VCC SPARE 'F14 GATES

LS1 U83C R81 RRSPEAK RCSPEAK 5 6 Battery Socket Reset, SMI Switches 33 SPEAKER 3 74F14 C52 R80 3 U83D Q4 4 3 SPEAK CSPEAK CRSPEAK 1 2 1 2MMBT3904 (SOT23) 9 8 0.1uF 470 C55 1 2 22pF 2 1 MMBD4148 (SOT23) (C) Advanced Micro Devices, Inc. (800) 222-9323

1 Am486 MICROPROCESSOR 74F14 U83F PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev 13 12 ROM_MISC.SCH 2.1 Date:Friday, December 04, 1998 Sheet 17 of 26 74F14

1 2 3 4 5 1 2 3 4 5 CLOCK GENERATOR

A A

1 4 VCC 2 3 C161 C155 B R39 B 10pF 10pF 4.7K 14.318MHz_SMD VCC VCC INSTALL PULLUP OSC

RESISTOR AND REMOVE CLKOSCIN 0-OHM RESISTOR FOR U17 R92 OSCin U15E 25MHz CPU AND PCI BUSR93 4.7K 1 14.318 ROSCC R41 RROSC RROSC1 R54 *4.7K CLKOSCOUT OSCout 28 11 10 OSC1 2 MCLK1 PLACE SERIES TERMINATORS AS S0 MCLK2 24 10 10 CLKPU2 11 S1 25 MCLK2 CLOSE TO U17 AS POSSIBLE 74F04 C60 10 S2 B2in 17 27 15pF CLKPU1 B1in 3 ST# R176 18 B1OUT1 B1out1 R31 10 0 5 B1OUT2 DOZE# B1out2 R33 0 PCICLK3 15 6 B1OUT3 PCICLK B1out3 8 R38 10 B1out4 B1OUT4 R36 10 PCICLK1 9 PCICLK2

B2out1 20 B2OUT1 R22 10 B2OUT2 CPUCLK1 C VCC B2out2 21 R35 10 C B2OUT3 CPUCLK2 R42 B2out3 22 R57 0 B2OUT4 R99 10 CPUCLK3 CLKAVDD1 14 AVDD B2out4 23 CPUCLK TC14 10 + C47 0.1uF VCC C41 C43 C46 C154 C33 C56 C57 C66 10uF L3 7 15pF 15pF 15pF 15pF 15pF 15pF 15pF 15pF VDD1 CLKAVDD2 CLKAVSS 12 16 FB PCICLK AND CPUCLK3 HAVE MULTIPLE LOADS AND ARE AVSS VDD2 + TC15 10uF C48 C170 THEVENIN TERMINATED AT THE END OF THE NET C65 0.1uF 0.1uF 0.1uF 4 CLKLF1 13 VSS1 19 LF1 VSS2 26 VSS3

IMI SC464

D D

(C) Advanced Micro Devices, Inc. (800) 222-9323 12 E 5204 E. Ben White Blvd. E Austin, TX 78741 AMD Proprietary/All Rights Reserved Title 4 3 Am486 MICROPROCESSOR ECLIPTEK ECSMAT-14.318MTR (COMPONENT SIDE VIEW) PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev CLOCK.SCH 2.1 Date:Friday, December 04, 1998 Sheet 18 of 26

1 2 3 4 5 SD[0..15] 1 2 3 4 5

VCC SD7 ISASD7 BUS CONNECTORS AND PULLUPS SD6 SD6 SD5 SD5 +12V -12V -5V VCC R75 R78 SD4 +12V -12V -5V VCC SD4 IOCHKJ GND -IOCHCK 1K GND -IOCHCK 4.7K SD3 SD3 RESDRVSL2 D7 RESDRVSL1 D7 +5V D6 SD2 +5V D6 SD2 50 IRQ9 D5 1 IOCHKJ SD1 50 IRQ9 D5 1 SD1 51 2 51 2 RSTDRV -5V D4 SD0 RSTDRV -5V D4 SD0 52 3 52 3 DREQ2 D3 DREQ2 D3 A IRQ9 53 4 IRQ9 53 4 A 54 -12V D2 5 54 -12V D2 5 -0WS D1 -0WS D1 DRQ2 55 6 SA19 DRQ2 55 6 SA19 56 +12V D0 7 SA18 56 +12V D0 7 SA18 57 GND IOCHRDY 8 57 GND IOCHRDY 8 N0WSJ SA17 3 N0WSJ SA17 58 -SMEMW AEN 9 58 -SMEMW AEN 9 SA16 SA16 59 -SMEMR A19 10 IOCHRDYJ 59 -SMEMR A19 10 IOCHRDYJ SA15 D7 SA15 SMEMWJ 60 -IOW A18 11 AEN SMEMWJ 60 -IOW A18 11 AEN MMBD4148 (SOT23) SMEMRJ 61 -IOR A17 12 SA14 SMEMRJ 61 -IOR A17 12 SA14 IOWJ 62 -DACK3 A16 13 SA13 IOWJ 62 -DACK3 A16 13 SA13 IORJ 63 DREQ3 A15 14 SA12 1 IORJ 63 DREQ3 A15 14 SA12 64 15 64 15 DACK3 -DACK1 A14 SA11 DACK3 -DACK1 A14 SA11 65 DREQ1 A13 16 65 DREQ1 A13 16 DRQ3 SA10 DRQ3 SA10 DACK1 66 -REFSH A12 17 DACK1 66 -REFSH A12 17 67 18 67 18 DRQ1 SYSCLK A11 SA9 DRQ1 SYSCLK A11 SA9 68 19 68 19 REFRESHJ IRQ7 A10 SA8 REFRESHJ IRQ7 A10 SA8 69 20 69 20 ATCLKO IRQ6 A9 SA7 ATCLKO IRQ6 A9 SA7 IRQ7 70 21 IRQ7 70 21 71 IRQ5 A8 22 SA6 71 IRQ5 A8 22 SA6 IRQ6 IRQ4 A7 SA5 IRQ6 IRQ4 A7 SA5 IRQ5 72 23 IRQ5 72 23 73 IRQ3 A6 24 SA4 73 IRQ3 A6 24 SA4 IRQ4 -DACK2 A5 IRQ4 -DACK2 A5 IRQ3 74 25 SA3 IRQ3 74 25 SA3 TC A4 TC A4 DACK2 75 26 SA2 DACK2 75 26 SA2 76 ALE A3 27 76 ALE A3 27 TC TC 77 +5V A2 28 SA1 77 +5V A2 28 SA1 B BALE BALE B 78 14.3MHZ A1 29 SA0 78 14.3MHZ A1 29 SA0 OSC1 79 GND A0 30 OSC1 79 GND A0 30 80 31 80 31

-MEMCS16 -SBHE LA23 -MEMCS16 -SBHE LA23 MEM16J 81 -IOCS16 LA23 32 SBHEJ MEM16J 81 -IOCS16 LA23 32 SBHEJ 82 33 LA22 82 33 LA22 IO16J IRQ10 LA22 IO16J IRQ10 LA22 83 34 83 34 IRQ10 IRQ11 LA21 LA21 IRQ10 IRQ11 LA21 LA21 IRQ11 84 35 LA20 IRQ11 84 35 LA20 85 IRQ12 LA20 36 85 IRQ12 LA20 36 IRQ12 IRQ15 LA19 LA19 IRQ12 IRQ15 LA19 LA19 IRQ15 86 37 IRQ15 86 37 87 IRQ14 LA18 38 LA18 87 IRQ14 LA18 38 LA18 IRQ14 -DACK0 LA17 IRQ14 -DACK0 LA17 DACK0 88 39 LA17 DACK0 88 39 LA17 DREQ0 -MEMR DREQ0 -MEMR DRQ0 89 40 MRDJ DRQ0 89 40 -DACK5 -MEMW -DACK5 -MEMW DACK5 90 41 MWTJ DACK5 90 41 91 DREQ5 SD8 42 91 DREQ5 SD8 42 DRQ5 SD8 DRQ5 SD8 MRDJ 92 -DACK6 SD9 43 92 -DACK6 SD9 43 DACK6 SD9 DACK6 SD9 MWTJ DRQ6 93 DREQ6 SD10 44 DRQ6 93 DREQ6 SD10 44 DACK7 94 -DACK7 SD11 45 SD10 DACK7 94 -DACK7 SD11 45 SD10 DRQ7 95 DREQ7 SD12 46 SD11 DRQ7 95 DREQ7 SD12 46 SD11 96 +5V SD13 47 SD12 96 +5V SD13 47 SD12 97 48 97 48 MASTERJ -MASTER SD14 SD13 MASTERJ -MASTER SD14 SD13

98 49 SA[0..19] 98 49 GND SD15 SD14 GND SD15 SD14 C SD15 SD15 C AMP 645169-3 C58 C64 AMP 645169-3 47pF 47pF RP16 10 ISA AT Connector O10 ISA AT Connector 10K-10P 9 O9 8 RP15 RP21 O8 7 10 10 O7 O10 O10 6 SA12 9 9 O6 5 O9 8 O9 8 SA13 VCC O5 4 O8 7 O8 7 O4 3 SA14 O7 6 O7 6 1 O3 2 SA15 VCC O6 5 SD0 VCC O6 5 SD15 C O2 SA16 O5 4 SD1 O5 4 SD14 RP19 10 SA17 O4 3 SD2 O4 3 SD13 10K-10P O10 9 1 O3 2 SD3 1 O3 2 O9 8 SA18 C O2 C O2 SD12 O8 7 SA19 SD4 SD11 4.7K-10P 4.7K-10P O7 6 SD5 SD10 O6 5 SD6 SD9 VCC O5 SD[0..15] 4 SA4 SD7 SD8 O4 3 1 O3 2 SA5 VCC VCC C O2 SA6 RP14 RP17 10 SA7 2 O2 C 1 RP20 O10 IRQ9 10K-10P 9 3 O3 1 C O2 2 O9 SA8 IRQ8J SD[0..15] D 8 4 O4 O3 3 D O8 SA9 IRQ7 7 5 O5 O4 4 O7 SA10 IRQ15 6 6 O6 O5 5 O6 SA11 IRQ14 5 IRQ3 7 O7 O6 6 VCC O5 IRQ10 4 IRQ4 8 O8 O7 7 O4 IRQ11 3 IRQ5 IRQ12 9 O9 O8 8 1 O3 2 10 9 IRQ6 SA1 O10 O9 LA23 C O2 10 SA2 O10 LA22 SA3 10K-10P LA21 10K-10P SA0 LA[17..23] LA20 LA19 SA[0..19] LA18 LA17

VCC

RP13 2 1 MEM16J O2 C 3 LA[17..23] IO16J O3 4 N0WSJ O4 REFRESHJ 5 6 O5 (C) Advanced Micro Devices, Inc. (800) 222-9323 MASTERJ O6 E 7 E 8 O7 5204 E. Ben White Blvd. O8 Austin, TX 78741 AMD Proprietary/All Rights Reserved 330-8P Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev ISA_CONN.SCH 2.1 Date:Friday, December 04, 1998 Sheet 19 of 26

1 2 3 4 5 1 2 3 4 5

Y1 SUPER I/O CHIP, IrDA INTERFACE, FLOPPY DISK INTERFACE, SERIAL PORT ACTIVITY LEDS VCC 1 4 2 3 SD[0..7]

C45 C44 39pF 24MHz_SMD 39pF R152 R153 1.5K 1.5K

SIOOSC2 SIOOSC1 SD[0..7] A A VCC SA[0..10] RRTXD1 RRRXD1

SA0 SD0 SA1 SD1 1 2 1 2 SA2 SA0 U43 SD2 D15 D16 SA1 21 20 15 72 6 47 67 95 SA[0..10] SA3 SD3 LED (2mA, SOT23) LED (2mA, SOT23) SA4 SA2 SD4 27 SA3 48 TXD1_LED SA5 SD5 1

VCC VCC SD0 TXD2 GND GND GND GND

SA6 29 SA4 OSC2 OSC1 49 SD6

SD1 3 3 SA7 30 SA5 50 SD7 31 SD2 51 2 3 SA8 SA6 SD3 32 SA7 53 SA9 33 SD4 54 U84A SA8 SA10 34 SD5 55 74ABT125 SA9 41 SD6 56 42 SD7 43 97 AEN 37 IOR# IRQ3 RXD1_LED4 SA10 IRQ3 38 IRQ4 RXD2 AEN 46 IOW# IRQ4 94 IRQ5 IORJ 44 TC IRQ5/ADRx#/PP_MODE1 40 IRQ6 5 6 IOWJ 45 IRQ6 39 TC IRQ7 U84B 35 IRQ7 B IOCHRDYJ 74ABT125 B 100 IOCHRDY DACK2# VCC DACK1 28 23 DRQ1 DACK2PWG 36 52 DRQ2 DACK3 96 DACK1# DRQ1/UR1_ADD1 98 DRQ2 DRQ3 DACK3#MR DRQ3 PWG 58 RSTDRV 57 R154 R155 PWRGD 1.5K 1.5K IRQ10 RXD1 78 RxD1 TxD1/PP_ADD0 79 TXD1 CTS1J 82 81 RTS1J DSR1J CTS1# RTS1#/PP_ADD1 RRTXD2 80 83 DTR1J RRRXD2 DCD1J 85 DSR1# DTR1#/PP_MODE0 RI1J 84 DCD1# R127 RI1#/IDE_EN 1 2 1 2 0 RXD2 88 89 TXD2 D17 D18 CTS2J 92 RxD2 91 DSR2J RTS2J LED (2mA, SOT23) LED (2mA, SOT23) 90 CTS2# 93 DTR2J DCD2J 87 DSR2# TxD2/FDC_EN RI2J 86 DCD2# RTS2#/UR2_ADD0 10 RI2#/IDE_ADD DTR2#/UR2_ADD1 3 3 IIRQ10 TXD1 9 8 TXD2_LED IRQ11 SIO_NCSJ C 1 C IDE_OE#/IRQ10 RPM U84C 18 DENSEL 2 MTR0J IIRQ11 NCSJ 74ABT125 19 MOT0 5 MTR1J IRTX 22 4 IRQ9 IIRQ9 MOT1 DR0J R130 IRRX 24 3 SIO_IRQIN DRV0 DR1J 99 7 FDIR DRV1 8

IDE_CS1#/IRQ11 STEPJ 13 1K DIR# 9 COMPONENT SIDE VIEW IDE_CS0#/IRQ9/UR1_ADD0 STEP# WDATAJ PDIR/IRQIN 10 WGATEJ 25 WDATA# 11 12 11 HDSEL RXD1 RXD2_LED 8 7 6 5 26 WGATE# 12 HDSEL# INDEXJ U84D 13 TRK0J R118 74ABT125 INDEX# 14 WRTPRTJ 1K IRTX/CFG_PORT TRK0# 16 IRRX/FDC_ADD RDATAJ VCC WP# 17 DSKCHG 9 10 RDATA# DSKCHG# 1 BUSY ACK# PE SLCT ERROR# SLCTIN# INIT# AUTOFD# STROB# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RP4 C 1 2 3 4 61 62 60 59 75 73 74 76 77 71 70 69 68 66 65 64 63 1K-10P TFDS6000 PP7 O2 O3 O4 O5 O6 O7 O8 O9 O10 PP6 PP5 M5113A J6 2 3 4 5 6 7 8 9 10 D D PP4 12 RPM PP3 34 PP2 56 PP1 78 INDEXJ MTR0J VCC SuperI/O IrDA Port PP0 910 11 12 DR1J DR0J 13 14 MTR1J 15 16 FDIR PP[0..7] PP[0..7] 17 18 STEPJ C67 19 20 R100 R101 R102 WDATAJ 0.1uF 21 22 WGATEJ 10 10 47 PSTROBJ 23 24 TRK0J PAUTOFDJ 25 26 WRTPRTJ IR1LEDA PINITJ 27 28 RDATAJ PSLCTINJ 29 30 HDSEL PERRORJ 31 32 DSKCHG

1 8 PSLCT 33 34 VCCIR1 PPE LEDC LEDA VCC 3 PACKJ CNN-34C C68 + C69 6.8uF 0.1uF PBUSY FLOPY-CON 4 GND (C) Advanced Micro Devices, Inc. (800) 222-9323 9 7 E GP1 TXD E 10 2 5204 E. Ben White Blvd. GP2 RXD IRTX 12 2 1 Austin, TX 78741 AMD Proprietary/All Rights Reserved IRRX Title 5 6 Am486 MICROPROCESSOR NC SD 4 3 3 PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev U44 IR1SD ECLIPTEK ECSMA-25.00MTR KINGBRIGHT SOT23 LED TFDS6000 (COMPONENT SIDE VIEW) (COMPONENT SIDE VIEW) SUPER_I/O.SCH 2.1 Date:Friday, December 04, 1998 Sheet 20 of 26

1 2 3 4 5 1 2 3 4 5

PP[0..7] VCC SERIAL AND PARALLEL PORT INTERFACES

RP3 2 O2 C 1 3 O3 PP0 4 O4 PP1 5 O5 6 O6 R6 7 O7 1K 8 O8 A 9 O9 A 10 PP[0..7] O10 RN5 J4 PSTROBJ 1K-10P PPSTROBJ 1 PP2 2 1 PPAUTOFDJ 3 PP3 4 14 5 6 PPP0 2 PAUTOFDJ 7 8 PPERRORJ 15 PPP1 3 22-8B PPINTJ 16 PPP2 4 PINITJ RN6 PPSLCTINJ 17 1 2 PPP3 5 3 PP4 4 18 PP5 5 6 PPP4 6 PSLCTINJ 7 PP6 8 19 7 PP7 PPP5 22-8B 20 8 RN7 PPP6 21 2 1 9 4 3 PPP7 22 6 5 10 8 7 PPACKJ 23 11 B B 22-8B PPBUSY 24 R14 22 12 PERRORJ PPPE 25 R17 22 13 PACKJ PPSLCT R15 22 PBUSY Parallel Port R16 22 PPE AMP 745967-7 R18 22 PSLCT

C26 C24 C21 C18 C16 C32 C27 C25 C23 C20 C17 C15 C31 C22 C19 C29 C30

180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF

C Serial Connector C VCC (Component Side View) U45 RDCD1P# RN13 RDSR1P# J9 DCD1P# DCD1J 21 RO3 RI3 9 1 2 RRXD1P# 1 5 DSR1J DSR1P# 22 RO2 RI2 8 3 4 RRTS1P# 6 9 RXD1 RXD1P 20 RO4 RI4 10 5 6 RTXD1P# 2 4 RTS1J 23 7 7 8 7 DI2 DO2 RTS1P# RCTS1P# 8 TXD1 19 11 RDTR1P# 3 3 CTS1J DI3 DO3 TXD1PCTS1P# 24 6 22-8B RRIN1P# 8 7 DTR1J 25 RO1 RI1 5 DTR1P# RN14 4 2 RI1J 18 DI1 DO1 12 RIN1P# 1 2 9 6 13 RO5 RI5 3 4 5 1 ON/OFF 3 C1+ C2+ 27 5 6 C70 7 8 SIO1C1P SIO1C2P C71 SERIAL PORT 0.1uF ConnectorParallel 0.1uF 22-8B AMP 745410-1 4 26 1 C1- C2- 28 C138 C139 C140 C141 C142 C143 C144 C145 SIO1C1M2 V+ V- 17 SIO1C2M C72 VCC GND C73 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF SIO1VP SIO1VM 1 14 VCC 0.1uF 0.1uF RS232-5V 2 LTC1349CG 15 D 3 D 16 4 VCC 17 U46 RN15 J8 5 RDCD2P# DCD2J 21 RO3 RI3 9 1 2 1 18 DSR2J 22 8 3 4 RDSR2P# 6 RXD2 RO2 RI2 RRXD2P# 6 20 RO4 RI4 10 5 6 2 RTS2J 23 7 7 8 RRTS2P# 7 DI2 DO2 19 TXD2 19 11 RTXD2P# 3 CTS2J DI3 DO3 7 24 6 DCD2P# 22-8B RCTS2P# 8 DTR2J 25 RO1 RI1 5 RN16 RDTR2P# 4 DSR2P# 20 RI2J 18 DI1 DO1 12 1 2 RRIN2P# 9 13 RO5 RI5 RXD2P 3 4 5 8 ON/OFF RTS2P# 3 C1+ C2+ 27 5 6 21 C74 7 8 TXD2PC75 9 CTS2P# SERIAL PORT 0.1uF 0.1uF 22 DTR2P# 22-8B AMP 745410-1 4 26 (Component Side View) 1 C1- C2- 28 RIN2P# C146 C147 C148 C149 C150 C151 C152 C153 10 2 V+ V- 17 23 C76 VCC GND C77 180pF 180pF 180pF 180pF 180pF 180pF 180pF (C) Advanced Micro Devices, Inc. (800) 222-9323 SIO2C1P SIO2C2P 180pF 11 E E VCC 0.1uF 0.1uF 5204 E. Ben White Blvd. 24 RS232-5V Austin, TX 78741 LTC1349CG AMD Proprietary/All Rights Reserved 12 SIO2C1M SIO2C2M 25 Title Am486 MICROPROCESSOR SIO2VP SIO2VM 13 PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev SERIAL_PARALLEL.SCH 2.1 Date:Friday, December 04, 1998 Sheet 21 of 26

1 2 3 4 5 1 2 3 4 5 INTERFACE FOR ISA BUS MEMORY AND HEX DISPLAYS

LA[17..23] ISAA[1..23]

ISAA23 U69 ISAA21 RSTDRV LA23 3 D0 Q0 2 ISAA22 IORJ LA22 4 D1 Q1 5 ISAA20 LA21 7 D2 Q2 6 ISAA19 BALE 8 9 LA20 D3 Q3 ATCLKO A 13 D4 Q4 12 A LA19 ISAA18ISAA17 LA18 14 D5 Q5 15 XBUSCSJ LA17 17 D6 Q6 16 18 19 D7 Q7 REFRESHJ I/O0 I/O30 I/O1 I/O31 1 U55I/O2 I/O32 11 OE# 93 56 BALE E SMEMWJ I/O3 I/O33 SMEMRJ 94 I/O4 I/O34 58 N0WSJ IOWJ 95 I/O5 I/O35 59 MEM16J 74ABT373 96 60 AEN I/O6 I/O36 XBUSCSJ IOCHRDYJ 97 61 MRDJ I/O7 I/O37 VCC ISAA1 99 62 SA[0..16] MWTJ I/O8 I/O38 ROMCE# ISAA2 6 69 ROMOE# U701OE# VCC I/O9 I/O39 ISAA3 8 70 ROMWE# 1 2OE# VCC 7 9 I/O10 I/O40 71 48 3OE# VCC 18 ISAA4 10 I/O11 I/O41 72 SA0 25 4OE# VCC 31 11 I/O12 I/O42 73 24 42 ISAA2 ISAA6 12 I/O13 I/O43EN245#75 ISAA5 ISAA7 SA1 1A1 1Y1 19 I/O14 I/O44DIR24582 SA2 47 1A2 1Y2 2 ISAA1 ISAA8 20 I/O15 I/O45 84 ISAA3 ISAA9 SA3 46 1A3 1Y3 3 21 I/O16 I/O46 85 ISAA10 SA4 44 1A4 1Y4 5 22 I/O17 I/O47 86 ISAA11 P80CS# SA5 43 2A1 2Y1 6 ISAA4 ISAA12 23 I/O18 87 SA6 41 8 ISAA6ISAA5 25 I/O19 I0/CLK0 88 P680CS# 2A2 2Y2 ISAA13 ATCLKO SA7 40 9 ISAA8 32 I/O20 I1/CLK1 B 2A3 2Y3 ISAA7 B SA8 38 11 34 I/O21 I2 13 37 2A4 2Y4 12 35 18 ATCLKO SA9 I/O22 I3 36 3A1 3Y1 13 ISAA9 ISAA14 36 26 SA10 35 3A2 3Y2 14 ISAA10 ISAA15 37 I/O23 I4/CLK2 54 BALE SA11 33 3A3 3Y3 16 ISAA11 ISAA16 38 I/O24 I5/CLK3 63 SA12 32 3A4 3Y4 17 ISAA12 ISAA17ISAA19 43 I/O25 I6 68 SA13 ISAA13 ISAA18ISAA20 I/O26 I7 30 4A1 4Y1 19 44 76 IORJ SA14 29 4A2 4Y2 20 45 I/O27 4 ISAA14 ISAA21 RSTDRV SA15 27 4A3 4Y3 22 ISAA22 46 I/O28 N/C SA16 26 4A4 4Y4 23 ISAA16 ISAA23 47 I/O29 N/C 5 ISAA15 49 N/C 7 21 GND GND 28 SA0 TDI N/C 24 4 GND GND 34 3 TCK N/C 27 10 GND GND 39 28 TMS N/C 31 15 45 53 33 GND GND TDO N/C 78 N/C 48 GND N/C 50 1 55 SD[0..15] ISAD[0..15] GND N/C 74ABT16244 2 57 VCC P48 VCC 16 GND N/C 74 MACH_TCK GND N/C 1 2 17 77 U711DIR VCC MACH_TMS 29 GND N/C 81 1 2DIR VCC 7 MACH_TDI 34 30 GND N/C 83 DIR245 24 VCC 18 MACH_TDO 56 40 GND N/C 98 VCC 78 C 1G# VCC 31 LOW 41 GND N/C 100 C 910 48 2G# 42 R134 1K 51 GND EN245# 25 HEADER2X5; SHRD 52 GND VCC 14 1A1 1B1 66 GND VCC 15 47 1A2 1B2 2 67 GND VCC 39 SD0 46 1A3 1B3 3 ISAD0 79 GND VCC 42 SD1 44 1A4 1B4 5 ISAD1 80 GND VCC 64 SD2 43 1A5 1B5 6 ISAD2 90 GND VCC 65 41 8 91 89 SD3 1A6 1B6 ISAD3 GND VCC 40 9 92 SD4 ISAD4 VCC 38 1A7 1B7 11 SD5 ISAD5 37 1A8 1B8 12 SD6 ISAD6 36 2A1 2B1 13 SD7 35 2A2 2B2 14 ISAD7 ISACNTL.J1 SD8 33 2A3 2B3 16 ISAD8 Rev. 1.6 SD9 32 2A4 2B4 17 ISAD9 MACH221SP-7Y SD10 30 2A5 2B5 19 ISAD10 SD11 29 2A6 2B6 20 ISAD11 U72 VCC U73 VCC SD12 27 2A7 2B7 22 ISAD12 SD13 26 2A8 2B8 23 ISAD13 ISAD43 DA VCC 14 ISAD0 3 DA VCC 14 SD14 ISAD14 ISAD52 DB LED 1 ISAD1 2 DB LED 1 SD15 21 GND GND 28 ISAD15 ISAD613 DC ISAD2 13 DC 4 34 12 12 GND GND ISAD7DD ISAD3 DD PORT 80 10 GND GND 39 NC 6 NC 6 15 45 P80CS# 5 9 5 9 GND GND STRB NC STRB NC D 8 11 8 11 D BLNK NC BLNK NC P80HD 4 4 LDC LDC 10 7 P80LD 10 7 74ABT16245 RDC GND RDC GND R135 330 R136 Hex Display 330 Hex Display TI - TIL311 TI - TIL311

MACH221SP 100 99 82 81 VCC VCC ISAD4 U74 ISAD0 U75 ISAD5 ISAD1 1 80 3 DA VCC 14 3 DA VCC 14 2 DB LED 1 ISAD2 2 DB LED 1 2 79 ISAD7 13 DC 13 DC PORT 680 JTAG Connector 12 DD 12 DD 78 6 6 P680CS# NC NC 1 2 5 STRB NC 9 5 STRB NC 9 ISAD6 8 11 8 11 (C) Advanced Micro Devices, Inc. (800) 222-9323 BLNK NC BLNK NC 4 P680HD ISAD3 4 E LDC LDC E 53 10 7 P680LD 10 7 5204 E. Ben White Blvd. RDC GND RDC GND Austin, TX 78741 R137 AMD Proprietary/All Rights Reserved 29 52 330 R138 Hex Display Hex Display 330 Title Am486 MICROPROCESSOR 30 51 TI - TIL311 TI - TIL311 9 10 PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev 2.1 31 32 49 50 Top View ISA_MEM1.SCH Date:Friday, December 04, 1998 Sheet 22 of 26

1 2 3 4 5 1 2 3 4 5 ISA BUS FLASH MEMORY

A A

ISAD[0..15]

ISAA[1..21]

ISAA1 ISAA2 U56 ISAA3 ISAD0 ISAA4 DQ0 29 25 31 ISAD1 ISAA5 A0 DQ1 B 24 33 B ISAA6 A1 DQ2 ISAD2 23 35 ISAD3 ISAA7 22 A2 DQ3 38 ISAA8 21 A3 DQ4 40 ISAD4 ISAA9 20 A4 DQ5 42 ISAD5 A5 DQ6 ISAA10 19 44 ISAD6 18 A6 DQ7 ISAA11 ISAD7 8 A7 30 ISAA12 7 A8 DQ8 32 ISAA13 6 A9 DQ9 34 ISAD8 ISAA14 5 A10 DQ10 36 ISAD9 ISAA15 4 A11 DQ11 39 ISAD10 3 A12 DQ12 41 ISAD11 VCC ISAA16 2 43 ISAA17 A13 DQ13 ISAD12 1 A14 DQ14 45 ISAA18 ISAD13 48 A15 DQ15/A-1 17 ISAD14 ISAA19 A16 R131 16 15 ISAD15 A17 10K A18 RY/BY# VCC WORD 47 RSTDRV# RSTDRV# 12 37 BYTE# RESET# VCC C114 C115 ROMCE# C ROMCE# 26 C ROMOE# 0.1uF 0.1uF ROMOE# 28 ROMWE# ROMWE# 11 CE# 46 OE# 27 WE# GND GND

29F800-55 TSOP48 1MByte ISA Flash Memory Configured as 512Kx16bit (29F800T device in "word" mode) Access at even ISA Memory addresses between 15MB and 16MB-1 Use CSR 12h bit 3 to access 0f00000-0ffffffh as ISA Memory (instead of DRAM, if installed) Flash chip A0 pin tied to ISA Address Bit 1; mulitply desired Flash chip address by 2h to find correct ISA address for access (ex: Flash chip address 555h is accessed at ISA address AAAh)

D D

E 5204 E. Ben White Blvd. E Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev ISA_MEM2.SCH 2.1 Date:Friday, December 04, 1998 Sheet 23 of 26

1 2 3 4 5 1 2 3 4 5 OPTIONAL Y2K RTC AND TEST INTERFACE PORT CONNECTOR

VCC

GA[2..9]

RTC Address/Data U22 VCC R141 10K Transferred on GA2 4 AD0 VCC 24 A FINALi LinkBus VCC GA3 5 AD1 A GA4 6 AD2 VBAT 20 VBAT GA5 7 AD3 GA6 8 AD4 VBAUX 22 R142 GA7 9 AD5 10K GA8 10 AD6 SQW 23 GA9 11 AD7 IRQ# 19 IRQ8J PWR# 1 RTCPWR# Y6 RTCKS# 18 KS# Set RAMCLR Bit in CR 4B to enable RAM_Clear Function 21 RSTDRV# RCLR# 2 RTCX1 4 1 X1 3 2 U15F

RTCCS# PWG 13 12 13 3 RTCX2 14 CS# X2 32.768KHz_SMD 15 ALE 12 12.5pF 74F04 17 WR# GND 16 RD# GND Set CS Bit in CR 4B for 12.5pF Xtal RTCAS DS1685-5 U77B ZIOWJ 4 B 6 B 5 RTCWR#

ENRTC 74F32 U77C (RTCSJ) 9 8 U77D ZIORJ 10 RTCRD# 12 11 74F32 13

74F32

4 3 ECLIPTEK ECPSM29T-32.768KTR (COMPONENT SIDE VIEW) C OPTIONAL Y2K COMPLIANT RTC C

T.I.P. CONNECTOR

SD[0..15]

SA[0..19] SA0 SA1 SA2 SA3 SA4 SA5 SA6 P31 SA7 SA8 2 1 SA9 EDGE OF BOARD 4 3 SA10 6 5 SA11 8 7 D SA12 SA13 T.I.P. CONNECTOR D 10 9 SA14 SA15 12 11 SA16 14 13 SA17 SA18 16 15 SA19 18 17 1 2 20 19 SD0 22 21 SD1 SD2 24 23 SD3 26 25 SD4 SD5 R119 ETHERNET IRQ 28 27 0 SD6 30 29 SD7 IRQ15 PLASTIC SHROUD 32 31 R120 PARALLEL PORT IRQ NOTCH ON TOP 34 33 0 AEN 36 35 IRQ12 R121 IORJ 38 37 SERIAL PORT1 IRQ IOWJ 40 39 0 R122 ENETIRQ IRQ11 42 41 TIP TEST IRQ 0 PARIRQ R123 44 43 IRQ14 SWIRQ SERIRQ1 0 SERIAL PORT0 IRQ 46 45 PWG SERIRQ0 IRQ10 RSTDRV 48 47 IOCHRDYJ 50 49 (C) Advanced Micro Devices, Inc. (800) 222-9323 52 51 VCC E 54 53 5204 E. Ben White Blvd. E 56 55 Austin, TX 78741 58 57 AMD Proprietary/All Rights Reserved 60 59 C113 Title + 10uF Am486 MICROPROCESSOR COND60 16V PCI CUSTOMER DEVELOPMENT PLATFORM C-CASE Size Document Number Rev RTC_TIP.SCH 2.1 Top View 59 60 Date:Friday, December 04, 1998 Sheet 24 of 26

1 2 3 4 5 1 2 3 4 5 PC KEYBOARD AND MOUSE INTERFACE

VCC

R145 470

KBINHIBIT A KEYBOARD INHIBIT FUNCTION A

R146 *2.2K

VCC VCC

R171 R172 F2 U78A 4.7K 4.7K FUSE--0.5A 1 2 B B L8 J11 VCC FB 74F06 MMDATA MDATA1 1 1 2 2 U78B L9 3 3 VCC FB MVCC 4 4 3 4 MMCLK M_CLK1 5 5 R173 R174 R175 6 6 1K 1K 10K C156 C157 74F06 7 GND 0.1uF 0.1uF 8 GND C158 C159 C160 47pF 47pF 0.1uF MOUSE_CON

U79 44 29 AMP 750329-2 KBSS# OSC ATCLK 4 ATCLKKKCLK T0 P10 KKDATA MMCLK 2 T1 VCC P11 30 MMDATA 43 P12 31 P13 32 RESET# P14 33 RSTDRV# VCC RSTDRV# 5 P15 35 VCC RD# P16 36 9 37 C IORJ XBUSCSJ CS# P17 KBINHIBIT C 7 38 VCC XBUSCSJ IORJ WR# IOWJ 11 P20 R44 IOWJ 24 8 EA P21 25 R45 4.7K SA2 A0 P22 MDATA SA2 10 26 4.7K P23 27 MCLK 28 PROG P24 39 IRQ1 IRQ1 U78C F1 6 SS# P25 40 IRQ12 IRQ12 P26 41 KCLK 5 6 KKCLK L2 FB FUSE--0.5A 14 D0 P27 42 KDATA GA3 15 D1 GA2 GA4 16 D2 NC1 1 74F06 GA5 17 D3 NC2 3 U78D J1 18 D4 NC3 12 KCLK1 1 19 23 9 8 KKDATA L1 FB GA7 D5 KDATA1 2 20 NC4 34 GA8 GA6 D6 21 NC5 3 GA9 D7 4 GND13 VCC 74F06 SYNC C28 C14 KBVCC 5 GA[2..9] 47pF 47pF C1 6

22 7 GA[2..9] M5042 0.1uF KYBD CONN D AMP 212044-1 D

EDGE OF BOARD (COMPONENT SIDE) (COMPONENT SIDE) EDGE OF BOARD

5 1 6 7 4 5-Pin 3 2 6-Pin 2 1 5 3 Din Mini-Din 7 6 4 (PINS 6 AND 8 7 GROUND THE METAL SHELL) U78E

KEYBOARD 11 10 CONNECTOR

3 1 74F06 U78F (C) Advanced Micro Devices, Inc. (800) 222-9323 5 4 E 2 MOUSE E CONNECTOR 13 12 5204 E. Ben White Blvd. Austin, TX 78741 6 5 AMD Proprietary/All Rights Reserved 4 3 74F06 Title Am486 MICROPROCESSOR 2 1 PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev KEYBOARD.SCH 2.1 Date:Friday, December 04, 1998 Sheet 25 of 26

1 2 3 4 5 SOCKET1

Am486 MICROPROCESSOR1 2 3 4 5 (PIN #)-PIN DESIGNATION (PIN SIDE VIEW)

(1)-D20 (18)-D19 (35)-D11 (52)-D9 (59)-GND (65)-DP1 (71)-GND (77)-GND (83)-INC (89)-GND (95)-GND (101)-GND (107)-D2 (113)-D0 (119)-A31 (136)-A28 (153)-A27

(2)-D22 (19)-D21 (36)-D18 (53)-D13 (60)-VCC (66)-D8 (72)-VCC (78)-D3 (84)-D5 (90)-VCC (96)-D6 (102)-VCC (108)-D1 (114)-A29 (120)-GND (137)-A25 (154)-A26 A A (3)-TCK (20)-GND (37)-CLK (54)-D17 (61)-D10 (67)-D15 (73)-D12 (79)-DP2 (85)-D16 (91)-D14 (97)-D7 (103)-D4 (109)-DP0 (115)-A30 (121)-A17 (138)-VCC (155)-A23

(4)-D23 (21)-GND (38)-VCC (55)-SKT1_NC (122)-A19 (139)-GND (156)-VOLDET

(5)-DP3 (22)-GND (39)-VCC (123)-A21 (140)-A18 (157)-A14

(6)-D24 (23)-D25 (40)-D27 (124)-A24 (141)-VCC (158)-GND

(7)-GND (24)-VCC (41)-D26 (125)-A22 (142)-A15 (159)-A12

(8)-D29 (25)-D31 (42)-D28 (126)-A20 (143)-VCC (160)-GND Am486 MICROPROCESSOR (9)-GND (26)-VCC (43)-D30 PIN SIDE VIEW (127)-A16 (144)-VCC (161)-GND

(10)-INV (27)-SMI# (44)-SRESET (128)-A13 (145)-VCC (162)-GND B B (11)-GND (28)-VCC (45)-UP# (129)-A9 (146)-VCC (163)-GND

(12)-HITM# (29)-CACHE# (46)-SMIACT# (130)-A5 (147)-A11 (164)-GND

(13)-INC (30)-WB/WT# (47)-INC (131)-A7 (148)-A8 (165)-A10

(14)-TDI (31)-TMS (48)-FERR# (132)-A2 (149)-VCC (166)-GND

(15)-IGNEE# (32)-NMI (49)-FLUSH# (56)-A20M# (62)-HOLD (68)-KEN# (74)-STPCLK# (80)-BRDY# (86)-BE2# (92)-BE0# (98)-PWT (104)-D/C# (110)-LOCK# (116)-HLDA (133)-BREQ (150)-A3 (167)-A6

(16)-INTR (33)-TDO (50)-RESET (57)-BS8# (63)-VCC (69)-RDY# (75)-VCC (81)-VCC (87)-BE1# (93)-VCC (99)-VCC (105)-VCC (111)-M/IO# (117)-VCC (134)-PLOCK# (151)-BLAST# (168)-A4

(17)-AHOLD (34)-EADS# (51)-BS16# (58)-BOFF# (64)-GND (70)-BE3# (76)-GND (82)-GND (88)-PCD (94)-GND (100)-GND (106)-GND (112)-W/R# (118)-GND (135)-PCHK# (152)-CLKMUL (169)-ADS#

C C SOCKET 1 SOCKET

1 153 153 1

D D

169 17 17 169

COMPONENT SIDE VIEW SOLDER SIDE VIEW (C) Advanced Micro Devices, Inc. (800) 222-9323

E 5204 E. Ben White Blvd. E Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Size Document Number Rev CPU_PINOUT.SCH 2.1 Date:Friday, December 04, 1998 Sheet 26 of 26

1 2 3 4 5 Index-1 , 2-25 , xix , 2-32 , 1-4 , 2-11 , 2-20 , iii , 1-8 , 2-11 , 2-35, 2-36 , 2-14 , 2-35, , 2-35, 2-36 , 2-35, 2-36 , B-2 , 2-35 , 2-11 , 2-7 , 2-7 , 2-6, A-1 , 2-6, A-1 , 2-21 billmaterials. of See limitations and EIP Flash memory description socket cache Level-2 limitations C cable, diskette drive memory cache chipset signal CLKCTL CLKMUL signal CLKPU2 signal clock multiplier CMOS, problems signal CMPSTJ software CodeKit PCI configuration, notational conventions, chipset logic core CPU adjustingpower, CPUV1 signal CPUV2 signal B bill of materials BOM ROM boot , 2-36 , 2-36 , 2-35 , 1-3 , xi, 2-3 , xi, Microprocessor PCI Customer Development Platform Platform Development Customer PCI Microprocessor , xiii , 1-2 , 2-35 , 2-36 , 2-6, A-1 , 2-15 ® , 1-8 , A-1 , 2-5 , xvii , 2-4 , 2-10 , 2-6, 2-21, A-1 , 2-6, 2-21, A-1 , 2-6, , 2-15 , 2-7 , 1-4 , 2-8 Am486 , xi development platform block diagram headers analyzer purpose restrictions troubleshooting block diagram avoiding damage, default settings documentation overview features installation requirements installing jumper summary diagram layout overview diagram overview Index Am486DX2-66 microprocessor Am486DX2-66 microprocessor Am486DX4-100 microprocessor Am486DX5-133 headers analyzer Am486 microprocessor Am486 PCI customer microprocessor Am486 33-MHz system clock A address boot A17, address boot A18, Numerics 25-MHz system clock

CPUV3 signal, 2-6, A-1 CPUVCC3, 2-6, A-1 F

D fan heat sink, 1-5, 1-6 Flash memory debugging in DRAM space, 2-25 monitor, 2-34 ISA, 2-23 support, 2-15 limitations, 2-7 defaults for jumpers and switches, A-1 floppy development support, 2-15 disk drive, 2-30 diskette starting from, 1-6 connecting drive, 1-4 frequency multiplier, 2-35 starting from, 1-6 DMA controller, 2-12 G documentation conventions, xix GND connectors description of, xvii , 2-33 ground wire manual contents, xvii , 2-33 reference material, xviii support, iii H

DRAM limit without buffering, 2-7 hard drive, IDE speed limit with EIP, 2-7 See IDE hard drive. using, 2-20 headers, analyzer, 2-15 drive heat sink, CPU, 1-5, 1-6 See IDE hard drive or floppy disk drive. hexadecimal display, 2-17 DS1685 real-time clock, 2-27 I E IBCSTJ signal, 2-36 EEPROM, serial, 2-13, 2-14 IDE hard drive ENRTC signal, 2-35 connection for, 2-31 errors, 1-8 starting from, 1-7 Ethernet controller, 2-13 IDSEL signal, 2-11 execute-in-place (EIP) Flash memory, 2-25 in-circuit emulator compatibility, 2-17 EXTSMI signal, 2-34 infrared support See IrDA interface.

Index-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual installing customer development platform, 1-4 K requirements, 1-3 troubleshooting, 1-8 KBINHIBIT signal interrupt controller, chipset function, 2-12 , 2-36 keyboard interrupt signals connecting DMA channel limitations, 2-7 , 1-5 connector PCI, 2-19 , 2-31 controller enable TIP interface, 2-18 , 2-36 error IrDA interface , 1-9 Super I/O, 2-29 ISA bus, 2-28 L

J LEDs, problems with, 1-8 Level-2 cache memory, 2-20 limitations J1 connector, 1-5 , 2-7 LinkBus J2 connector, 1-5 , 2-12 literature support J3 connector, 1-5 , iii locations, part J4 connector, 2-30 , 2-5 logic analyzer headers J5 connector, 1-5, 2-31 , 2-15

J6 connector, 1-4, 2-30 J7 connector, 2-31 M J8 connector, 2-29 J9 connector, 2-29 M1487 southbridge chip, 2-12 JP2 jumper, 2-6, A-1 M1489 northbridge chip, 2-11 JP29 test header, 2-17 MACH device, 2-15 JP3 jumper, 2-6, A-1 memory JP30 test header, 2-17 boot ROM, 2-21 JP31 test header, 2-17 cache, 2-20 JP32 jumper, 2-6, 2-21, 2-22, A-1 DRAM, 2-20 JP33 jumper, 2-6, 2-21, 2-22, A-1 EIP Flash memory, 2-25 JP34 connector, 2-34 Flash memory, 2-23 JP4 jumper, 2-6, A-1 map, 2-24 JTAG port, 2-15 problems, 1-8 jumpers serial EEPROM, 2-13, 2-14 defaults, A-1 monitor, debugging, 2-34 summary, 2-6, A-1 mouse, 2-31

Am486® Microprocessor PCI Customer Development Platform Index-3 power supply N connecting, 1-5 using, 2-33 PREQJ0 signal, 2-17 NMI signal , 2-34 PREQJ1 signal, 2-17 nonvolatile data , 2-14 PREQJ2 signal, 2-17 northbridge chip , 2-11 programmable interval timer, 2-12 P PWG signal, 2-34 R P36 analyzer header, 2-16 P38 analyzer header , 2-16 R11 resistor, 2-35 P39 analyzer header , 2-16 R145 resistor, 2-36 P40 analyzer header , 2-16 R146 resistor, 2-36 P41 analyzer header , 2-16 R148 resistor, 2-36 P42 analyzer header , 2-16 R170 resistor, 2-36 P43 analyzer header , 2-16 R176 resistor, 2-36 P44 analyzer header , 2-16 R58 resistor, 2-35 P45 analyzer header , 2-16 R59 resistor, 2-35 P46 analyzer header , 2-16 R70 resistor, 2-35 P47 analyzer header, 2-16 R71 resistor, 2-35 parallel port , 2-30 R93 resistor, 2-35 part locations , 2-5 real-time clock (RTC), 2-27 PCI bus RESET signal, 2-34 arbiter , 2-12 resistor options, 2-35 configuration addressing , 2-11 ROM description , 2-19 boot, 2-21 interrupt signals , 2-19 EIP Flash memory, 2-25 limitations , 2-7 ISA Flash memory, 2-23 peripherals needed to use board, 1-3 PGNTJ0 signal, 2-17 S PGNTJ1 signal, 2-17 PGNTJ2 signal, 2-17 schematics, B-10 pin-grid-array (PGA) socket, 2-17 serial EEPROM, 2-13, 2-14 port 680h display, 2-17 serial ports port 80h display, 1-6, 1-7, 2-17 connector, 2-29 ports Super I/O, 2-29 See serial ports or parallel port. SL1 ISA slot, 1-5, 2-28 POST (Power-On Self-Test codes), 1-6, 1-7 SL2 ISA slot, 1-5, 2-28 power management SLT1 PCI slot, 1-5 not implemented, 2-7, 2-14 SLT2 PCI slot, 1-5

Index-4 Am486® Microprocessor PCI Customer Development Platform User’s Manual SMI signal, 2-34 southbridge chip, 2-12 W super I/O IrDA interface, 2-29 WWW support overview, 2-28 , iii serial ports, 2-29 support, iii Y SW1 switch, 2-34 SW2 switch, 2-34 year-2000 (Y2K), 2-27 SW3 switch, 2-34 switch summary, 2-34 Z system clock speed, 2-35, 2-36 T zero-insertion-force (ZIF) socket, 2-17 technical support, iii test interface port (TIP), 2-18 test points, PCI, 2-17 third-party support, iii timer, chipset function, 2-12

TIP board, 2-18 TURBO signal, 2-35 U

U25 ZIF socket, 2-8 U44 IrDA module, 2-29 U54 serial EEPROM, 2-13 U81 serial EEPROM, 2-14 V

VGA cable, connecting, 1-5 card, connecting, 1-5 monitor problems, 1-8 voltage limitations, 2-7

Am486® Microprocessor PCI Customer Development Platform Index-5

Index-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual