RAC6000 Industrial Computers Technical Reference Guide RAC6000 Industrial Computers Technical Reference Guide
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Intel® Server Board S3420GP
Intel® Server Board S3420GP Technical Product Specification Intel order number E65697-010 Revision 2.4 January, 2011 Enterprise Platforms and Services Division - Marketing Revision History Intel® Server Board S3420GP TPS Revision History Date Revision Modifications Number Feb. 2009 0.3 Initial release. May 2009 0.5 Update block diagram. July. 2009 0.9 Updated POST error code and diagram. Aug. 2009 1.0 Updated MTBF. Nov. 2009 1.1 Additional details for memory configuration. Dec. 2009 1.2 Added Intel® Server Board S3420GPV details. Dec. 2009 2.0 Updated processor name. Jan. 2010 2.1 Corrected the typo. Apr. 2010 2.2 Corrected the typo, updated processor name and remove CCC certification marking information. July. 2010 2.3 Corrected the typo. Jan.2011 2.4 Corrected the typo. Added RDIMM support on S3420GPV. Updated Table 45. Add USB device readiness beep code information. ii Revision 2.4 Intel order number E65697-010 Intel® Server Board S3420GP TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. -
SAMPLE CHAPTER 1 Chapter Personal Computer 1 System Components the FOLLOWING COMPTIA A+ ESSENTIALS EXAM OBJECTIVES ARE COVERED in THIS CHAPTER
SAMPLE CHAPTER 1 Chapter Personal Computer 1 System Components THE FOLLOWING COMPTIA A+ ESSENTIALS EXAM OBJECTIVES ARE COVERED IN THIS CHAPTER: Ûß1.2 Explain motherboard components, types and features Nß Form Factor Nß ATX / BTX, Nß micro ATX Nß NLX Nß I/O interfaces Material Nß Sound Nß Video Nß USB 1.1 and 2.0 Nß Serial Nß IEEE 1394 / FireWire Nß Parallel Nß NIC Nß Modem Nß PS/2 Nß Memory slots Nß RIMM Nß DIMM Nß SODIMM CopyrightedNß SIMM Nß Processor sockets Nß Bus architecture 86498book.indb 1 7/22/09 5:37:17 AM Nß Bus slots Nß PCI Nß AGP Nß PCIe Nß AMR Nß CNR Nß PCMCIA Chipsets Nß BIOS / CMOS / Firmware Nß POST Nß CMOS battery Nß Riser card / daughterboard Nß [Additional subobjectives covered in chapter 2] Ûß1.4 Explain the purpose and characteristics of CPUs and their features Nß Identify CPU types Nß AMD Nß Intel Nß Hyper threading Nß Multi core Nß Dual core Nß Triple core Nß Quad core Nß Onchip cache Nß L1 Nß L2 Nß Speed (real vs. actual) Nß 32 bit vs. 64 bit Ûß1.5 Explain cooling methods and devices Nß Heat sinks Nß CPU and case fans 86498book.indb 2 7/22/09 5:37:18 AM Nß Liquid cooling systems Nß Thermal compound Ûß1.6 Compare and contrast memory types, characteristics and their purpose Nß Types Nß DRAM Nß SRAM Nß SDRAM Nß DDR / DDR2 / DDR3 Nß RAMBUS Nß Parity vs. Non-parity Nß ECC vs. non-ECC Nß Single sided vs. double sided Nß Single channel vs. -
AF IC05 Motherboards Unit 1
AF_IC05_ Motherboards Unit 1 Contents Introduction..................................................................................................................................2 Glossary.......................................................................................................................................3 Form factors.................................................................................................................................4 Common standards:...........................................................................................................5 ATX...........................................................................................................................6 Micro-ATX.................................................................................................................6 Mini-ITX.....................................................................................................................7 Motherboard components............................................................................................................8 CPU socket................................................................................................................9 Memory slots....................................................................................................................11 Chipset.............................................................................................................................12 Traditional chipset...................................................................................................13 -
PDSM4+ 1.0.Indb
PDSM4+ PDSME+ USER’S MANUAL Revision 1.0 The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this manual, or to notify any person or organization of the updates. Please Note: For the most up-to-date version of this manual, please see our web site at www.supermicro.com. SUPERMICRO COMPUTER reserves the right to make changes to the product described in this manual at any time and without notice. This product, including software, if any, and documenta- tion may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any medium or machine without prior written consent. IN NO EVENT WILL SUPERMICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, THE VENDOR SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA. Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara County in the State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product. -
A Multiple-Bus, Active Backplane Architecture for Multiprocessor Systems Scott Alan Irwin Iowa State University
Iowa State University Capstones, Theses and Retrospective Theses and Dissertations Dissertations 1990 A multiple-bus, active backplane architecture for multiprocessor systems Scott Alan Irwin Iowa State University Follow this and additional works at: https://lib.dr.iastate.edu/rtd Part of the Computer Sciences Commons, and the Electrical and Electronics Commons Recommended Citation Irwin, Scott Alan, "A multiple-bus, active backplane architecture for multiprocessor systems " (1990). Retrospective Theses and Dissertations. 9509. https://lib.dr.iastate.edu/rtd/9509 This Dissertation is brought to you for free and open access by the Iowa State University Capstones, Theses and Dissertations at Iowa State University Digital Repository. It has been accepted for inclusion in Retrospective Theses and Dissertations by an authorized administrator of Iowa State University Digital Repository. For more information, please contact [email protected]. Kmwi m««m» tM: gMgea)^ g«v% ,*%&v nî % -"T w}-t r << _ ^ y, , 6 "^"'"'1 ;/< c . i'7 L., '"0!^ ' ,/,i ' } C V' »,, VI i'.i? K !** ' ,'\''\^ja 4% /.ly - f ^ \''' ' %A. , .%V ' %Kie ^ w, * . s» fsf/aK, .y/;, %,,r. INFORMATION TO USERS The most advanced technology has been used to photograph and reproduce this manuscript from the microfilm master. UMI films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margins, and improper alignment can adversely affect reproduction. -
Pentium II Processor Thermal Design Guidelines
Pentium® II Processor Thermal Design Guidelines February 1999 Order Number: 243331-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® II processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1997 - 1999 *Third-party brands and names are the property of their respective owners. -
Bi-Directional Optical Backplane Bus for General Purpose Multi-Processor B Oard-To-B Oard Optoelectronic Interconnects
JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 13, NO. 6, JUNE 1995 1031 Bi-Directional Optical Backplane Bus for General Purpose Multi-Processor B oard-to-B oard Optoelectronic Interconnects Srikanth Natarajan, Chunhe Zhao, and Ray. T. Chen Absfract- We report for the first time a bidirectional opti- cal backplane bus for a high performance system containing nine multi-chip module (MCM) boards, operating at 632.8 and 1300 nm. The backplane bus reported here employs arrays of multiplexed polymer-based waveguide holograms in conjunction with a waveguiding plate, within which 16 substrate guided waves for 72 (8 x 9) cascaded fanouts, are generated. Data transfer of 1.2 GbUs at 1.3-pm wavelength is demonstrated for a single bus line with 72 cascaded fanouts. Packaging-related issues such as Waveguiding Plate transceiver size and misalignment are embarked upon to provide n a reliable system with a wide bandwidth coverage. Theoretical U hocessor/Memory Board treatment to minimize intensity fluctuations among the nine modules in both directions is further presented and an optimum I High-speed Optoelectronic Transceiver design rule is provided. The backplane bus demonstrated, is for general-purpose and therefore compatible with such IEEE stan- - Waveguide Hologram For Bi-Directional Coupling dardized buses as VMEbus, Futurebus and FASTBUS, and can Fig. 1. Optical equivalent of a section of a single bidirectional electronic function as a backplane bus in existing computing environments. bus line. I. INTRODUCTION needed to preserve the rising and falling edges of the signals HE LIMITATIONS of current computer backplane buses increases. This makes using bulky, expensive, terminated Tstem from their purely electronic interconnects. -
International Standard ISO/IEC 10859 Was Prepared by Joint Technical Committee ISO/IEC JTC1, Information Technology, SC 26: Microprocessor System
This is a preview - click here to buy the full publication INTERNATIONAL ISO/IEC STANDARD 10859 First edition 1997-06 Information technology – 8-bit backplane interface: STEbus and mechanical core specifications for microcomputers Technologies de l'information – Interface de fond de panier 8 bits – Bus STE ISO/IEC 1997 All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher. ISO/IEC Copyright Office • Case postale 56 • CH-1211 Genève 20 • Switzerland This is a preview - click here to buy the full publication – 2 – 10859 © ISO/IEC:1997 CONTENTS Page FOREWORD ................................................................................................................... 3 IEEE STANDARD FOR A 8-BIT BACKPLANE INTERFACE: STEBUS INTRODUCTION ............................................................................................................. 4 Clause 1 General .................................................................................................................... 5 2 Functional description............................................................................................... 9 3 Signal lines............................................................................................................... 10 4 Arbitration................................................................................................................ -
Dell EMC Poweredge R640 Technical Guide
Dell EMC PowerEdge R640 Technical Guide Regulatory Model: E39S Series Regulatory Type: E39S001 June 2021 Rev. A08 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2017 - 2021 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. Contents Chapter 1: Product overview......................................................................................................... 5 Introduction...........................................................................................................................................................................5 New technologies................................................................................................................................................................ 5 Chapter 2: System features...........................................................................................................7 Product comparison............................................................................................................................................................ 7 Technical specifications.................................................................................................................................................... -
SFF-TA-1005 Universal Backplane Management
Published SFF-TA-1005 Rev 1.3 SFF-TA-1005 Specification for Universal Backplane Management (UBM) Rev 1.3 January 14, 2020 Secretariat: SFF TA TWG Abstract: This specification defines the Universal Backplane Management structure. This specification provides a common reference for systems manufacturers, system integrators, and suppliers. This specification is made available for public review, and written comments are solicited from readers. Comments received by the members will be considered for inclusion in future revisions of this specification. The description of a connector in this specification does not assure that the specific component is actually available from connector suppliers. If such a connector is supplied it shall comply with this specification to achieve interoperability between suppliers. POINTS OF CONTACT: Josh Sinykin/Jason Stuhlsatz Chairman SFF TA TWG Broadcom Limited Email: [email protected] 4385 River Green Parkway Duluth, GA 30096 Ph: 678-728-1406 Email: [email protected] /[email protected] Universal Backplane Management (UBM) Page 1 Copyright © 2020 SNIA. All rights reserved. Published SFF-TA-1005 Rev 1.3 Intellectual Property The user's attention is called to the possibility that implementation of this specification may require the use of an invention covered by patent rights. By distribution of this specification, no position is taken with respect to the validity of a claim or claims or of any patent rights in connection therewith. This specification is considered SNIA Architecture and is covered -
Xeon Replaces Pentium Pro: 7/13/98
1997 COMPUTER PRESS ASSOCIATION WINNER ♦ BEST COMPUTER NEWSLETTER VOLUME 12, NUMBER 9 JULY 13,1998 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Xeon Replaces Pentium Pro Intel Targets Servers and Workstations by Keith Diefendorff sure applied on the low end by AMD, Cyrix, and IDT. The problem for Intel is that it needs a high ASP to fuel the semi- Intel has plugged the gaping hole at the top end of its conductor R&D and fab improvements that keep it ahead of product line—previously served by the aging Pentium Pro— its competitors. with a Deschutes-based processor module the company Having so far failed to stimulate demand for higher labels Pentium II Xeon. As Figure 1 shows, the new processor performance (and higher priced) processors in PCs, Intel family will serve the midrange to high-end server and work- will try to take a larger share of the higher-margin worksta- station markets until the 64-bit Merced processor enters ser- tion and server markets. While these markets are each about vice in 2000. only 1% of the size of the PC market in unit volume, they can Pentium Pro was previously the only processor in easily bear 10 times the processor price. This fact makes these Intel’s lineup capable of addressing this high-end segment, markets immensely profitable and gives Intel an opportunity because it’s the only processor that supports four-way multi- to increase revenue and ASP. processing (MP), memories larger than four gigabytes, and Beyond the desire to prop up revenue and ASP, Intel fast ECC L2 caches larger than 512K—all minimum require- realizes that strategically it needs to own the markets on both ments of the high-end market. -
The Motherboard ‐ Chapter #5
The Motherboard ‐ Chapter #5 Amy Hissom Key Terms Advanced Transfer Cache (ATC)— A type of L2 cache contained within the Pentium processor housing that is embedded on the same core processor die as the CPU itself. Audio/modem riser (AMR) — A specification for a small slot on a motherboard to accommodate an audio or modem riser card. A controller on the motherboard contains some of the logic for the audio or modem functionality. Back side bus — The bus between the CPU and the L2 cache inside the CPU housing. Bus speed — The speed, or frequency, at which the data on the motherboard is moving. Communication and networking riser (CNR) — A specification for a small expansion slot on a motherboard that accommodates a small audio, modem, or network riser card. CISC (complex instruction set computing) — Earlier CPU type of instruction set. Cooler — A combination cooling fan and heat sink mounted on the top or side of a processor to keep it cool. Discrete L2 cache — A type of L2 cache contained within the Pentium processor housing, but on a different die, with a cache bus between the processor and the cache. Dual-voltage CPU — A CPU that requires two different voltages, one for internal processing and the other for I/O processing. Execution Trace Cache — A type of Level 1 cache used by some CPUs to hold decoded operations waiting to be executed. Expansion bus — A bus that does not run in sync with the system clock. EPIC (explicitly parallel instruction computing) — The CPU architecture used by the Intel Itanium chip that bundles programming instructions with instructions on how to use multiprocessing abilities to do two instructions in parallel.