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User Manual Compactpci Backplanes User Manual CompactPCI Backplanes 73972-101 Rev.000 CompactPCI Manual Overview What is The latest specification for PCI-based industrial computers is called CompactPCI. It is electrically, a superset of desktop PCI with a different physical form factor. CompactPCI utilizes the Eurocard form factor popularized by the VME bus. Defined for both 3U (100mm by 160 mm) and 6U (160mm by 233 mm) card sizes, CompactPCI has the following features: Standard Eurocard dimensions (compliant with IEEE 1101.1 mechanical standards) High density 2mm Pin-and-Socket connectors (IEC approved and Bellcore qualified) Vertical card orientation for effective cooling Easy card retention Excellent shock and vibration characteristics Metal front panel User I/O connections on front or rear of module Standard chassis available from many suppliers Uses standard PCI silicon, manufactured in large volumes Staged power pins for Hot Swap capability Eight slots in basic configuration. Easily expanded with Bridge Chips What is PICMG PICMG (PCI Industrial Computer Manufacturers Group) is a consortium of over 600 companies who collaboratively develop open specifications for high performance telecommunications and industrial computing applications. The members of the consortium have a long history of developing leading edge products for these industries. CompactPCI Connector The CompactPCI connector is a shielded 2mm pitch, 5+2 row connector, compliant to IEC 61076-4-101. Main features of this connector are the pin stagging for hot swap and shielding for EMI/RFI protection. Page 1 of 25 CompactPCI Manual Schroff CPCI Backplanes Schroff CompactPCI Backplanes Schroff CompactPCI backplanes are fully compliant to the latest PICMG specifications. PICMG 2.0 R 3.0 cPCI Core Specification PICMG 2.1 cPCI Hot Swap Specification PICMG 2.6 Bridging Specification PICMG 2.9 System Management Bus Specification PICMG 2.10 Keying Specification Schroff CompactPCI backplanes are specially designed to achieve exellent power distribution, best signal integrity, virtually zero cross talk, and minimum clock skew. The SMD components used on Schroff CompactPCI backplanes lead to a much lower failure rate than conventional components. Schroff uses ceramic capacitors on the CompactPCI backplanes to gain a better noise reduction at frequencies above 10MHz. This feature reduces the radiated and conducted noise caused by the processor and PCI clock signals. In addition, ceramic capacitors have no limitation in useful lifetime, as compared to aluminium capacitors that dry out after 5 to 10 years, and are unaware of the hazardous fire risks known from tantalum electrolytics’. Schroff CompactPCI Backplane Features Isolated Assembling / Connection to ChassisGND Schroff cPCI backplanes have a specially designed pattern of mounting holes to assemble the backplane isolated or connected to ChassisGND. For isolation between BackplaneGND and ChassisGND M2.5 screws and isolating washers should be used in at least every second connector position. If noise reduction shall be achieved by connecting DigitalGND to ChassisGND conductive spring washers are recommended instead of isolating ones. VI/O Schroff CompactCPCI backplanes have a complete power plane for the VI/O voltage. The VI/O plane can be connected using a bridge on the power bugs to +3.3V or +5V. By default, Schroff CompactPCI backplanes have VI/O connected to +5V with blue coding keys on P1. VI/O can also be set to 3,3V with the conversion kit 21101-658 (including 8 yellow keys and a tool) and change of the VI/O bridge position on the rear side of the backplane. Schroff CompactPCI backplanes are, on request, also avaiable with VI/O set to 3,3V. Stiffener The Schroff 6U CompactPCI backplanes are equiped with Stiffeners to reduce bending of the backplane during insertion and extraction of the cPCI cards to a minimum. Page 2 of 25 CompactPCI Manual Schroff CPCI Backplanes Geographical Addressing (GA) Geographical addressing is set by default to start from number one from left (upper) position within the chassis. If more than one backplane shall be assembled, a change of geographical addresses can be made. Cut copper links in between SMD pads to open, apply a zero Ohm resistor to close. Package size shall be 0603. Position is labelled "nGA[x]" where "n" stands for slot# , and "x" for address#, see chapter „Mechanical and Electrical Interface”. Physical Slot Addresses Physical Slot#0(1)12345678910 GA[4] (J2-A22) GND GND GND GND GND GND GND GND GND GND GND GA[3] (J2-B22) GND GND GND GND GND GND GND GND open open open GA[2] (J2-C22) GND GND GND GND open open open open GND GND GND GA[1] (J2-D22) GND GND open open GND GND open open GND GND open GA[0] (J2-E22) GND open GND open GND open GND open GND open GND Physical Slot#1112131415161718192021 GA[4] (J2-A22) GND GND GND GND GND open open open open open open GA[3] (J2-B22) open open open open open GND GND GND GND GND GND GA[2] (J2-C22) GND open open open open GND GND GND GND open open GA[1] (J2-D22) open GND GND open open GND GND open open GND GND GA[0] (J2-E22) open GND open GND open GND open GND open GND open 66MHz Operation Schroff cPCI backplanes are designed in accordance with the requirements of cPCI Core Specification, Revision 3.0 (PICMG 2.0 R3.0). Up to 5 Slots 66MHz operation is possible, signal M66 is HIGH (open). Backplanes of higher slot count also fulfil the 66MHz operation requirements in terms of clock trace length and skew, but M66 is tied to GND to disable 66MHz operation by default. This link is made by a removable copper link. For test purposes, it can be opened and closed again by using a zero Ohm resistor of size 0603. For position of the link see chapter „Mechanical and Electrical Interface”. Hot Swap Schroff cPCI backplanes fulfill the requirements for Basic Hot Swap of the Hot Swap Specification PICMG 2.1 R2.0. The signal BD_SEL# is tied to GND by a removable copper link. It can be replaced by a resistor-capacitor combination, both of package size 0603. Position is labelled "nB" where "n" stands for slot# , see chapter „Mechanical and Electrical Interface”. The P1 connector on Schroff cPCI backplanes has pin stagging needed for hot swap capabilities. Termination Termination on backplanes according to PICMG 2.0 R 3.0 is recommended in one case only. If, on a 8 slot backplane, strong buffers are used and only the system and the first adjacent slot are occupied and all others are empty. Schroff has implemented a special connector on the 8 Slot cPCI backplanes, where a Termination Board can be assembled. For slot counts 4 to 7, this connector is used for assembling a cPCI Bridge, see chapter „Mechanical and Electrical Interface”. Schroff is offering a 64-bit Termination Board, order code 23006- 931. Page 3 of 25 CompactPCI Manual Connector Pinouts Connectors on Schroff CompactPCI Backplanes Pin Assignment CPCI Connectors Table 1: CompactPCI System Slot 64-Bit Connector Pin Assignment Pin Z A B C D E F 22 GND GA4 GA3 GA2 GA1 GA0 GND 21 GND CLK6 GND RSV RSV RSV GND 20 GND CLK5 GND RSV GND RSV GND 19 GND GND GND SMB_SDA(11) SMB_SCL(11) SMB_ALERT#(11) GND 18 GND BRSVP2A18 BRSVP2B18 BRSVP2C18 GND BRSVP2E18 GND 17 GND BRSVP2A17 GND PRST# REQ6# GNT6# GND 16 GND BRSVP2A16 BRSVP2B16 DEG# GND BRSVP2E16 GND 15 GND BRSVP2A15 GND FAL# REQ5# GNT5# GND 14 GND AD[35] AD[34] AD[33] GND AD[32] GND 13 GND AD[38] GND V(I/O)(2) AD[37] AD[36] GND 12 GND AD[42] AD[41] AD[40] GND AD[39] GND 11 GND AD[45] GND V(I/O)(2) AD[44] AD[43] GND 10 GND AD[49] AD[48] AD[47] GND AD[46] GND 9 GND AD[52] GND V(I/O)(2) AD[51] AD[50] GND 8 GND AD[56] AD[55] AD[54] GND AD[53] GND 7 GND AD[59] GND V(I/O)(2) AD[58] AD[57] GND 6 GND AD[63] AD[62] AD[61] GND AD[60] GND 5 GND C/BE[5]# GND V(I/O)(2) C/BE[4]# PAR64 GND 4 GND V(I/O)(2) BRSVP2B4 C/BE[7]# GND C/BE[6]# GND 3(3) GND CLK4 GND GNT3# REQ4# GNT4# GND 2(3) GND CLK2 CLK3 SYSEN#(3) GNT2# REQ3# GND 1(3) GND CLK1 GND REQ1# GNT1# REQ2# GND 25 GND 5V REQ64# ENUM# 3.3V 5V GND 24 GND AD[1] 5V V(I/O)(2),(4) AD[0] ACK64# GND 23 GND 3.3V AD[4] AD[3] 5V(4) AD[2] GND 22 GND AD[7] GND 3.3V(4) AD[6] AD[5] GND 21 GND 3.3V AD[9] AD[8] M66EN C/BE[0]# GND 20 GND AD[12] GND V(I/O)(2) AD[11] AD[10] GND 19 GND 3.3V AD[15] AD[14] GND(4) AD[13] GND 18 GND SERR# GND 3.3V PAR C/BE[1]# GND 17 GND 3.3V IPMB_SCL IPMB_SDA GND(4) PERR# GND 16 GND DEVSEL# GND (PCIXCAP) V(I/O)(2) STOP# LOCK# GND 15 GND 3.3V FRAME# IRDY# GND TRDY# GND 14 KEY AREA 13 KEY AREA 12 KEY AREA 11 GND AD[18] AD[17] AD[16] GND(4) C/BE[2]# GND 10 GND AD[21] GND 3.3V AD[20] AD[19] GND 9 GND C/BE[3]# GND AD[23] GND(4) AD[22] GND 8 GND AD[26] GND V(I/O)(2) AD[25] AD[24] GND 7 GND AD[30] AD[29] AD[28] GND(4) AD[27] GND 6 GND REQ0# GND 3.3V(4) CLK0 AD[31] GND 5 GND BRSVP1A5 BRSVP1B5 RST# GND(4) GNT0# GND 4 GND IPMB_PWR HEALTHY#(13) V(I/O)(2),(4) INTP INTS GND 3 GND INTA# INTB# INTC# 5V(4) INTD# GND 2 GND BRSVP1A2(10) 5V BRSVP1C2(10) RSV(10) RSVI(10) GND 1 GND 5V -12V BRSVP1C1(10) +12V 5V GND Pin Z A B C D E F Page 4 of 25 CompactPCI Manual Connector Pinouts Table 2: CompactPCI Peripheral Slot 64-Bit Connector Pin Assignment (1)(10, 11) Pin Z A B C D E F 22 GND GA4 GA3 GA2 GA1 GA0 GND 21 GND RSV RSV RSV RSV RSV GND 20 GND RSV RSV RSV GND RSV GND 19 GND RSV RSV RSV RSV RSV GND 18 GND BRSVP2A18 BRSVP2B18 BRSVP2C18 GND BRSVP2E18 GND 17 GND BRSVP2A17 GND RSV RSV RSV GND 16 GND BRSVP2A16 BRSVP2B16 RSV GND BRSVP2E16 GND 15 GND BRSVP2A15 GND RSV RSV RSV GND 14 GND AD[35] AD[34] AD[33] GND AD[32] GND 13 GND AD[38] GND V(I/O)(2) AD[37] AD[36] GND 12 GND AD[42] AD[41] AD[40] GND AD[39] GND 11 GND AD[45] GND V(I/O)(2) AD[44] AD[43] GND
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