Vmebus for Software Engineers Introduction
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Getting Started with Your VXI-1394 Interface for Windows NT/98 And
VXI Getting Started with Your VXI-1394 Interface for Windows NT/98 VXI-1394 Interface for Windows NT/98 November 1999 Edition Part Number 322109D-01 Worldwide Technical Support and Product Information www.ni.com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 794 0100 Worldwide Offices Australia 03 9879 5166, Austria 0662 45 79 90 0, Belgium 02 757 00 20, Brazil 011 284 5011, Canada (Calgary) 403 274 9391, Canada (Ontario) 905 785 0085, Canada (Québec) 514 694 8521, China 0755 3904939, Denmark 45 76 26 00, Finland 09 725 725 11, France 01 48 14 24 24, Germany 089 741 31 30, Greece 30 1 42 96 427, Hong Kong 2645 3186, India 91805275406, Israel 03 6120092, Italy 02 413091, Japan 03 5472 2970, Korea 02 596 7456, Mexico (D.F.) 5 280 7625, Mexico (Monterrey) 8 357 7695, Netherlands 0348 433466, Norway 32 27 73 00, Poland 48 22 528 94 06, Portugal 351 1 726 9011, Singapore 2265886, Spain 91 640 0085, Sweden 08 587 895 00, Switzerland 056 200 51 51, Taiwan 02 2377 1200, United Kingdom 01635 523545 For further support information, see the Technical Support Resources appendix. To comment on the documentation, send e-mail to [email protected] © Copyright 1998, 1999 National Instruments Corporation. All rights reserved. Important Information Warranty The National Instruments VXI-1394 board is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. -
Publication Title 1-1962
publication_title print_identifier online_identifier publisher_name date_monograph_published_print 1-1962 - AIEE General Principles Upon Which Temperature 978-1-5044-0149-4 IEEE 1962 Limits Are Based in the rating of Electric Equipment 1-1969 - IEEE General Priniciples for Temperature Limits in the 978-1-5044-0150-0 IEEE 1968 Rating of Electric Equipment 1-1986 - IEEE Standard General Principles for Temperature Limits in the Rating of Electric Equipment and for the 978-0-7381-2985-3 IEEE 1986 Evaluation of Electrical Insulation 1-2000 - IEEE Recommended Practice - General Principles for Temperature Limits in the Rating of Electrical Equipment and 978-0-7381-2717-0 IEEE 2001 for the Evaluation of Electrical Insulation 100-2000 - The Authoritative Dictionary of IEEE Standards 978-0-7381-2601-2 IEEE 2000 Terms, Seventh Edition 1000-1987 - An American National Standard IEEE Standard for 0-7381-4593-9 IEEE 1988 Mechanical Core Specifications for Microcomputers 1000-1987 - IEEE Standard for an 8-Bit Backplane Interface: 978-0-7381-2756-9 IEEE 1988 STEbus 1001-1988 - IEEE Guide for Interfacing Dispersed Storage and 0-7381-4134-8 IEEE 1989 Generation Facilities With Electric Utility Systems 1002-1987 - IEEE Standard Taxonomy for Software Engineering 0-7381-0399-3 IEEE 1987 Standards 1003.0-1995 - Guide to the POSIX(R) Open System 978-0-7381-3138-2 IEEE 1994 Environment (OSE) 1003.1, 2004 Edition - IEEE Standard for Information Technology - Portable Operating System Interface (POSIX(R)) - 978-0-7381-4040-7 IEEE 2004 Base Definitions 1003.1, 2013 -
VM E Bus S Ingle -B Oard C Om Puter
DATASHEET KEY FEATURES 2eSST VMEbus protocol with The Motorola MVME6100 The promise of the VME 320MB/s transfer rate across series provides more than just Renaissance is innovation, the VMEbus faster VMEbus transfer rates; it performance and investment provides balanced performance protection. The MVME6100 MPC7457 PowerPC® processor from the processor, memory series from Motorola delivers running at up to 1.267 GHz subsystem, local buses and I/O on this promise. The innovative 128-bit AltiVec coprocessor for subsystems. Customers looking design of the MVME6100 parallel processing, ideal for for a technology refresh for their provides a high performance data-intensive applications application, while maintaining platform that allows customers backwards compatibility with to leverage their investment in Up to 2GB of on-board DDR their existing VMEbus infra- their VME infrastructure. ECC memory and 128MB of structure, can upgrade to the fl ash memory for demanding The MVME6100 series supports MVME6100 series and applications booting a variety of operating take advantage of its enhanced systems including a complete Two 33/66/100 MHz PMC-X performance features. range of real-time operating sites allow the addition of systems and kernels. A VxWorks industry-standard, application- board support package and specifi c modules Linux support are available for Dual Gigabit Ethernet interfaces the MVME6100 series. for high performance networking The MVME6100 series is the fi rst VMEbus single-board computer (SBC) designed with the Tundra Tsi148 VMEbus interface chip offering two edge source synchronous transfer (2eSST) VMEbus performance. The 2eSST protocol enables the VMEbus to run at a practical bandwidth of 320MB/s in most cases. -
VMIVME-7648 Intel® Pentium® III Processor-Based Vmebus Single Board Computer
VMIVME-7648 Intel® Pentium® III Processor-Based VMEbus Single Board Computer ® • Pentium III FC-PGA/PGA2 socket processor-based single board computer (SBC) with 133 MHz system bus • 1.26 GHz Pentium III processor with 256 Kbyte advanced transfer cache or 933 MHz Pentium III processor with 256 Kbyte advanced transfer cache • 512 Mbyte PC-133 SDRAM using a single SODIMM • Internal AGP SVGA controller with 4 Mbyte display cach ® • 133 MHz system bus via Intel 815E chipset • Dual Ethernet controllers supporting 10BaseT and 100BaseTX interfaces • Onboard Ultra DMA/100 hard drive and floppy drive controllers (uses VMEbus P2 for connection to IDE/floppy) • Two high performance 16550-compatible serial ports • PS/2-style keyboard and mouse ports on front panel • Real time clock and miniature speaker included L2 cache operates at the same clock frequency as the processor, thus • Dual front panel universal serial bus (USB) connections improving performance. • Two 16-bit and two 32-bit programmable timers • 32 Kbyte of nonvolatile SRAM DRAM Memory: The VMIVME-7648 accepts one 144-pin SDRAM • Software-selectable watchdog timer with reset SODIMM for a maximum memory capacity of 512 Mbyte. The onboard • Remote Ethernet booting DRAM is dual ported to the VMEbus. • PMC expansion site (IEEE-P1386 common mezzanine card standard, 5 V) BIOS: System and video BIOS are provided in reprogrammable flash • VME64 modes supported: memory (Rev. 1.02 is utilized from our VMIVME-7750 SBC). A32/A24/D32/D16/D08(EO)/MBLT64/BLT32 • VMEbus interrupt handler, interrupter and system controller Super VGA Controller: High-resolution graphics and multimedia- • Includes real time endian conversion hardware for little- quality video are supported on the VMIVME-7648 using the 815E AGP endian and big-endian data interfacing (patent no. -
From Camac to Wireless Sensor Networks and Time- Triggered Systems and Beyond: Evolution of Computer Interfaces for Data Acquisition and Control
Janusz Zalewski / International Journal of Computing, 15(2) 2016, 92-106 Print ISSN 1727-6209 [email protected] On-line ISSN 2312-5381 www.computingonline.net International Journal of Computing FROM CAMAC TO WIRELESS SENSOR NETWORKS AND TIME- TRIGGERED SYSTEMS AND BEYOND: EVOLUTION OF COMPUTER INTERFACES FOR DATA ACQUISITION AND CONTROL. PART I Janusz Zalewski Dept. of Software Engineering, Florida Gulf Coast University Fort Myers, FL 33965, USA [email protected], http://www.fgcu.edu/zalewski/ Abstract: The objective of this paper is to present a historical overview of design choices for data acquisition and control systems, from the first developments in CAMAC, through the evolution of their designs operating in VMEbus, Firewire and USB, to the latest developments concerning distributed systems using, in particular, wireless protocols and time-triggered architecture. First part of the overview is focused on connectivity aspects, including buses and interconnects, as well as their standardization. More sophisticated designs and a number of challenges are addressed in the second part, among them: bus performance, bus safety and security, and others. Copyright © Research Institute for Intelligent Computer Systems, 2016. All rights reserved. Keywords: Data Acquisition, Computer Control, CAMAC, Computer Buses, VMEbus, Firewire, USB. 1. INTRODUCTION which later became international standards adopted by IEC and IEEE [4]-[7]. The design and development of data acquisition The CAMAC standards played a significant role and control systems has been driven by applications. in developing data acquisition and control The earliest and most prominent of those were instrumentation not only for nuclear research, but applications in scientific experimentation, which also for research in general and for industry as well arose in the early sixties of the previous century, [8]. -
A Multiple-Bus, Active Backplane Architecture for Multiprocessor Systems Scott Alan Irwin Iowa State University
Iowa State University Capstones, Theses and Retrospective Theses and Dissertations Dissertations 1990 A multiple-bus, active backplane architecture for multiprocessor systems Scott Alan Irwin Iowa State University Follow this and additional works at: https://lib.dr.iastate.edu/rtd Part of the Computer Sciences Commons, and the Electrical and Electronics Commons Recommended Citation Irwin, Scott Alan, "A multiple-bus, active backplane architecture for multiprocessor systems " (1990). Retrospective Theses and Dissertations. 9509. https://lib.dr.iastate.edu/rtd/9509 This Dissertation is brought to you for free and open access by the Iowa State University Capstones, Theses and Dissertations at Iowa State University Digital Repository. It has been accepted for inclusion in Retrospective Theses and Dissertations by an authorized administrator of Iowa State University Digital Repository. For more information, please contact [email protected]. Kmwi m««m» tM: gMgea)^ g«v% ,*%&v nî % -"T w}-t r << _ ^ y, , 6 "^"'"'1 ;/< c . i'7 L., '"0!^ ' ,/,i ' } C V' »,, VI i'.i? K !** ' ,'\''\^ja 4% /.ly - f ^ \''' ' %A. , .%V ' %Kie ^ w, * . s» fsf/aK, .y/;, %,,r. INFORMATION TO USERS The most advanced technology has been used to photograph and reproduce this manuscript from the microfilm master. UMI films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margins, and improper alignment can adversely affect reproduction. -
Single-Board Celeron Processor-Based Vmebus CPU User’S Manual GFK-2055
GE Fanuc Automation Programmable Control Products IC697VSC096 Single-Board Celeron Processor-Based VMEbus CPU User’s Manual GFK-2055 514-000431-000 A December 2001 GFL-002 Warnings, Cautions, and Notes as Used in this Publication Warning Warning notices are used in this publication to emphasize that hazardous voltages, currents, temperatures, or other conditions that could cause personal injury exist in this equipment or may be associated with its use. In situations where inattention could cause either personal injury or damage to equipment, a Warning notice is used. Caution Caution notices are used where equipment might be damaged if care is not taken. Note Notes merely call attention to information that is especially significant to understanding and operating the equipment. This document is based on information available at the time of its publication. While efforts have been made to be accurate, the information contained herein does not purport to cover all details or variations in hardware or software, nor to provide for every possible contingency in connection with installation, operation, or maintenance. Features may be described herein which are not present in all hardware and software systems. GE Fanuc Automation assumes no obligation of notice to holders of this document with respect to changes subsequently made. GE Fanuc Automation makes no representation or warranty, expressed, implied, or statutory with respect to, and assumes no responsibility for the accuracy, completeness, sufficiency, or usefulness of the information contained herein. No warranties of merchantability or fitness for purpose shall apply. The following are trademarks of GE Fanuc Automation North America, Inc. Alarm Master Genius PROMACRO Series Six CIMPLICITY Helpmate PowerMotion Series Three CIMPLICITY 90–ADS Logicmaster PowerTRAC VersaMax CIMSTAR Modelmaster Series 90 VersaPro Field Control Motion Mate Series Five VuMaster Genet ProLoop Series One Workmaster ©Copyright 2002 GE Fanuc Automation North America, Inc. -
VMIVME-7807 Intel® Pentium® M-Based VME Single Board Computer
VMIVME-7807 Intel® Pentium® M-Based VME Single Board Computer • Available with either the 1.1 GHz, 1.6 GHz or 1.8 GHz Pentium® M processor • Up to 2 Mbyte of advanced L2 cache • Up to 1.5 Gbyte DDR SDRAM • Up to 1 Gbyte bootable CompactFlash on secondary IDE (see ordering options) • Internal SVGA and DVI controller • Serial ATA support through P2 rear I/O ® • 400 MHz system bus via Intel 855GME chipset • Ethernet controller supporting 10BaseT and 100BaseTX through the front panel • Gigabit Ethernet controller supporting 10BaseT, 100BaseTX and 1000BaseT interface with optional Vita 31.1 support Ordering Options • Four asynchronous 16550 compatible serial ports August 4, 2004 800-007807-000 B A B C D E F • Four Universal Serial Bus (USB) Rev. 2.0 connections, two on VMIVME-7807 – the front panel and two rear I/O A = Processor • PMC expansion site (PCI-X, 66 MHz) 1 = Reserved • 32 Kbyte of nonvolatile SRAM 2 = 1.1 GHz Pentium M ® 3 = 1.6 GHz Pentium M • Operating system support for Windows XP, Windows 2000, 4 = 1.8 GHz Pentium M ® ® ® ® VxWorks , QNX , LynxOS and Linux B = System DDR SDRAM 0 = Reserved 1 = 512 Mbyte Functional Characteristics 2 = 1 Gbyte 3 = 1.5 Gbyte Microprocessor: The VMIVME-7807 is based on the Pentium M C = CompactFlash processor family. The enhanced 1.1 GHz and the 1.6 GHz Pentium M 0 = No CompactFlash 1 = 128 Mbyte processors have 1 Mbyte of L2 cache, while the 1.8 GHz Pentium M 2 = 256 Mbyte 3 = 512 Mbyte processor has 2 Mbyte of L2 cache. -
Bi-Directional Optical Backplane Bus for General Purpose Multi-Processor B Oard-To-B Oard Optoelectronic Interconnects
JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 13, NO. 6, JUNE 1995 1031 Bi-Directional Optical Backplane Bus for General Purpose Multi-Processor B oard-to-B oard Optoelectronic Interconnects Srikanth Natarajan, Chunhe Zhao, and Ray. T. Chen Absfract- We report for the first time a bidirectional opti- cal backplane bus for a high performance system containing nine multi-chip module (MCM) boards, operating at 632.8 and 1300 nm. The backplane bus reported here employs arrays of multiplexed polymer-based waveguide holograms in conjunction with a waveguiding plate, within which 16 substrate guided waves for 72 (8 x 9) cascaded fanouts, are generated. Data transfer of 1.2 GbUs at 1.3-pm wavelength is demonstrated for a single bus line with 72 cascaded fanouts. Packaging-related issues such as Waveguiding Plate transceiver size and misalignment are embarked upon to provide n a reliable system with a wide bandwidth coverage. Theoretical U hocessor/Memory Board treatment to minimize intensity fluctuations among the nine modules in both directions is further presented and an optimum I High-speed Optoelectronic Transceiver design rule is provided. The backplane bus demonstrated, is for general-purpose and therefore compatible with such IEEE stan- - Waveguide Hologram For Bi-Directional Coupling dardized buses as VMEbus, Futurebus and FASTBUS, and can Fig. 1. Optical equivalent of a section of a single bidirectional electronic function as a backplane bus in existing computing environments. bus line. I. INTRODUCTION needed to preserve the rising and falling edges of the signals HE LIMITATIONS of current computer backplane buses increases. This makes using bulky, expensive, terminated Tstem from their purely electronic interconnects. -
International Standard ISO/IEC 10859 Was Prepared by Joint Technical Committee ISO/IEC JTC1, Information Technology, SC 26: Microprocessor System
This is a preview - click here to buy the full publication INTERNATIONAL ISO/IEC STANDARD 10859 First edition 1997-06 Information technology – 8-bit backplane interface: STEbus and mechanical core specifications for microcomputers Technologies de l'information – Interface de fond de panier 8 bits – Bus STE ISO/IEC 1997 All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher. ISO/IEC Copyright Office • Case postale 56 • CH-1211 Genève 20 • Switzerland This is a preview - click here to buy the full publication – 2 – 10859 © ISO/IEC:1997 CONTENTS Page FOREWORD ................................................................................................................... 3 IEEE STANDARD FOR A 8-BIT BACKPLANE INTERFACE: STEBUS INTRODUCTION ............................................................................................................. 4 Clause 1 General .................................................................................................................... 5 2 Functional description............................................................................................... 9 3 Signal lines............................................................................................................... 10 4 Arbitration................................................................................................................ -
SFF-TA-1005 Universal Backplane Management
Published SFF-TA-1005 Rev 1.3 SFF-TA-1005 Specification for Universal Backplane Management (UBM) Rev 1.3 January 14, 2020 Secretariat: SFF TA TWG Abstract: This specification defines the Universal Backplane Management structure. This specification provides a common reference for systems manufacturers, system integrators, and suppliers. This specification is made available for public review, and written comments are solicited from readers. Comments received by the members will be considered for inclusion in future revisions of this specification. The description of a connector in this specification does not assure that the specific component is actually available from connector suppliers. If such a connector is supplied it shall comply with this specification to achieve interoperability between suppliers. POINTS OF CONTACT: Josh Sinykin/Jason Stuhlsatz Chairman SFF TA TWG Broadcom Limited Email: [email protected] 4385 River Green Parkway Duluth, GA 30096 Ph: 678-728-1406 Email: [email protected] /[email protected] Universal Backplane Management (UBM) Page 1 Copyright © 2020 SNIA. All rights reserved. Published SFF-TA-1005 Rev 1.3 Intellectual Property The user's attention is called to the possibility that implementation of this specification may require the use of an invention covered by patent rights. By distribution of this specification, no position is taken with respect to the validity of a claim or claims or of any patent rights in connection therewith. This specification is considered SNIA Architecture and is covered -
ESA IP Cores 2 Introductionintroduction
ESAESA IPIP CoresCores PresentPresent statusstatus andand futurefuture plansplans KostasKostas MarinisMarinis TECTEC--EDM,EDM, ESTEC/ESAESTEC/ESA [email protected]@esa.int AgendaAgenda IntroductionIntroduction HistoryHistory andand backgroundbackground ListList ofof availableavailable IPIP corescores OverviewOverview ofof ESAESA IPIP CoresCores serviceservice ASIC/ASIC/ SoCSoC developmentsdevelopments ((re)usingre)using ESAESA IPIP corescores SpaceSpace missionsmissions usingusing ESAESA IPIP CoresCores ESAESA activitiesactivities onon IPIP corescores andand SystemSystem--LevelLevel ModelingModeling ConclusionsConclusions May 12, 2010 ESA IP Cores 2 IntroductionIntroduction What is an Intellectual Property (IP) core? A reusable design in HDL format (VHDL, Verilog, etc). ESA IP cores are “soft cores”, i.e. technology independent. Can be synthesized and targeted to any ASIC or FPGA technology. Why an IP Cores service by ESA? Promote and consolidate the use of functions, protocols and/or architectures for space use (e.g. SpaceWire, CAN, TMTC, etc) Counteract obsolescence and discontinuity of existing space standard ASICs Facilitate the reuse of results from TRP/GSTP programs, thus reducing costs of large IC developments (e.g. Systems-on-Chip) Centralize IP users’ feedback to improve quality of existing IPs and identify future needs Not a profit-oriented service May 12, 2010 ESA IP Cores 3 HistoryHistory andand backgroundbackground ESA IP cores service originates from internal & external developments