Vacuum Tubes
3 Handouts Lab 3 (2) Lecture notes
Linear without feedback Characteristics independent of temperature Wider dynamic range
• Vacuum Tubes, BJT or FET? • • Circuit Analysis: Amplifier & Feedback NY Times – “Guitar heroes favor vacuum tube amplifiers in • Classic BJT Circuits their instruments” • Arduino Intro – “Many recording engineers tend to use vacuum‐ tube equipment in their studios” Acknowledgements: Yanni Coroneos, Henry Love – “Some listeners pay thousands of dollars for high‐ Neamen, Donald: Microelectronics Circuit Analysis and Design, 3rd Edition end tube‐based stereo systems and CD players.”
6.101 Spring 2020 Lecture 5 1 6.101 Spring 2020 Lecture 5 2
BJT or FET Transistor Configurations TRANSISTOR AMPLIFIER CONFIGURATIONS
high input impedance, for voltage gain = 1 ; use low input impedance for low impedance general amplification +15V in amplifier output +15V +15V • Depends on application stage. sources, for high frequency response.
R R • Amplifiers R L R R L
BJT 2 2 2 + – BJT +
+ + + + + • are more linear that MOSFET, better fidelity (low harmonic + + + + +
R + 1 VOUT VOUT V Vin R 1 RE V V in R OUT in R1 distortion) E RE - - • can drive low impedances at higher power - - - -
• lower noise with low source impedance [a] Common Emitter Amplifier [b] Common Collector [Emitter Follower] Amplifier [c] Common Base Amplifier • Operate at < 2 V – MOSFET • high input impedance FET • Voltage controlled device => lower power
Common gate Common drain [Source follower] Common source
6.101 Spring 2020 Lecture 5 3 6.101 Spring 2020 Lecture 5 4 Miller Effect* – Common Emitter Input Impedance and Frequency Response
log scale (dB) V
A
R 0 V -3dB V1 C 2 slope = -6 dB / octave slope = -20 dB / decade
log f 1 f or f HI -3dB V jX j C 1 A 2 C v V R jX 1 j RC 1 1 C R j C 1 Degrees Av PHASE LAG sRC 1 0o C C [1 g (R R )] -45o M m C L 1 High frequency cutoff f -90o hi 2 RC
* Agarwal & Lang Foundations of Analog & Digital Electronics Circuits p 861 log f f or f HI -3dB
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Low Frequency Hybrid‐ Equation Chart Cascode Amplifer
• Two transistor amplifer: common emitter (CE) with a common base No Miller effect • Miller effect avoided by setting gain of CE stage Miller effect low. • CE stage provides high input impedance • Common base (CB) provides gain without Miller effect; base is grounded. High gain applications Unity gain, low High gain, better high Moderate input resistance output resistance frequency response High output resistance High input resist. Low input resistance Neamen p445
6.101 Spring 2020 Lecture 5 7 6.101 Spring 2020 Lecture 5 8 Objectives Three Stage –Push Pull Amplifier
• Perform an analysis into the behavior of a complicated circuit using basic properties of BJT’s (npn, pnp)
• Calculate gain of the system
• Discuss crossover distortion issues in push‐pull amplifiers
• Understand feedback
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Three Stage Amplifer –Block Diagram Q3‐Q4 Push Pull
• Q3: Emitter Follower (positve cycle) • Q4: Emitter Follower (negative cycle) • Overall gain ~1
• Q3 & Q4 Vbe are always one diode drop
• Crossover distortion about zero crossing
Feedback
6.101 Spring 2020 Lecture 5 11 6.101 Spring 2020 Lecture 5 12 Crossover Distortion Q2 –High Gain Stage
• Since last stage is an emitter follower, node n4 should be biased near zero volts.
• Q2 is a common emitter configuration with a pnp transistor.
• For pnp configuration, reverse the polarity of the voltages from a npn.
0g mr
ICQ gm VTH 26mv VTH
ICQ o RL gm 38* ICQ Av gm RL VTH o 15 g I A 570 m CQ 104 v 6.101 Spring 2020 Lecture 5 13 6.101 Spring 2020 Lecture 5 14
Q1 Analysis Biasing
6.101 Spring 2020 Lecture 5 15 6.101 Spring 2020 Lecture 5 16 Biasing –Quiescent Point Biasing –Quiescent Point
• v(n5) = Vout = 0 Determine the quiescent point 0.6 ma v(n1) - v(n3) = 0.6 • For BJT + v(n2) = 15 – 0.6 0.6 – assume Vbe = 0.6V - – assume base current neglible -12.4 • Apply KVL, KCL -13.0
if
KCL : it 0.6 ir v(n3) (15) 0 v(n3) it 0.6 1k 10k
v(n3) 13 or v(n1) 12.4v
v(n1) 12.3v for 30k / 3k
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Key Observations Classic BJT Circuits/components
• Darlington Pair • Crossover distortion caused by base • Matched transistors emitter voltage. • Short circuit protection • Feedback results in overall gain • Currrent mirror independent of β • Schottky diode • Biasing not precise, highly dependent • Baker Clamp on supply voltage (poor supply voltage rejection) • Vbe multiplier
6.101 Spring 2020 Lecture 5 19 6.101 Spring 2020 Lecture 5 20 MPSA13 Darlington Matched Pair
• Close electrical and thermal characteristics
• Supermatched pairs also available
• Used in differental amplifiers and measurement equipment
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Super Matched Pair 7805 Regulator Short Circuit Protection
• When voltage across R16 exceeds ~0.6 volt, Q14 diverts away base drive to Q15.
• Characteristics approach • Note Darlington pair theoretical transistor Q15, Q16
• Vbe matched to 50 µv
• hFE matched to 2%
6.101 Spring 2020 Lecture 5 23 6.101 Spring 2020 Lecture 5 24 356 Op‐Amp Short Circuit Protection Current Mirror
6.101 Spring 2020 Lecture 5 25 6.101 Spring 2020 Lecture 5 26
Schottky* Diode Baker* Clamps • Reduces turn off time by limiting saturation • Schottky diode formed with metal‐semiconductor junction vs pn junction • Baker Camp with diodes • Lower forward voltage drop: 0.15‐0.45 vs 0.6‐0.7 for pn junction
• Almost zero reverse recovery times. • Baker clamp with • Used in 74LS series logic Low‐power Schottky diode Schottky
* Walter Schottky *named by Richard Baker (1956); drawings from http://en.wikipedia.org/wiki/Baker_clamp
6.101 Spring 2020 Lecture 5 27 6.101 Spring 2020 Lecture 5 28 Vbe Multipler Arduino, Teensyduino • Low cost open source microcontroller and development system
• Many variants: Uno, Nano, Pro, Teensy ….
• Arduino Nano – 16MHz ATmega328, 32KB flash, 1KB EEPROM, 2KB SRAM (R1 R2 ) – 22 I/O ports: analog/digital V V – 5V (19ma) operation R BE 2 • Teensy 3.2 – 72Mhz MK20DX256, 256KB flash, 2KB EEPROM, 16KB SRAM – 34 I/O ports , 21 analog input (2 16bit ADC), 1 12bit DAC
• Ideal for prototyping, process controller or state machines
• Maybe useful for final project but only in a secondary manner: – data display, control logic
• Originals vs clones
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Teensy 3.2 ‐ Nano Arduino Nano
SPI: +5, GND, MISO, MOSI, SCK Teensy 3.2 Nano J2 – pin 1 J2 – pin 4 7-12 VDC in 5V in or out Processor: MK20DX256 ATmega328 Clock Speed: 72 MHz 16 Mhz reset Flash Memory: 256 KB 1 KB ATMEGA 328P CPU
RAM: 64 KB 2KB J2 – pin 14 3.3V @20ma Operating Voltage 3.3 V3.3 V
GPIO 34 14 J1 – pin 1 Analog Inputs 21 8 Mini USB: DAC 1 0 programming & +5V LEDs: power PWM 12 6 Power, LED, Rx, Tx UART 3 external
6.101 Spring 2020 Lecture 5 31 6.101 Spring 2020 Lecture 5 32 Arduino Nano Nano Multifunction I/O Pins Partial List
J1 – pin 1 Pin Function 1 Function 2 Function 3 D13 digital I/O SCK (SPI) Built‐in LED D12 digital I/O MISO
CH340 D11 digital I/O MOSI FTDI Clone 3.3V regulator D3,5,6,9,10,11 digital I/O PWM D3 digital I/O Interrupt 1 LM1115 J2 – pin 1 5V D2 digital I/O Interrupt 0 D1 digital I/O Tx D0 digital I/O Rx A0-A7 10-bit analog D3, D5, D6, D9, D10, and D11 provide inputs referenced to 5V 8-bit PWM output with analogWrite() A5 analog in SCL or AREF using the analogReference() D10 (SS), D11 (MOSI), D12 (MISO), A4 analog in SDA function; D13 (SCK) same as SPI header
A4 (SDA) and A5 (SCL) support I2C
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Serial Interface Teensy 3.2 L ground AGND Vin (93.7-5.5) Keep analog and digital • Arduino Nano clone uses CH340G; need to install serial port AGND grounds separate Micro USB: 3.3V 100ma driver. programming & +5V pin 23 power LP38691 TI LDO 3.3V MK20DX256 • Drivers on http://web.mit.edu/6.101/www/s2020/drivers/ ARM Cortex-M4 have been tested. pin 13 – CH341SER_MAC: OSX Mojave
serial port: cu.wchusbserial1410 MKL02Z32VFG4 Kinetis L Peripheral IO – CH34x_Install_Windows_v3_4.zip: Windows DAC, ADC serial port: COM3… COMx
– CH340_LINUX.zip: Ubuntu 14.04 // driver install serial port: /dev/ttyUSB0 make ground sudo make load pin 0
pin 12 6.101 Spring 2020 Lecture 5 35 6.101 Spring 2020 Lecture 5 36 Teensy 3.2 Bottom
Teensy 3.2 Top
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Teensy ‐ Lab 3 part 2 Teensy 3.2
Solder headers to Teensy Load sketch & verify display Attached spacer to TFT display Circuit will be used in PPG and ECG Wire circuit labs
6.101 Spring 2020 Lecture 5 39 6.101 Spring 2020 Lecture 5 40 Laser Cutting Process (it’s just as cool as it sounds) • high‐power laser beam optically guided to machine head
• head moves in 2D (x, y)
source: Universal Laser Systems • beam fired in rapid pulses while head moves
• material is ablated or vaporized
• fumes extracted
source: cutmaps.com source: n-e-r-v-o-u-s.com
Design UCP (Universal Control Panel)
• user generates 2D design • vector vs. bitmap • user sets power, speed for each color in file • machine traces vectors – moves in steady line – line width < 0.001 inch – “hairline” • or rasters bitmaps – sweeps back and forth to fill in source: wikipedia Laser “Printing” Laser Cuting – CorelDraw
Pink lines are board outline Black lines will be rastered
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Laser Cutting Lab (Optional)
• Mon 2/25 4:15 and 5:15p EDS • Laser Cut base • Mount RLC‐BJT/MOSFET testor
6.101 Spring 2020 Lecture 5 47