0-9, and Symbols A

Total Page:16

File Type:pdf, Size:1020Kb

0-9, and Symbols A Index Note : Online information is listed by print page number and a period followed by “e” with online page number (54.e1). Page references preceded by a single letter with hyphen refer to appendices. Page references followed by “f ,” “ t ,” and “ b ” refer to fi gures, tables, and boxes, respectively. 0-9, and symbols ID (ASID) , 436 VAX fl oating-point formats , D-29 inadequate , 497.e5–497.e6 ALU control , 249–251 . See also 1-bit ALU , A-26–A-29 . See also shared , 507–508 Arithmetic logic unit (ALU) Arithmetic logic unit (ALU) single physical , 507 , 507–508 bits , 250–251 , 250 f adder , A-27 f virtual , 436 logic , C-6–C-7 CarryOut , A-28 Address translation mapping to gates , C-4–C-7 for most signifi cant bit , A-33 f for ARM cortex-A53 , 458 f truth tables , C-5f , C-5 f illustrated , A-29f defi ned , 418–419 ALU control block , 253 logical unit for AND/OR , A-27 f fast , 428–430 defi ned , C-4–C-6 performing AND, OR, and addition , for Intel core i7 , 458 f generating ALU control bits , C-6 f A-31 , A-33 f TLB for , 428–430 ALUOp , 250 , C-6 b –C-7 b 64-bit ALU , A-29–A-31 . See also Address-control lines , C-26f bits , 250 , 251 Arithmetic logic unit (ALU) Addresses control signal , 253 from 63 copies of 1-bit ALU , A-34 f b a s e , 6 9 Amazon Web Services (AWS) , 415b with 64 1-bit ALUs , A-30f byte , 70 AMD Opteron X4 (Barcelona) , 533 , 534f defi ning in Verilog , A-36–A-37 defi ned , 68 AMD64 , 148 , 148 , 215 , 173.e5 illustrated , A-35f m e m o r y , 7 8 b Amdahl’s law , 391 , 493–494 ripple carry adder , A-29 virtual , 418–419 , 438 , 439 b corollary , 49 7090/7094 hardware , 248.e6 Addressing defi ned , 49 base , 118 f fallacy , 546 A in branches , 115–117 and (and) , 64f displacement , 118 AND gates , A-12–A-13 , C-7 Absolute references , 127 immediate , 118f AND operation , 90 , A-6 Abstractions PC-relative , 115–116 , 118f andi (and immediate) , 64f hardware/soft ware interface , 22 register , 118 f Annual failure rate (AFR) , 408–409 principle , 22 RISC-V modes , 117–118 versus MTTF of disks , 408b –409 b to simplify design , 11 x86 modes , 151 Antidependence , 325 Accumulator architectures , 173.e1–173.e2 Addressing modes Antifuse , A-77 A c r o n y m s , 9 desktop architectures , D-5–D-6 Apple computer , 54.e6 Active matrix , 18 Advanced Vector Extensions (AVX) , 216 , Apple iPad 2 A1395 , 20f add (add) , 64 f 217 logic board of , 20 f addi (add immediate) , 64f , 72 , 84 AGP , B-9–B-10 processor integrated circuit of , 21 f Addition , 172–175 . See also Arithmetic Algol-60 , 173.e6 Application binary interface (ABI) , 22 binary , 172 b –173 b Aliasing , 434 Application programming interfaces fl oating-point , 196–199 , 204 Alignment restriction , 70 (APIs) operands , 173 , 173 All-pairs N-body algorithm , B-65 defi ned , B-4 signifi cands , 195b –196 b Alpha architecture graphics , B-14 speed , 175 b bit count instructions , D-29 Architectural registers , 335–336 Address interleaving , 370–371 fl oating-point instructions , D-28–D-29 Arithmetic , 170 Address select logic , C-24 , C-25 f instructions , D-27–D-29 addition , 172–175 Address space , 418 , 421b no divide , D-28 addition and subtraction , 172–175 extending , 467b PAL code , D-28 division , 181–189 fl at , 467 unaligned load-store , D-28 fallacies and pitfalls , 220–223 I-1 I-2 Index Arithmetic (Continued) microcode , C-30 Biased notation , 81 , 193 fl oating-point , 189–214 number acceptance , 126 Binary numbers , 82 historical perspective , 225 object fi le , 126 ASCII versus, 109 b multiplication , 175–181 A s s e m b l y l a n g u a g e , 1 5f conversion to decimal numbers , 77 b parallelism and , 214–215 defi ned , 14 , 125 defi ned , 74 Streaming SIMD Extensions and fl oating-point , 205f Bisection bandwidth , 525 advanced vector extensions in illustrated , 15 f Bit maps x86 , 215–216 programs , 125 defi ned , 18 subtraction , 172–175 RISC-V , 64 f , 8 5 b –86 b g o a l , 1 8 subword parallelism , 214–215 translating into machine language , storing , 18 subword parallelism and matrix 85 b –86 b Bit-Interleaved Parity (RAID 3) , 481.e4 multiply , 216–220 Asserted signals , 240 , A-4 Bits Arithmetic instructions . See also Associativity ALUOp , 250 , 251 Instructions in caches , 395 b –396 b defi ned , 14 desktop RISC , D-11f , D-11 f degree, increasing , 394–396 , 442 dirty , 428 b embedded RISC , D-13 f increasing , 399–400 guard , 212 logical , 241–242 set, tag size versus, 399 b –400 b patterns , 212b –213 b operands , 67–74 Atomic compare and swap , 123 b reference , 426b Arithmetic intensity , 531–532 Atomic exchange , 122 rounding , 212 Arithmetic logic unit (ALU) . See also Atomic fetch-and-increment , 123b sign , 75 ALU control ; Control units Atomic memory operation , B-21 state , C-8–C-10 1-bit , A-26–A-29 Attribute interpolation , B-43–B-44 sticky , 212 64-bit , A-29–A-31 auipc’s eff ect , 156 valid , 374–376 before forwarding , 297f Automobiles, computer application in , 4 Blocking assignment , A-24 branch datapath , 244–245 Average memory access time (AMAT) , Blocking factor , 404 hardware , 174 392 Block-Interleaved Parity (RAID 4) , 481. memory-reference instruction calculating , 392 b e4–481.e5 use , 235 Blocks for register values , 242 B combinational , A-4–A-5 R-format operations , 243 f defi ned , 365–366 signed-immediate input , 300 Bandwidth , 29–30 fi nding , 442–443 ARM Cortex-A53 , 234 , 332–340 bisection , 525 fl exible placement , 392–396 address translation for , 458f external to DRAM , 388 least recently used (LRU) , 399 caches in , 459 f memory , 388 locating in cache , 397–399 data cache miss rates for , 460f network , 523–524 miss rate and , 381f memory hierarchies of , 457 Barrier synchronization , B-18 multiword, mapping addresses to , performance of , 460–462 defi ned , B-20 380 b –381 b specifi cation , 333 f for thread communication , B-34 placement locations , 441 TLB hardware for , 458 f Base addressing , 69 , 118 placement strategies , 394 ARPAnet , 54.e9 Base registers , 69 replacement selection , 399 Arrays , 405 f Basic block , 95 b replacement strategies , 444 logic elements , A-18–A-20 Benchmarks , 528–538 spatial locality exploitation , 381 multiple dimension , 210 defi ned , 46 state , A-4–A-5 pointers versus, 141–144 Linpack , 528 , 248.e2–248dir.e3 , valid data , 374–376 procedures for setting to zero , 141 f 248.e3 Bonding , 28 ASCII multiprocessor , 528–538 Boolean algebra , A-6–A-7 binary numbers versus, 109 b NAS parallel , 530 Bounds check shortcut , 96 character representation , 108 f parallel , 529 f Branch datapath defi ned , 108–109 PARSEC suite , 530 ALU , 244–245 symbols , 111 SPEC CPU , 46–48 operations , 244–245 Assemblers , 125–127 SPEC power , 48–49 Branch if Equal (beq) , A-32 defi ned , 14 SPECrate , 528 Branch if greater than or equal, unsigned function , 125–127 Stream , 538 b (bgeu) , 95–96 Index I-3 Branch if less than (blt) instruction , compiling assignment with registers , set-associative cache , 395 95–96 67 b –68 b steps , 383 Branch if less than, unsigned (bltu) , compiling while loops in , 94 b –95 b in write-through cache , 383 95–96 sort algorithms , 141 f Cache performance , 388–408 Branch instructions translation hierarchy , 124 f calculating , 390 b –391 b pipeline impact , 306f translation to RISC-V assembly hit time and , 391–392 Branch not taken language , 65 impact on processor performance , assumption , 305–306 variables , 104 b 390–391 defi ned , 244 C.mmp , 577.e3–577.e4 Cache-aware instructions , 470 Branch prediction C + + language , 173.e7 , 150.e26 Caches , 373–388 . See also Blocks b u ff ers , 308 Cache blocking and matrix multiply , accessing , 376–382 as control hazard solution , 272 463–466 in ARM cortex-A53 , 459 f defi ned , 271–272 Cache coherence , 452–456 associativity in , 395b –396 b dynamic , 272 , 308–312 coherence , 452 bits in , 380 b static , 322 consistency , 452 bits needed for , 380 Branch predictors enforcement schemes , 454 contents illustration , 377f accuracy , 310 implementation techniques , 482. defi ned , 19–22 , 373–374 correlation , 310–311 e10–482.e11 direct-mapped , 374 , 375f , 380 , 392 information from , 310–311 migration , 454 empty , 376 tournament , 311–312 problem , 452 , 453 f , 456 b FSM for controlling , 447–452 Branch table , 97–98 protocol example , 482.e11–482.e15 fully associative , 393 Branch taken protocols , 454 GPU , B-38 cost reduction , 306–307 replication , 454 inconsistent , 383 defi ned , 244 snooping protocol , 454–456 index , 378 Branch target snoopy , 482.e16 in Intel Core i7 , 459 f addresses , 244 state diagram , 482.e15 f Intrinsity FastMATH example , b u ff ers , 310 Cache coherency protocol , 482.e11–482. 385–387 B r a n c h e s . See also Conditional e15 locating blocks in , 397–399 branches fi nite-state transition diagram , 482.e14 f locations , 375 f addressing in , 115–117 functioning , 482.e13 f multilevel , 388 , 400–403 compiler creation , 93–94 mechanism , 482.e13f nonblocking , 458 decision, moving up , 306–307 state diagram , 482.e15 f physically addressed , 434–435 delayed , 272 , 306–308 states , 482.e12 physically indexed , 434b –435 b ending , 95b write-back cache , 482.e14 f physically tagged , 434b –435 b execution in ID stage , 307 Cache controllers , 457 primary , 400 , 407–408 pipelined , 308b coherent cache implementation secondary , 400 , 407–408 target address , 306–307 techniques , 482.e10–482.e11 set-associative , 393 Branch-on-zero instruction , 258–259 implementing , 482.e1 simulating , 466 b Bubble Sort , 140 snoopy cache coherence , 482.e16 size
Recommended publications
  • ARM Против Intel: Успешная Стратегия Для RISC Или Выгода Для CISC?
    ARM против INTEL: успешная стратегия для RISC или выгода для CISC? Брайан Дайперт (BRIAN DIPERT), старший технический редактор, EDN Корпорация ARM и владельцы лицензии на ее продукты намерены расши- рить присутствие на рынке и занять ниши, традиционно занимаемые процессорами Intel x86. В ответ Intel решила потеснить корпорацию ARM в сегменте рынка электронных устройств. корпорации ARM и Intel окончатель- пустили при переходе с ARM11. ядро повышенную защиту. второй тип про- но вступили в открытую конкуренцию. Cortex-A8 обеспечивает поддержку цессоров ориентирован больше на первая активно продвигает технологию попарно запускаемых суперскалярных беспроводную передачу данных и под- RISC, в то время как Intel делает упор инструкций и имеет более глубокий держивает большой набор протоколов на процессоры с набором команд CISC. конвейер в каждом ядре, содержащий передачи данных и голоса. еще три года назад, когда Intel представ- 13 уровней вместо 8. Блок вычислений с ляла свой первый процессор семейства плавающей запятой в отличие от ARM11 NVIDIA — ставка на мультимеДиа Atom, компания ясно дала понять, что является обязательным. кроме того, компания Nvidia стала обладатель- нацелена не только на настольные ком- для Cortex-A8 требуется 64-разрядный ницей лицензии на ARM после несколь- пьютеры среднего уровня и ноутбуки, SIMD-вычислитель Neon. ких приобретений: компании MediaQ но и на портативные устройства, в кото- в Cortex-A9 разработчик сам решает, в 2003 г. и PortalPlayer в 2006 г. первая рых исторически пальма первенства реализовывать ли Neon и блок опера- снк Nvidia, Tegra, содержала процессор принадлежит ARM. в ответ ARM пред- ций с плавающей запятой. оба они не ARM11. она не получила широкого при- ставила ядро Cortex-A15, область при- являются обязательными.
    [Show full text]
  • R&D and the Market for Acquisitions
    R&D and the Market for Acquisitions Gordon PhillipsW and Alexei Zhdanov** COMMENTS WELCOME: First version January 10, 2010. This Version: February 20, 2011 We provide a new theory and empirical tests showing how an active acquisition market posi- tively aects rm incentives to innovate and conduct R&D. Our model shows how the incentives of small rms to conduct R&D in order to innovate increase with competition, demand and the probability that they are taken over. In contrast, we show that large rms optimally may decide to purchase smaller innovative rms and conduct less R&D themselves. Empirically, we document that the R&D of small rms responds more than the R&D of larger rms to demand shocks and the probability of being an acquisition target. The results also show that rm R&D increases with product-market competition and with industry acquisition liquidity and that these eects are stronger for smaller rms. WUniversity of Maryland and NBER, **University of Lausanne and Swiss FinanceInstitute. Phillipscanbereachedat [email protected], Zhdanov can be reached at [email protected]. We would like to thank Denis Gromb, Urs Peyer and seminar participants at Insead for helpful comments and discussion. R&D and the Market for Acquisitions ABSTRACT We provide a new theory and empirical tests showing how an active acquisition market posi- tively aects rm incentives to innovate and conduct R&D. Our model shows how the incentives of small rms to conduct R&D in order to innovate increase with competition, demand and the probability that they are taken over.
    [Show full text]
  • A Study of the Soc and Smartphone Industries
    Vertical Structure and Innovation: A Study of the SoC and Smartphone Industries Chenyu Yang∗ Department of Economics, University of Maryland, College Park December 19, 2019 Abstract This article studies how vertical integration and upstream R&D subsidy affect innovation and welfare in vertically separated industries. I formulate a dynamic structural model of a dominant upstream firm and oligopolistic downstream firms that invest in complementary innovations. I estimate the model using data on the System-on-Chip (SoC) and smartphone industries. The results suggest that a vertical merger can increase innovation and welfare, mainly driven by the investment coordination of the merged firms. I also find that subsidizing the upstream innovation increases overall private investment, innovation and welfare. 1 Introduction In vertical industries, upstream and downstream innovations are often complementary. Upstream firms upgrade the core technology essential to performance enhancement, and downstream firms combine the technology with innovative designs in new consumer products. Examples of com- plementary innovations include traction batteries (upstream) and electric vehicles (downstream), CPUs (upstream) and personal computers (downstream) and System-on-Chips (SoCs, upstream) ∗Department of Economics, University of Maryland, College Park; [email protected]. I would like to acknowl- edge the generous financial support provided by Rackham Graduate School and Michigan Institute for Teaching and Research in Economics (MITRE) at the University of Michigan. I am grateful for the guidance and support from my advisers Jeremy Fox, Daniel Ackerberg, Ying Fan and Srinivasaraghavan Sriram. I benefited greatly from the comments of many seminar participants, two anonymous referees and the editor Marc Rysman. All errors are mine.
    [Show full text]
  • Dr. Ishaq Unwala 11400 Rockwell Pl Phone #: (512) 567 - 4467 Austin, TX 78726 [email protected]
    Dr. Ishaq Unwala 11400 Rockwell Pl Phone #: (512) 567 - 4467 Austin, TX 78726 [email protected] WORK EXPERIENCE University of Houston Clear Lake, Houston, TX Aug '14 - present Assistant Professor of Computer Engineering Teaching graduate level classes in Computer Engineering. Areas of interest Design, Test and Verification of digital designs. Oracle Corporation, Austin, TX Senior Hardware Engineer Sep '10 - Jan '14 Recently employed at Oracle Corporation in Computer and Microelectronic Technology (CMT) division, formerly Sun Microsystems. The CMT division designs, develops and implements complete SPARC systems, including SPARC Core, SOC for SPARC Core, and Solaris Operating System. I was responsible for functional verification of the SPARC Core. I have worked on two SPARC processor cores, Tahoe (S4) and Siete (S5). Functional verification includes many sub-tasks, including working with logic design team on design specification documents, Test Generation, Test Environment design and development, Functional Coverage specification and implementation, root causing Test failures, Formal verification, use and design of many other Design Tools. - Project : Siete (S5) CPU (2013-2014) Most recently I worked on design verification of the Load Store Unit for a new SPARC processor. I proposed, specified, and implemented a new test generator for testing of the Load Store unit (LSU) for the SPARC Core. The new test generator provided hundreds of tests that otherwise would have to be hand written. I wrote testing and coverage specification for LSU blocks. Design and verification work is still in progress. Siete is projected to tape-out in March 2015. - Project : Tahoe (S4) CPU (2010-2013) I specified, designed and implemented the unit test environment (UTE) for the Instruction Fetch Unit (IFU) design for Tahoe.
    [Show full text]
  • Apple Inc. This Article Is About the Technology Company
    Apple Inc. This article is about the technology company. For other companies named "Apple", see Apple (disambiguation). Apple Inc. Type Public Traded as NASDAQ: AAPL NASDAQ-100 Component S&P 500 Component Industry Computer hardware Computer software Consumer electronics Digital distribution Founded April 1, 1976 (incorporated January 3, 1977 as Apple Computer, Inc.) Founder(s) Steve Jobs Steve Wozniak Ronald Wayne[1] Headquarters Apple Campus, 1 Infinite Loop, Cupertino, California, U.S. Number of 357 retail stores(as of October 2011) locations Area served Worldwide Key people Tim Cook (CEO) Arthur Levinson (Chairman)[2] Sir Jonathan Ive (SVP, Industrial Design) Steve Jobs (Chairman, 1976-1985/2011; CEO, 1997– 2011) Products Products list[show] Services Services list[show] [3] Revenue US$ 108.249 billion (FY 2011) [3] Operating income US$ 33.790 billion (FY 2011) [3] Profit US$ 25.922 billion (FY 2011) [3] Total assets US$ 116.371 billion (FY 2011) [3] Total equity US$ 76.615 billion (FY 2011) Employees 60,400 (2011)[4] Subsidiaries Braeburn Capital FileMaker Inc. Anobit Website Apple.com Apple Inc. (NASDAQ: AAPL ; formerly Apple Computer, Inc.) is an American multinational corporation that designs and sellsconsumer electronics, computer software, and personal computers. The company's best-known hardware products are the Macintoshline of computers, the iPod, the iPhone and the iPad. Its software includes the Mac OS X operating system; the iTunes media browser; the iLife suite of multimedia and creativity software; the iWork suite of productivity software; Aperture, a professional photography package; Final Cut Studio, a suite of professional audio and film-industry software products; Logic Studio, a suite of music production tools; the Safari web browser; and iOS, a mobile operating system.
    [Show full text]
  • Of 48 in the UNITED STATES DISTRICT COURT for the EASTERN DISTRICT of TEXAS MARSHALL DIVISION Plaintiff, V. Defendant. Ci
    Case 2:17-cv-00207 Document 1 Filed 03/16/17 Page 1 of 48 PageID #: 1 IN THE UNITED STATES DISTRICT COURT FOR THE EASTERN DISTRICT OF TEXAS MARSHALL DIVISION SOVERAIN IP, LLC, Plaintiff, Civil Action No._________ v. JURY TRIAL DEMANDED APPLE, INC. Defendant. COMPLAINT FOR PATENT INFRINGEMENT Plaintiff Soverain IP, LLC (“Soverain” or “Plaintiff”), by and through its attorneys, brings this action and makes the following allegations of patent infringement relating to U.S. Patent Nos.: 7,191,447 (“the ‘447 patent”) 8,935,706 (“the ’706 patent”); 5,708,780 (“the ‘780 patent”); and 6,212,634 (“the ‘634 patent”) (collectively, the “patents-in-suit” or the “Soverain Patents”). Defendant Apple, Inc. (“Apple” or “Defendant”) infringes each of the patents-in-suit in violation of the patent laws of the United States of America, 35 U.S.C. § 1 et seq. INTRODUCTION 1. This case arises from Apple’s infringement of Soverain’s data extraction and network management patent portfolio. Soverain is the owner by assignment and exclusive licensee to twenty-four issued United States patents, multiple pending patent applications,1 and numerous foreign patent assets.2 2. The patents asserted in this case arose from the innovative work of Open Market, Inc. (“Open Market”), an innovative tech firm that in 1993 developed groundbreaking technologies for the then-nascent Internet. Open Market was founded at a time when conducting commercial transactions over the Internet was in its beginning stages. Previous uses of the Internet had largely been limited to academic research and military defense work. 1 See U.S.
    [Show full text]
  • Advanced Processing Techniques Using the Intrinsity(Tm
    TM WHITE PAPER the Faster processor company TM Advanced Processing Techniques Using the Intrinsity™ FastMATH™ Processor Originally Presented to the Embedded Processor Forum; May 1, 2002 Tim Olson, Senior Design Architect Note: All information contained in this document that relates to the FastMATH processor also applies to the FastMATH-LP™ processor. 1. Abstract The Intrinsity™ FastMATH™ processor combines a MIPS32™ core, a matrix/vector engine, and dual RapidIO™ interfaces for a 2 GHz adaptive signal processor™ product capable of up to 64 giga operations per second (GOPS) (peak) computing performance. (See Section 8 on page 7 for more information on performance.) It is an embedded microprocessor designed for areas such as adaptive signal processing, image analysis, and other fields that benefit from flexibility, speed, and an architecture optimized for mathematical computation. With its 4 × 4 matrix of process- ing elements, it can compete favorably with most custom hardware designs, but uses a standard software program- ming model. This enables field enhancements without having to change hardware. This document describes the architecture, what it can do, and techniques for using it effectively. Samples are available now. 2. Introduction The FastMATH processor is a fixed-point embedded processor that delivers application-specific integratec circuit (ASIC) level performance for real-time adaptive signal processing and other vector and matrix math intensive prob- lems. It combines multi-gigahertz clock speeds with native matrix data operations and high-speed I/O for efficient partitioning of complex problems across multiple units. With its clock speed, plus its strong architectural advantages, it delivers ASIC-level performance with the flexibility of a software design.
    [Show full text]
  • Iphone Es Una Línea De Teléfonos Inteligentes Diseñada Y Comercializada Por Apple Inc
    iPhone es una línea de teléfonos inteligentes diseñada y comercializada por Apple Inc. Ejecuta el sistema operativo móvil iOS antes conocido como "iPhone OS" hasta mediados de 2010. El iPhone dispone de una cámara de fotos de 8 megapíxeles y un reproductor de música (equivalente al del iPod) además de software para enviar y recibir mensajes de texto y mensajes de voz. También ofrece servicios de Internet como leer correo electrónico, cargar páginas web y conectividad por Wi-Fi. La primera generación de teléfonos eran GSM cuatribanda con la tecnología EDGE; la segunda generación ya incluía UMTS con HSDPA.;2la sexta generación ya incluía 4G LTE. Steve Jobs anunció el iPhone en 2007,3 tras varios rumores y especulaciones que circulaban desde hacía meses.4 El iPhone se introdujo inicialmente en los Estados Unidos el 29 de junio de 2007. Fue nombrado «Invento del año» por la revista Time en 2009.5 El 11 de julio de 2008 el iPhone 3G salió a la venta, estando disponible en 22 países6 y en 70 para finales de año. Esta versión soportaba la transmisión de datos por 3G a una velocidad más rápida y tecnología AGPS.2 Para el evento WWDC 2009 se presentó el iPhone 3GS (S de Speed, velocidad), presentando el mismo diseño que el 3G, pero con hardware mejorado. El iPhone 3GS es hasta dos veces más rápido que su predecesor cargando páginas web o ejecutando aplicaciones, saca partido del estándar OpenGL ES 2.0 para ofrecer mejores gráficos 3D, soporta HSDPA a 7,2 MB (también conocido como 3.5G), cuenta con una nueva cámara de 3 megapíxeles con enfoque automático y grabación de vídeo, control por voz, brújula y soporte integrado para el Nike+iPod.[cita requerida] El día 7 de junio de 2010 en la WWDC 2010 Apple presentó el iPhone 4, con un diseño renovado tanto estéticamente, abandonando su estética redondeada, como a nivel hardware.
    [Show full text]
  • 1 in the United States District Court for the Eastern
    Case 2:15-cv-01547 Document 1 Filed 09/24/15 Page 1 of 151 PageID #: 1 IN THE UNITED STATES DISTRICT COURT FOR THE EASTERN DISTRICT OF TEXAS MARSHALL DIVISION ST. LUKE TECHNOLOGIES, LLC , Plaintiff, Civil Action No._________ v. JURY TRIAL DEMANDED APPLE, INC., Defendant. COMPLAINT FOR PATENT INFRINGEMENT Plaintiff St. Luke Technologies, LLC (“St. Luke” or “Plaintiff”), by and through its attorneys, brings this action and makes the following allegations of patent infringement relating to U.S. Patent Nos. 8,316,237 (“the ‘237 patent”); 7,181,017 (“the ‘017 patent”); 7,869,591 (“the ‘591 patent”); 8,904,181 (“the ‘181 patent”); 7,587,368 (“the ‘368 patent”); 8,498,941 (“the ‘941 patent”; and 8,566,247 (“the ‘247 patent”) (collectively, the “patents-in-suit”). Defendant Apple, Inc. (“Apple” or “Defendant”) infringes the patents-in-suit in violation of the patent laws of the United States of America, 35 U.S.C. § 1 et seq. INTRODUCTION 1. In an effort to expand its product base and profit from the sale of infringing cloud computing encryption technologies and information record infrastructure technologies, Apple has unlawfully and without permission copied the technologies and inventions of Dr. Robert H. Nagel, David P. Felsher, and Steven M. Hoffberg. 2. Dr. Nagel, Mr. Felsher, and Mr. Hoffberg are the co-inventors of the ‘237, ‘017, ‘591, ‘181, and ‘247 patents (collectively, the “Secure Third-Party Communications Patents” or “STPC patents”). The STPC patents have been cited in over 550 United States patents and patent applications as prior art before the United States Patent and Trademark Office.
    [Show full text]
  • Intrinsity(Tm) Fastmath(Tm) Application to Computed Tomography
    TM WHITE PAPER the Faster processor company SM Intrinsity™ FastMATH™ Application to Computed Tomography Written by G. P. Yost, PhD 1. Introduction This document describes the science of computed tomography and the application of the Intrinsity FastMATH processor to this problem. The FastMATH processor is designed as a high-speed parallel-processing matrix engine, programmable in C or other high-level languages, and we will show that it is well-suited to tomography problems. We begin with a brief discussion of computerized tomography (CT, sometimes called CAT for computerized axial tomography) systems. For specificity, we concentrate on x-ray systems designed for scanning of airport baggage, but most of the same principles apply to medical x-ray tomography, positron emission tomography (PET), single-photon emission tomography (SPECT), and other systems. In its most sophisticated form, the system makes use of a colli- mated cone-beam x-ray source that emits pulsed x-rays at rapid intervals. A detector system configured in finite-sized elements lies in the beam on the opposite side of a conveyor belt upon which the scanned object (e.g., luggage) is being moved continuously. The source and detector co-rotate about the conveyor belt as it moves so that the luggage is scanned from multiple angles. The detector elements record the line integral of the absorptivity on each exposure. By use of the Fourier slice theorem, the x-ray absorption of each volume element can be reconstructed from a com- plete set of these line integrals. The space resolution will depend on a number of factors, including the number of scans per unit angle, the angular range covered, and several others.
    [Show full text]
  • Sisteminės Programos
    Kompiuterių diagnostika Šiuolaikiniuose mobiliuose kompiuteriuose naudojamos vienlustės sistemos yra sudarytos iš ARM Cortex-A branduolių ir papildomos aparatūros. Pagrindiniai tokių SoC gamintojai yra Qualcomm, Samsung, Apple, NVIDIA. Kinijos gamintojai, kurių SoC dažniausiai naudojami kiniškų brandų telefonuose ir planšetėse: MediaTek, Allwinner, Rockchip, Spreadtrum. 2 . Hummingbird SoC naudoja patobulintą Cortex-A8 banduolį ir PowerVR SGX540 GPU branduolį. 1Ghz. Išleistas 2010 metais. Exynos 4 SoC: 1.4-1.6 GHz Quad-core. ARM Cortex-A9 architektūra. Gamintas 2011-2012 metais. Exynos 5 Dual SoC: 1.7 GHz du ARM Cortex-A15 architektūros branduoliai. Įvairios modifikacijos gaminamos nuo 2012 metų iki dabar. Exynos 5 Octa naudoja ARM sukurtą big.LITTLE konfigūraciją, t.y. turi keturis Cortex-A15 ir keturis Cortex- A7 branduolius. Dažnis 1.2-2.1 Ghz. Exynos 5 Hexa turi du Cortex-A15 ir keturis Cortex-A7 branduolius. Exynos 7 Octa. Cortex-A57+Cortex-A53 (big.LITTLE konfigūracija). 1.5-2.1 Ghz 3 . 2010 metais Apple nusipirko ARM SoC gamintoją Intrinsity ir tapo ARM architektūros licencijos savininke bei pradėjo pati projektuoti savo vienlustes sistemas. A4 SoC (naudojamas iPhone 4 ir iPad 1) yra analogiškas Samsung Hummingbird, tik naudoja PowerVR SGX 535 GPU. 1Ghz. A5 SoC (naudojamas iPad 2 ir būsimajame iPhone 5): 2x Cortex A9, PowerVR SGX 543MP2 GPU. A6 ir A6X: Naudojamas iPhone5 ir iPad4. Apple projektuotas, iki 1,4 GHz. PowerVR SGX 543MP3 ir SGX 554MP4 GPU. Gamyklos: Samsung. A7: pirmasis Apple 64 bitų ARMv8 architektūros procesorius. Naudojamas iPhone 5S ir iPad Air. Gaminamas 2013-2014 metais. A8: naudojamas iPhone 6 ir iPhone 6 Plus, 1.4 Ghz, dual core.
    [Show full text]
  • Ipad Seminar Report
    iPAD Seminar Report Submitted in partial fulfilment of the requirements for the award of the degree of Bachelor of Technology in Computer Science Engineering of Cochin University Of Science And Technology by ABHISHEK RANJAN (12080002) DIVISION OF COMPUTER SCIENCE SCHOOL OF ENGINEERING COCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGY KOCHI-682022 AUGUST 2010 Division of Computer Engineering School of Engineering Cochin University of Science & Technology Kochi-682022 CERTIFICATE Certified that this is a bonafide record of the seminar work titled IPAD Done by ABHISHEK RANJAN of VII semester Computer Science & Engineering in the year 2010 in partial fulfillment of the requirements for the award of Degree of Bachelor of Technology in Computer Science & Engineering of Cochin University of Science & Technology Dr.David Peter S Ms. SHEKHA CHENTHARA Head of the Division Seminar Guide ACKNOWLEDGEMENT I thank GOD almighty for guiding me throughout the seminar. I would like to thank all those who have contributed to the completion of the seminar and helped me with valuable suggestions for improvement. I am extremely grateful to Dr. David Peter, Head Of Division, Division of Computer Science, for providing me with best facilities and atmosphere for the creative work guidance and encouragement. I would like to thank my course coordinator Mr.Sudheep Elayidom and Seminar guide Ms. Shekha chenthara , Lecturer, Division of Computer Science, for all help and support extend to me. I thank all Staff members of my college and friends for extending their cooperation during my seminar. Above all I would like to thank my parents without whose blessings, I would not have been able to accomplish my goal.
    [Show full text]