Xcell Journal Issue 46, Summer 2003

SU 6 UMR20 CL ORA XILINX, INC. XCELL JOURNAL ISSUE 46, SUMMER 2003

Issue 46 Summer 2003 XcellXcelljournaljournal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS

LowLow CostCost SolutionsSolutions forfor HighHigh PerformancePerformance ResultsResults

NEW PRODUCTS Spartan-3 FPGAs Open New Markets and Applications RocketPHY Delivers 10 Gbps SONET Performance in CMOS

SOFTWARE ISEISE 5.2i5.2i SupportsSupports Spartan-3 FPGAs Now Precision SynthesisSynthesis ToolTool forfor Next-Generation Designs

APPLICATIONS Scaleable SPI-4.2 “Lite”“Lite” SolutionSolution forfor Spartan-3 FPGAs Software-Compiled System Design Methodology

TECHNOLOGY Adaptive I/O Solution Accelerates Serial Design Second-Generation XCITE Lowers PCBPCB CostsCosts

COVER STORY

Spartan-3 FPGAs on 90 nm Technology R Will Change the Way You Design Logic SEE THE NEXT NEXT BIG THING IN IBM POWERPC SOLUTIONS. Get the product differentiation edge you need with IBM. Discover how to speed your designs with the powerful combination of Xilinx FPGA solutions and IBM PowerPC processor cores. Stay ahead of your competition with IBM Microelectronics’ leading-edge technology, design expertise and process manufacturing excellence. High performance with flexibility. IBM PowerPC microprocessors, embedded processors and cores deliver cutting-edge performance, scalability and power efficiency. Real Support. With integrated product roadmaps, PowerPC licensing options and a network of distributors offering PowerPC products, IBM is the logical PowerPC choice. Visit www.ibm.com/powerpc/xcell

IBM Microelectronics

©International Business Machines Corporation, 2003. All rights reserved. All other products are trademarks or registered trademarks of their respective companies. LETTER FROM THE EDITOR Welcome to Our Programmable World

alph Waldo Emerson said it best: Do not go where the path may lead. Go instead where there R is no path and leave a trail. EDITOR IN CHIEF Carlis Collins Here at Xilinx, we do not follow the trends of business and technology – we set them. [email protected] 408-879-4519 Take, for example, our new family of Spartan™-3 Platform FPGAs – the first reprogrammable MANAGING EDITOR Tom Durkin [email protected] logic devices to be manufactured with the state-of-the-art 90 nm process technology. Because 90 nm 530-271-0899 device geometries enable more transistors in a smaller area, Xilinx has reduced die size with this ASSOCIATE EDITOR Jack Shandle new generation of Platform FPGAs by as much as 80 percent – and increased density to as many COPY EDITOR Charmaine Cooper Hussain as 5 million system gates with as many as 1,200 user I/Os. Perhaps most important of all, XCELL ONLINE EDITOR Tom Pyles Spartan-3 FPGAs are priced to replace ASICs in high-volume production. Now the FPGA you [email protected] 720-652-3883 use to prototype your design can be the FPGA you use in the manufacture of your design.

CONTRIBUTING EDITORS Jane Middleton Peter Bergsman We are also pleased to announce in this edition of XJ the RocketPHY family of 10 Gbps CMOS

ADVERTISING SALES Dan Teie Physical Layer (PHY) transceivers. Designed on a standard 0.15 µm CMOS process, RocketPHY 1-800-493-5551 devices are the first Xilinx family of Physical Layer OC-192 SONET-compliant transceivers ART DIRECTOR Scott Blair optimized for a wide range of 10 Gbps optical interconnect applications. This technology is also used in our new Virtex-II Pro™ X FPGAs. Xcell journal Many of you may be reading Xcell Journal for the first time at Programmable World 2003. Welcome to our world. It’s growing bigger, faster, and better every day. A subscription to XJ is Xilinx, Inc. 2100 Logic Drive free for the asking (see URL below). We hope you enjoy and gain valuable knowledge from this San Jose, CA 95124-3400 Phone: 408-559-7778 edition. Much of what we publish is brand new to the world. In our Fall 2003 issue, we will show FAX: 408-879-4780 ©2003 Xilinx, Inc. you what may very well be the beginning of the end of all fixed logic design. But if you just can’t All rights reserved. wait for the latest news and information on programmable logic and systems, visit Xcell Online Xcell is published quarterly. XILINX, the Xilinx logo, CoolRunner, Rocket Chips, Rocket IP, Spartan, and (www.xilinx.com/publications/xcellonline/), where you’ll find frequent reports on what’s happening Virtex are registered trademarks of Xilinx, Inc. ACE Controller, ACE Flash, Alliance Series, AllianceCORE, ChipScope, CORE Generator, Fast CONNECT, Fast FLASH, in the world of programmable logic. Fast Zero Power, Foundation, HDL Bencher, IRL, J Drive, LogiCORE, MicroBlaze, MultiLINX, NanoBlaze, PicoBlaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Smart-IP, System ACE, Virtex-II Pro, Virtex-II EasyPath, WebFITTER, WebPACK, WebPOWERED, XACT-Floorplanner, XACT-Performance, XAPP, XC designated products, Xilinx Foundation Series, Xilinx XDTV, and XtremeDSP are trademarks, and The Programmable Logic Company is a service mark of Tom Durkin Xilinx, Inc. Other brand or product names are registered trademarks or trademarks of their respective owners. Managing Editor The articles, information, and other materials included in this issue are provided solely for the convenience of our readers. Xilinx makes no warranties, express, implied, statutory, or otherwise, and accepts no liability with respect to any such articles, information, or other materials or their use, and any use thereof is To subscribe to the printed Xcell Journal, or to view the Web-based Xcell Online Journal, visit: solely at the risk of the user. Any person or entity using such information in any way releases and www.xilinx.com/publications/xcellonline/ waives any claim it might have against Xilinx for any loss, damage, or expense caused thereby. TABLE OF CONTENTS

COVER STORY 2020

New RocketPHY Transceiver 7 Family Debuts at 10 GbpsE A new family of 10 Gbps serial I/O transceivers dramatically cuts costs in light-speed applications. New Spartan-3 FPGAs Are Cost-Optimized These transceivers make it possible to create unique for Design and Production optical connectivity designs. The new Xilinx Spartan-3 FPGA family offers up to 5 million system gates with the lowest cost per gate and lowest cost per I/O compared to any other programmable logic alternative. Why use a gate array or standard cell ASIC when you can get a low-cost, high-density, and faster time-to-market solution with Spartan-3 FPGAs? 46 Xcell Online Web Xclusives NSPICE Bridges Simulation Gap Check out Xcell Online (www.xilinx.com/publications/xcellonline/) A next-generation, mixed-domain for these late-breaking Xcell Online Web Xclusives and more: SPICE tool with directly integrated S-parameter data capability provides • Xilinx 300 mm and 90 nm Process Technologies: the most accurate simulation of Why This Is Important to Designers. combined silicon and system behavior. • Is Your FPGA Design Secure? It Is with Xilinx – and Here’s How It Works. • PCI Express Advanced Switching: Solve Your PCI Implementation Problems. • Why The Boeing Company Chose Virtex-II Pro Platform FPGAs for Image Processing. SUMMER 2003, ISSUE 46 Xcell journal

Get the EasyPath Solution View from the Top...... 6 The Virtex-II and the Virtex-II Pro New Spartan-3 FPGAs Are Cost-Optimized...... 7 EasyPath solutions are a cost-effective Spartan-3 Family Opens New Applications...... 10 alternative to ASIC conversion – saving you money while ISE 5.2i Delivers Head Start to Spartan-3 Designers...... 14 significantly decreasing Spartan-3 FPGAs Add SPI-4.2 “Lite” Core ...... 16 your time to market. 58 New RocketPHY Transceiver Family – 10 Gbps...... 20 Accelerate Your Multi-Gigabit Serial Design ...... 24

High-Speed Serial Interface Design...... 28 How to Design a 3DES Kit for Cadence Tools Speeds RocketIO Designs...... 30 Security Microcontroller Software-Compiled System Design...... 32 Using IP cores and a pre-integrated Tarari and Celoxica — Fast Algorithm Acceleration ...... 38 IP platform, engineers at SoC Solutions Next-Generation FPGA Synthesis...... 44 built a custom microcontroller platform in less than two weeks. NSPICE Bridges Simulation Gap...... 46 69 Optimize Pin Assignments Early...... 49 Got the BGA Blues?...... 52

Reduce Resistor Counts and Lower Costs...... 56 Platform Delivers Fast, Get the EasyPath Solution ...... 58 Flexible AC Servomotor- Xilinx Chips Fight Drunk Driving...... 63 Control Designs FPGAs Are the Brains Behind “Smart” Cars ...... 64 New digital motor-control applications How to Design a 3DES Security Microcontroller...... 69 exceed the capabilities of How to Use Free Software in Embedded Designs...... 74 conventional solutions. 82 Xilinx Delivers HyperTransport Lite Reference Design...... 79 Low-Cost IP Connectivity Lets Diverse Systems Communicate...... 80

Platform Delivers Fast, Flexible AC Servomotor Designs ...... 82

Xilinx FPGA Blasted into Orbit...... 86 Xilinx FPGA Blasted into Orbit MyXPA Helps You Get the Most from the XPA Program ...... 90 Xilinx Events and Tradeshows...... 91 A radiation-hardened Xilinx FPGA gives the Australian FedSat Fuzzy Logic ...... 93 satellite powerful reconfigurable Xilinx Partner Yellow Pages...... 94 computing capabilities. Spartan-3 Data Sheet ...... 102

86 Reference Pages...... 106 Viewfrom the top Move Over, von Neumann

Extraordinary advances in pro- Programmable logic devices performing many operations grammable logic in parallel are replacing microprocessors by providing much technologies are making it possible higher performance at far lower cost. Here’s one example. for FPGAs to offer unique new ways to build advanced by Wim Roelandts designs that were CEO, Xilinx, Inc. previously impossible. In fact, many traditional design components are becoming obsolete as FPGAs become faster and less expensive. The standard microprocessor is no longer the only way – or the best way – to develop high- performance, low-cost computers. Programmable logic devices are dramatically changing the way computers are designed. Instead of using a single CPU that executes instructions serially (the von Neumann approach), with programmable logic you can easily run multiple tasks in parallel and achieve an impressive increase in performance while drastically reducing costs. The benefits are too overwhelming to ignore, and programmable logic is the key. The von Neumann architecture is already 50 years old – it’s clearly time for a change. A Xilinx customer, Wincom Systems, will soon introduce a new Web server that can handle the work of 50 to 300 conventional microprocessor-based servers each costing Programmable logic has always been far Conclusion $5,000 or more – and it costs approximately less expensive to develop than ASICs. Now Programmable logic devices can do much $2,500. It does all this without relying on the device costs have been dramatically more than just replace conventional com- microprocessors, and the server fits in a box reduced as well. For example, an FPGA ponents. You can create designs that are the size of a DVD player. This remarkable that cost $1,000 in 1996 costs less than far more profitable and far more power- improvement in cost and performance is $10 today – and today’s device offers far ful than alternative solutions. Your busi- being realized in a variety of other new more features at a much higher speed. In ness depends on getting new designs to designs that will soon come to market. addition, the introduction of 90 nm tech- market ahead of your competition – Because FPGAs can easily handle mas- nology will position our costs to be low- designs that provide maximum value, at sive numbers of calculations in parallel, ered once again. Next year, our largest minimal costs. Programmable logic deliv- they are far faster than conventional DSPs FPGA will have approximately 20 million ers what you need, today. And it just or microprocessors in many applications. gates, compared to 20,000 in 1993. keeps getting better.

6 Xcell Journal SummerSpring 2003 NewNew Spartan-3Spartan-3 FPGAsFPGAs AreAre Cost-OptimizedCost-Optimized forfor DesignDesign andand ProductionProduction TheThe newnew XilinxXilinx Spartan-3Spartan-3 FPGAFPGA familyfamily offersoffers upup toto 55 millionmillion systemsystem gatesgates withwith thethe lowestlowest costcost perper gategate andand lowestlowest costcost perper I/OI/O comparedcompared toto anyany otherother programmableprogrammable logiclogic alternative.alternative. WhyWhy useuse aa gategate arrayarray oror standardstandard cellcell ASICASIC whenwhen youyou cancan getget aa low-cost,low-cost, high-density,high-density, andand fasterfaster time-to-markettime-to-market solutionsolution withwith Spartan-3Spartan-3 FPGAs?FPGAs?

by Rob Schreck Senior Marketing Manager Xilinx, Inc. [email protected]

Today’s design engineers deal with a dilemma every time they start a new logic development project. They want to develop a product fast and get it to market first – but they also must meet demands to lower costs. Many times, engineers have turned to ASIC solutions to meet their cost objectives, but that often means high NRE costs and long development times. Using ASICs also often means running the risks of: • Missing the market window • Losing out to competition • Design problems • Design changes • Skyrocketing NRE costs.

Summer 2003 Xcell Journal 7 Xilinx offers you a better solution with • Digital clock managers (DCMs) and FPGAs. These 300 mm wafers deliver the new class of Spartan™-3 Platform pre-engineered clock networks facilitate almost 2.5 times the number of die com- FPGAs. Built on four generations of proven the design of high-speed systems. pared to the mature 200 mm wafers, but at Spartan success in high-volume consumer a fraction of the cost per die. We also • High-speed multipliers are embedded and automotive applications, this new implemented a dual wafer fabrication strat- for DSP applications, such as adaptive family of Platform FPGAs delivers unprece- egy, using world-class foundries at both filters and forward error correction. dented density, field reprogrammable func- IBM and UMC to reduce production risks tionality, and competitive price points. You • Programmable SelectIO™-Ultra sup- and increase capacity. also get a platform with the density, scalabil- ports 23 I/O standards and provides a Our process technology leadership ity, and features to tackle tough connectivity, low-cost bridge from one I/O standard makes Xilinx the world’s lowest-cost, DSP, and embedded design problems. to another. lowest-risk FPGA provider. The Xilinx With Spartan-3 FPGAs, you investment in design opti- can develop logic for many new mization, 90 nm manufactur- consumer, networking, and ing technology, and 300 mm automotive applications, includ- wafer production delivers ing blade servers, low-cost price points for Spartan-3 routers, and medical imaging. FPGAs at under $20 for a 1M- You can get those products to gate FPGA and under $100 market fast, because you manu- for a 4M-gate FPGA. facture the system with the same FPGA you use to develop and Delivering More prototype the design. I/Os in Smaller Die Spartan-3 FPGAs offer a Driving Down FPGA Costs remarkably small die for the Design engineers have been number of logic gates using looking for an alternative to long 90 nm process technology. ASIC development cycles and Naturally, with a smaller die high ASIC NRE costs. To sup- comes a smaller perimeter for port an industry requirement the necessary number of I/O that has grown to over $20 bil- Figure 1 - Staggered pad technology pads. This could be a problem lion, Xilinx set the goal of low for an application that cost, unprecedented density • XCITE digitally controlled impedance demands a high I/O count. range, and high capability for the Spartan-3 technology supports increased signal However, by using staggered pad technolo- family of FPGAs so they could be used both integrity for both single-ended and gy (Figure 1), Xilinx is able to deliver two for prototyping and for production of high- differential I/Os. rows of I/Os on each edge of the die versus volume products. To meet that aggressive one row found in all other FPGAs and target, Xilinx developed this Platform FPGA The result is a cost-optimized FPGA ASIC alternatives. You get more I/Os in a architecture with a small die size, a wide fabric that is, nevertheless, flexible, scala- smaller die, resulting in a low cost per I/O logic density range, and sufficient I/Os to ble, and able to provide the capability to and low cost per gate for Spartan-3 FPGAs. support the mid-range of gate array and support many designs. standard cell logic designs. In addition, Spartan-3 FPGAs: Xilinx included the features most needed for Process Leadership in 90 nm The Complete Design Platform today’s designs: Xilinx integrated a large logic density range Spartan-3 Platform FPGAs offer a complete with all of the above features – and then solution of logic, memory, and I/Os – along • Up to 1.8 Mb of block RAM can be took another giant step to drive down cost with features such as multipliers – to provide used for large FIFOs and data storage. using a new 90 nm process technology. The a rich fabric to support connectivity, DSP, • Abundant distributed RAM, imple- Spartan-3 FPGA family is the first pro- and embedded design applications (Figure 2). mented from logic cells, can be used grammable logic built with this process for small FIFOs, shift registers, and technology, which leads to die sizes 50% to Spartan-3 Connectivity Solution constant coefficients. This combination 80% smaller than any competing solution. Many design problems revolve around get- of block RAM and distributed RAM Xilinx also uses 300 mm wafer technol- ting data on and off the FPGA. The best provides a unique flexibility found ogy to deliver the efficiency and capacity way to ease these connectivity problems is a only in Xilinx FPGAs. needed to produce high-volume Spartan-3 robust I/O solution. All Spartan-3 I/O pins

8 Xcell Journal Summer 2003 processor. When you combine the MicroBlaze processor and available peripherals with Spartan-3 logic, memory, and I/Os, you can develop a custom embedded design for your specific requirements. You increase on-chip integration, reduce board cost, and minimize the risk of vendors choosing to make obsolete a specific microcontroller.

Xilinx Complete Development Support Spartan-3 FPGAs also come fully supported in the current Xilinx ISE 5.2i software design suite (Figure 3). ISE 5.2i is the most prevalent design methodology in the industry, with more than 150,000 installed users. ISE includes a full spectrum of easy-to-use productivity options that can be inserted to fit in almost any existing corporate logic design methodology. Xilinx ISE tools increase your productivity, which in turn slash design times by as much as 50% when compared to Figure 2 - Spartan-3 Platform FPGA ASIC methodologies. For design verification, the Xilinx support the Xilinx SelectIO™-Ultra func- ChipScope™ Pro debugging environ- tionality, dramatically increasing design ment delivers unmatched power to flexibility. Each user I/O pin can support any uncover critical bottlenecks and opti- of the 23 electrical interface standards. With mize your design. the abundant I/Os in the Spartan-3 FPGA For engineers using the MicroBlaze family, you get the lowest cost per parallel processor to develop a field program- interconnect available in the industry. mable controller, Xilinx offers a com- The differential I/O standards assist you plete hardware and software solution in achieving higher performance, lower with the Xilinx Embedded Design Kit power consumption, and lower pin count. (EDK). Software tools similar to those These standards are supported by soft IP used for IBM PowerPC™ designs are building blocks for important new interface available to: Figure 3 - ISE 5.2i design suite protocols, such as PCI 32/33 and PCI • Configure peripherals 64/33, RapidIO™, POS PHY Level 4, • Develop protocols Flexbus 4, SPI-4, and HyperTransport™. significant DSP capability that can deliver up To further simplify the design process and to 330 billion MACs/second. This economical • Integrate the logic. reduce costs, the Spartan-3 FPGAs support and robust performance makes Spartan-3 Then you can verify your design in the XCITE digitally controlled impedance tech- devices a cost-effective solution for low-cost system at speed in the Spartan-3 FPGA. It’s nology for both single-ended and differential applications, such as digital communications, an easy solution for today’s complex designs. I/O standards. XCITE technology provides video and imaging, and industrial control. I/O impedance matching that adapts to In addition, the partnership between Xilinx Conclusion changes in supply voltage and temperature. and The MathWorks offers a simple, familiar The Xilinx Spartan-3 FPGA offers the lowest XCITE technology reduces board cost by design flow with MATLAB™/Simulink™ cost FPGA in the industry, as well as a true eliminating the need for most external ter- software to design the DSP functions. low-cost design platform for many applica- mination resistors. What’s more, XCITE tions. You get the density and features you technology increases signal integrity. Industry’s Lowest Cost need for a wide range of designs, plus a devel- Soft Processor Solution opment environment to get you through the Low-Cost Points for High-Performance DSP The high feature set of the Spartan-3 FPGA design cycle and into production quickly. To The abundant RAM resources – along with family provides a low-cost platform for learn more about the Spartan-3 family, visit 18X18 multipliers – give Spartan-3 FPGAs a embedding the Xilinx MicroBlaze™ soft www.xilinx.com/spartan3/.

Summer 2003 Xcell Journal 9 Spartan-3Spartan-3 FamilyFamily OpensOpens NewNew MarketsMarkets Spartan-3Spartan-3 FPGAsFPGAs invadeinvade andand ApplicationsApplications traditionaltraditional ASICASIC marketsmarkets withwith competitivecompetitive priceprice pointspoints andand value-addedvalue-added reprogrammability.reprogrammability.

by Robert Bielby Sr. Director, Strategic Solutions Marketing Xilinx, Inc. [email protected]

Nineteen years ago, Xilinx introduced the field programmable gate array, or FPGA. The concept was simple: by building a gate array based upon SRAM technology, you could develop a chip directly on your desktop, doing away with the high non- recurring engineering costs associated with custom ASICs. The benefits of this technology were immediate and obvious – instant turnaround time and infinite reprogrammability. The idea of a “foundry on the desktop” caught on over time as designers began to rely on FPGAs for product development and limited production deployment. However, because of the inherent silicon overhead cost for reprogrammability (easily more than 20:1 for an FPGA vs. ASIC), FPGAs were not considered cost- effective for higher volume applications.

10 Xcell Journal Summer 2003 In 1998, Xilinx forever changed the eras, CD players, DVD players, personal of up to 1,120 user I/Os, the Spartan-3 playing field with the introduction of the computers, set-top boxes, personal video FPGA family opens up the world of pro- Spartan™ FPGA family. Based on the recorders, plasma displays, MP3 players, grammability to an even greater suite of highly successful XC4000 FPGA architec- home theater, home audio, karaoke applications than ever before. ture, the Spartan FPGA family heralded a machines, and a host of other applications new era in programmable logic by deliver- too extensive to list here. It’s almost safe to Driving New Markets ing products at price points previously not say that if you can think of an application, With such a wide density range and pin considered possible in the industry. there’s a very good chance that it contains a count, the Spartan-3 family can compete Through streamlined packaging, speed Spartan FPGA. with the majority of ASIC design starts. In grades, test, and process technology, Xilinx The effect of a low-cost FPGA hasn’t gone effect, in the future, it’s going to be harder to achieved significant cost reductions. These unnoticed on the Xilinx bottom line: Today figure out where you won’t find Spartan-3 reductions opened a wide range of new more than 13% of Xilinx revenue is generat- FPGAs than where you will find Spartan-3 markets and applications that could reap ed in nontraditional consumer applications. FPGAs. Although this comment may be the time-to-market benefits somewhat fanciful, the list and flexibility of program- of markets and applications mable logic. in those markets that are a Since the introduction perfect match for the new, of the first Spartan family, low cost Spartan-3 family is Xilinx has maintained an quite broad: unabated trend of delivering successively improved Automotive Spartan families almost The newest innovations in yearly. Each new family automobiles today are not offered significant cost and centered on improved fuel performance benefits over efficiency or improved per- the previous families. formance, but instead are Additionally, each family focused on improving the provided additional, new driver and passengers’ driv- features leading to an even ing experience and safety. greater reduction in bill of This emerging new technol- materials costs. ogy is called telematics. The extent of the cost Telematics represents the reductions cannot be over- greatest innovation in the stated: The Spartan-II, the automotive industry since third-generation Spartan perhaps the introduction of family, featured the 100,000-gate With the recent introduction of the the car itself. Imagine what would be possi- XC2S100 family member for just $10. Spartan-3 family, Xilinx continues to build ble if all of your personal information This represents a 100:1 reduction in cost on the momentum established six years ago appliances and entertainment devices could over the equivalent density device that was – delivering FPGAs at price points that are communicate and share information with introduced just five years earlier. unmatched in the industry. Based on a 90 one another in a single environment. In The Spartan-II FPGA not only delivers nm SRAM technology and manufactured such a scenario, your cell phone could a lower cost per gate than its predecessor, it on 300 mm wafers, the Spartan-3 family communicate directly to your PDA, which also includes embedded features, such as enjoys the industry’s most advanced process would allow you to review your email, logic level translators, embedded memory technology. This technology allows the download a MP3 audio track, and play it blocks, and integrated phase locked loops, Spartan-3 family to maintain an inarguable on the car stereo while you checked your all at the $10 price point. Thus, it’s no sur- price/performance advantage over not only stock portfolio and looked for the best prise that more than 45 million units of the competitors’ FPGAs but also ASICs. route to go to work. Multifunction telem- Spartan-II series family have been shipped The Spartan-3 family also represents a atics is both possible and available in high- since its introduction. significant breakthrough both in density end cars today. Equally as impressive is the range and range and I/O pin count when compared to The challenges to optimal telematics, types of applications where Spartan FPGAs previous the Spartan families. With a 100:1 however, are many, because the emergence are used in production. Applications such range in density spanning from 50,000 of new standards, technologies, and short as PC add-in cards, children’s digital cam- gates to 5,000,000 gates and an I/O count development cycles complicate product

Summer 2003 Xcell Journal 11 development and deployment. Cost- effective, flexible solutions such as those made possible by Spartan-3 devices will enable you to stay current in this rapidly growing and evolving market.

Medical The latest breakthroughs in telemedicine leverage advances in networking and broadband technologies to provide local care by a remote physician or a team of dis- persed specialists. New programs, such as Telestroke, have been developed to support medical doctors who practice medicine in small rural com- munities or in community hospitals where there are no local specialists in stroke treat- ment. The Telestroke program is a system drive the long-awaited consumer demand These examples are but a small sampling to connect medical staffs who work at for digital television sets. The image proof the many exciting new markets and appli- emergency rooms of small hospitals with cessing requirements demand both a cost- cations for Spartan-3. stroke specialists by using videoconference effective yet high-performance digital systems, ISDN, and desktop computers. signal processing technology such as that eSP Simplifies System Design These two parties examine the patient offered by Spartan-3 devices. Two years ago, Xilinx introduced the simultaneously, test the extent of the industry’s first Web portal dedicated to stroke, investigate scanned films of the Home Networking accelerating product development for a patient’s internal organs, and determine The connected home market – consisting wide range of markets and applications. the types of strokes that the patient may of home networking equipment, software, With a focus on providing solutions and have suffered. The system enables stroke residential gateways, home control, and tutorials primarily targeting new and specialists to tell doctors in the emergency automation products – is estimated to be emerging standards and protocols, the room what appropriate medication to pre- $9.2 billion worldwide by 2006. The cur- aptly named eSP (emerging standards and scribe and what operations to perform. rent growth of the connected home market protocols) Web portal has proved to be an The cost sensitivities of this technology, has been spurred over the past year by a effective industry resource validated by which combine a wide range of complex surge in popularity of wireless networking more than seven million visits to date. technologies, are again well addressed by technology and basic home routers to The eSP portal covers a wide range of Spartan-3 FPGAs. enable broadband and resource sharing, markets and applications, including: including file and printer sharing. • Both consumer and professional digital Digital Video Multiple other factors will continue to video technologies The digital television set market is poised to fuel this growth, including the need for net- enter a period of sustained growth. Various work security. Home routers and residential • Wireless networking regional digital broadcasting standards have gateways will need “firewall” protection for • Home networking been established in most countries – ATSC always-on connections. Additionally, the high definition in the U.S. and South Korea, release of Windows™ XP, the first true • Automotive telematics ISDB in Japan, and DVB in most of the rest “home network friendly” operating system • Metro access networking technologies. of the world. More countries continue to from Microsoft, has greatly simplified the roll out digital television services every task of interconnecting and sharing With the introduction of the Spartan-3 month. And there is more to come. In the resources. The next wave in home network- family, Xilinx has expanded the breadth of U.S., high-definition cable signals are being ing will be the broad-based sharing of video the eSP portal to highlight and provide offered by an increasing number of cable and audio – adding new complexities and solutions and tutorials on the new markets service providers in an increasing number of challenges but also benefits to the consumer. and applications now addressed by this rev- markets. Localized media centers with global sharing olutionary new FPGA family. To learn Meanwhile, digital terrestrial broadcasts will drive new solution models that will more about the new Spartan-3 markets, are expected to begin in Japan this year. The again greatly benefit from the programma- applications, and solutions, visit the eSP deployment of digital video services will bility and flexibility of Spartan-3 FPGAs. portal at www.xilinx.com/esp/.

12 Xcell Journal Summer 2003 Thousands of Designers. Infinite Applications. One Powerful Resource.

by red we Po sP POR eWEB TAL Online innovation Powered by Powered by Whether you’re designing next-generation consumer, digital video, automotive, industrial, or even broadband applications, the eSP web portal can help make your innovation a reality. Featuring everything from technology tutorials, market overviews, and system block diagrams to reference boards, IP cores and more, this is the ultimate resource for all your design solutions.

The power of 3 The high-performance, low-cost Spartan-3 platform FPGA features a range of density options from 50,000 to 5 million gates, as well as the lowest I/O and gate costs available. This makes it the ideal device for a wide variety of applications. Now, our eSP web portal gives you access to a complete suite of Spartan-3 silicon, software, and IP solutions optimized for your design.

For more information, visit us at www.xilinx.com/esp/s3.

www.xilinx.com/esp/s3

® 2003 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx and Spartan are registered trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc. ISEISE 5.2i5.2i DeliversDelivers HeadHead StartStart toto Spartan-3Spartan-3 DesignersDesigners Xilinx ISE 5.2i design and development software allows you to take full advantage of the features of the newly released Xilinx Spartan-3 family of FPGAs.

by Lee Hansen Product Solutions Marketing Manager Xilinx, Inc. [email protected]

Why wait for critical software design support of the latest FPGA family when Xilinx ISE 5.2i design software already supports the new, low-cost Spartan™-3 FPGAs right now? You can hit the ground running with the newest and best-in-class FPGAs and development tools – including third-party software support. Spartan-3 FPGAs are based on the pioneering Virtex™-II Platform FPGA architecture introduced in late 2000. Virtex-II FPGAs exploded beyond the supposed limits of what a programmable logic device could do. Since then, the Xilinx ISE design environment has kept pace with the technology to make full use of the Platform FPGA architecture, including tight partner tool integration.

14 Xcell Journal Summer 2003 Leverage the Architectural Advantage Spartan-3 FPGAs are ready to use with Synplicity™ and Mentor Graphics Exemplar synthesis support now. That means all of the internal logic structures can be put to maximum use in your Spartan-3 design today – not six months to a year from now, which is the usual time- line when a new architecture is released. The ISE 5.2i toolset and synthesis partners support inferencing of internal logic structures. This allows the synthesis tools to make maximum performance choices for your design during implementation, and makes it easier to code, debug, and read HDL source code. Spartan-3 devices also contain the “active interconnect” routing pioneered in Virtex-II FPGAs. The active interconnect technology, with its buffered routing, allows more logic structures to be reached design wizard. Just set the appropriate focusing on individual module performance with minimum impact on signal delay attributes in the dialog box, and fully rather than overall design completion. time. Because timing delay is minimized, editable VHDL or Verilog™ code is writ- Modular design functionality speeds the even for long signal routes, you also see less ten into your HDL source, saving valu- design flow through to faster completion. impact to timing during the re-place-and- able design time. This HDL source is Although incremental design and mod- route phase. With active interconnect tech- “correct by construction” without requir- ular design have similar capabilities, the nology, more signal paths stay in time spec ing you to understand every nuance of incremental design approach provides a than with traditional architectures. the device architecture. simple design flow and faster runtimes ISE 5.2i offers architecture wizard The full range of I/O options for when all modules are available. On the support for the Spartan-3 DCMs (digital Spartan-3 FPGAs are completely support- other hand, the modular design option clock managers), as shown in Figure 1. ed in ISE, including differential routing, provides individual independence inside a The architecture wizard lets you program which gives you the maximum in system team environment and can be used when the advanced clock features of the I/O protocol choices. Xilinx XCITE digital you need the flexibility for design modules Spartan-3 DCMs through an easy-to-use internal resistor I/O termination is fully to arrive at different times. supported in ISE, greatly reducing the The area mapping capabilities of ISE number of external resistors on your board Floorplanner and PACE enable quick and and freeing up valuable PCB real estate for easy logic grouping, leading to better timing essential devices. results and faster design performance. RPMs (relationally placed macros) allow design Productivity Options teams to save floorplanned HDL designs for A full spectrum of ISE design productivity later design reuse. RPMs let managers best options is available to optimize your utilize their HDL resources and deliver Spartan-3 design. Incremental design tech- repeatable, guaranteed design performance. nology slashes design recompile times by limiting the re-implementation phase to only Conclusion the design modules that need to change. The With ISE 5.2i and Spartan-3 FPGAs, you rest of the design is frozen and intact, pre- now have at your fingertips the lowest cost serving previous performance results. FPGA design options available today. ISE Now included at no extra cost in ISE 5.2i 5.2i extends these advantages by adding the is a modular design capability delivering a design edge that delivers more productivity divide-and-conquer, team-based approach and lower design costs, all in a package to high-density design. Teams of engineers that’s built on proven Xilinx architectural Figure 1 - ISE 5.2i DCM architecture wizard can complete their modules in parallel, design advantages.

Summer 2003 Xcell Journal 15 by Krista Marks Sr. Engineering Manager, IP Solutions Division Xilinx, Inc. Spartan-3 FPGAs Add [email protected] Paul Ingersoll Solutions Marketing Manager SPI-4.2 “Lite” Core Xilinx, Inc. [email protected]

Finding creative ways to keep costs low has to Slash Design Costs become a mandate for designers of advanced systems. This is especially true in the telecommunications space, where the The SPI-4.2 “Lite” solution for Spartan-3 FPGAs delivers demand for ultra-fast 10 Gbps infrastructure performance is still in the formative 2.5 Gbps but remains compliant with the SPI-4.2 10 Gbps stages. Therefore, providing 10 Gbps levels of performance is not a market or product specification to deliver a low-cost, high-end solution perfect priority at this time. for existing MAN/LAN networks. Instead, metro access and WAN/LAN equipment providers are focused on building and servicing the more mainstream 2.5 Gbps infrastructure as a way to ride out the current economic dol- drums. Their priorities have shifted from features and performance to cost and risk avoidance. Given these market conditions, designers of Ethernet, Packet-Over-SONET, and ATM applications have demonstrated a keen interest in low-cost solutions for interconnecting PHY devices and traffic management components such as network processors and ASSPs using the SPI-4.2 interconnect standard. Xilinx is responding to this interest with a pre-engineered, drop-in SPI-4.2 “Lite” intellectual property (IP) core that can be implemented on its low-cost Spartan-3 devices. The core is fully compliant with the 10 Gbps (OC-192) OIF- SPI4-02.0 specification while operating at a reduced line rate of 2.5 Gbps (OC-48). This article provides an overview of the benefits of the solution and the details of the SPI-4.2 Lite core.

Spartan-3 FPGAs and SPI-4.2 Lite The sweet spot for new telecommunications equipment over the next 12 to 18 months will be products running at 2.5 Gbps. Because POS-PHY Level 3 (SPI-3) is targeted to 2.5-Gbps OC-48 applica-

16 Xcell Journal Summer 2003 tions, one way to meet this demand is to SPI4.2 Lite Core Specifications: single combined EOP/SOP control word. build SPI-3 compliant interfaces inside You can request the insertion of idle • Performance: 200 Mbps on SPI-4.2 these products. cycles or training patterns regardless of the However, a powerful alternative to • Supported families: Virtex™-II, source FIFO status. By allowing the inser- building a SPI-3 interface is to build an Spartan-3 tion of idle bus cycles in response to user interface using the SPI-4.2 Lite solution • Slices Required: 1,450 requests, flow control latency is greatly hosted on a Spartan-3 FPGA. This reduced. In addition, the SPI-4.2 Lite approach achieves 2.5 Gbps line rates • SelectRAM™ blocks: 6 core is able to transfer contiguous data while still adhering to the OIF SPI-4.2 • Global clock buffers: 3 bursts across the SPI-4.2 interface. The 10 Gbps specification. Furthermore, the source FIFO will refrain from transmit- PCB design is simplified because this • Digital clock managers: 2. ting data until an entire burst has been solution delivers better flow control than The source and sink cores provide data written into the FIFO. Once a burst has the SPI-3 standard and uses fewer pins. storage implemented with FIFOs using dual- been written into the FIFO, the data will Hosting the SPI-4.2 Lite IP core on a port SelectRAM blocks that support inde- be transferred across the SPI-4.2 interface Spartan-3 allows gigabit network pendent read/write clock domains. These without interruption until the entire burst providers to meet the demand for 2.5 FIFOs allow the storage of up to 512 data has been transmitted. Gbps performance at the lowest possible words. The design optimizations developed cost – while also putting their designers for the full-rate SPI-4.2 source core are also in a great position for the transition to implemented in the Lite Floorplanner Snap Shot 10 Gbps data rates. Because the core release. This includes the XC2V3000-FF1152 runs at a line rate of 2.5 Gbps, compared unique ability of the to 10 Gbps for the full-rate core, it can Xilinx SPI-4.2 solution be successfully hosted on a low-cost Tx to maximize bandwidth Tx Spartan-3 device that delivers the requi- utilization by not insert- site performance to achieve the lower Rx ing filler idle cycles on the Rx line rate. SPI-4.2 interface. Under The SPI-4.2 Lite solution is a great normal operating condi- starting point for network equipment tions, back-to-back pack- SPI-4.2 Lite IP Core SPI-4.2 Full-Rate IP Core providers that will scale their products to ets are separated by a 1450 Slices = 10% 3550 Slices = 25% 10 Gbps data rates when the market moves in that direction. Because the Figure 1 - Lite core requires 15% fewer slices. SPI-4.2 Lite solution running at 2.5 Gbps is functionally compliant with the OIF SPI-4.2 10 Gbps specification, the OC-48 2.5G Line Card internal interface, the functional testing, Spartan-3 and the back-end application logic can Optical OC-48 NPU Traffic SER I/F PHY (ASSP) SPI-4.2 USERS (ASSP) Manager DES all be reused. In the line card design, as Lite Core DESIGN shown in Figure 2, IP reuse is straight- forward. Only the size of the SPI core will change. This significantly reduces the development time associated with building equipment targeted at a 10 Gbps-dominated marketplace. OC-192 10G Line Card Virtex-II

SPI-4.2 Lite Core Overview Optical OC-192 SPI-4.2 NPU Traffic SER I/F PHY (ASSP) Full-Rate USERS (ASSP) Manager DES The SPI-4.2 Lite core is delivered as inde- Core DESIGN pendent source (Tx) and sink (Rx) cores. A block diagram of the SPI4.2 Lite IP core and its interfaces is shown in Figure OC-48 FPGA USER DESIGN AND PCB LAYOUT 3. It is a drop-in replacement for the CAN BE REUSED FOR OC-192 APPLICATIONS Xilinx full-rate SPI-4.2 IP core – the signals and functionality of both the full-rate and Lite SPI4.2 core are identical. Figure 2 - SPI-4.2 Lite and full-rate design reuse example for OC-48 and OC-192 line cards

Summer 2003 Xcell Journal 17 SPI-4.2 Lite Interfaces SPI-4.2 Lite Sink Core The SPI-4.2 Lite core has four primary interfaces: 1. User interface User FIFO 2. SPI-4.2 interface Interface Interface SPI-4.2 3. Status interface Sink Receive Sink Status Status Interface Interface 4. Calendar interface, as shown Interface Registers in Figure 3. Sink Calendar Calendar The core also has a set of static configu- Interface Buffer ration signals that are used for in-circuit customization of the core. The SPI-4.2 core’s interface supports up to 200 Mbps (100 MHz LVDS DDR I/O) for an aggre- SPI-4.2 Lite Source Core gate bandwidth of 2.5 Gbps. Like the full- rate SPI-4.2 IP core, the FIFO status path User FIFO operates at a quarter of the data rate and its Interface Interface electrical interface can be user-configured SPI-4.2 to be either LVTTL or LVDS. Source Transmit In order to support the widest range of Source Status Status Interface Interface applications, the SPI-4.2 Lite core offers Interface Registers you a choice of either a 32-bit or 64-bit Source Calendar Calendar user interface. The user interface operates Interface Buffer at up to 150 MHz for both the 32-bit and 64-bit core configurations. With the 64-bit interface at frequencies greater than 100 MHz, the user interface can operate at a Figure 3 - Block diagram of SPI-4.2 Lite and full-rate core higher bandwidth than the SPI-4.2 interface. You can transmit and receive data Guide. These documents help you quickly Conclusion from two FIFOs implemented in dual-port integrate the SPI-4.2 core into your design. The compact SPI-4.2 Lite core combined SelectRAM blocks that each support inde- The SPI-4.2 Design Example Guide with the low-cost Spartan-3 architecture pendent read/write clock domains. provides RTL code (along with a user’s provides a powerful SPI-4.2 interconnect This interface is designed with standard guide) that enables you to simulate the solution that helps telecommunications FIFO handshaking signals to simplify the core immediately with automatically gen- and networking infrastructure providers user’s logic. For additional flexibility, the erated SPI-4.2 packet data. This illustrates respond to the pressure to deliver low-cost source FIFO status channel interface how to connect to each of the core’s inter- solutions in today’s marketplace. The SPI- comes in two configurations: the address- faces. The provided code is also synthesiz- 4.2 Lite core is packaged with the full-rate able interface and the transparent interface. able so you can run it through Xilinx core and is offered at $18,000 (USD). The addressable calendar can be pro- implementation tools. This allows you to Customers with an in-maintenance license grammed to indicate the order and fre- instantly view the layout of the core in the for the full-rate core are entitled to receive quency of the channel’s status on the user Floorplanner, simulate the core with back- the new SPI-4.2 Lite core as an update. interface, enabling a polling implementa- annotated timing information, and quick- For more information, or to evaluate tion. The transparent calendar has a 2-bit ly evaluate performance compliance. the new SPI-4.2 Lite core, please contact interface for all channel configurations and The SPI-4.2 Quick Start Guide con- your Xilinx sales representative. is updated in the order that it is received by tains the information necessary for you to the sink interface, allowing minimal laten- modify the core to meet your design References cy in the flow control implementation. requirements. It walks you through the [1] PMC-Sierra, Inc., POS-PHY™ Level-4, A process of selecting the correct designs and Saturn Packet and Cell Interface Specification for OC-192 SONET/SDH and 10Gb/s Quick Start to Implementation netlists, customizing the timing and con- Ethernet Applications. Issue 5: June 2000. Two Xilinx implementation documents are straints necessary for their particular appli- [2] OIF-SPI4-02.0 System Packet Interface provided with the core: the SPI-4.2 Design cation, and running the automated Level-4 (SPI-4) Phase 2: OC-192 System Example Guide and the SPI-4.2 Quick Start implementation scripts. Interface for Physical and Link Layer Devices.

18 Xcell Journal Summer 2003 It’s another industry first from THE PROVEN SOLUTION. THE FAST TRACK TO SAVINGS. ®_ Xilinx a Platform FPGA with Using serial technology, you can significantly reduce system costs through IBM PowerPC ™ processors and serial transceivers ranging from fewer pins, smaller PCBs, smaller connectors, lower EMI, better signal integrity and noise immunity. The Xilinx “Serial Tsunami” 622Mbps to 3.125 Gbps today, and 10 Gbps just around the corner. initiative brings you simplified designs, scalable bandwidth, and risk-free programmable serial solutions. For ALL THE SUPPORT YOU NEED volume production, Xilinx offers Virtex-II Pro EasyPath The high-performance Virtex-II Pro™ RocketIO™ serial transceivers are devices to further your cost savings. implemented on the industry’s most widely adopted FPGA fabric, including high-speed DSP and processing for the complete solution. Our extensive SERIAL DESIGN MADE EASY library of serial IP cores and reference designs supports all major standards. Take advantage of our in-depth serial training courses, complete with The reconfigurability of the Platform FPGA can dynamically accommodate development and characterization boards, transceiver characterization data, any spec changes. And together with industry leading partners such as hands-on labs, and dedicated web portal. Ride the Serial Tsunami today. Mentor and Cadence, Xilinx provides all the tools and training you need. Visit www.xilinx.com/serialsolution.

The Programmable Logic CompanySM www.xilinx.com/serialsolution

©2003, Xilinx, Inc. All rights reserved. The Xilinx name, the Xilinx logo are registered trademarks. RocketIO and SelectIO, Virtex-II Pro are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks and registered trademarks are the property of their respective owners. NewNew RocketPHYRocketPHY TransceiverTransceiver FamilyFamily DebutsDebuts atat 1010 GbpsGbps A new family of 10 Gbps serial I/O transceivers dramatically cuts costs in light-speed applications. These transceivers make it possible to create unique optical connectivity designs.

by Robert Bielby dards such as PCI halted its traditional planes, as the performance limitations of Senior Director, Strategic Solutions Marketing approach of scaling bandwidth by dou- LVTTL signaling became too great. Xilinx, Inc. bling both bus width and frequency with The benefits of the SelectIO solution [email protected] the introduction of the 64-bit, 133 MHz were clear – high-performance signaling PCI-X node. PCB layout constraints technologies integrated on an FPGA plat- On May 5, 2003, Xilinx unveiled another restricted PCI-X to a bus width of 64 bits form that allowed for direct communica- key first in the programmable logic indus- while standard single-ended signaling tion with the higher speed I/O interfaces. try – the RocketPHY family of 10 Gbps technologies capped out at 133 MHz. With SelectIO technology, you could sim- CMOS Physical Layer (PHY) transceivers. With the introduction of PCI Express, the plify bridging between standards, eliminate Designed for a wide range of applications industry signaled the end of the parallel external transceivers, improve cost, and and markets including MAN, WAN, LAN, I/O era – serial signaling technologies are reduce board area, all the while delivering and SAN, the RocketPHY family repre- now becoming mainstream. higher performance I/O signaling. sents the next milestone in our commit- Xilinx has responded by delivering inno- Xilinx expanded upon the vision of pro- ment to supporting the imminent vative solutions that address these industry- viding integrated support for high-speed transition to serial signaling technologies. wide transitions. In 1999, Xilinx led the I/O signaling in subsequent FPGA families The Xilinx serial I/O technologies, charge with the introduction of the with the introduction of the Virtex-II and named the “Serial Tsunami Initiative,” are Virtex™ FPGA family. The Virtex family the more recent Virtex-II Pro™ families. causing a virtual tidal wave of new stan- introduced SelectIO™ technology, an The Virtex-II family opened up the reach of dards to emerge, bringing you the signifi- industry first, to support multiple I/O sig- high-speed I/O signaling through the inte- cant benefits of lower cost, lower power naling standards that were programmable gration of LVDS I/Os capable of operations consumption, reduced electromagnetic on a pin-by-pin basis. The Virtex family up to 622 MHz using a source-synchronous emissions, and simplified PCB design. provided direct support for a wide range of clocking topology. In conjunction with new high-performance I/O signaling tech- RocketIO™ technology, the Virtex-II Pro The Serial Tsunami Initiative nologies, including GTL, STTL, HSTL, family extended the I/O signaling capabili- Five years ago, it was clear that the tradi- and BTL. These standards were rapidly ties to 3.125 Gbps using CML-based differ- tional approach to scaling I/O performance gaining market acceptance in chip-to-chip ential serial signaling technologies with was reaching its limitations; industry stan- interfacing, memory interfacing, and back- integrated clock recovery.

20 Xcell Journal Summer 2003 Introducing RocketPHY Transceivers The latest in our comprehensive portfolio of high-speed serial I/O solutions is the RocketPHY family of Physical Layer transceivers. Designed on a standard 0.15 µm CMOS process, RocketPHY devices are the first Xilinx family of Physical Layer transceivers that support SONET-compliant jitter and are optimized for a wide range of 10 Gbps optical interconnect applications. The RocketPHY family of low-cost, low-power CMOS transceivers consists of three family members that support multi- rate operation from 9.9532 Gbps to 10.709 Gbps; they include a serializer/deserializer (SERDES), an inte- Figure 1 - RocketPHY is OC-192 jitter compliant grated clock multiplication unit (CMU), and clock/data recovery (CDR) circuitry. • 16-bit LVDS parallel interface compli- • Line and diagnostic loopback modes The parallel interface of the RocketPHY ant to OIF SFI-4 and IEEE 802.3ae • On-chip CML and LVDS termination family is directly compliant with Xilinx XSBI (3.3V supply) Virtex-II Pro FPGAs and other industry • Differential CML driver for PMD • Seamless interfacing to Virtex FPGA framers and media access controllers interface families and ASSPs via Versatile Parallel (MACs), through XSBI and SFI-4, 16-bit Interface differential LVDS interfaces. • FIFO to de-couple transmission clock – Back clocking mode (622 MHz or • Multi-rate 10 GHz transmit clock 311 MHz) RocketPHY Features output RocketPHY devices offer: – Forward clocking mode (622 MHz • Parallel interface bit order swapping or 311 MHz) • Multi-rate 9.9532 Gbps to 10.709 • Serial data polarity inversion Gbps integrated CMOS transceiver • Transmitter/receiver lock detection (on transmit) (MUX/DeMUX, CDR, CMU) • Three transmitter reference clock • 17 mm x 17 mm, 256-ball, fine-pitch, • SONET OC-192/SDH STM- modes with clean-up PLL plastic BGA package 64/Telcordia compliant – TX reference clock • CMOS manufacturing process – 9.9532 Gbps SONET data rate – RX recovered clock (line timing) • Power supplies: 1.8V and 3.3V – 155.52 MHz or 622.08 MHz refer- – TX parallel input clock – 1.5W typical power consumption. ence clock – Exceeds OC-192 jitter generation, RocketPHY Family Member Supported Standards Target Applications Parallel Interface jitter transfer, and jitter tolerance specifications, as shown in Figure 1 RocketPHY 10G Ultra MSATM SONET OC-192 MSA Modules XSBI SDH STM-64 XFP Modules SFI 4 • SONET FEC support G.709 10Gbs Ethernet – 10.709 Gbps data rate (G.709) 10Gb Fibre Channel

– 167.33 MHz or 669.325 MHz refer- RocketPHY 10G SONET/SDH OC-192 SONET/SDH-based SFI 4 ence clock SDH STM-64 transmission systems, ADMs • IEEE 802.3ae 10 Gigabit Ethernet Standard (Base R, W) compliant RocketPHY 10GbE/FC 10Gbs Ethernet Transmission equipment, XSBI 10Gb Fibre Channel NICs, test equipment, – 10.3125 Gbps data rate edge routers, storage, area networks – 161.13 MHz or 644.53 MHz reference clock Table 1 - RocketPHY family overview

Summer 2003 Xcell Journal 21 Applications Each of the three RocketPHY devices is optimized for specific applications as Memory shown in Table 1. A basic application Virtex-II Pro Virtex Interfacing block diagram is shown in Figure 2. Interfacing

SONET OC-192 and SDH STM-64 RocketPHY Framer NPU Physical MAC O/E Virtex-II Pro Backplane In SONET/SDH operation, the trans- Layer Virtex-II Pro ceiver connects to the SONET/SDH Transceiver framer via the parallel 16-bit LVDS Virtex-II Virtex-II interface. It receives and transmits Interfacing Interfacing Virtex-II Interfacing SONET-framed 16-bit words at a rate of Control Plane 622.08 Mbps. The 16-bit words are converted from/to a serial bitstream at Figure 2 - Basic RocketPHY application block diagram 9.9532 Gbps. An LVPECL reference clock of either 155.52 MHz or 622.08 OC-192 SONET Optical Module 16-bit MHz may be used (see Figure 3). LVDS Rx O/E Xilinx SONET 9.9532 Gbps Optical Transport Network Operations XGC1120 SFI-4* Framer (SONET + FEC) Tx O/E 16-bit In Optical Transport Network (OTN) LVDS operation for OC-192 applications, the *SFI-4 = SERDES Framer Interface per the Optional Internetworking Forum (OIF) for OC-192 SONET systems. Uses a 622.08 Mbps data rate on 16 LVDS channels. transceiver connects to the SONET/SDH framer via the parallel 16-bit LVDS inter- Figure 3 - SONET OC-192 and SDH STM-64 Application face. It receives and transmits SONET- framed 16-bit words at 669.325 Mbps. OC-192 SONET + FEC Optical Module 16-bit The 16-bit words are converted to a serial LVDS bitstream at 10.709 Gbps. An LVPECL Rx O/E Xilinx FEC/ 10.70926 Gbps reference clock of either 167.33 MHz or XGC1120 SFI-4* Framer 669.325 MHz may be used (see Figure 4). Tx O/E 16-bit LVDS 10 Gigabit Ethernet – *SFI-4 = SERDES Framer Interface per the Optional Internetworking Forum (OIF) for OC-192 SONET systems. Uses a 669.325 Mbps data rate on 16 LVDS channels. 10G Base-R and 10G Base-W Ethernet In 10G Base-R operation, the transceiv- Figure 4 - Optical Transport Network Operations (SONET + FEC) Applications er forms the PMA (Physical Medium Attachment), which is located below the 10GbE Optical Module PCS (Physical Coding Sublayer). It 16-bit LVDS receives and transmits 64B/66B encoded 10GBase-R Rx O/E Xilinx PCS/MAC data in 16-bit words at 644.53 Mbps. 10.3125 Gbps or XGC1120 XSBI* The serial data rate is 10.3125 Gbps. An 10GBase-W Tx O/E VAS/PCS/MAC LVPECL reference clock of either 16-bit 161.13 MHz or 644.53 MHz may be LVDS *XSBI = 10 Gbps 16-Bit Interface per IEEE 802.3a for 10 GbE systems. Uses a 644.53 Mbps data rate used. No frame detection or alignment on 16 LVDS channels. occurs. Figure 5 - 10 Gigabit Ethernet: 10G Base-R and 10G Base-W Ethernet applications In 10G Base-W operation, the transceiver forms the PMA, which is located below the WIS (WAN Interface 16-bit LVDS Sublayer). It receives and transmits SONET Rx Xilinx Framer 64B/66B-encoded and SONET scram- XFP 10GbE MAC Tx XGC1120 bled data in SONET-framed 16-bit 10GFC MAC 16-bit words at a rate of 622.08 Mbps. The LVDS operation is the same as that described Figure 6 - XFP and MSA module applications for SONET (see Figure 5).

22 Xcell Journal Summer 2003 provides continuous serial signaling support from 2 Gbps through 10 Gbps with an enhanced Physical Coding Sublayer (PCS) and CMU supplying extended support for telecom-based applications, including those requiring OC-48 SONET jitter compliance. Combined with the new RocketPHY family, Xilinx offers the broadest range of serial solutions address- ing the various connectivity hierarchies for a wide range of markets and applications (see Figure 8).

Conclusion Over the past five years, it has become evident that core logic performance Figure 7 - 300 MSA vs. XPF cost comparison has far exceeded the capabilities of traditional LVTTL signaling technologies. Furthermore, the approach to scaling I/O RocketPHY XFI bandwidth by simultaneously increasing 0C-192 frequency and bus width has also reached STM-64 TELECOM Virtex-II Pro X OTN G.709 its limitations, principally because of both 0C-4 8 cost and technical feasibility. Virtex-II Pro 10 GFC Through the introduction of innova- 1 G FC 2 G FC STORAGE Serial ATA Infiniband tive products such as the Virtex FPGA family and its subsequent generations, 1 GbE 10 GbE NETWORKING Xilinx has been able to provide solutions XAUI BACKPLANE Proprietary Aurora Proprietary Aurora X that address the ever-changing landscape

Serial DATA & CONTROL PLANE of I/O signaling and interfacing. The Rapid I/O PCI Express more recent trend in the industry, serial signaling, has not gone unnoticed; with 622 Mbps 3.125 Gbps 10.709 Gbps the introduction of Virtex-II Pro and Figure 8 - Seamless serial solutions from 622 Mbps to 10 Gbps Virtex-II Pro X FPGAs, Xilinx has demonstrated technical and market lead- 10G Fibre Channel and The XFP standard promises to offer half ership in delivering seamless solutions for Proprietary Designs the size, one-third the cost, and one-fifth serial signaling applications ranging from The RocketPHY transceivers support pro- the power requirements; it will serve to 622 Mbps to 10 Gbps. prietary applications with serial data rates further fuel the 10 Gbps optical revolu- Now, with the introduction of the ranging from 9.6 Gbps to10.709 Gbps, in tion, as seen in Figure 6. XFP not only RocketPHY family of Physical Layer trans- addition to emerging standards such as defines the dimensions of the optical mod- ceivers, Xilinx is further expanding its 10G Fibre Channel. The transmit reference ule itself, but also a standard signaling range and breadth of serial solutions by clock can be either R/16 or R/64 where R interface called XFI, ensuring interoper- delivering the FPGA industry’s first 10 is the serial data rate. ability with industry-standard Physical Gbps, OC-192 SONET-compliant trans- Layer transceivers. The RocketPHY family ceiver optimized for multi-market optical XFP – The Future of 10 Gbps is compatible with both XFP and MSA transceiver applications. With this line up, Optical Networking optical modules standards (see Figure 7). Xilinx is delivering a suite of serial solu- One of the latest innovations occurring in tions that are unparalleled in the industry. the optical module market is the transition Virtex-II Pro X – For additional product details, see from the relatively large, costly, 300-pin, RocketPHY Technology Built-in www.xilinx.com/phy/. multi-source agreement (MSA) optical Xilinx will also introduce the new Virtex- For applications, block diagrams, modules to a new, lower-cost, smaller II Pro X architecture in May 2003, with demonstration boards, intellectual proper- form-factor optical transceiver named integrated 10 Gbps RocketIO SERDES ty, and other solutions for RocketPHY “XFP” for 10 Gbps Form-Factor Plugable. support. The Virtex-II Pro X SERDES applications, see www.xilinx.com/esp/.

Summer 2003 Xcell Journal 23 by Derek R. Curd APG Technical Marketing Manager Xilinx, Inc. [email protected]

Accelerate Your The shift to high-speed serial I/O technology has enabled designers to push the performance of systems well beyond that of traditional parallel bus-based architectures. Multi-gigabit serial links are capable of transmitting data at substantially Multi-Gigabit greater speeds, with significantly lower power, and with a fraction of the pins required for system-synchronous (common clock) or source-synchronous (clock forwarding) schemes. However, with all the advantages of Serial Design serial I/O technology, you must address a number of new design challenges when The Xilinx “Adaptive I/O” solution enables rapid prototyping, integrating high-speed serial links into your design. Board design, for example, enhanced diagnostic testing, and in-system performance becomes a more involved issue when deal- ing with signal integrity and transmission optimization for high-speed serial I/O designs. line effects of multi-gigabit serial signals. In addition, standards compliance and interoperability testing require new characterization techniques and additional resources during the development process. The Xilinx “Adaptive I/O” solution for the Virtex-II Pro™ family of Platform FPGAs gives you the power and flexibility to meet these serial I/O design challenges head-on. Leveraging the combination of the RocketIO™ multi-gigabit transceivers (MGTs) and the IBM PowerPC™ 405 embedded processor core, the Adaptive I/O solution gives you the performance and system-level management functions you need to accelerate the development of your high-speed serial design. The solution is delivered in the form of three pre-engineered reference designs that can be easily integrated into your existing design environment to provide rapid prototyping ability, enhanced characterization and diagnostic testing, and in-system performance optimization of your high-speed serial links. Although the reference designs take advantage of the integrated processor in the Virtex-II Pro device, no PowerPC or C-programming expertise is required to use the Adaptive I/O solution.

24 Xcell Journal Summer 2003 Multi-Gigabit Signal Integrity MGT transmitter and receiver. The PCS table through the RocketIO primitive Designing with multi-gigabit serial I/O interfaces with the FPGA fabric and man- attribute TX_DIFF_CTRL. The peak-to-peak technology requires greater attention to ages encode/decode functions, clock syn- swing at the output of the MGT transmit- issues that affect signal integrity, such as chronization, clock correction, and channel ter can be varied from approximately 400 attenuation, noise, and reflections. At bonding operations. mV to 800 mV (800 mV to 1600 mV multi-gigabit frequencies, board traces peak-to-peak differential) in increments of behave like transmission lines, introducing 100 mV. Adjusting the swing control level the need for a more detailed understanding gives you the flexibility to meet the require- Short Trace of the signal topologies and characteristics ments of a wide range of serial I/O stan- of the transmission medium. Jitter effects, dards and ensures interoperability with dielectric losses, and impedance matching many other devices over a variety of signal issues must all be carefully considered to lengths and topologies. ensure reliable data transfer across a serial Long Trace link at the intended baud rate. Programmable Pre-Emphasis Serial I/O technology provides benefits at High-speed serial signals experience signifi- various levels within a system, enabling the cant attenuation (signal loss) due to the “skin creation of high-speed links from chip to effect” and dielectric losses of the transmis- chip, board to board, and box to box. sion medium, particularly over longer dis- Clearly, signal topologies and even the trans- tances. Pre-emphasis is a technique whereby mission medium can vary significantly the highest-frequency components of the depending on the type of application. The Figure 1 - The backplane distance dilemma serial signal are boosted to compensate for complexity of the design challenge and level of signal integrity analysis required will also vary accordingly. For example, transmitting PCS PMA over several feet of coaxial cable presents different challenges than transmitting over a From FPGA Transmit TX+ Fabric TX DATA CRC 8B / 10B FIFO Serializer few inches of FR4 laminate board. Encode Buffer TX- Consider the example of a serial back- TX Clock Generator plane (Figure 1) in which the distance a signal must travel can change substantially REFCLK 20X Multiplier depending on which slot a board is plugged Channel Bondry CRC and into. The signal attenuation and determin- Clock Connection RX Clock Generator istic jitter imposed on the longer backplane To FPGA Elastic 8B / 10B Recieve RX DATA Deserializer RX+ trace will be greater than on the shorter Fabric Buffer Decode Buffer RX- trace. In scenarios such as this, it is often (digital) (analog) desirable to modify or “tune” the drive characteristics of the MGT transmitter to match the characteristics of a particular Figure 2 - RocketIO multi-gigabit transceiver signal path, ensuring the highest possible signal quality and reliable recovery of the Among the list of other common these losses, significantly extending the dis- data at the receiver end. SERDES functions, there are two pro- tance the signal can be reliably transmitted grammable features contained within the over a given type of conductor. Solving the Backplane Dilemma MGT blocks to optimize transmission over Virtex-II Pro MGTs have four levels of The RocketIO MGTs in Virtex-II Pro a wide variety of signal topologies and programmable pre-emphasis (from 10% to devices include many advanced features to transmission media: 33%) selectable through the RocketIO simplify the development of serial I/O-based primitive attribute TX_PREEMPHASIS. At • Programmable differential swing control systems. The MGT blocks are composed of maximum pre-emphasis, RocketIO MGTs two distinct sub-blocks (Figure 2): the phys- • Programmable pre-emphasis. are capable of transmitting a 3.125 Gbps ical media attachment (PMA) block and the serial signal error-free over more than 40” physical coding sub-layer (PCS) block. The Programmable Differential Swing of standard FR4 printed circuit board PMA is responsible for the serialization and Control material (Figure 3). deserialization (SERDES) of the data stream Virtex-II Pro MGTs have five levels of pro- The Adaptive I/O solution solves the as well as the actual physical interface for the grammable differential swing control selec- backplane dilemma by giving you the abil-

Summer 2003 Xcell Journal 25 ity to dynamically adjust the programma- The MGT attribute settings for each slot PLB-attached universal asynchronous ble swing control and pre-emphasis levels ID value are predefined with simple modi- receiver transmitter (UART). Using a stan- of the MGTs in response to changing sig- fications to a “C” file array structure. The dard serial cable connection to a PC, the nal topologies, while leaving the rest of the end result is that the MGTs can adapt to up UART can communicate with a simple PC FPGA design unchanged. For example, to 16 different signal topologies automati- terminal program such as Hilgraeve Inc.’s referring again to Figure 1, the Virtex-II cally and provide optimal signal transmis- HyperTerminal, giving you the ability to Pro MGT transmitter can be automatically sion without the need for separate control the bit-error rate testing from your configured to have different swing control bitstreams. The use of the PowerPC 405 keyboard and see the test results continu- and pre-emphasis settings in response to core to manage the MGT attribute modifi- ously updated on your PC screen. the changing trace length associated with cations results in a very resource-efficient Using the results from the XBERT each slot location. design. The total solution consumes only module, a practical bit-error rate (for 67 slices (about 2% of an XC2VP4 device), example, < 10-12) can be calculated for and can thus be easily integrated into your multi-gigabit serial links. And, almost any Virtex-II Pro design. because the XBERT is a soft implementation built from FPGA logic resources, it Enhanced Characterization and can be used for characterization or diag- Diagnostic Testing nostic testing and then removed from the In addition to managing the signal integri- final design. The XAPP661 reference ty aspects of multi-gigabit serial I/O design solution gives you the ability to design, significant time and resources can perform sophisticated bit-error rate test- be spent on standards compliance, inter- ing more efficiently and at a fraction of operability testing, and general characteri- the cost of other solutions. Figure 3 - 3.125 Gbps over 44” zation of the serial links during the of FR4 with 33% pre-emphasis development process. Furthermore, multi- Putting It All Together gigahertz oscilloscopes, bit-error rate test The XAPP660 reference design provides the Application Note XAPP660 (www.xil- (BERT) modules, and other required test ability to automatically adapt the MGT inx.com/xapp/xapp660.pdf), with complete equipment can quickly consume a good transmitter attributes to meet changing sig- reference design files, provides you with an portion of your program budget. nal topologies or other system requirements. entirely self-contained solution for dynam- The Adaptive I/O solution again offers And XAPP661 enables enhanced character- ic configuration of the MGT swing control a pre-engineered solution for simplifying ization or diagnostic testing of serial links and pre-emphasis attributes (Figure 4). The the development and reducing the with an interactive user interface. PowerPC 405 core is used to perform overall cost of MGT-based designs. However, the Adaptive I/O solution reconfiguration of the MGT attributes via Application Note XAPP66 (www.xilinx.com/ takes things one step further. Application the internal configuration access port xapp/xapp661.pdf), with associated reference Note XAPP662 (www.xilinx.com/xapp/ (ICAP), an interface similar to SelectMAP, design files, describes the Xilinx bit-error rate xapp662.pdf) combines the XBERT char- which allows the FPGA configuration logic test (XBERT) module for enhanced charac- acterization module of XAPP661 with the to be accessed over general interconnects terization and diagnostic testing (Figure 5). MGT partial reconfiguration capability of inside the device. The XBERT module includes a pattern gen- XAPP660 to provide a complete MGT After power-up and initial configura- erator capable of generating eight different development platform for real-time per- tion with a base FPGA design, the pseudo-random bit sequence (PRBS) pat- formance optimization, adaptive system PowerPC processor reads a 4-bit slot ID terns as defined by ITU-T (International calibration, and field diagnostic testing. register to determine the swing control Telecommunication Union-Standardization The XAPP662 reference design adds an and pre-emphasis settings that should be Sector) Recommendation 0.150. It also ICAP controller interface to the internal PLB assigned to each MGT for the given sig- includes a built-in error detector and of the system described in XAPP661, adding nal topology. The PowerPC core then frame/bit-error counters for tracking the the ability to modify the MGT differential modifies the MGT attributes by manag- total number of transmitted frames and total swing control and pre-emphasis settings during a partial reconfiguration of select con- number of associated bit-errors. ing characterization and diagnostic testing figuration bits over the ICAP interface, The XBERT module is controlled and (Figure 6). Using a standard intellectual leaving the rest of the FPGA design monitored by the PowerPC core over the property interface (IPIF) module available unchanged. processor local bus (PLB) interface. In from Xilinx, the ICAP controller module is The slot ID can be a static code deliv- addition, the PowerPC core reads the status easily integrated into the PLB-based system. ered from the backplane or a dynamic value of the frame and bit-error counters and With this solution, you have the power driven by internal logic or another device. then transmits this information to the to perform an iterative loop, alternating

26 Xcell Journal Summer 2003 between MGT attribute changes and bit- testing of your MGT serial links. any PLB- or OPB- (on-chip peripheral bus) error rate testing through a command line Portions of the XAPP662 reference based system to provide MGT attribute interface on your desktop PC. The end design can also be easily integrated into reconfiguration under control of the result is a complete solution for real-time your final design. The IPIF-to-ICAP inter- PowerPC core. This can be a preferred solu- performance optimization and reliability face module, for example, can be used in tion to XAPP660 for systems that already incorporate a PLB or OPB bus structure. In addition, any in-system communication link can interface to the on-chip UART, introducing the possibility of remote system upgrade or field diagnostic testing. DSOCM Managing the Product Life Cycle PPC 405 Together, the three components of the

DCR bus DMA Xilinx Adaptive I/O technology provide Engine ICAP you with solutions to help you manage your ISOCM high-speed serial systems in all phases of the DCR Register

++ product life cycle. In the development Slot ID (4-bits) -- MGT ++ -- phase, the ability to perform real-time per- 3.125 Gb/s formance optimization with interactive Serial Link control over MGT attributes and the Figure 4 - Dynamic reconfiguration of MGT differential swing control and pre-emphasis attributes XBERT module provides you with rapid prototyping and efficient characterization. In your fielded production design, the

User MGT partial reconfiguration controller of Interface UART XAPP660 or XAPP662 gives you the power to automatically adapt your MGT transmitter characteristics in response to BRAM Instruction I-Cache & Data different signal topologies or changing sys- PPC 405 tem environments on the fly. This ensures D-Cache that every link is optimized for performance and minimum bit-error rate without the need for multiple bitstreams or external PLB

++ XPERT -- components. Core Connect ++ MGT -- IPIF Module Lastly, the Adaptive I/O solution gives 3.125 Gb/s Serial Link you the ability to perform in-field system calibration or diagnostic testing to ensure Figure 5 - XBERT module for enhanced characterization and diagnostic testing your end product is maintained for maximum reliability and performance.

User Interface Conclusion UART The Xilinx Adaptive I/O solution enables rapid prototyping, enhanced characteriza- BRAM Instruction tion, and in-system performance optimiza- I-Cache & Data PPC tion of your multi-gigabit serial I/O 405 designs. The combination of RocketIO D-Cache ICAP MGTs and the IBM PowerPC 405 core IPIF provides you with a complete platform for

PLB developing, optimizing, and delivering ++ XPERT --

Core Connect ++ MGT -- world-class, high-speed serial solutions. IPIF Module 3.125 Gb/s To learn more about the three reference Serial Link designs that make up the Adaptive I/O Figure 6 - Complete platform for real-time optimization of MGT serial links solution, visit www.xilinx.com/search/ vsearch.htm.

Summer 2003 Xcell Journal 27 by Bill Okubo Solutions Marketing Manager, Global Services Xilinx, Inc. High-SpeedHigh-Speed SerialSerial [email protected] With the tremendous increase in connectivity bandwidth requirements, our industry is experiencing a rapid move InterfaceInterface Design:Design: away from parallel interface architectures toward high-speed multi-gigabit serial standards. Serial interfaces will ultimately be deployed in nearly every electronic product LearnLearn Fast,Fast, imaginable – including chip-to-chip interfacing, backplane connectivity, system boards, and box-to-box communications. Serial interfaces reduce system costs, simplify system design, and provide scalability FinishFinish FasterFaster to meet new bandwidth requirements. These emerging technologies sometimes XilinxXilinx GlobalGlobal ServicesServices providesprovides youyou withwith thethe skills,skills, courses,courses, require special knowledge in order to create high-speed serial I/O solutions – skills and andand informationinformation neededneeded toto meetmeet thethe designdesign challengeschallenges ofof FPGAFPGA experience that may be new to traditional programmableprogrammable systemssystems thatthat interfaceinterface embeddedembedded processorsprocessors programmable logic designers. Service organizations play an increasing- withwith multi-gigabitmulti-gigabit serialserial transceivers.transceivers. ly important role in providing the knowledge about programmable systems needed to solve high-performance architectural challenges. To ensure the success of design teams, while keeping overall cost down, Xilinx Global Services offers a complete portfolio of services for the Virtex-II Pro™ FPGA family. Xilinx Education Services, Xilinx Design Services (XDS), and support. xilinx.com all provide the experience and skills to help you successfully develop high- speed serial solutions and embedded systems, as well as FPGA logic design.

Designing with RocketIO Transceivers High-speed serial I/O channels can replace parallel buses in many systems and will result in lower overall costs – if designed correctly. These channels can significantly reduce board space and simplify board design while freeing I/O resources for other applications. To teach you how to create these high-speed serial designs efficiently, Xilinx provides training designed to reduce significantly the rigors of getting up to speed on this new technology.

28 Xcell Journal Summer 2003 Designing with RocketIO Multi- Gigabit Transceivers is a two-day course that teaches how to fully utilize RocketIO™ transceivers in Xilinx Virtex- II Pro FPGAs. By mastering the details of high-speed serial designs, you learn to develop fast and efficient serial interfaces that will operate flawlessly. In addition to classroom instruction, more than half of this class is taught in the lab, where you learn how to efficiently synthesize, implement, and debug designs. Designing with RocketIO Multi- Gigabit Transceivers teaches you the skills necessary to: • Fully utilize the ports and attributes of RocketIO transceivers • Effectively use advanced RocketIO features such as CRC, channel bonding, clock correction, comma detection, 8b/10b encoding, programmable termination, and pre-emphasis • Use the Architecture Wizard to instantiate RocketIO primitives in designs distance of the link. Partial reconfigura- you use, such as data sheet updates for • Achieve compatibility with high-speed tion offers you a way to avoid storing mul- Virtex-II Pro FPGAs. I/O standards using RocketIO tiple bitstreams on a system, allowing each Tech Tips for RocketIO is a new sup- system’s RocketIO configuration to be port tool that includes information such as: • Recognize and understand the data personalized using either on-board streams of popular communications switches or software control. Partial • RocketIO FAQ standards such as Gigabit Ethernet and reconfiguration can also be used to switch • Documentation about RocketIO PCI Express. a RocketIO channel from one physical • Top Answers for RocketIO. standard to another without any service Xilinx Design Services Has RocketIO Expertise disruption on the unaffected channels. Designers who work with Virtex-II Pro In addition to providing partial recon- Conclusion FPGAs need to know with certainty that figuration under software control, XDS has Before you start your next high-speed the RocketIO multi-gigabit transceivers embedded software expertise to help you serial design, save yourself time and effort (MGTs) will perform according to their deliver fully integrated and dynamically by taking advantage of the skills and specific requirements. To allow the meas- configurable systems. XDS can help you experience offered by Xilinx Global urement design parameters such as bit-error develop the high-level communications Services. Learn more about the services rate, latency, and resynchronization time, protocol for FPGA programmable logic available for RocketIO MGTs at: and physical-layer characterization involves and embedded software. www.support.xilinx.com/support/gsd. the building and reuse of embedded hard- The course description for Designing ware and software systems on Virtex-II Pro Web-Based Tech Tips with RocketIO MGTs is available at: FPGAs. XDS has experience with and A comprehensive support resource is www.support.xilinx.com/support/training/ access to various Xilinx characterization essential to fast design cycles and first-time abstracts/rocketio.htm. boards to carry out such measurements. success for a new serial I/O design. For information about the serial I/O Experience with partial reconfiguration Available 24/7, support.xilinx.com has expertise of Xilinx Design Services, see: of RocketIO MGTs is also important online information on the latest down- www.support.xilinx.com/xds. when you’re designing Virtex-II Pro loads, techXclusives, and other recent sup- FPGAs. For example, electrical transmis- port-related news. MySupport.xilinx.com RocketIO Tech Tips are available on sion characteristics commonly vary from can be personalized so that you see only support.xilinx.com at: www.support. serial link to serial link depending on the the information related to the devices that xilinx.com/xlnx/xil_tt_home.jsp.

Summer 2003 Xcell Journal 29 Kit for Cadence SPECCTRAQuest Tools Speeds RocketIO Designs Instead of taking weeks, you can now create and verify gigahertz-speed serial links on PCBs in days.

Unique Features The RocketIO Design Kit for SPECCTRA- Quest allows you to develop optimal constraints for PCB systems. The constraints drive the PCB floorplanning, routing, and verification process. The RocketIO Design Kit for SPECCTRAQuest includes:

• Ready-to-simulate system-level topologies for typical use of the device on the board/system • Verified I/O buffer models • Large package model • Test-bench and correlation data • Connector models for backplane applications • Device-specific scripts and tools to evaluate simulation results • Instructional video describing how to get by Xcell Staff and verify gigahertz-speed serial links started with the design kit. quickly. Operating within the Cadence More than 500 designers and engineers SPECCTRAQuest Signal Integrity have downloaded the Xilinx RocketIO™ Expert environment, the kit is a proven Design Kit for Cadence Design Systems’ approach for characterizing the interac- Price and Availability SPECCTRAQuest™ design and analysis tions between the Xilinx Platform FPGA The RocketIO Design Kit for environment for high-speed digital sys- and the rest of the system. SPECCTRAQuest is provided free to Xilinx tems. Customers have clearly been pleased The design kit is the result of an customers who have signed the appropriate with the kit’s results in shortening time-to- alliance between Xilinx and Cadence to non-disclosure agreement. More informa- market and reducing costs. help you exploit the capacity and perform- tion is available at www.support.xilinx.com/. The design kit helps reduce the time ance of the Xilinx Virtex-II Pro FPGA The Cadence SPECCTRAQuest Signal needed to implement Virtex-II Pro™ family. “Our customers’ ability to quickly Integrity Expert product starts at a U.S. list RocketIO transceivers because it takes design-in the Virtex-II Pro Rocket IO price of $24,200 for a one-year license. For advantage of concurrent design efficiencies technology is critical,” said Rich Sevcik, pricing outside of North America, contact using technologies that address silicon, senior vice president and general manager your local Cadence office or distributor. package, and board design. of FPGA products at Xilinx. “By working More information regarding other Serial The kit acts as an electronic blueprint with Cadence, we can minimize the Tsunami design resources is available at that enables you to create, implement, design-in time for our mutual customers.” www.xilinx.com/serialsolution.

30 Xcell Journal Summer 2003 good information, right under your nose.

It’s a never-ending cycle: Every new generation of processors and buses means a new need for speed—in your customers and in you. As edge rates go sub-nanosecond and schedules get shorter, signal integrity problems get tougher just when you need to solve them faster and with fewer compromises. Perhaps we can help.

Working with designers around the world, we’ve seen scope probe loading lead many people down a wrong road. Probe impedance varies with frequency, so it can cause errors in bias, amplitude, offset, rise time and propagation delay. The circuit may even stop or start whenever you connect the probe.

You can reduce or eliminate these problems with an active probe, which provides high resistance, low capacitive loading, a flat response—

Eye displays in a logic analyzer can show voltage and and a more accurate view of what’s really happening in your circuit. time data from multiple channels simultaneously, helping you spot sub-nanosecond problems in much less time Sharing tips like this is just one of the ways Agilent can help you than conventional methods. find the causes of signal integrity problems now and design them out next time.

There’s more where this came from at www.agilent.com/ find/moresi, where you can download application notes about probing, normalization, de-embedding and more, www.agilent.com/find/moresi order a CD-ROM, and attend a series of FREE signal u.s. 1-800-452-4844, ext. 1000 canada 1-877-894-4414, ext. 7728 integrity eSeminars.

©2002 Agilent Technologies ADEP3471209 We cannot solve Software-Compiled our problems with the same thinking System Design Optimizes we used when Xilinx Programmable we created them. – Albert Einstein Celoxica and Xilinx have partnered Systems to fine-tune software-compiled by Chris Sullivan system design for the benefit of Director of Strategic Alliances Celoxica, Ltd. designers using Virtex-II Pro and [email protected] MicroBlaze programmable systems. Milan Saini Technical Marketing Manager Xilinx, Inc. [email protected]

Okay, so none of us will claim to be Einstein, but programmable system design might be the next development challenge we face. With the advent of the Xilinx Virtex-II Pro™ Platform FPGA and the MicroBlaze™ soft processor, we now have access to unrivalled levels of product flexibility and performance. This technology – for the first time – enables us to partition and re-partition systems between hardware and software at any time during the development cycle. We can even re-partition the hardware and software mix after the product has gone to market. This complete reprogrammability means the system can be optimized over and over again. But for design teams looking to use this powerful technology, system design can be a challenge. Exploring whether a design is even feasible can cost many months of time, effort, and expense, let alone finding the optimal design. And if system verification does not begin right from the start, projects can miss their specifications or take too long to get to market – reducing your ability to compete, your business credibility, and your all-important bottom line. It’s a design headache you don’t need.

32 Xcell Journal Summer 2003 Meeting the Design Challenge • Demonstrate a complete A remedy for this headache is the system verification flow synergy of software-compiled • Deliver competitive Quality system design and programmable of Results (QoR) systems technology. Software- compiled system design is a • Exceed time-to-market methodology that provides a expectations seamless bridge between hard- • Support design re-use ware and software (Figure 1). It strategies enables the system partition, verification, and hardware/software • Maximize current EDA co-design to be driven directly and IP investments. from the system specification. Software-compiled system design Project Plan was specifically developed for Phase 1: Profile and verify programmable systems and pro- Phase 2: Partition and verify vides an efficient, cost-effective, and quality driven co-design Phase 3: Design and verify solution. Phase 4: Implement and verify

Software-Compiled System Design Tools At the heart of software- • Celoxica Nexus PDK compiled system design is the • Celoxica DK Design Suite principle of providing a direct • Wind River Xilinx Edition link between the programmable Figure 1 - Software-compiled system design flow toolset platform and the originally • Xilinx ISE 5.1i defined system functionality. This provides the necessary system verification flow and offers confidence to JPEG 2000 is a standards-based image Phase 1: Profile and Verify the designer who wants to fully explore the coding system that uses state-of-the-art A multitude of applications can benefit design space – pushing the envelope of design compression techniques based on wavelet from hardware acceleration and product innovation and product differentiation. technology (Figure 2). Its architecture flexibility. To demonstrate this, we selected The methodology also deploys novel lends itself to a range of uses from con- JPEG 2000; our starting point for the technology that permits more informed and sumer electronics, such as digital cameras, design was the C specification code. flexible hardware/software partitioning. This to medical imaging, remote sensing, sur- To drive our system verification flow, we enables tradeoff analysis, partition and re- veillance systems, and scanners. ran the specification code through an partition at any stage in the design, and by appropriate target – in this instance the using higher level languages (HLLs) for both Project Specifications IBM PowerPC™ 405 GP. From this we hardware and software design, the methodolo- • Maximize overall system performance simulated and verified the functionality of gy allows the system specification to be written • Innovate and differentiate from the our system and established a test bench in a form that both teams can immediately use, competition that remained constant and consistent without costly and time-consuming rewrites. throughout the design. • Demonstrate an efficient and effective We then began code profiling to estab- co-design environment So Prove It lish where our program spent its time and To demonstrate the capabilities of software- • Use software specification as a starting determine which functions called other compiled system design, Celoxica and Xilinx point for system design functions during execution. We found partnered to undertake the co-design of a profiling was useful, as it quickly identi- • Improve communication between JPEG 2000 codec (compressor/decompres- fied the functions in a program that were hardware and software design teams sor) for implementation in a Virtex-II Pro processor hungry or compute intensive. FPGA. In particular, we wanted to address • Simplify partitioning and migration of That made them possible candidates for the design challenge of system partitioning, code between software and hardware offload into the FPGA fabric. However, co-verification, and the easy integration of for better overall Quality of Design the profiling does not analyze dataflow hardware and software. (QoD) between hardware and software, nor burst

Summer 2003 Xcell Journal 33 hardware/software integration, the DSM Original Pre processing RGB to YUV Wavelet allows the designer to iteratively explore, Image Conversion Transform test, and verify multiple partition alternatives. The designer can quickly create and

Rate easily move ports that are used to send data Control between the software and hardware by using the API standard (Figures 5 and 6). Tier-1 Coded Quantization Tier-2 100100001110010 As each option is explored, the designer can Encoder Encoder Image verify the partitioning with the software Figure 2 - Top-level block diagram for JPEG 2000 operation used as a test bench throughout the project. In our project, the DSM validated the profiling information determined in Phase length or frequency, so designer intervention designer to confidently explore and innovate 1 of our design flow. It helped analyze the is mandatory to understand the dynamics of in the design space, analyzing hardware/soft- data flow and the burst length and fre- our hardware/software interaction. ware tradeoffs, and identifying the optimal quency between our hardware and soft- Using Wind River’s WindView™ visual- system partition for the best QoD. ware, and fine-tuned the partition to meet ization and diagnostic tool, we determined Facilitating this is the data streaming the project’s criteria. Moreover, the DSM’s that the DWT (discrete wavelet transform) manager (DSM), a portable co-design API inherent portability meant the design and Tier 1 encoder were the processor-inten- (Figure 4) supplied with Celoxica’s DK could be repartitioned at any stage in the sive functions, consuming 87% of processing Design Suite. Developed specifically for design flow, redefining the system archi- time (Figure 3). We selected them for further programmable system partitioning and tecture and easily accommodating late scrutiny and tradeoff analysis. specification changes.

Phase 2: Partition and Verify Phase 3: Design and Verify Validating the system partition With the optimal partition deter- against the requirements of the mined and verified, we began the design specification is cardinal in design optimization phase of our programmable system design. project. Software-compiled system Typically the system designer design makes use of HLLs for both maps a system-level architecture hardware and software design. into specific hardware and soft- HLLs allow the system specifica- ware components, making direct Figure 3 - WindView trace of tion to be written in a form that reference to the project specifica- entire JPEG 2000 algorithm both the hardware and software tion and factors such as compo- teams can immediately use – with- nent availability, cost, and out costly and time-consuming technical feasibility. rewrites. Additionally, HLLs sim- The consequences of the sys- plify the migration of code between Handel-C Application Handel-C Application tem partition cascade through the hardware and software. Because design flow to physical implemen- FPGA there is a common language base tation and final system perform- and common level of abstraction Hardware DSM Library ance is greatly dependent upon between the hardware and software, partitioning decisions. It makes Hardware Bus Controller there is improved communication little sense to invest time, money, and shared understanding between and effort optimizing and refining Interface the development teams. an incorrect partition – it is inher- As we did in our partitioning ently sub-optimal. Software Bus Controller phase, we used the DSM through- Uniquely, software-compiled Software DSM Library out the design optimization phase. system design provides the designer The DSM provided a functionally with a flexible partitioning capabil- Processor accurate simulation environment ity that permits partition and re- Software Application Software Application that allowed our hardware and soft- partition at any stage in the design ware to interact – keeping them process. Moreover, it is linked to a connected throughout design opti- verification flow that enables the Figure 4 - DSM portable codesign API mization (Figure 7).

34 Xcell Journal Summer 2003 The software was run as a native exe- cutable on the PPC 405 GP, and the Step 1: Port the software code to hardware: “initialize_coder()”, from MQ coder hardware was run using the simulation and debugging capability of Celoxica’s Software “C” code Hardware “Handel-C” code DK Design Suite. We used a utility pro- my_32bit initialize_coder (mq_coder_state *mq_coder) macro proc initialize_coder (mq_A, mq_B, mq_C, mq_CT) { { mq_coder->A = 0x00008000; par // execute statements in parallel gram to monitor the data passing mq_coder->C = 0x00000000; { mq_A = 0x00008000; if (mq_coder–>B == 0xFF) mq_C = 0x00000000; between the applications to assist with mq_coder–>CT = 13; else if (mq_B == 0xFF) debugging. Because all of the API func- mq_coder–>CT = 12; mq_CT = 13; else return 0; mq_CT = 12; tions were provided, this allowed com- } } } plete system development to begin – without the development platform being available. Once we got it working, the Figure 5 - Porting software to hardware application was easily transferred to the target platform for final testing. Co- simulation between hardware and soft- Step 2: Create a DSM interface to transfer and verify data: ware was made possible by connecting Software “C” code Hardware “Handel-C” code DK with the Tornado™ environment my_32bit DSMinitialize_coder(mq_coder_state // local registers from Wind River (Figure 8). *mq_coder) DsmWord mq_A, mq_B, mq_C, mq_CT; { int Count; while (1) As our system specification was DsmWord Values[3]; // registers for I/O to HW { // read mq_coder–>B from software // set up data to send to hardware: DsmRead (PortS2H, &mq_B); described in ANSI-C, we progressed our Value[0] = (DsmWord) mq_coder–>B; // call Handel–C macro to do the work... // send data to hardware initialize_coder(mq_A, mq_B, mq_C, mq_CT) design in ANSI-C and used hardware lan- DsmWrite (PortS2H, Value,1, &Count); // write mq_coder–>A,C,CT back to software // read data back from hardware DsmWrite(PortH2S,mq_A); guage extensions defined in Handel-C to DsmRead (PortH2S, Value,3, &Count); DsmWrite(PortH2S,mq_C); DsmWrite(PortH2S,mq_CT); mq_coder–>A = Value[0]; } describe our hardware. These hardware mq_coder–>C = Value[1]; mq_coder–>CT = Value[2]; extensions enable, for example, efficient return 0; } control over area, timing, clocks, RAMs, ROMs, and interfaces. Figure 6 - Setting up the DSM interface to test and verify partition alternatives Combining multiple DSM calls, we made optimizations to the software. And we applied hardware optimization techniques, such as increasing parallelism, Hardware code Software code replacing for() loops with while() loops, optimization optimization pipelining, and syntax duplication. E.g., pipelining HW SW E.g., combining to increase DSM multiple DSM calls throughput into single call Specification Change At this stage in the design, a specification Figure 7 - Functionally accurate simulation environment change was introduced. A novel lifting algorithm was developed that performs a two-dimensional DWT and thus provides faster processing time. The algorithm was readily available as a HDL IP block, and we decided, with respect to design time and maximizing IP investment, to integrate the IP into the design as a black box. The integration was simplified by using the interface declaration available in Handel-C for connecting third-party IP into a software-compiled system design flow (Figure 9).

Phase 4: Implement and Verify Figure 8 - Co-simulation between Celoxica’s DK Design Suite and Wind River’s Implementation to the target platform was Tornado visualization and debugging environment simplified by using the platform abstraction layer (PAL). The PAL shields designers from

Summer 2003 Xcell Journal 35 low-level hardware interfaces, easing the integration of FPGAs with physical resources. This is done by developing a library of low-level interfaces to specific platform resources, such as I/O or memory. This library, called the platform support library (PSL), is then accessed by the hardware application on the FPGA using a simple and consistent application programming interface – the PAL API (Figure 10). The target platform was a Wind River Figure 9 - Interface declaration “black-boxed” HDL IP SBC405GP (single board computer refer- into a software-compiled system design flow ence design) with a Proteus FPGA daugh- ter card, effectively a Virtex-II Pro prototyping platform (Figure 11). This Handel-C Application Handel-C Application development environment supported timing simulation, emulation, and block opti- PAL-CORE PAL-CORE mization, and it was used prior to final implementation in a Virtex-II Pro ML300 Platform Abstraction Layer Platform Abstraction Layer Application Programming Interface Application Programming Interface Evaluation Platform (Figure 12).

Platform Support Library (PSL) PAL Sim Object code was compiled into the PPC405GP under Wind River’s Board Board VxWorks™ RTOS, with the hardware Peripheral 1 Peripheral 2 Peripheral 1 Peripheral 2 implementation using the direct EDIF out- Design quickly implemented in hardware for prototyping and timing verification Direct hardware implementation from Handel-C optimized for target device put generated by Celoxica’s DK Design Platform abstraction encourages application portability and supports strategies for design re-use Suite. This EDIF netlist was optimized for the Virtex-II Pro Platform FPGA (Figure Figure 10 - PAL block diagram 13), ensuring maximum efficiency for best QoR. Optionally, the DK Design Suite can also output RTL-level VHDL or Verilog, pre-optimized for traditional synthesis tool flows (Figure 14). Figure 11 - Virtex-II Pro

prototyping platform Results The results (Tables 1 and 2) from the Celoxica DK Design Suite were compared to the handcrafted VHDL authored by a JPEG 2000 domain expert. Handel-C’s systematic and ANSI-C-like Figure 12 - Virtex-II Pro approach to the problem led to substan- ML300 evaluation platform tial savings in design time. An expert Handel-C engineer with no prior knowledge of the JPEG 2000 standard was able to get the algorithm to a working hardware implementation in less than half the time it took to code the VHDL. The other key success we had was that the design was easily able to meet the system timing constraints. The results provide clear validation that design abstraction leads to increased designer productivity without necessarily compromising performance or area.

36 Xcell Journal Summer 2003 Conclusion Software-compiled system design is a Figure 13 - proven methodology for programmable Optimized EDIF system co-design. It provides a solution for output for Virtex-II system partitioning, co-verification, and Pro directly generated by the DK hardware/software integration across a Design Suite spectrum of design styles and applications. For use by all members of your design team, from the system architect to the verification engineer, software-compiled system design enables code sharing between hardware, firmware, and software designers from system specification through to implementation. The Celoxica DK Design Suite is a Figure 14 - Optional fully featured development toolset that VHDL/Verilog enables a complete implementation of a output from the software-compiled system design. It is DK Design Suite interoperable with popular third-party optimized to feed traditional syn- tools and languages and provides fast co- thesis flows simulation between C/C++, Handel-C, HDLs, instruction set simulators (ISSs), and modeling languages such as Open SystemC™ and MATLAB™. Software-compiled system design methodology offers you compelling benefits, and it is an efficient and effective design strategy for Xilinx programmable systems.

Celoxica 1st pass 2nd pass Final HDL Observations Slices 646 546 758 800 Comparable Device utilization 6% 5% 7% 7% Speed (MHz) 110 130 151 128 HC faster Lines of code 386 386 395 435 Design time (days) 6 7 (6+1) 7 (6+1) 20* HC quicker *Lena used as testbench throughout, *Doesn’t include input bit width 12, max 1k image partitioning spec. development Expert vs. Novice

Table 1 - Rapid Handel-C (HC) implementation for area efficiency Celoxica 1st pass Celoxica Final HDL Observations Slices 1.347 1.999 620 HDL smaller Device utilization 12% 18% 6% Speed (MHz) 89.5 115.5 76 HC faster Lines of code 310 330 800 Design time (days) 10 12 (10+2) 30* HC quicker Average cycles per code block 108 108 67.5 Processing time (per code block ms) 1.206 0.939 0.888 HDL faster Simulation time for Lena JPEG 5 mins 5 mins Hours Expert vs. Novice

Table 2 - Rapid Handel-C implementation for performance optimization *Doesn’t include partitioning spec. development

Summer 2003 Xcell Journal 37 TarariTarari andand CeloxicaCeloxica DeliverDeliver FastFast andand EasyEasy AlgorithmAlgorithm AccelerationAcceleration

Hardware acceleration speeds the entire design cycle, by Dale Riley Systems Engineer and the combination of Tarari’s Content Processing Platform Tarari, Inc. and Celoxica’s DK Design Suite makes it fast and painless. [email protected] Traditional methods of porting algorithms for hardware acceleration usually require many steps that are both difficult and time-consuming. The algorithms must be ported to a hardware language, simulated by themselves, and then proto- typed on FPGAs. During this prototype stage, the FPGA must also connect to the software environment. The complete task often requires a team of hardware engineers well-versed in FPGA development, another hardware engineer to develop the platform, and a software engineer to write the interfaces from software to hardware. In addition, software developers must wait for the hardware to be completed and tested before integration. Software developers can get a head start on developing and debugging software using the Tarari Content Processing Platform™ (CPP) and the Celoxica DK Design Suite to co-simulate the algorithm and quickly convert new or existing C code to hardware for significant acceleration. Celoxica’s C-to- gates technology eliminates the language conversion step. Tarari’s CPP eliminates the need to understand the complexities of interconnects and software interfaces, enabling developers to concentrate on performance rather than functionality.

38 Xcell Journal Summer 2003 Tarari Content Processing Platform • 4 MB of ZBT SSRAM for high-speed, Xilinx FPGAs are located under the fan/heat The concept of hardware acceleration is a low-latency local storage sink/shroud assembly as shown in Figure 2. simple one: Create a piece of hardware ded- This placement ensures that the components • A 2M-gate XCV2000 Virtex™-II icated to completing tasks much faster than don’t overheat. The FPGAs require external Platform FPGA performing as the con- software or general-purpose hardware. The cooling because they are pushed to their per- tent processing controller (CPC) that: reality of creating that piece of dedicated formance limits in terms of clock speed and hardware, however, is much more complex. – Provides all connectivity between the there is little to no airflow to cool them. Consider just a PCI interface. It has a PCI Bus, DDR SDRAM, and con- All data flow and control logic is imple- bus with several possible configurations, tent processing engines (CPEs) mented on the CPC. Using DMA technol- such as 32- or 64-bit buses, or 33- or 66- – Dynamically reconfigures FPGAs ogy, the CPC can act as a PCI bus master, MHz clocks. During operation there are allowing data transfer between the host sys- many states and conditions to keep track – Hosts core content processing logic tem memory and the onboard DDR of and control. Even SDRAM has some- – Has maximum total data throughput SDRAM. The bandwidth of the DDR what complex controls. You could buy of 4 GBps SDRAM is approximately four times the each of these elements of the design, but bandwidth of the PCI or CPE buses. This then you would have to create interfaces – Supports bus-master direct- high bandwidth allows the CPC to multi- and control mechanisms between them memory-access (DMA) mode. plex accesses to the memory and makes it and tie them all together. • Two independent content processing appear that multiple devices are simultane- All of this work has been completed engines (CPE) each consisting of: ously accessing the memory. Finally, the with the Tarari CPP. CPC controls programming of the CPEs – A 1M-gate XC2V1000 Virtex-II Figure 1 shows a block diagram of the for fast reconfigurability. Platform FPGA Tarari CPP that includes: The Tarari CPP contains the entire sup- – Independent busses for fast algorith- port infrastructure needed to deploy a PCI • A half-length PCI-compliant card mic processing and continuous oper- solution, allowing you to focus on algorithm • 32- or 64-bit bus width operating at ation during reconfiguration development rather than on hardware imple- 33- or 66-MHz bus speeds mentation details. Another key advantage is – Dynamic reconfigurability, allowing time to market; using the Tarari CPP allows • 256 MB of DDR SDRAM for high- upgrades via software. you to skip the work involved in designing capacity global storage The Tarari CPP is a fully developed PCI the PCI infrastructure and bypass all of the • LEDs for status and debug card with three Virtex-II FPGAs. The three manufacturing steps as well. The card is

8 LEDs

CPLD ZBT SSRAM Content CPE Bus 1 MB 532 MBps Processing 266 MBps Flash Content 16-bit Engine (CPE) 18-bit Processing EEPROM ZBT SSRAM Controller XC2V1000 (CPC) 1 MB 2.128 GBps CPE to CPE bus 64-bit DDR SDRAM 64-bit 256 MB ZBT SSRAM CPE Bus Content 532 MBps 1 MB 2 266 MBps I C Bus 16-bit Processing 18-bit XC2V2000 Engine (CPE) ZBT SSRAM XC2V1000 Serial Temp 1 MB EEPROM Sensor 528 MBps 64-bit 8 LEDs PCI Bus

Figure 1 - Tarari Content Processing Platform block diagram

Summer 2003 Xcell Journal 39 • Takes advantage of wide data widths • CPU execution time far exceeding data transfer time over PCI. Where these criteria are met, there has been considerable success with FPGA solutions for the following applications: • Security/encryption – RSA, DES/3- DES, SHA, MD5, AES/Rijndael • Streaming applications – video processing, pattern matching/filtering, compression/decompression • Vector engines. Candidate products and applications incorporating these basic hardware blocks include: • Network security • Media streaming Figure 2 - Tarari PCI card with three Xilinx Virtex-II FPGAs located underneath heat sink/fan shroud • XML/Web services accelerations delivered to you ready for production original software application and verify • Image processing deployment. Your algorithm firmware can the functionality and characteristics of • High-performance computing be downloaded to the card at runtime, and a system. applications. no hardware customization is required. • Quickly identify and extract critical Plug it in and start accelerating. Algorithm Example portions of the algorithms as candi- The GZIP (GNU zip) algorithm is a dates for hardware implementation. Development Flow commonly used utility that compresses The first step is to select an algorithm for • Make informed partitioning decisions and decompresses data files using the hardware acceleration. Selection is usually for optimum use of hardware resources “Deflate” and other patent-free algo- done using profiling tools that identify and verify performance and function- rithms at www.gzip.org. The key feature software bottlenecks. The next step is to ality in simulation. of GZIP decompression is that it operates determine memory usage, dataflow, and • Perform cycle-accurate hardware simu- on a 1-bit wide stream of data, requiring suitability of the identified code sections lations. that all operations reading from the input that will be implemented in an FPGA. The data stream are performed sequentially. following step is to estimate the size, speed, • Directly implement C-based hardware Although GZIP decompression fulfills a and performance metrics at each stage of designs onto the Tarari CPP. limited number of the algorithm selection the design cycle. With so many parameters This approach reduces the time it takes criteria described above, the results to consider, designers increasingly rely to design accelerated applications, thus demonstrate that the general technique of upon hardware/software co-design, co- lowering cost, improving time to market, offloading a CPU and exploiting algo- simulation, and prototyping as essential and minimizing risks. rithm parallelism can improve system elements of the development flow. performance. The Tarari CPP is built on the develop- Applications ment framework shown in Figure 3 to meet The best candidate algorithms for hard- Porting GZIP C Source Code these needs. The flow emphasizes rapid ware acceleration with Tarari’s CPP board to Handel-C development with a common C-based lan- fit one or more of the following criteria: To reduce the time required to implement guage for both hardware and software com- • High operation-per-byte ratio the GZIP decompression, GNU C source ponents. This allows maximum code was used for the example. The majori- experimentation and exploration of the • Benefits from running multiple ty of the algorithm was used with little or no design space for better quality of design. instantiations (parallel processing, modification to provide an immediate basis Using this framework, you can: multi-threading) for prototyping and a controlled test frame- • Create system models directly from the • Capable of being pipelined work in which to enhance and optimize the

40 Xcell Journal Summer 2003 algorithm. Making use of Handel-C’s simple maximum performance. Consequently, the pipelined block RAM access macros support for parallelism via the par{} con- for this improved performance, a simple mentioned above. Copy operations struct is an example. interface eliminated the double clock resulting from a length/distance pair are The process for porting the GZIP constraint by using pipelined access to performed using a pipelined loop as algorithm to hardware was to write the the block RAM. shown in the code in Figure 4, which code for one “module” of the system at a reads from one port of the sliding win- time in Handel-C. Note that the modules LZ77 Decompressor dow block RAM and writes back to the correspond to algorithmic stages in the The main component in the hardware other port. This results in fast operation decompression algorithm, as shown in implementation is the “sliding window,” by processing one byte every clock cycle Table 1, rather than more traditional which is 32 KB in size with byte-wide once the pipeline is full. hardware blocks. access. The sliding window is built using Simulation Testing of GZIP Modules A significant advantage of developing a GZIP decompression algorithm in

Specification Handel-C is that the simulator can be used to test the functionality of the design before implementation. These simulations Minimal Tool Chain DK SW Tool are performed rapidly – a model of the Similar Languages HW SW Handel-C C entire GZIP decompression algorithm can Standardized APIs simulate 100 KB of compressed data in 25 BSP BSP Platform Abstraction seconds or less on a Pentium™ III 850 OS External IP (optional) MHz system. During development of each GZIP module in Handel-C, we conducted

HDL C Implementation simulations to verify their operation. The software GZIP source code was modified EDIF LIB LIB to produce test harnesses implemented as BIT OBJ C functions called directly from the Handel-C code.

Data Throughput Given the maximum clock rate of the Figure 3 - Tarari CPP design to be 133 MHz – verified by using development framework the Xilinx ISE 5.1i timing analyzer – the Tarari CPP Host CPU data throughput of the GZIP decompression algorithm was calculated from simula-

Optimized Block Memory Accesses The Handel-C language supports the use of block RAM by adding the specification void Decompress(….) { with {block=1} after a RAM declaration. … This specification results in using block while(1) par memory to build the RAM and generat- { //1 byte per cycle once pipe is full ing a RAM clock at double the algorithm … clock rate, which is used to implement ReadWindowAddr(CopyPos); // Pipe Stage 1 - Set address single-cycle access to the block RAM. R eadW indowData(TempData); // Pipe Stage 2 - Read This process provides a quick route to W riteW indow(CurrentPos,TempData); // Pipe Stage 3 – Write hardware prototype for the design. … However, using the single-cycle block } RAM access limits the algorithm clock … rate to half of the RAM clock rate. Some } portions of the GZIP decompression algorithm are sequential in nature, so a high clock rate is desirable to achieve Figure 4 - Example of pipelined loop code for Handel-C for LZ77 sliding window

Summer 2003 Xcell Journal 41 tion results in terms of the number of clock Implementation The final implementation size was 40% cycles required to decompress given files. The Handel-C GZIP decompression algo- of one Virtex-II 1000 Platform FPGA Table 2 shows the theoretical peak rithm was synthesized directly to EDIF with speed exceeding the 133 MHz and maximum sustained decompressed using the compiler. Xilinx ISE 5.1i tools required for maximum DDR data access data output rate from the GZIP decom- were used to place-and-route the circuitry on the Tarari CPP card. pression algorithm. The actual data out- and to configure the Xilinx FPGAs on the put rate depends on the level of Tarari CPP. A board-support package GZIP Decompression compression – highly compressed files (BSP) of function calls is provided in the Rate (Mbytes/s) result in a higher rate. Tarari Content Processor Development In comparison, software GZIP has a Kit. The BSP provides a layer of abstraction Theoretical peak 130 peak data output rate of approximately that shields users from “low-level detail” Maximum sustained 116 25 MBps on an average Pentium III- and is used during both simulation and based system. implementation of the design. Table 2 - Performance results for GZIP decompression

Module Function Conclusion Application acceleration is simplified using 1 Main Detects the type of a compressed data block, and calls the the combination of the Tarari CPP and the appropriate modules to decompress it. Coordinates operation Celoxica DK Design Suite. Together they of all other modules in the application. provide the ability to deliver hardware acceleration products with much lower 2 Optimized block Provides a simple interface for pipelined access to block NRE costs than traditional methods and memory access RAM on Xilinx FPGAs. Required to achieve high clock rates. with a quicker time to market. Used to provide RAMs for Huffman tables and LZ77 sliding The GZIP decompression algorithm window. was used to demonstrate the platform’s ability to deliver significant acceleration 3 Bitstream reader Reads a variable number of bits from the input bitstream. and an overall performance improvement for applications. The Celoxica DK Design 4 Builder for tree description For dynamic compressed blocks. Uses the tree Suite allowed interactive simulation and Huffman decoder description generated from the input bitstream to build a debugging of the GZIP decompression Huffman decoder table for the tree descriptions for the main algorithm. Interactive simulation delivers Huffman decoders. both rapid proof of concept and the completion of development in only two 5 Tree description For dynamic compressed blocks. Decodes the Huffman months. The Celoxica DK Design Suite – Huffman decoder codes from the input bitstream, generating tree descriptions along with the other design tools, exam- for the “literal/length” and “distance” Huffman decoders. ples, and documentation from Celoxica – enable you to quickly develop and deploy 6 Builder for “literal/length” Uses the tree description generated from the input highly accelerated products. Huffman decoder bitstream or the static bit-length codes to build a Huffman You could continue to optimize per- decoder table for the “literal/length” Huffman decoder. formance for a specific algorithm or, more important, incorporate additional algo- 7 Builder for “distance” Uses the tree description generated from the input rithms to deliver even higher application Huffman decoder bitstream or the static bit-length codes to build a Huffman performance benefits. Systems deployed at decoder table for the “distance” Huffman decoder. customer sites with Tarari CPPs can take advantage of these enhancements due to 8 “Literal/length” and “distance” Decodes the Huffman codes from the input bitstream, the built-in reconfiguration capabilities of Huffman decoders generating “literal” values and “length/distance” pairs. the Virtex-II FPGAs, resulting in an overall lower cost of ownership. 9 LZ77 decompress Uses the LZ77 algorithm on the stream of “literal” values To find out more about hardware acceler- and length/distance pairs to reconstruct the original uncom- ation using the Tarari Content Processor pressed data. Development Kit, visit www.tarari.com/ products-cpdk.html. To discuss how your applications can be accelerated, contact Table 1 - Modules and descriptions for Handel-C GZIP decompression algorithm Tarari at [email protected].

42 Xcell Journal Summer 2003 FPGA Design

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©2003 Mentor Graphics Corporation. All Rights Reserved. Mentor Graphics is a registered trademark of Mentor Graphics Corporatio PRECISION SYNTHESIS Mentor Graphics Synthesis provides the most comprehensive analysis for complex FPGAs with the only complete, built-in incremental timing analys Synthesis provides the most comprehensive analysis for complex FPGAs with the only Quickly find and optimize the most critical paths and avoid frustrating trial-and-error design iterations. Visit Quickly find and optimize the most critical paths and avoid frustrating trial-and-error design today or call

Use Mentor Graphics Use Mentor design tools. FPGA Avoid messy timing mistakes. messy timing Avoid Next-GenerationNext-Generation FPGAFPGA SynthesisSynthesis RequiresRequires ASIC-LevelASIC-Level CapabilitiesCapabilities TheThe samesame breakthroughsbreakthroughs thatthat makemake FPGAsFPGAs competitivecompetitive withwith ASICsASICs alsoalso imposeimpose designdesign andand verificationverification challengeschallenges thatthat requirerequire advancedadvanced methodologiesmethodologies andand debugdebug capabilities.capabilities. MentorMentor Graphics’Graphics’ PrecisionPrecision SynthesisSynthesis tooltool providesprovides them.them.

by Tom Hill FPGA Growth breakthroughs, however, add design and Product Manager – Precision Synthesis FPGA design methodology has many verification challenges and require new Mentor Graphics advantages. You control the entire design methodologies and debug capabilities. [email protected] and layout processes. Design cycle times For designers to take full advantage of are faster, photo-mask costs are non- FPGA technology, the supporting software In the fast-moving world of programmable existent, and there are no minimum order tools must be capable of solving designers’ logic, EDA vendors face the persistent chal- restrictions. On the other hand, the low toughest challenges. Mentor Graphics lenge of creating design tools and method- performance, comparatively smaller gate introduced its Precision™ Synthesis plat- ologies to keep pace with the increasing densities, and high unit costs of FPGAs form to solve this new set of problems. complexity and capacity of silicon. have historically relegated them to small, ASICs have historically provided a cost- low-volume designs. ASICs claimed the Precision Synthesis Concepts effective solution for the electronics indus- remainder of the market. Three major considerations drove the try; this technology is responsible for Xilinx is overcoming these market bar- development of the Precision Synthesis considerable growth and innovation. The riers by developing reconfigurable, system- platform’s architecture: popularity of ASIC technology has provided level FPGAs such as the Virtex-II Pro™ 1. Intuitive user interaction the driving force in the EDA industry and Platform FPGA, which integrates embed- dictated the direction for software develop- ded microprocessor cores, memory, and 2. Excellent Quality of Results (QoR) ment. ASIC development is, however, mov- hard and soft macros. These features pro- 3. Advanced analysis. ing beyond the reach of many mainstream vide you with the benefits of reduced sys- designers due to high upfront (NRE) tem-development times, improved power Intuitive Use charges and a longer time-to-market. consumption, increased volume, and When you interact with an EDA product, FPGAs are filling this void and will become expanded board space, as well as the flexi- the tool should add speed and reliability to the dominant approach for designers and bility to make changes right up to produc- the development, analysis, and debug of a the new driving force in the EDA industry. tion time. These dramatic technological design. Although the tool must drive the

44 Xcell Journal Summer 2003 design process, it must also be capable of wide range of applications. The adapting to each user’s design style. The complexity of large systems results Precision Synthesis platform was constructed from the detailed timing and with this in mind. You see only the tasks and clocking requirements being data that are relevant to a particular point in designed into these devices. This the design process. Extraneous data is hidden timing complexity can lead to until needed. Selective visibility allows you to excessive design iterations or even concentrate on the task at hand and provides undetected timing problems affect- an intuitive approach to synthesis (Figure 1). ing printed-circuit-board debug. The Precision Synthesis platform also To solve these new timing issues offers push-button synthesis flow without and guarantee a reliable design, the compromising results or flexibility. This Precision Synthesis platform ease-of-use feature was achieved by replacing includes a timing engine and Figure 1 - Precision Synthesis Design Center user-configured synthesis options with auto- design analysis capabilities. Its mated configuration. Optimization algo- PreciseTime™ timing engine pro- rithms configure options based on an vides a completely interactive, analysis of a design against its constraints, standalone timing analysis envi- thus eliminating the need to specify effort ronment designed to handle the levels or optimization “goals.” most complicated clocking Intuitive use can be enhanced by utiliz- schemes with speed and accuracy. ing industry standards and knowledge The PreciseTime engine’s capabili- whenever possible. We adopted, for exam- ties extend beyond timing analysis ple, the Synopsys Design Constraint to include: (SDC) format for defining timing con- • Reports of internal clocks, straints. As many ASIC designs are now including clock propagation completed in FPGAs, the SDC format information through simple Figure 2 - Critical path schematic eases the migration of designs between the gates, dividers, and DCMs two design environments. • Reports of missing constraints that pre- optimization at each level of abstraction. Excellent Quality of Results vent comprehensive timing analysis They will benefit from a seamless method- The Precision Synthesis tool includes a suite • Reports of timing paths that cross ology that allows easy migration through- of unique algorithms called Architecture asynchronous clock domains (These out each phase of the design. Signature Extraction (ASE) optimization reports help you verify clock isolation The Precision Synthesis product desig- that automatically focuses specific optimiza- or the existence of metastable safe syn- nation represents a synthesis technology tions on those areas of the design that are chronization logic.) platform that encompasses a family of syn- most likely to hinder overall performance, thesis products created by Mentor • Powerful schematic viewing with such as finite state machines (FSM), cross- Graphics to address high-end FPGA design schematic-fragment-generation capabil- hierarchical paths, or paths with excessive issues from different levels of abstraction. ities and multiple critical-path viewing combinational logic. The ASE technology Built to keep pace with the ever- (Figure 2). uses an automated, heuristic approach to changing programmable logic world, the deliver smaller and faster designs without First-time success on your printed cir- Precision Synthesis platform is a choice iterative manual user intervention. cuit board requires a fully and accurately worth considering for next-generation The Precision Synthesis platform’s ASE constrained design during synthesis; FPGA implementations. By incorporating technology takes full advantage of Xilinx PreciseTime was designed to do just that. an intuitive user interface, excellent QoR, device features by providing the smallest and unparalleled accuracy, it can handle the design that meets your target frequency. This Next-Generation FPGA Synthesis toughest FPGA designs. saves you time by reducing design iterations, The FPGA synthesis domain is rapidly Mentor Graphics is committed to pro- and money by helping you fit into smaller expanding beyond the RTL space to vide you with the latest set of EDA tools to devices or lower speed grades in the process. encompass the architectural and physical enable electronic design innovation. For realms. This expansion will produce signif- more information about the Precision Advanced Analysis icant gains in both designer productivity Synthesis platform or Mentor Graphics’ FPGA devices are now being used to and chip performance. Designers will complete FPGA-design product family, implement highly complex designs for a require tools with powerful algorithms for visit www.mentor.com/fpga/.

Summer 2003 Xcell Journal 45 NSPICENSPICE BridgesBridges SimulationSimulation GapGap A next-generation, mixed-domain SPICE tool with directly integratedintegrated S-parameterS-parameter datadata capabilitycapability providesprovides thethe mostmost accurate simulation of combined silicon and system behavior.

46 Xcell Journal Summer 2003 by Yu Liu However, most existing SPICE tools still end of this prolonged process, it is likely Director of Simulation Products require you to model S-parameter data that the system will be inaccurate and Apache Design Solutions from backplanes, boards, and transmission restricted to a limited frequency range [email protected] lines into lumped RLC (resistance, induc- because the poles/zeroes will have to be tance, and capacitance) “black box” models, reduced and approximated. Streamlining the simulation of entire com- or SPICE subcircuits. This timeworn plex system environments – from chip, to lumped RLC approach is necessitated by Benefits of S-Parameter Integrated NSPICE package, to board, to connector, to back- the inability of existing time-domain As shown in Figure 1, integrating S- plane, and back again to chip – has become SPICE tools to take in the frequency- parameter data directly into a mixed- one of the most urgent needs of designers domain S-parameter data directly. domain, high-capacity SPICE tool offers a today. The problem becomes even more There are two main problems with this faster and more accurate alternative to challenging because the supply chain for approach. First, lumped models do not lumped approaches. NSPICE is fully com- multi-gigabit serial I/O connectivity accurately represent distributed frequency- patible with HSPICE (an analog circuit requires tighter integration among many dependent effects, particularly in the high simulator marketed by Synopsys). It per- different parties: chip and board designers, system integrators, and backplane and connector suppliers. Internet applications for data, audio, video, and graphics have spawned a myriad of competing standards to relieve the serial I/O bottleneck, including 10 Gigabit XAUI, InfiniBand™ and PCI Express™. The only effective way to address the design, simulation, and integration of multi-gigabit serial I/Os on multiport networks is to bridge the circuit simulation gap between chips and systems. NSPICE, a next-generation SPICE (Simulation Pro- gram with Integrated Circuit Emphasis) tool developed by Apache, co-simulates Figure 1 - Comparison of S-parameter lumped RLC approach with S-parameter integrated in NSPICE nonlinear SPICE models for the transmitter and receiver circuitry. Together with linear frequency range. Second, the model gener- forms mixed-domain simulation with scattering parameters (S-parameters) for ation process can result in a massive quan- direct S-parameter data, generating accu- connectors and backplanes, NSPICE tity of elements, taxing both you and the rate eye diagram patterns and output wave- bridges the simulation for chip-to-chip and SPICE tool. forms. NSPICE co-simulates the nonlinear other complex topologies. To illustrate the modeling complexity, SPICE models for the transmitter and let’s examine a simple two-port passive linear receiver circuitry together with linear S- Limitations of S-Parameter Lumped RLC network that has four S-parameters: reflec- parameters for connectors and backplanes, At high frequencies, the S-parameter is the tion at both ports, as well as forward and thereby bridging the simulation for chip- most accurate form of broadband frequency backward transmission. Correspondingly, a to-chip and other complex topologies. representation for such off-chip, passive net- four-port network contains 16 S-parameters. Figure 2 depicts a typical application: a works as packages, boards, and backplanes. A passive structure such as an FR-4 back- 3.125 Gbps SERDES system consisting of S-parameters are preferred over other fre- plane can possess hundreds of poles/zeros a transmitter with PLLs (phase locked quency domain parameters (Y and Z, for across a broad frequency range. Using the loops, represented by a SPICE netlist), example) primarily because S-parameters lumped approach, you must generate mod- connectors, backplanes, linecards (repre- range between the values of 0 and 1, and els by fitting and optimizing each pole/zero sented with S-parameter models), cables they are well behaved across a broad frequen- combination from S-parameter data. This (represented with transmission-line mod- cy range. In addition, S-parameters are the process can result in hundreds of thousands els), and a receiver (represented by a SPICE easiest parameters to measure using a vector of elements in large multiport networks. netlist). The entire system requires simulat- network analyzer. By matching the signal The lumped model development time ing more than 10,000 devices, on top of impedance without reflection and saving the alone can take up to several weeks, not hundreds of thousands of RLC parasitics. results to a standard file, you can directly counting the SPICE simulation time and As shown in Figure 3, the total turn access S-parameter data for simulation. resulting convergence issues. And at the time using NSPICE, from reading in S-

Summer 2003 Xcell Journal 47 parameters to generating eye diagrams, is at accuracy has already been lost in the fit- compatible with HSPICE and SPICE least 10 times faster than lumped model ting process, so customers are now models and netlists. NSPICE also supports generation and simulation approaches, requesting vendors to provide the S- pseudo-random bit stream (PRBS) genera- which can consume several weeks. For parameter data directly. NSPICE can tion and eye diagrams. smaller circuits that are less than a few simulate the system using whatever mod- thousand elements, the turn time in els are available for each component, in Working with NSPICE NSPICE for an eye diagram can be shrunk any combination of lumped models, To illustrate the typical usage of NSPICE, down to only a few minutes. transmission models, and S-parameters. assume that a channel simulation configura- Until recently, some connector, back- NSPICE is written in C++ and employs tion has the following components: encrypt- plane, and board suppliers provided only hierarchical algorithms offering improved ed models from the IP vendor for the fitted lumped models to their customers, performance, memory efficiency, and bet- transmitter and receiver, S-parameter models because that was the only way to simulate ter convergence using advanced matrix for the backplane, and lumped models for the effects in SPICE. Unfortunately, solver technology. The product is fully the connectors and packages from the manufacturer. After constructing a SPICE netlist that represents your channel configuration, you can run transient time-domain simula- Vdd tion on the entire system using NSPICE – without translating the S-parameter models – and generate eye diagrams directly from the simulation results. In addition, NSPICE supports advanced analysis, such as frequen- FR-4 Backplane Line Card cy modulation, to simulate the on-chip PLL Tx Rx response together with off-chip resonance Coax Cable effects, thereby enhancing the accuracy of the PLL simulation. The Xilinx flagship Virtex™-II Connectors Platform FPGA demands simulation that accurately correlates the RocketIO™ serial transceiver behavior and performance with Figure 2 - Typical 3.125 Gbps SERDES system with S-parameters actual silicon. By modeling serial backplane, chip-to-chip, and other topologies with direct S-parameter data, NSPICE provides the most accurate simulation of silicon behavior.

Conclusion Adapting to the ever-increasing demands of networking bandwidth requires the use of technology that seamlessly bridges the time- domain and frequency-domain aspects of large systems. A true, mixed-domain SPICE, integrated with actual S-parameter data, benefits the entire supply chain for multi-gigabit serial connectivity by providing the most accurate prediction of silicon and system behavior. Predicting behavior accurately ensures significant system cost savings, easier integration, and, most important, accurate and consistent operation across a broadband frequency range. To learn more about NSPICE, visit www.apache-da.com or contact Figure 3 - Turn time using NSPICE, from reading in S-parameters to generating eye diagrams [email protected].

48 Xcell Journal Summer 2003 OptimizeOptimize PinPin AssignmentsAssignments EarlyEarly By minimizing wire crossing and printed circuit board route complexity, DesignF/X pin assignment software reduces routing layers and enables your systems to run faster and come to market sooner.

by Robert Chatwani Vice President of Marketing Product Acceleration, Inc. [email protected]

Sanjay Thatte Consultant Product Acceleration, Inc. [email protected]

According to the International Tech- nology Roadmap for Assembly and Packaging, sponsored by International SEMATECH, the package pin count for high-performance ICs is expected to reach 4,009 by year 2007. With densities of this magnitude, proper pin assignment is essential to maximize the component, board, system performance, and to deliver products on time and on budget. Xilinx’s Serial Tsunami Initiative addresses density-related problems from the FPGA component perspective, but you also need the right board-level EDA tools. Most of today’s EDA board-level tools focus solely on schematic and layout issues. In doing so, they fail to address many of the complex problems – such as board performance, cost, and schedule slippage – that are created by sub-optimal pin assignment.

Summer 2003 Xcell Journal 49 In addition to enhancing performance by reducing routing layers, DESIGNF/X VALUE CALCULATOR = Input automating pin assignments at the Example - Board Design Using FPGA = Output front end of the design process gives Current With DF/X Benefits you more time for signal integrity Time Fully loaded Time Cost Time required analysis, functional simulation, and required labor rate savings savings Worker weeks Worker weeks $ / hour Worker weeks Dollars even system packaging activity. The Product Design end result is higher quality products Architecture & delivery 6.0 5.0 $ 80.0 1.0 $ 3,200 with significant reductions in design Simulation closure 6.0 4.0 $ 80.0 2.0 $ 6,400 time, engineering costs, and product FPGA design flow iterations 3.0 0.0 $ 80.0 3.0 $ 9,600 manufacturing costs. PCB Layout The DesignF/X™ automated Component placement 2.0 0.4 $ 80.0 1.6 $ 5,120 design and optimization tool from Optimization setup 0.0 0.2 $ 80.0 (0.2) $ (640) PAI (Product Acceleration Inc.) helps Board layout 8.0 7.0 $ 80.0 1.0 $ 3,200 you analyze and optimize the component pin assignments very early in Totals 25.0 16.6 8.4 $ 26,880 the product development cycle – Key Metrics during concept development, device Avg designs per engineer per yr = 3.0 selection, early component architecture and placement, and early FPGA Dollar savings per design = $ 26,880 device floorplanning. The DesignF/X Total savings per month = $ 6,720 Total savings per year = $ 80,640 tool helps shorten development time Margin improvement per design = 33.7% and time-to-market, improves the Time improvement per design = 33.6% performance of the finished product, and reduces the costs of development and of the finished product as well. Figure 1 - Analysis of cost saving using DesignF/X tool suite

DesignF/X Benefits and labor costs. The use of FPGAs clear- Operational Metrics The DesignF/X tool suite enhances product ly implies a desire to control engineering Apart from the costs of R&D, other key feasibility, reduces engineering time and costs. However, traditional approaches operational metrics that determine product costs, and improves operational metrics. require the FPGA designer to interact success are the cost of production and with and wait for task completion by a time-to-market. Product Feasibility systems hardware designer and a PCB lay- The choice of an FPGA-based design Often, high-density PCB routing challenges out engineer. Only then can the FPGA approach implies that time-to-market is a are solved through thinner traces combined designer analyze and optimize pin assign- key operational metric for the success of with extremely small, blind, or buried vias ments, using a manual and iterative your project. However, poor pin assign- and increased PCB layers. These solutions, process. These delays and iterations affect ment can result in PCBs that are more however, can result in significantly degrad- the direct cost of the activities, creating expensive to manufacture, with up to a ed system performance and forced opera- unnecessary task dependencies, forcing 10% cost increase with each additional tion at lower system clock speeds. In some extensive change management overhead, board layer. In addition, increased PCB cases, the degradation is so bad it results in and impacting the overall project layer counts may result in longer order the loss of market relevance for a product. momentum. cycles and a narrow supply base. This With the DesignF/X tools, these issues The DesignF/X tool suite employs intelli- becomes extremely important when layer are avoided through earlier, smarter, and gent algorithms to create an accurate impact counts rise above 24, and critical at more faster analysis and optimization of pin analysis and optimize pin assignment early, than 40 layers, at which point the PCB assignments on critical system compo- before you spend time creating symbols, itself represents a significant portion of the nents. In turn, this enables fundamental schematics, and developing the PCB layout. overall system cost. product viability and increases the odds of Consequently, the FPGA designer handles By avoiding increased order cycles and market success. board-level issues regarding pin assignment extended development cycles, DesignF/X directly, without the task and process delay tools help you gain significant time-to- Engineering Costs and Timelines imposed by traditional processes. The result market advantages. By helping to reduce Engineering costs are driven by individ- is an immediate improvement in project the complexity of the PCB and its layer ual task lengths, inter-task relationships, engineering costs and timelines. count, the DesignF/X software lets you

50 Xcell Journal Summer 2003 a “situation analysis” based on various com- case, an NGD file is used as input to binations of component connectivity and PACE. Any additional FPGA pin and placement, resulting in optimized pin area constraints can then be developed assignments. The optimization is per- using PACE and saved for use in the formed in terms of the board itself and of Xilinx place-and-route flow. the system as a whole, with special atten- Figure 3 illustrates how DesignF/X- tion paid to detecting and reducing wire generated pin assignment constraints can crossing. Figure 2 illustrates the effective- be used easily in an FPGA design flow. ness of DesignF/X detection and reduction of wire crossing. Conclusion Once you are satisfied with the results, Unlike other EDA board-level design tools you can create output files consisting of – which focus on schematic and layout optimized component pin assignments and issues – the DesignF/X suite from PAI pro- related reports. These individual compo- vides you with what you need to reduce nent pin assignments can then be used as design time and costs through pre-layout pin assignment constraints for the internal pin optimization. With an intuitive user design of those components. interface, Java-based design, powerful Original pin assignments can be written algorithms, and accurate analysis capabili- in the Xilinx PAD file format. The ties, DesignF/X software enhances the DesignF/X program outputs the optimized quality, performance, and cycle-time pin assignments in the corresponding for- parameters of board design projects. The mat, enabling DesignF/X software to fit PAI product suite is designed to coexist Figure 2 - Before and after DesignF/X seamlessly into your FPGA design flow with within existing methodologies – protect- wire-crossing reduction minimal disruption to existing processes. ing your investment in tools, skills, reduce recurring product costs, improve Future releases of the DesignF/X tool and processes. For more information order cycles, and expand the pool of avail- suite will support bidirectional data about DesignF/X and PAI’s software solu- able suppliers. exchange with Xilinx PACE software to tions, visit www.prodacc.com or email Figure 1 compares the cost of designing create pin and area constraints. In this [email protected]. a product with – and without – the DesignF/X package. In this example, the DesignF/X tool suite enables an organiza- FPGA/ASIC tion to reduce costs by nearly $27,000 per Board FPGA/ASIC Board & System ConceptBoard Design & Board & System Release ConceptDesign Design & Verification Release design and shorten product design cycle Design Verification Verification Verification time from 25 weeks to just over 16 weeks. This reflects a greater than 33% improvement in margin per design and a savings of Design Constraints more than eight worker-weeks. By using Design Constraints HDL Design Timing Physical Pin HDL Design Timing Physical Pin Assignments DesignF/X tools early in the design Assignments process, you can help avoid costly iterations due to improper pin assignments and Logical / Physical Logical / Physical Test Synthesis FPGA/ASIC Test Synthesis reduce the time of your FPGA design flow FPGA/ASIC Design & Design & iterations to nearly zero. Verification Verification Place and Route Place and Route Design Flow Using DesignF/X Timing Analysis / Timing Analysis / Begin by importing your component infor- Post Route Verification Post Route Verification mation or creating it rapidly from your datasheet or ASCII pin file. You then spec- Design Goals Met ? No Design Goals Met ? ify the connectivity between the target No FPGA and other major components, as Yes Yes well as their approximate placement. This process includes a definition of pin/signal mobility and basic constraint information. The DesignF/X software then performs Figure 3 - Typical board/system design flow

Summer 2003 Xcell Journal 51 GotGot thethe BGABGA Blues?Blues? Learn how to obtain visibility into the pins of a ball grid array package using Boundary Scan and the Universal Scan debugging tool.

52 Xcell Journal Summer 2003 by Rick Folea Scan Cells CTO Ricreations, Inc. IOB IOB IOB IOB IOB [email protected]

The first prototype of a board populated with BGAs returns from assembly. You IOB IOB attach the Xilinx download cable, apply power, attempt to download test data, and IOB IOB you get – nothing. Debugging is easy when you have access to signal pins – but this INTERNAL IOB IOB board has BGAs, so you can’t probe the pins LOGIC effectively. You wish you could: • Monitor how mode-select pins are set IOB IOB • Check continuity across BGA solder connections IOB IOB • See if the oscillator is connected Instruction Register to the part TDI TDO • Check the DIN/DONE/CCLK line continuity Bypass Register

• See if the data/address or other signals Figure 1 - The yellow Boundary Scan cells are located between the analog are active or connected to the part. front end of the IOB and the internal logic. It would be wonderful if you could peel the chip open. But you can’t. There are, however, • Boundary Scan operational modes – configure the part). Two of the registers are more sophisticated ways to access BGA pins. What are they and how do they affect shown in Figure 1: the instruction register This article introduces Universal Scan™ – the scan cells and the information you and the bypass register. a new tool that takes advantage of IEEE can access? To use Boundary Scan, you simply shift 1149.1 Boundary Scan, commonly known as an instruction into the instruction register JTAG, a feature already built into every Xilinx The Scan Chain and then shift data in/out of the associated device. It provides visibility and control over At the most fundamental level, Boundary data register. the pins under that BGA – or any JTAG Scan is illustrated in Figure 1. Logic occu- The bypass register is used to skip over a device – quickly, easily, and inexpensively. pies the interior of the device. Pins occu- part in a scan chain. Skipping parts of the py the perimeter, or boundary. The scan chain allows you to bypass the bound- JTAG Background – The Basics interconnects between each pin and the ary register and exit in a single TCK cycle. You are probably already familiar with the internal logic pass through the Boundary Scan logic in each of the scan cells JTAG interface – TCK, TDI, TDO, and Scan logic blocks (yellow in Figure 1). consists of a group of registers that cap- TMS – and how JTAG is used to configure Boundary Scan blocks are on the logic tures the state of signals entering and exit- Xilinx devices. You may not be as familiar side of the IOB (input/output block). ing the device, and a group of registers with Boundary Scan, another powerful test They are normally transparent to the that can drive these same signals. The technology. operation of the device; signals flow operation of these cells depends on the unimpeded through them. Boundary Scan mode. Boundary Scan Overview Each of these blocks is connected Manufacturers may define many Understanding and using Boundary Scan around the boundary of the part to form a Boundary Scan modes for a given device, requires only three basic pieces of information: giant shift register (the boundary register). but only the three required by the IEEE When in Boundary Scan mode, TDI is 1149.1 standard are necessary for success- • How the scan chain is connected – connected to one end of the shift register, ful debugging. These modes are: SAM- Where does Boundary Scan reside inside and TDO is connected to the other end. PLE/PRELOAD, EXTEST, and BYPASS. your Xilinx device? TCK and TMS are used to shift data in and • How the scan cells are connected – out of this giant shift register. SAMPLE PRELOAD How does Boundary Scan interface with TDI and TDO can be connected to In the SAMPLE/PRELOAD mode of your signals? numerous registers (such as those used to Boundary Scan, the logic inside the yellow

Summer 2003 Xcell Journal 53 blocks of Figure 1 is represented in greater DATA IN (TDI) detail in Figure 2. One capture register is dedicated to

1 each signal typically associated with an D Q INPUT OUTPUT TRISTATE 0 I/O buffer ( , , ). LE On a command set by the test engineer, these registers, or scan cells, capture the IOB.I state of all three signals (or however many there are for the pin). Once data is cap- 1 tured, it is shifted out (the red path in D Q 0 Figure 3), and the state of the pin is dis- LE played. Data can be captured at any time. It is asynchronous with signals flowing in IOB.Q IOB.T and out of the device. The capture process does not interfere with the 1 D Q circuit’s operation. 0 LE EXTEST When a part is in EXTEST mode, data that the test engineer wants to apply to the OUTPUT, TRISTATE – and in some cases, SHIFT/ Figure 2 - In SAMPLE/PRELOAD mode, the scan CAPTURE DATA OUT logic consists of three capture registers. I/O signals INPUT – signals is shifted into the scan (TDO) CLK-DR captured in the latches are shifted out serially. chain. Although the capture registers from SAMPLE/PRELOAD still capture the states of the signals flowing through the device, Update Registers they never go anywhere. The signals are cut DATA IN (TDI) off from their normal function and the data shifted into the update registers is 1 applied to the signals, as shown in Figure 3. D Q D Q 0 Captured data is shifted out as update data LE LE is shifted in.

1 IOB.I BYPASS 0 We have already touched on BYPASS. In 1 this mode, the Boundary Scan chain is D Q D Q 0 bypassed and all TDI data flows through

LE LE 1 the part in one TCK cycle.

0 IOB.Q Applying Boundary Scan to Access Pins IOB.T 1 Using the JTAG state machine to imple- 1 ment Boundary Scan can be tedious. But D Q D Q 0 0 the new Universal Scan debug tool from LE LE Ricreations Inc. automates much of the work. You simply drop virtual parts on the screen, connect the JTAG signals to the parallel port, and hit the SCAN button. Instantly, the activity of every pin under SHIFT/ CAPTURE DATA OUT UPDATE EXTEST the BGA (or around any JTAG part) (TDO) CLK-DR appears on your PC display. Each of the red or black dots in Figure 4 Figure 3 - In EXTEST mode, normal signal flow is interrupted and data that had been represents a pin. Red represents a logic High; shifted into the update registers by the test engineer is applied to the signals. black a logic Low. Blue is a pin that can’t be scanned (power, ground, and such).

54 Xcell Journal Summer 2003 If a pin is toggling, that means there is you can drive signals from the BGA to a con- signal activity on that pin. Typically, this is nector. This gives total visibility and control all we want to know when we use an oscil- over every scan-enabled pin on the part. You Let Xilinx help loscope to debug – whether the pin is high, are only limited by your imagination. Let Xilinx help low, or toggling. The Universal Scan tool is Because Boundary Scan is independent an activity indicator. You instantly see – in of internal activity, the part does not have you getget youryour real time – if the mode select pins are set to be configured for this testing. You can correctly, if the oscillator is connected, if the take the board right off the factory floor message outout toto data bus or address bus is active, and so on. and start testing it before the Universal Scan software does not VHDL/Verilog/firmware is ready. thousands ofof require netlists, test executives, test fixtures, or other board-test periph- programmable erals. You don’t have to maintain a parts library, because the Universal logic users Scan program doesn’t need it. You simply supply the BSDL files, worldwide. which are freely available from vendor websites, and the Universal That’s rightright ...... byby advertisingadvertising Scan tool builds a virtual part on youryour productproduct oror serviceservice inin thethe the fly. All that is required is a Xilinx Xcell Journal, you’llyou’ll reachreach JTAG-enabled part; packaging more than 70,000 engineers, doesn’t matter. designers, and engineering A valuable aspect of Boundary managers worldwide. Scan testing is that, while in SAMPLE/PRELOAD mode, you can Figure 4 - Virtual switches and LEDs help organize The Xilinx Xcell Journal isis anan monitor all the pins while your and control the pin information. award-winningaward-winning publication,publication, circuit is running at full speed dedicated specifically without any impact on the system. Conclusion toto helpinghelping programmableprogrammable SAMPLE/PRELOAD mode is completely Using Boundary Scans to probe otherwise logiclogic usersusers –– andand itit works.works. transparent to the system. How often have inaccessible pins under a BGA is an easy, you touched an oscilloscope probe to a pin three-step process with the Universal We offer affordable advertising only to create probe loading that changes Scan tool: ratesrates andand aa varietyvariety ofof advertisementadvertisement the circuit’s operation, especially with new 1. Drag and drop the parts under test sizessizes toto meetmeet anyany budget!budget! high-speed circuits? Boundary Scan does on the PC screen. not have that problem – it is completely 2. Connect the JTAG chain to the Call today : unobtrusive. parallel port. (800)(800) 493-5551493-5551 Because watching pins blink on the or e-mail us at screen can be tedious, the Universal Scan 3. Hit the Scan button. [email protected] screen display offers virtual indicators Instantly you can monitor the activity (LEDs) that you connect to the pins to of every JTAG-enabled BGA pin (or JoinJoin thethe otherother leadersleaders organize those aspects of the circuit’s activ- around any scan-enabled device) on your inin ourour industryindustry andand advertiseadvertise ity that interest you. It also has virtual PC display. inin thethe XcellXcell Journal!Journal! switches that allow you to manually drive a You don’t need test fixtures, netlists, or pin to a known state. test executives. The devices don’t have to be To perform a continuity test between configured. You can start testing the board two devices, put one device into EXTEST right off the factory floor before the mode and toggle the virtual switches con- firmware is complete. nected the output buffers. The LEDs con- You’ll find information on the Universal nected to the other device’s input buffers Scan toolset on the www.xilinx.com website R will show the result. Performing a continu- by following this click chain: Products/System ity test this way is quick, easy, and does not Resources/Configuration Solutions/Third-Party require touching the board. Tools/Universal Scan. Or you can go directly To monitor results on an oscilloscope, to www.UniversalScan.com.

Summer 2003 Xcell Journal 55 ReduceReduce ResistorResistor CountsCounts Second-generation XCITE andand LowerLower CostsCosts technologytechnology providesprovides controlledcontrolled impedanceimpedance driversdrivers andand on-chipon-chip terminationtermination forfor single-endedsingle-ended andand differential I/Os for Virtex-II Pro Platform FPGAs.

by Rob Schreck Senior Marketing Manager Xilinx, Inc. [email protected]

Today’s high-performance chips with fast signal rates require termination to prevent signal reflections and to maintain signal integrity. Historically, engineers have used external termination resistors. However, with advanced packaging technologies and availability of hundreds of I/Os, external termination resistors are no longer viable, especially for ball grid array packages. To solve this problem, Xilinx pioneered adaptive on-chip termination with XCITE (Xilinx Controlled Impedance Technology) in Virtex™-II Platform FPGAs. XCITE dynamically eliminates drive strength vari- ation due to process, temperature, and voltage fluctuations. XCITE uses two external high-precision resistors per I/O bank to incorporate equivalent input and output impedance internally for hundreds of I/O pins. Not only is the cost of the resistors saved (and the additional manufacturing costs that accrue with them), but with fewer printed circuit board respins the cost of developing PC boards also decreas- es, as illustrated in Figure 1.

56 Xcell Journal Summer 2003 bility and independent operability on each

Reduce Resistors I/O bank. When applied to inputs, XCITE provides controlled impedance input parallel termination. When applied to outputs, XCITE provides controlled impedance series as well as parallel termination. Each of the eight Virtex-II Pro I/O banks supports XCITE, controlled by just two external reference resistors per bank.

Improve PCB Layout Conclusion As shown in Table 1, Virtex-II Pro Platform Figure 1 - Reduced component count with XCITE FPGAs offer second-generation XCITE technology that gives you increased signal Smooth Out Signals integrity for both single-ended and differential signaling. Using XCITE technology allows you to dramatically reduce the number of resistors to lower your component costs. The increased signal integrity of each Virtex-II Pro Platform FPGA design reduces the risk of board re-design, delivering even more cost reduction. Simplify your designs and lower your costs with Virtex-II Pro FPGAs with XCITE. For more infor- Signal Integrity mation, go to www.xilinx.com/xcite/. Figure 2 - Increased signal integrity with XCITE Second-Generation Technology Proved in the field and used extensively by customers means you can rest assured about its functionality – another Xilinx innovation Increase Signal Integrity for lowering risk, improving design efficiency, and maximizing With XCITE, you can eliminate hundreds performance. of external resistors and increase the signal integrity of your boards for single-ended Lower Costs By using XCITE, you need fewer resistors, fewer PCB traces, connectivity solutions such as low-voltage and less board real estate – all resulting in lower PCB costs. complementary metal-oxide semiconduc- Absolute I/O Flexibility Use any termination on any I/O bank. Non-XCITE technology alter- tors (LVCMOS). With higher performance natives deliver limited functionality with compromising banking I/O becoming more pervasive, you need restrictions. XCITE input buffers support full and half impedance. this capability not only in single-ended connectivity, but in differential signals as well. Support for Popular Standards Wide support for many I/O standards, including LVDS, LVDSEXT, Now, Xilinx offers second-generation LVCMOS, LVTTL, SSTL, HSTL, GTL, and GTLP. XCITE technology in the Virtex-II Pro™ Maximum I/O Bandwidth With less ringing and reflections, you can maximize your Platform FPGA family, extending to I/O bandwidth. popular connectivity standards like low- voltage differential signaling (LVDS), as Immune to Temperature Temperature and voltage variations lead to significant impedance shown in Figure 2. and Voltage Changes mismatches. XCITE provides complete immunity by dynamically adjusting on-chip termination with digitally controlled impedance Second Generation XCITE technology at all temperatures and voltages. Second-generation XCITE for Virtex-II Eliminates Stub Reflection XCITE technology improves discrete termination techniques by Pro FPGAs provides controlled imped- eliminating the distance between the package pin and resistor. ance drivers and on-chip termination for single-ended and differential I/Os. Increased System Reliability With fewer components on board, XCITE delivers higher reliability. XCITE can be used on any I/O block in any bank, thus offering absolute flexi- Table 1 - XCITE benefits for Virtex-II Pro Platform FPGAs

Summer 2003 Xcell Journal 57 The Virtex-II and the Virtex-II Pro EasyPath solutions are a cost-effective alternative to ASIC conversion Get the – saving you money while significantly decreasing your EasyPath time to market. by Frank Toth Marketing Manager, Advanced Products Xilinx, Inc. [email protected]

Once a working prototype is developed, designers using high-density FPGAs need a risk-free method of reducing the cost of Solution components used in their end-market products and systems. The traditional ASIC approach is expensive and error prone. The designer typically relies on an ASIC conversion methodology provided by either the FPGA or the ASIC supplier. These methods are supported by a wide range of claims for conversion accuracy and performance. Typically, 30 to 40 weeks is required to accomplish such a conversion for mass production. Xilinx attacks this problem head-on with our introduction of the Virtex-II EasyPath™ series solutions, including a Virtex-II Pro™ version, as the newest member of the Virtex™-II family of Platform FPGAs. The EasyPath solution slashes the conversion time to 10 to 12 weeks (Figure 1), and delivers a 30% to 80% cost reduction without risk and without additional investment of engineering time or other resources.

Traditional Conversion: Trial and Error Conventional conversions require direct time and expense for the services of the ASIC manufacturer for fabrication masks and test programs, and for the engineer-

58 Xcell Journal Summer 2003 ing cost of verification and simulation. When the completed system is transferred into production, further system engineer- EasyPath Conversion ing time and expense are needed to 10-12 weeks requalify the final production system EasyPath with this new ASIC. As systems become faster, timing and clocking budgets are tighter, and any slight Custom ASIC Conversion 30-40 weeks change in critical paths brought about by ASIC conversion can cause timing mismatches and race conditions. All of these Design Prototype Build Proto Eval Production factors introduce substantial risk of delay and escalating cost. 6-8 weeks 6-8 weeks 8-12 weeks 10-12 weeks

Risk-Free, Quick, and Easy Figure 1 - EasyPath conversion time compared to custom ASIC conversion. The Virtex-II and Virtex-II Pro EasyPath FPGAs emerge from the conversion process ready for full production without any need for a requalification or proof of performance that would normally be NCD PCF required of new ASIC silicon. EasyPath sil- Test BGN BIT Coverage icon is identical to the FPGA prototype, Report with the logic and routing resources used Customer by the customer design completely tested Specifies V-II & Test, Assemble Immediate for functionality and performance at speed. V-II Pro: and Mark Generate Test Production Density, Speed EasyPath Program Ships & Package per Customer Streamlined Process Once the design is settled and the qualifi- cation completed, you can simply submit four design files (Figure 2), which are stan- Assign dard outputs from any Virtex-II and Part Number Virtex-II Pro design. The EasyPath product is tested for performance and functionality using the same Figure 2 - EasyPath flow techniques as those applied to the prototype FPGA. Designers order the same speed grade, package, and density as they did for the original FPGA. Typical lead times for production quantities range in weeks rather Verifault Fault Test Test than months – from the engineering confir- Graded Library Library mation of the design submittal to full production silicon (thousands of units). There is no need for the customary first Analyze Pull Customer Resources Required Required Design Used in Test Tests for article testing and no risk of the delays that Tests File Design Generation Customer result from multiple spins of ASIC silicon. Design

Generate Test Coverage Aggregate Test Test The manufacturing test of EasyPath silicon Coverage Coverage is based on a foundation of proven FPGA Report test techniques that assure complete testing of the customer design. Typical ASIC testing relies on the com- Figure 3 - EasyPath test program pleteness of vectors generated by the cus-

Summer 2003 Xcell Journal 59 tomer or the ASIC supplier. The ASIC sup- tomer design, as well as testing critical library, with each routing resource tested plier works in conjunction with the design- structures at speed. Using multiple bit- using “source” and “load” techniques er to cover all the possible test cases with stream loads, each resource is instrumented (Figure 4). The “source” provides the stim- vectors to assure correct operation. using a library of Verifault™ verified test ulus, and the “load” evaluates the response. In contrast to this approach, EasyPath designs (Figure 3). The EasyPath solution takes advantage testing is based on instrumenting and test- The resources used in the EasyPath of some of the unique architectural features ing all of the resources used by the cus- design are matched against this proven test of the Virtex-II and Virtex-II Pro FPGAs.

Resource Under Test State Machine: (Block RAM, Driven Source Net 2 LUT RAM, Error to a known Generates Generation Logic DDL, etc.) Detector level Stimulus & Expected Slice Net 1 Outputs Net 3

Tests to cover all Figure 5 - FPGA testing using self tests routing external to slice. Additional When testing routing, for example, you coverage within Slice can allow unused routing resources to be the slice. tied to a known state to test for shorts. Readback As for complicated circuitry such as block Detection Net n Logic RAMs and multipliers, we use multiple bitstreams to instantiate built-in self-test (BIST) structures (Figure 5) designed to thoroughly test these complex circuits. Figure 4 - Routing test using source/load library Error detectors (Figure 6) check for the correct operation of each circuit. Critical resources within the device are speed tested using standard FPGA techniques to guar- startabc antee the device operates at the desired Start DQ CE Token_out EN speed grade. A rin EN data dout DIA start done enbram B Conclusion basel DIB bg sel bgn reout bgxcont ddout The Virtex-II and Virtex-II Pro EasyPath spc pcd WEA solutions eliminate your risk, and give you spc pcd WEB errou b complete control over the expense of con- DQ roa start done t cma a DOA verting to a lower cost solution for CE lea cmp wea advanced systems. Now you can reduce web portsel we errou b total system cost without the need for addi- DQ cmb rob t a DOB CE leb cmp sifa ifad tional engineering resources. You won’t dcmp sifa ifad have to requalify the system for new silicon, or worry about the cost and delay of start done

up up RAM Block a AddrA ASIC silicon respins. You can confidently cc carry_borrow AddrB predict the crossover point for realizing the rev countn enable cost savings of the conversion. ifa_control In light of current market pressures and rstart start tight inventory management, a conventional we ClkA cntl cntl bg ClkB ASIC will not always be the optimum cost seg seg rwr cmp D Q rdone rdone RSTA(SSRA) reduction solution. The Xilinx Virtex-II Pro RSTB(SSRB) EasyPath solution provides you with a risk- free, rapid, and easily implemented cost Figure 6 - IFA13 BIST circuit reduction alternative. Check it out at www.xilinx.com/easypath/.

60 Xcell Journal Summer 2003 World-class partners and services Embedded PowerPC processing solutions Xtreme DSP solutions

Comprehensive family of 10 devices Ultimate connectivity solutions Industry’s best FPGA fabric

Over 200 IP core solutions

Industry-leading ISE software solutions

Virtex-II Pro™ FPGAs deliver more capabilities and Virtex-II Pro EasyPath Solution for Lower Production Costs performance than any other FPGA. For high-volume system production, Xilinx offers a lower cost path In a single device, you get the highest density, most memory, with Virtex-II Pro EasyPath. You can immediately take advantage of best performance, and at no additional charge 400MHz Power PCTM dramatic cost reduction at no risk processors and 3.125 Gbps RocketIOTM serial transceivers. This and no effort. No other company can gives you the fastest DSP, connectivity and processing solutions in offer you this flexibility for design the industry. and production. The Power to Develop Your Design Visit www.xilinx.com/virtex2pro today to get the price and

The Xilinx ISE 5.2i software tools are the easiest to use solution for performance you’re looking for.

high-density logic. With over 200 IP cores, ChipScope Pro debug environment, and compile times up to 6x faster than our nearest competitor,

you can quickly take your Virtex-II Pro FPGA The Programmable Logic CompanySM design from concept to reality. www.xilinx.com/virtex2pro

©2003, Xilinx, Inc. All rights reserved. The Xilinx name, the Xilinx logo are registered trademarks. Rocket I/O and SelectI/O, Virtex-II Pro are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc. The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM, IBM logo, PowerPC, PowerPC logo, and CoreConnect. All other trademarks and registered trademarks are the property of their respective owners. DESIGN CHAIN

Using a Virtex-II Pro for your next design? Make a note to call us.

Network equipment designers face many design challenges, but integrating multi-gigabit transceivers into the system doesn’t need to be one of them. The Xilinx RocketIO Design Kit for SPECCTRAQuest™ includes a complete electronics blueprint that allows you to simulate and implement Virtex-II Pro RocketIO transceivers on your PCB. Together, Cadence and Xilinx provide the technology to speed your time-to-volume and reduce your development costs.

WWW.CADENCE.COM/PARTNERS/ROCKETIO.HTML

© 2003 Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks, and SPECCTRAQuest is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders. by Xcell Staff

Late last year, Canadian-based Alcohol Countermeasure System (ACS) introduced Xilinx Chips Fight the Elan™ personal breath tester, which measures an individual’s blood alcohol con- centration. Developed in collaboration with Xilinx, the Elan tester demonstrates the creative potential for new mass market Drunk Driving products that exploit low-cost, low power- consuming FPGAs. The Elan tester analyzes and displays blood alcohol (%BAC) test results on a Low-cost high-performance Xilinx technology 3-digit LCD display within 10 seconds, yet it’s not much bigger than a cigarette lighter powers development of inexpensive alcohol and costs just $49 USD. breath testers for drivers and law enforcement. Stopping Repeat Offenders ACS and Xilinx have also developed a high-end, voice-recognition alcohol breath tester that will help law enforcement manage repeat offenders. Available today in beta form, the ACS WR3 ignition inter- lock device locks the auto ignition until the driver passes a sobriety analysis by breath- ing and humming into the mouthpiece. What makes this new technology unique is the voice recognition feature – enabled by Xilinx chips – which makes it impossible for the offender to cheat and activate the vehicle Figure 1 - The Elan alcohol breath tester from ACS. with the breath of another individual.

Xilinx FPGAs Key Component “Xilinx low-cost programmable chips provided the technology we required to produce the most advanced alcohol breath testers on the market today,” said Nigel Correia, operations manager at Alcohol Countermeasure Systems. “We needed leading-edge technology combined with low power and low cost, and Xilinx delivered.” ACS partners with North American and European law enforcement agencies in the deployment of its technology. The Elan alcohol breath tester is available to the public and can be ordered directly from ACS online at www.acs-corp.com.

Summer 2003 Xcell Journal 63 FPGAsFPGAs AreAre thethe BrainsBrains BehindBehind “Smart”“Smart” CarsCars Digital signal processing with Virtex-II Pro FPGAs from Xilinx enables a wide range of sophisticated electronics designed to make driving safer.

64 Xcell Journal Summer 2003 by Robert Green example, has now evolved into adaptive output control signals, each under the European Marketing cruise control (ACC), which automatical- control of its own processor (a Xilinx Xilinx, Inc. ly controls the throttle. ACC brakes to MicroBlaze™ 32-bit soft processor, for [email protected] match the speed of the vehicle in front example, or even an embedded IBM and keep a safe distance from it. If the PowerPC™ in a Virtex-II Pro™ FPGA, Karen Parnell vehicle ahead accelerates or changes lanes, Figure 2). Product Marketing Manager, Automotive ACC returns to the pre-set speed of the The high-speed section is dedicated to Xilinx, Inc. cruise control. the real-time processing of video coming [email protected]

According to a study carried out by

Visteon Corporation, safety is the number ENTERTAINMENT one concern of vehicle customers. It’s at DVD the heart of the consumer priority hierar- INFORMATION/ chy (Figure 1). COMMUNICATION Increasingly, equipment designers are ADVANCED SAFETY turning to programmable technology to Remote make cars – and driving – safer. Far Car Safety is at the core NAVIGATION Functions beyond the more familiar tire and braking of consumer needs SAFETY technology, side impact protection, and Vehicle Tracking GPS News, airbags, today’s “driver assistance” systems Auto Panic Sports, E-mail Distress Button Stocks have evolved from the physical to the Signal electronic domain. The latest electronics- Web Voice Vehicle Surfing Games Real-Time Control Diagnostics rich vehicles use sensors to continuously Traffic Reports evaluate surroundings, display relevant information, and in some instances, even take control of the vehicle. Personal Data Access e.g., contacts, calendar Safer, More Efficient – and More Comfortable Driver assistance systems can offer basic Video-On-Demand safety features, such as adding infrared (IR) cameras to improve visibility, but the more advanced equipment can warn the Figure 1 - Hierarchy of consumer needs (courtesy Visteon Corporation) driver of potentially dangerous situations. Using a wider array of sensors, these elec- Other new developments may also from the cameras mounted at the front of tronic systems enable the vehicle to be serve to make traffic more efficient. The the vehicle. Given the critical nature of aware of surrounding traffic, lane direc- “electronic tow bar,” for example, will the application – crash avoidance, emer- tion, and potential collisions. The ulti- enable truck convoys in which the lead gency procedures, and alerts – real-time mate aim is to enable the vehicle to react vehicle is driven manually and the follow- processing is absolutely essential. automatically – whether this involves giving trucks are driven automatically. In Typically, two or more cameras will be ing the driver information or assisting addition to taking some of the burden used to capture a stereo image, thus with car control – so that occupants are from drivers, the distance between trucks enabling calculation of image depth kept safe. can be greatly reduced because the elec- (directly related to real distances from For example, some of the latest trucks tronic driving device reacts faster than a objects) in the FPGA. This information, are equipped with video cameras that cap- human. Not only does this save valuable combined with radar and laser measure- ture images of the lane ahead. If the vehi- road space, but by traveling in the slip- ments, plus the information collected cle changes lanes without using indicators stream of the vehicle in front it saves fuel from gyros and wheel sensors to detect – a sign, perhaps, that the driver is as well. motion, yields a very accurate map of the fatigued – an alert is sounded through the vehicle’s surroundings and its path. cabin loudspeakers. Xilinx FPGAs in Driver Assistance Systems Capturing and processing this informa- Driver assistance can also make drivers A driver assistance system is partitioned tion in real time requires the use of math- more comfortable by automating routine into very high-speed input processing and intensive digital signal processing (DSP) actions. Conventional cruise control, for relatively low-speed sensor inputs and algorithms. Software processing cannot

Summer 2003 Xcell Journal 65 meet these performance requirements, and easily develop the unique, optimized edge FPGA hardware also enables testing at it often takes several conventional DSP detection, image depth, and enhancement real-time rates, something that is impossi- processors to perform such high-speed algorithms that will differentiate system ble to do in software. tasks. Frequently, even ASSP (application- performance from the competition. specific standard product) video processors After processing the video, the decision XtremeDSP – Real-Time Image Processing cannot match the extremely high-speed tree mechanisms can be partitioned So why can Xilinx FPGAs offer faster DSP performance of Xilinx FPGAs, also between hardware (for speed-critical algo- video processing than conventional DSPs? known as XtremeDSP™ processing. rithms such as sudden object avoidance) The fundamental reason has to do with In addition, using fully flexible FPGAs and processor software (for sounding the FPGA architecture’s inherent ability to rather than off-the-shelf video compo- alerts such as lane drift warnings). process data in parallel. In contrast, a DSP nents enables equipment manufacturers to Partitioning speed-critical processes into processor takes in successive instructions and data, and processes them in a serial fashion.

R In addition, the latest Virtex- II Pro family of devices from Obstacle PHY Camera Detection Xilinx also has an array of

PHY embedded, high-performance R PHY Camera R R External Multimedia multiplier blocks to increase Memory Mem I/F Hardware image-processing power even Decisions further. This enables the FPGA PHY Laser to be configured as a large array PHY Radar of multiply-accumulate (MAC) R Lane Detection engines performing multiple OPB/OPB PHY Gyroscope Bridge operations concurrently (in a single clock cycle) as opposed to PHY Wheel CAN Sensors multiple cycles through the sin- PHY CAN I/F gle or few MAC engines avail- Other PHY Accelerator able in conventional DSPs R DSP R External (Figure 3). Memory PHY Brakes Another advantage of Xilinx Mem I/F FPGAs is that you can size the array precisely to suit the calculation requirements, which is ideal Figure 2 - Concept of FPGA in ACC driver assistance system, with pre-verified Controller Area Network (CAN) interface core for performing calculations on

Conventional DSP FPGA Performance Advantage Performance Limitations

Data In • Fixed inflexible architecture Reg Data In • Flexible architecture – Typically 1-4 MAC units Reg Reg Reg Reg – Distributed DSP resources (LUT, – Fixed data width registers, multipliers, and memory) Loop C0 C1 C2 C255 Algorithm • Serial processing limits data Parallel processing maximizes MAC unit • 256 times throughput data throughput – Time-shared MAC unit – Support any level of parallelism – High clock frequency creates – Optimal performance/cost Data Out difficult system challenge tradeoff

e.g., 256 Tap FIR Filter = 256 MAC operations per sample e.g., 256 Tap FIR Filter = 256 MAC operations per sample 256 MAC operations in 256 clock cycles in DSP All 256 MAC operations in 1 clock cycle in FPGA

Figure 3 - Xilinx FPGAs offer unrivaled DSP performance.

66 Xcell Journal Summer 2003 images. Calculations can be performed on be revised during maintenance without Conclusion clusters of pixels, such as discrete cosine trans- costly recalls or extra manpower. The new wave of driver assistance systems form (DCT) macroblocks, concurrently with requires high-performance image process- other blocks in the picture instead of having IQ Solutions for Automotive Applications ing without sacrificing flexibility, espe- to scan the entire picture sequentially. And To address the needs of automotive elec- cially during early stages of research and because processing can now be done in real tronics equipment designers, Xilinx has development of object detection and time, less memory is needed for buffering created a new range of devices with an automotive network technologies. The pixel values when using FPGAs. extended industrial temperature range use of Xilinx FPGAs at the heart of such In addition to real-time performance, option. Called the “IQ” range (Table 1), it systems offers the industry’s best DSP the reprogrammability of Xilinx FPGAs comprises current Xilinx industrial grade performance, unrivaled support for net- also offers superb system flexibility, (I) FPGAs and CPLDs qualified to a new work connectivity standards, and gives enabling algorithm upgrades even after extended temperature grade (Q). system architects a fully flexible design deployment. This is important, as current The first products qualified to operate platform with which to work. Working in driver support systems are still in the early at the new temperature grade are real time, these systems provide emer- stages of research and development. As Spartan™-XL 3.3V FPGAs ranging from gency driver alerts, assist car control, and edge- and object-detection algorithms 5K gates to 30K gates, and the 36 and 72 significantly increase safety. improve over time, hardware upgrades can macrocell XC9500XL be accomplished in a matter of minutes 3.3V CPLDs. In the and with no board redesign. coming months, the IQ Temperature Grade/Range °C family will be expanded Product C I Q Bridging Automotive Networks to include FPGA devices FPGA T = 0 to +85 T = -40 to +100 T = -40 to +125 Today, multiple network technologies up to 300K gates, and J J J have emerged that cover various functions CPLDs up to 512 macro- CPLD TA = 0 to +70 TA = -40 to +85 TA = -40 to +125 and features in the car. These technologies cells in density (Table 2). Table 1 - Temperatures supported by Xilinx products range from multimedia networks, such as media oriented systems transport (MOST) in the cockpit, to car control Xilinx IQ Solutions Silicon Selector networks like FlexRay™ automotive con- Product Family Packages Voltage Density Range trol systems. As vehicles evolve into a truly networked arena, equipment manufactur- XC9500XL CPLDs VQ44, VQ64, TQ100 3.3V 36 - 72 Macrocells ers must determine which standard will be CoolRunner XPLA3 CPLD VQ44, VQ100, TQ144, PQ208 3.3V 32 - 512 Macrocells the most successful or offer the greatest CoolRunner-II CPLD VQ44, VQ100, TQ144, PQ208 1.8V 32- 512 Macrocells advantage over other network protocols. However, one of the real benefits of Spartan-XL FPGA VQ100, TQ144, PQ208, BG256 3.3V 5K - 40K Gates using an FPGA rather than an ASSP is Spartan-II FPGA TQ144, PQ208, FG256, 2.5V 15K - 200K Gates that it allows you to produce designs that Spartan-IIE FGPA TQ144, PQ208, FT256, FG456 1.8V 50K - 300K Gates precisely match interfaces and peripherals to the system requirements – particularly Table 2 - Xilinx IQ solutions silicon for automotive applications useful when trying to interface with protocols in the early stages of development. When you’re trying to get a product to Further Information market quickly, a chipset or ASIC (application specific integrated circuit) re-spin is both costly and time-consuming. www.xilinx.com/esp/technologies/consumer/automotive.htm Xilinx Emerging Standards and Protocols (eSP) With an FPGA, if the specification of a www.xilinx.com/automotive Xilinx Automotive Products – The IQ Range network protocol changes during a standard’s early days, all it takes to support the www.xilinx.com/dsp Xilinx DSP Central latest revision is a relatively simple redesign in software and a download of the new www.xilinx.com/products/logicore/coredocs.htm#DSP Xilinx DSP Core Solutions Documents hardware configuration. You can even do it www.xilinx.com/ipcenter Xilinx IP and Core Solutions Catalog over a wide area network using Xilinx IRL™ (Internet Reconfigurable Logic) www.visteon.com Visteon Corporation Home Page technology, which means the hardware can

Summer 2003 Xcell Journal 67

HowHow toto DesignDesign aa 3DES3DES SecuritySecurity MicrocontrollerMicrocontroller UsingUsing IPIP corescores andand aa pre-integratedpre-integrated IPIP platform,platform, engineersengineers atat SoCSoC SolutionsSolutions builtbuilt aa customcustom microcontrollermicrocontroller platformplatform in– lessin less than than two two weeks. weeks.

by James Bruister President SoC Solutions, LLC [email protected]

Today’s seemingly limitless access to information has also brought forth a need to secure personal and corporate information from unauthorized access and to protect privacy. This need for secure data not only applies to securing wired and wireless communications, but is also important in applications where access control, data integrity, confidentiality, and authentication are required. For this reason, cryptography will find its way into a host of common devices, including bank ATMs, kiosks, information portals, video surveillance equipment, building access controls, and the like.

Summer 2003 Xcell Journal 69 The problem of securing data is a com- The 3DES core uses a three-key con- stored result. In a typical application, a plex one, and applications requiring cryp- catenated DES algorithm to provide 192 communications port such as Ethernet, tographic processing are varied. Many bits of security. Keys can be stored in mem- PCI, USB, or a simple COM port would devices need 3DES (Triple Data ory or input through a software application, be used as a data I/O port. Encryption Standard) hardware accelera- which is run on the secure microcontroller’s The design includes a direct memory tion, because software implementations are microprocessor core. The microprocessor access engine to read and write data simply too slow. In addition, most designs controls data movement to and from mem- from/to the 3DES core to internal FPGA require a combination of features not read- ory. It also sets up the 3DES engine. Extra SRAM or external memory. Also included ily available in off-the-shelf components. microprocessor bandwidth is available for are an internal SRAM controller, an To implement a custom interface or pro- additional application software. We used a interrupt controller, timers, UARTS, and tocol that meets the product’s specific func- 32-bit microprocessor, although a Xilinx an external bus interface. tional requirement, you must either develop MicroBlaze™ core could also be used in The process of encrypting or decrypt- with FPGAs or spin an ASIC. In both cases, our secure microprocessor design. Figure 1 ing a file is simple. The microprocessor the most common approach is to first code is a flow diagram of an encryption/decryp- fills memory from data acquired either the design in a hardware description lan- tion microcontroller device. under software control or through a guage such as Verilog or VHDL, and then synthesize the design to the targeted silicon, such as a Xilinx Virtex™ FPGA. In this article, we will describe how we built a secure microcontroller platform µP using our PiP-EC02 Embedded Con- Control troller IP platform with the addition of our 3DES core.

A Better Approach Encrypted At SoC Solutions, we believe the best Data In I/O or approach to implementing these secure COM Memory Decrypted designs is to start with an IP platform, or Port Data Out IP reference design, which we define as a pre-developed, pre-integrated Verilog or VHDL design. Also known as soft designs or soft cores, these can be target- 3DES ed to FPGA devices. Cryptographic Figure 1 - Secure microcontroller Processor 3DES Secure Data data flow diagram Encryption/Decryption Application Many applications, such as online private information transfers, require that data files or streamed information be secured Reference Design COM port. The microprocessor then sets by encrypting the payload data. 3DES is The two main hardware components of up the DMA engine with a source considered to be very secure because it can the reference design are the microproces- address, destination address, and a block use three separate keys to encrypt data. sor core chip and a platform FPGA, such length. The processor writes a start bit to Our secure microcontroller imple- as a Xilinx Spartan™ or Virtex device. All the DMA engine and then “lets ‘er rip.” ments a smart device that stores 3DES- of the functions (excluding the micro- The DMA engine reads a sub-block from encrypted data in memory; it then processor) are implemented in the FPGA the source address, sends it to the 3DES decrypts the data before storing it back to using SoC Solutions’ IP platforms and core for processing, and then writes the memory. This is useful where data is pro- soft cores. processed sub-block results to the desti- vided as medium to large data files (or The secure microcontroller reference nation address. streams) and where the microprocessor design provides the basis, or starting Timers can be used to poll the DMA has limited bandwidth to do the math- point, for the custom design. This imple- engine dma_done flag to know when the intensive encryption (or decryption) mentation uses the microprocessor to operation is complete. The interrupt con- while simultaneously processing other load memory, control the start of encryp- troller can also be used to signal the end tasks or applications. tion/decryption, and then verify the of the 3DES operation.

70 Xcell Journal Summer 2003 Week 1 RTL Design and PiP-EC02 + DES Engine Verification P AHB APB

Started with PiP-EC02 as a Watchdog UARTs base RTL design Timers GPIO

APB Designed and integrated Bridge the RTL code for 3DES wrapper and DMA engine. Interrupt Controller SRAM Controller

SDRAM Simulated with Modelsim XE, AHB µP Synthesized with Synplify, if

Routed with Xilinx ISE. F D 3DES I AHB M Cryptographic F Arbiter A Processor O Week 2 EBI & Board Level Verification SDRAM and Debug Controller

Designed a simple C/C++ program using RDS02 API to control secure micro hardware. FLASH SRAM Figure 3 - IP block

implementation of SRAM Debugged the hardware and secure microcontroller software using the RDS02.

Ported the design to a specific microprocessor. (EBI). The IP block implementation is Week 2 shown in Figure 3. Now we were ready to try our design in Used the same FPGA hardware and C/C++ code debugged with Next, we designed an interface for the real hardware. To debug our secure micro- the RDS02. 3DES core to the AHB. We selected the controller, we chose the SoC RDS02 AHB to enable fast DMA for 3DES pro- Rapid Development System – illustrated Figure 2 - Secure microcontroller cessing. The 3DES interface and wrapper in Figure 4 – which allowed us to use development flow consisted of a combination of a custom Microsoft Visual Studio™ tools to quickly DMA controller, input FIFO (16x32), out- make software changes and debug the Co-Development is the Key put FIFO (16x32), and the 3DES core. hardware on the fly. We used the Xilinx We developed our secure microcontroller The PiP-EC02 provided the AHB arbiter ChipScope™ integrated logic analyzer in less than two weeks. Figure 2 shows the template. Using the arbiter template to (ILA) to debug the actual design on the development method we used. make the DMA connection to the system Virtex-E development board, shown in bus was a very simple design process. Figure 5. All of these tools were run on the Week 1 The complete design was then simulated same computer. Stepping through code To get the design started quickly, we used using a Mentor Graphics Modelsim XE and triggering the ILA was very easy. the SoC Solutions PiP-EC02 pre-integrated (Xilinx Edition) simulator supplied by Using the RDS02 proved to be an embedded controller platform. The PiP- Xilinx. The PiP-EC02 provided the AHB ideal way to debug, because we tried EC02 contained the needed microprocessor functional model (BFM), as well as all the many, many software iterations. Each controller subsystem, which included an test fixtures we needed to test the micro- iteration took only seconds to recompile advanced high-performance bus (AHB) and processor subsystem. We wrote a simple test and re-run. By comparison, the same ARM™ peripheral bus (APB) on-chip, bench to load memory, start the DMA software iteration would have been far interrupt controller, two timers, internal engine, and then check the encrypted (or more time-consuming if we had used typ- SRAM controller, 16550 UART, AHB decrypted) results that were stored back ical microprocessor development tools. It arbiter, and external memory controller into memory. would have taken up to five minutes to

Summer 2003 Xcell Journal 71 reload the system flash memory using the JTAG port. Once we were satisfied our secure microcontroller hardware was solid and the software was debugged, it was time to port the design to a microprocessor. In our example, we ported the design to an ARM7™ board called the “Brain Board,” shown in Figure 6. Here again, we took advantage of the PiP-EC02. The PiP-EC02 package provided the boot code and software drivers we needed for the UART, memory controllers, timers, and interrupt controller. As for software, all we had to do was add C/C++ code developed on the RDS02 – and modify the RDS02 API function calls to call ARM7 load and store functions. To do this, we used software- Figure 4 - SoC RDS02 Rapid Development System defined macros to retarget the API function calls – nothing much to it. The hardware port was also just a matter of a simple edit to the AHB microprocessor interface and a Verilog, Synplicity, and Xilinx recompile. We then retested the secure microcontroller design on the Brain Board running ARM code, and we were done – a prototype in less than two weeks.

Secure Microcontroller Features • PiP-EC02 embedded controller platform • AHB, SRAM controller, interrupt controller, UART, timers, AHB – APB bridge, external bus interface, general purpose I/O Figure 5 - Virtex-E development board by Avnet • 3DES cryptographic processor core • DES – DMA controller

Conclusion 3DES security is just the kind of value-add our customers are turning to as a way of differentiating their products from the competition. By using a co-development approach instead of coding the design first and then synthesizing it, we were able to design in security in less than two weeks. For more information on SoC Solutions, visit www.xilinx.com/products/ Figure 6 - SoC Solutions’ “Brain Board” logicore/alliance/soc/soc.htm or contact [email protected].

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PCI Extender Now Shipping! 64-bit/66MHz Active Extender ts! - Intel® 21154 PCI-to-PCI bridge - Active PCI Extender with THREE 32/64-bit slots DN6000k10/DN6000k10S - Easy access to all PCI signals Up to five -- 2VP70/2VP100's - 5V 3.3V or 3.3V 5V signal translation - Frequency division of PCI Clock - Numerous LEDs show system status A Sample of Our Services: - +3.3V not needed on host Mr. Freaky Says: - FPGA/ASIC/Board Design Mr. Lazy Says: "This stuff is WAY - Turnkey Verilog/VHDL "I hate searching for cool!" Design and Verification bugs; these guys made my life easy!" - White-Backed - ASIC FPGA Design Translation Mousebird - HW Emulation and Testing - Blue Naped Mousebird - Algorithmic Acceleration The DINI Group 1010 Pearl Street, Suite 6 La Jolla, CA 92037-5165 ASIC http://www.dinigroup.com 600M+ Voice: (858) 454-3419 Gates FAX: (858) 454-1728 SOLD! Email: [email protected] by Andrey Filippov, Ph.D. President Elphel, Inc. How to Use Free [email protected] Just recently, Gordon Moore “renewed” his law for another decade, predicting that the density of integrated circuits will continue Software in FPGA to double every 18 months. At this daunt- ing pace, how is it possible to keep up with the ever-growing challenges of electronics design? One answer is to effectively reuse Embedded Designs what others have done before, so you can focus on the really new issues. Looking to bring the Free Software/Open Source Software movement The growing number of successful adoptions of the Free Software and Open into the realm of hardware design, Andrey Filippov built a low-cost, Source Software (FS/OSS) development high-performance network camera using a Spartan-IIE FPGA and free models has proved the effective reuse of WebPACK development software from Xilinx. software in applications development. Xilinx programmable logic devices represent a “frontier” between the hardware and the software worlds. They offer a unique opportunity to apply FS/OSS solutions to hardware design. I strongly believe that the potential for successful applications of the FS/OSS models to hardware design is even higher than for software itself – you can always make a profit by selling the actual hardware. In this article I’ll show how this approach helped me to create a high- speed, high-resolution network camera (a class of cameras that do not need additional computers to serve digital images and video over the LAN or the Internet).

Background I had my first experience with GNU/Linux less than two years ago when I realized I would have to program the network cameras I designed around the ETRAX100LX processor. The processor, made by Axis Communications AB, was optimized for running GNU/Linux. Having the experience of designing many microprocessor-based systems that were mostly programmed in assembly languages, I was really amazed that in just a couple of weeks my camera was able to serve JPEG images over a LAN using HTTP protocol. It was possible to control acquisition and view images using any standard web browser.

74 Xcell Journal Summer 2003 That Model 303 camera combined soft- pletely troubleshoot a one-time pro- I did not use that IP, however, because it ware from multiple sources – GNU/Linux grammable FPGA by simulation, it would prevent me from having an open itself, specific code for the ETRAX plat- would be too difficult and time con- source design. So, I just used the IP specs as a form, and many, many others. I just had to suming. On the other hand, the temporary substitute for my own lack of add specific drivers for my hardware and Xilinx Spartan™-IIE XS300E chip expertise in Xilinx devices. modify some of the existent programs. was five times higher (in gate count) Knowing that my project was doable in What impressed me the most was the ease than the biggest anti-fuse FPGA I terms of hardware, I downloaded for free of navigation in big, third-party software was able to design. Having the WebPACK™ 4.2i software from the Xilinx systems where I could find just the right option to switch between simulation website to try it out. I wanted to see if there place to insert small patches of code to and actual hardware testing proved was anything else I was not aware of, at the modify functionality. to be much more efficient. moment, that would prevent me from follow- Being primarily an electronics designer, I ing my plan. – Make the system flexible with started to think it was possible to make sim- To get some initial experience with both upgradeable “hardware” algorithms ilar productivity enhancements to the hard- Xilinx devices and software, I read Xilinx in the same way as it is done with ware/FPGA part of the camera system. Application Note XAPP610 and decided to software – this would significantly try an 8x8 DCT core (needed for JPEG increase the lifespan of the product. Design Goals compression). The application note provid- Starting the design of a new camera – – Increase the number of possible ed Verilog sources, which allowed me to Model 313, shown in Figure 1 – I had the product applications by providing a synthesize, map, and place-and-route the following goals in mind: customizable development platform. design – but I had problems trying to simu- • A high-performance, simple network • Use free, downloadable development late the design. camera that fully supports the frame tools so you could customize my prod- It turned out that the “lite” version of a rate/resolution of megapixel CMOS sen- uct without spending thousands of third-party simulator bundled for free with sors. That means 15 fps at 1280x1024 dollars on software. the WebPACK software had limitations on resolution (or proportionally, 60 fps at design complexity. The most obvious prob- 640x512 resolution, for example). Selecting the Right FPGA lem was the 500-line limit on the source code. The XAPP610 DCT implementation alone • Use a reconfigurable FPGA for image When I started to think about the new cam- was bigger, but I was able to try simulation by acquisition/processing/compression – era design, my only FPGA experience was removing comment lines and combining as opposed to two specialized ASIC with anti-fuse devices of up to 60K gates. So, multiple lines into one. chips and one-time-only programma- I was open to consider different FPGAs that The “lite” simulator did run, but that ble devices (as was used in the model matched my design goals. (At that point, I workaround trick would not work for my 303 camera). That goal came from the was not even sure it was possible.) complete project, so I had to forget about that following requirements to: Soon I came upon a good candidate. It was the largest (at that time) member of the simulator and use something different. – Simplify the product development. Xilinx Spartan-IIE family – a 300K-gate All the rest of the WebPACK software I estimated if that if I were to com- XS300E. worked just fine for me. Eventually, I was able To find out if the XS300E was to utilize more than 98% of the chip’s capable of handling JPEG com- resources to meet all of my timing constraints. pression of 1.3 megapixel images at 15 fps, I “window-shopped” System Architecture for commercial IPs that per- Now that I knew I could fit my design to a formed similar tasks. I was able Spartan-IIE, I switched to the schematic to find some device utilization and PCB design. The Model 313 camera specs that indicated that I would consists of two boards, shown in Figure 2. have enough room to implement The small board has just the CMOS image all the functions I needed: frame buffer sensor and closely related circuitry. SDRAM control, image fixed patter noise The main board consists of a 1.48 by elimination, color space conversion, and 3.50 inch, four-layer PCB that has the fol- CPU interfacing. lowing principal components: • 32-bit, 100 MHz processor Figure 1 - Model 313 (ETRAX100LX, Axis Elphel network camera Communications) running a

Summer 2003 Xcell Journal 75 • IEEE 802.3af compliant power over LAN uses an isolated DC-DC converter to supply 3.3V from the input 48 VDC. An additional converter provides 1.8V to the Spartan core.

FPGA Code Most of the system functionality is imple- Figure 2 - Main PCB of Model 313 camera mented in the Xilinx Spartan-IIE FPGA. The code is written in Verilog HDL and is available for download at my Elphel website GNU/Linux operating system. The the-fly FPN (fixed pattern noise) elimi- under the GNU/GPL (general public processor has multiple embedded nation (subtraction of the background license) license. It is designed around a four- peripherals, including a network MAC. frame and multiplying each pixel by its channel SDRAM controller that uses reverse sensitivity). • 10/100 Mb Ethernet PHY embedded block RAM modules as “ping- (BCM2521A4KPT, Broadcom). • 3-PLL programmable clock generator pong” buffers to provide quasi-simultaneous (CY22393FC, Cypress). This part pro- • 16 MB (4Mx32) SDRAM system block access for the following data sources vides fixed frequencies that have to be memory (MT48LC4M32LFFC-8, and receivers: available during system startup (20 Micron). • Image data from the sensor, either MHz processor PLL input and 25 processed or raw, one- or two-bytes per • 8MB (4Mx16) flash memory MHz for the network PHY). It also pixel, arranged as 256 (128) pixel lines (MT28F640J3FS-12, Micron) used to generates two programmable clocks • Calibration data to the FPN elimination store GNU/Linux, applications, Web that add extra flexibility for FPGA module prepared by software in advance, pages, configuration files, as well as operation (in other words, it is possible 128x16-bit blocks bitstreams for the FPGA configuration. to compare simulation results with the • Spartan-IIE, 300K-gate, reconfig- actual maximal operation frequency for • Data to the JPEG compressor, arranged urable FPGA (Xilinx XC2S300E- any particular module). as square blocks of 16x16 bytes 6FT256) used to control image acquisition, processing, frame storage in SDRAM, image compression, and transfer to the system memory using the processor DMA channel. The FPGA is configured using JTAG pins connected to the general- purpose parallel port of the processor. • Image memory, 16 MB (8Mx16) SDRAM (MT48LC8M16LFFF-8, Micron) connected directly to the FPGA so that accesses do not interfere with the system bus. This memory is dedicated to the image frame buffer that is used to store both the uncompressed image data as well as calculated coefficients for the on- Figure 3 - The importance of the JPEG encoder in the Spartan-IIE dwarfs the other components on the PCB.

76 Xcell Journal Summer 2003 • CPU access to the SDRAM (normally 4. Modification of the “heart” of the cam- • The resultant product has unique fea- used to read raw sensor data and write era – the Spartan-IIE XS300E FPGA. tures that I was desperately looking for back the calibration data for the FPN as a customer. I wanted a camera I As of now, the camera has only a baseline elimination). could modify to fit my needs. In many JPEG compression algorithm implemented cases, the required modifications I The JPEG encoder uses two-thirds of the in the FPGA, which can serve still JPEG wanted were really minor – but still FPGA resources, as shown in Figure 3. The images and Apple Quicktime movies that are impossible in a proprietary camera. encoder consists of the chain of the process- made of a sequence of the JPEG-encoded ing modules, some of which use block RAM frames. On several occasions I was asked, “Isn’t for data buffering and table storage: By adding new software to the camera that scary to open your design? What if – Bayer-to-YCbCr converter processor and HDL code to the FPGA, you somebody will use it and get all the can use the camera for experiments with money?” – 8x8 DCT based on the Xilinx advanced image/video compression algo- XAP610, modified to provide block- • First of all, the license used for the rithms – such as 2000JPEG for better asynchronous operation and to Elphel products (GNU/GPL) is size/quality still images or MPEG (-1, 2, 4) increase dynamic range not exactly the same as the public for video. Additionally, you could program domain. Any company that wants to – Quantizator and zigzag encoder the camera processor and FPGA for motion manufacture cameras based on Elphel detection, pattern recognition, particle dis- – RLL encoder designs will have to play by the same crimination — or whatever else you may rules – the GPL legal protection is no – Huffman encoder think of. weaker than that of closed source – Bit stuffer. Conclusion proprietary licenses. The output data is transferred to the sys- So how did the FS/OSS approach help me to • It is actually impossible to steal this tem memory using the CPU DMA channel. create the Elphel Model 313 camera? Maybe kind of an open design. Even if some- it did not cut my FPGA development time in one in some far-away country (where Results the same proportion as it did for the software there are no copyright laws and GPL is Since the Elphel Model 313 reconfigurable, development – the area where it is really not enforceable) manufactured a deriv- high-resolution network camera was first mature. But the overall FS/OSS co-design ative closed product, it would lack the described in the LinuxDevices online maga- technique really worked: critical feature of Elphel cameras – zine Dec. 3, 2002 (and Dec. 4, in Slashdot), • I used free Xilinx 2-d DCT imple- their custom reconfigurability with many of the inquiries I received have been mentation that utilized about 30% of Spartan FPGAs. about its open nature as a user-customizable the chip resources. It did not meet platform. exactly the requirements of my design • Elphel has more cameras under devel- There are four possible kinds of cus- – but this is where the advantage of opment, and I would consider wider tomization of the camera. Three of them are free code is obvious: I could modify availability of the products based on inherited from the previous Model 303 cam- the code in a way I liked. With closed the Model 313 design as free promo- era and are related to the open software: proprietary IPs you can’t do this. tional material for my company. 1. Modification of the user interface with Web design tools URLs for more information: 2. Addition of new applications (or modification of existent ones) that can be • www.xilinx.com/spartan2e/ – Spartan-IIE FPGA family downloaded to the camera • www.xilinx.com/ise/webpack5/ – latest free ISE WebPACK software 3. Modification of the kernel (Linux) to • www.xilinx.com/xapp/xapp610.pdf – Application Note XAPP610 add new drivers. “Video Decompression Using IDCT” However, only the use of the Xilinx • www.elphel.com – schematics and software for Model 303 and 313 network cameras reconfigurable FPGA – supported by the free-for-download ISE WebPACK develop- • developer.axis.com/products/etrax100lx/ – Axis ETRAX 100LX platform ment tools – made it possible to increase the • www.fsf.org – Free Software Foundation camera performance nearly 100 times. This hardware/software customization turned out • www.opensource.org – Open Source™ Initiative to be the most powerful of the four possible • www.linuxdevices.com – previous articles on network cameras. types of customization:

Summer 2003 Xcell Journal 77 WIND RIVER® PLATFORMS

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1.800.545.WIND www.windriver.com Transport Technology Consortium members – ensures that the HyperTransport technology will continue to satisfy the ever- increasing need for bandwidth,” said XilinxXilinx DeliversDelivers Gabriel Sartori, president of the consortium. “The reference design demonstrates how HyperTransport technology enables next-generation networks by providing a universal connection that reduces the num- HyperTransportHyperTransport LiteLite ber of buses within a system, provides a high-performance link for embedded applications, and enables highly scalable multiprocessing systems.” “By combining the highly flexible ReferenceReference DesignDesign Xilinx Virtex-II FPGA solution with our MIPS-based processors, OEMs can easily add additional features with minimal Xilinx Virtex-II Platform FPGAs and Broadcom’s impact to their design schedules,” said Krishna Anne, strategic marketing man- MIPS-based processors enable rapid development ager of Broadcom’s Broadband Processor of gigabit Internet protocol products. Business Unit. Collaboration between companies like Broadcom and Xilinx – both HyperTransport Technology Consortium members – ensures that the HyperTransport technology will continue to satisfy the ever-increasing need for bandwidth.

The HT-Lite reference design is used as a slave interface to end an HT chain supporting an 8-bit link width at a design speed of by Xcell Staff This reference design underscores the 400 MHz DDR (800 Mbps per I/O). The companies’ commitment to a technology HT-Lite core uses fewer than 1,900 slices in A new minimal HyperTransport™ (HT- relationship aimed at providing interopera- a Virtex-II FPGA. Lite) reference design for Xilinx Virtex™-II ble interfaces for use in communications, The HT-Lite reference design is available Platform FPGAs enables rapid development networking, and consumer applications. now free of charge. Documentation and of designs using Broadcom™ MIPS™- The HT-Lite reference design is one of sev- instructions for downloading the reference based processors. The Virtex-II FPGA lever- eral efforts resulting from Broadcom’s mem- design can be found at www.xilinx.com/ ages Xilinx flexible SelectIO™-Ultra bership in the Xilinx Reference Design xapp/xapp639.pdf. Customers in need of a technology and Broadcom’s minimal Alliance Program. full-featured HyperTransport solution can HyperTransport IP to create a bridge “Collaboration between companies like use the full HT core, also available now at between processors and ASSPs. Broadcom and Xilinx – both Hyper- www.xilinx.com/ipcenter/.

Summer 2003 Xcell Journal 79 Low-Cost IP Connectivity Lets Diverse Systems Communicate The proliferation of interface and communication standards from industry to industry has made it difficult to get systems talking to each other. A configurable low-cost board solves the problem.

by Grant Stockton President & CEO Technovare Systems, Inc. [email protected]

Tough economic conditions and cost sensitivity are making it difficult for designers of commercial and industrial equipment to provide the one feature customers request most – network connectivity. Network connectivity and the ability to manage systems from a Web interface are highly valued. But implementing them has remained elusive because companies do not want to design them in as a standard feature during an economic downturn.

80 Xcell Journal Summer 2003 Solving Problems for Diverse Applications added, you will find the communication Most commercial and industrial applica- protocol that you employ most frequently tions have developed their own set of stan- is often not sufficient to handle the system’s dards, protocols, and communication bandwidth requirements. To address this interfaces based upon their own unique problem, the NEP board incorporates a requirements. high-speed Ethernet connection. Systems CAN is widely used in the industrial- that are now communicating over low- automation market, for example, and two- speed interfaces such as RS-232 can easily wire communication is widely used in migrate to IP-based Ethernet. building-automation applications. The The NEP board’s unique user-defined Figure 1 - NEP board TSINET100BT32C convergence of industry-specific commu- interface allows applications to take full nications protocols such as these with IP- advantage of 10/100 BaseT Ethernet data Technovare’s Network Enabled based Ethernet has created a large number rates by allowing parallel and high-speed Processor™ (NEP) board shown in Figure 1 of nodes in which translation from one serial connectivity to the host system. provides an off-the-shelf solution to this network to another is required. Just as every industry has its own com- dilemma by letting system designers inte- munications protocol, every system usu- grate networking into their feature set ally has its own user interface. The quickly and without the expense of an proliferation of interfaces generally • Programmable interface implemented by additional design cycle. requires user-interface software on the Spartan FPGA The NEP board integrates an embedded host computer that communicates with Web server that performs all of the process- • 10/100 BaseT Ethernet interface the system via RS-232, USB, or some ing and services required for network con- other standard interface. Any other host nectivity such as TCP/IP, SNMP, HTTP, • Dual UART interfaces for RS-232 and RS- computer wanting to communicate with Telnet, and FTP. A key enabling feature of 485 to support serial data transmission, the system must first be loaded with the the NEP board is a user-definable interface translation, and control interface software and be directly con- implemented by a Xilinx Spartan™ FPGA. nected to the system. • USB1.1 interface transmits up to 12 Mbps The Spartan FPGA’s flexibility and This problem is alleviated with the serial data configurability allows host systems to com- NEP board’s embedded Web server. Any municate with the NEP board using any • 4 MB SDRAM, 16 MB flash memory host computer with a Web browser can digital format, protocol, or standard. log into the system from any location on Standard interfaces such as RS-232 and • 32-bit Motorola ColdFire™ microprocessor the entire Internet – with proper authori- RS-485 are available on all versions of the zation – and have access to the user inter- • VxWorks™ real-time operating system with NEP board. Once TCP/IP processing has face that runs on the NEP board. embedded TCP/IP stack taken place, data can be sent out over a Equipped with a 32-bit RISC proces- standard network connection consisting of • Remote configuration and in-circuit sor, 4 MB of SDRAM, and 16 MB of a single 10/100 BaseT Ethernet port. firmware update capability flash memory, the NEP board’s Web serv- Cores for many parallel and serial er can serve sophisticated Web pages con- interfaces such as I2C, SDLC, EPP, USB, • PC/104 form factor. sisting of HTML-based pages and Java and CAN are available and can be inte- script. For systems that require more grated on request. memory space, a PCMCIA expansion In addition to providing you with a card will be available shortly. network-connectivity solution, the NEP Table 1 - NEP board features board is also a generic processing platform Conclusion that can offload your host system of com- The NEP board is ideal for these appli- The NEP board delivers a user-friendly, puting overhead and even run an entire cations. It provides pre-configured com- Web-based interface that creates network embedded application. Equipped with munications interfaces for many standard connectivity to everyday existing systems. Motorola’s 5272 Coldfire™ 32-bit RISC protocols as well as the ability to create The board’s affordable price – about $150 processor, Wind River Systems’ custom interfaces for ones that do not for 1,000-unit orders – lets system designers VxWorks™ RTOS, 4 Mbytes of SDRAM, already exist. Its interface translation capa- integrate their applications into existing and 16 MB of flash RAM, the NEP board bility between UART and 10/100 BaseT and future systems without affecting cost is a formidable processing platform for Ethernet permits easy integration into or product delivery schedules. For more many embedded applications. Its primary existing computer and control systems. information, visit Technovare’s website at features are shown in Table 1. As systems mature and more features are www.technovare.com.

Summer 2003 Xcell Journal 81 PlatformPlatform DeliversDelivers Fast,Fast, FlexibleFlexible ACAC Servomotor-ControlServomotor-Control DesignsDesigns New digital motor-control applications exceed the capabilities of conventional solutions. InternationalInternational Rectifier’sRectifier’s AcceleratorAccelerator platformplatform solvessolves thisthis problemproblem andand reducesreduces developmentdevelopment timetime byby eliminatingeliminating programming,programming, coding,coding, debugging,debugging, andand codecode maintenance.maintenance.

by Jasbinder Bhoot achieved by regulating the motor cur- DSPs and microcontrollers can no longer Senior Manager, Strategic Solutions rent. It requires high-performance com- keep pace with the new generation of appli- Xilinx, Inc. putation in the range of tens of cations that require not just higher perform- [email protected] microseconds. Speed control, on the ance but more flexibility as well – without other hand, requires relatively moderate increasing cost and resources. International Toshio Takahashi computation speeds, typically in the Rectifier Inc. provides an answer in its Technical Manager range of hundreds of microseconds. Accelerator™ Motor Control Design International Rectifier Both functions are usually implement- Platform. The Accelerator platform lever- [email protected] ed by a DSP or microcontroller. A motion- ages low-cost Spartan™ FPGA technology control ASIC is sometimes added to to provide a re-configurable signal-process- Digital signal processors (DSPs) and complete high-performance functions ing architecture that uses soft peripherals. microcontrollers have traditionally been such as the PWM (pulse-width modula- It achieves unmatched motor-control per- used for digital motor-control applications tion) waveform generator, encoder signal formance with feedback-control-loop band- in both low-performance AC inverter interface, and so forth. widths of up to 5 KHz. drives and high-performance servo drives. Many demanding servomotor applica- But a new generation of applications is tions such as high-speed factory automa- New Challenges in Motor Control pushing their performance limits. tion systems and fly-by-wire/drive-by-wire A class of new motor-control applications Motor control requires both torque vehicle control systems require higher lev- that require both high performance and the and speed control. Torque control is els of timing performance than ever before. flexibility to support a variety of motor-

82 Xcell Journal Summer 2003 Functions that are far from the machine side and closer to the host communication Software-Intensive Hardware-Rich Environment Environment (or a man-machine interface) require - Lots of memory - Less memory much slower processing. These tasks are - Fast computation - Fastest computation usually very complex and require a large - No dedicated hardware - Motion Peripheral Hardware Power Module amount of memory. Torque control, for

Multi-Axis Gate Driver BLDC example, can be implemented using a sim- Networking Closed- Drop and Servo Position Loop ple step function, but position coordina- Power Protection Motor User Sequencing Coordinate Speed Torque Management I/O PLC and Control Control tion and interpolation require many more Peripheral Interpolation Host Current Host control parameters and therefore require COMM Sensing COMM Encoder more memory.

MillisecondsHundreds of Micro- Tens of Nano- Motor control is made even more microseconds Tens of seconds nano- seconds microseconds seconds complex by a chain-reaction phenome- non. Torque control requires higher per-

PC formance than speed control, for

Programmer example, but the impact on system Figure 1 - Servomotor drive system functional overview requirements does not stop there. The integral of torque is speed and the inte- feedback scenarios cannot be served may be delayed. Or there may be tasks that gral of speed is position. Due to this economically by off-the-shelf DSPs and are one-time driven events. Each task is con- chain reaction, each parameter requires a microcontrollers. These devices have three trolled by a multitasking operating system different processing speed. A real-time inherent limitations: that is closely coupled with a DSP’s or micro- operating system is needed to satisfy these 1. Traditional DSPs and microcontrollers controller’s interrupt structure. various processing speeds. used fixed hardware logic to imple- Figure 1 shows a functional overview of ment motion peripherals and commu- a typical servo-drive system. The computa- Standalone DSPs Can’t Cut It! nication ports. This limits your ability tional requirements can be divided into In order to meet the challenges, most to adapt the design to different types two segments: standalone motion-control DSPs must of feedback devices and peripherals. 1. A hardware-rich environment for tasks increase memory resources for program- that require very fast computation 2. High-end servomotors require signifi- ming and data. Even this many not solve cant computation power for torque 2. A software-intensive environment for the problem because software solutions for control. A single DSP or microcon- tasks in which performance in less logic peripherals are difficult to implement troller cannot always meet perform- critical; software implementation, without sacrificing performance. ance requirements. Multiple DSPs or however, requires additional memory Stated in numerical terms, the torque- microcontrollers are needed, often bandwidth and programming effort. control loop computation update rate for with an ASIC to perform the motion- control tasks. This not only adds cost AC Power but also introduces complex function- Accelerator Chip Set Analog Speed al partitioning. Reference

3. DSPs and microcontrollers require a FPGA (Spartan-II -300) select A/D DC Bus A/D MUX Interface Feedback high level of support to maintain the RS-232C DC Bus Dynamic BRAKE or Brake Control torque algorithms. Although the Multi-Axis RS-422 ++ Host Space - θ Dead - j Vector maintenance task is easier if the algo- SPI Host e Time or + PWM IR2137 Interface Register Interface - rithms are written in a high-level FAULT Other Host Parallel Controller ++ FLT_CLR language such as C, they are typically Interface Configuration Registers Ks dt Monitoring written in assembly language. Registers Period/duty Counters IR2175 jθ 2/3 e Period/duty Typical Servo-Drive Control Architecture Counters IR2175

Resolver Analog In a typical digital closed-loop servo control 1/T Counter Reference Quadrature Filter Speed Decoding system, functions are divided into subtasks Measurement

that operate at different update rates depend- Encoder or Motor ing on the available bandwidth and process- Resolver ing priority. For example, certain tasks need Figure 2 - Accelerator block diagram to be implemented in real-time while others

Summer 2003 Xcell Journal 83 implemented in the DSP or microcontroller. the communication protocol. The pro- Motion-peripheral functions are implement- grammable nature of the FPGA I/O ed in a dedicated ASIC. allows direct interfacing to International Dividing tasks between two ICs is nec- Rectifier’s high-voltage ICs, the IR2137 essary because torque control demands a and the IR2175, which control and sense much faster computation update rate and electrical power to the motor. it becomes extremely difficult to perform torque control and the other control FPGA Technology Makes the Difference functions. Therefore, the traditional Spartan-II FPGAs deliver the performance approach of using a DSP or microcon- that allows critical control functions to be troller – with or without an ASIC – is implemented in hardware rather than soft- Figure 3 - The Accelerator motor-control platform rapidly approaching the point of being ware. By implementing these parameters in unable to satisfy performance demand, hardware, latency and execution time do a servo drive must be in the 25-microsec- faster development time, and easy, low- not vary: The solution is inherently fast ond range to achieve 4-KHz torque band- cost software maintenance. and deterministic. The FPGA-based solu- width. There are also a wide range of tion provides computation speed of the emerging motion functions that require The Accelerator Platform current-control function well below 5 very specific programming, fast computa- International Rectifier’s Accelerator plat- microseconds, which in turn enables high tion, and unique digital logic. Unique form is a complete reconfigurable motor- PWM carrier frequency update. The FPGA logic of this type includes dead time drive-control design platform. Based on the also allows the torque-control loop compensation, monitoring the tempera- Xilinx Spartan FPGA family, it provides response to reach 5 KHz at the -3 dB point. ture of the power devices, accurate motor- the flexibility needed for many motion This high-bandwidth torque control loop phase voltage-feedback sensing, current peripheral types as well as the high band- provides low harmonic current ripple. sensing, and motor-machine parameters. width needed for torque control. Flexibility Interfacing with recently introduced low- These functions require speeds in the is achieved by providing various object- inductance servomotors such as linear nanosecond range. code sets, which are used to reprogram the motors becomes much easier. Implementing motion functions in an FPGA as needed. ASIC plus a DSP also presents a challenge Figure 2 shows a block diagram of the Customizable Motion-Peripheral Logic because it requires functional partitioning. All Accelerator system. All necessary control Servo applications require many different closed-control functions (including torque algorithms are implemented in the types of interface circuits to accommodate control, speed control, and positioning) are Spartan-II FPGA, including the logic for a variety of sensors and feedback devices.

Closed Loop Velocity Control, Sequencing Control Closed Loop Current Control 2 Update Rate = PWM Carrier Frequency / 2 Update Rate = PWM Carrier Frequency x1 or x2 MUX 8-Channel EXT_REF CNVST Serial A/D DCV_FDBK A/D CLK Interface Feedforward Interface DATA Path Enable 2

Velocity VQLIM VQLIM+ DC Bus Dynamic Optional SPDKI - Current Sense Control BRAKE SPDKP CURKI Brake Control Enable GSenseL IQREF INT_REF PI CURKP + GSenseU ModScl VQ 6 +++ VQS Gate START PI RAMP Signals STOP -- jθ Space Dead DIR Vector PWM Time Sequence + VD e VDS FLTCLR PI FAULT Control IDREF SYNC Accel IQLIM+ - FAULT Rate Decel IQLIM- PWMmode PWM ACTIVE Rate VDLIM- Slip VDLIM+ PWMen 2Pen Dtime Gain 4096 Slip Gain AngleScale MaxEncCount RCV Enable InitZval SND RS-232C/ SpdScale 3 RS-422 I2 I3 ++ Encoder RTS I1 x I2 Interface I1 IO dt A/B/Z CTS Configuration I3 Quadrature Registers Decoding Encoder 3 Hall A/B/C SCK Host 0 EncType SDO SPI IQ Scale 4096 Register Optional InitZ Zpol SDI Slave Current Sense CS Interface Interface IQ I2 I3 IV IR2175 Motor 0 I1 x I2 I1 Phase Monitoring I3 Interface Current V 17 jθ Data Registers 2/3 Motor Parallel ID e IW IR2175 Address 0 I1 x I2 I1 Phase Control Interface I2 I3 I3 Interface Current W

IQ Scale 4096

Current Current Communication Modules Offset W Offset V

Figure 4 - Detailed control function block diagram

84 Xcell Journal Summer 2003 Motor-position sensors may be either an Accelerator Approach Traditional Approach encoder or resolver, for example, depending on the specific application requirements. There are many different types of encoders, IRACS201/IRACO201 Hardware Design Software Design Mechanical Design Design Platform (28 man-weeks) (44 man-weeks) (Nine man-weeks) such as incremental, absolute, sine, cosine, or serial-data types. Each requires very different logic to implement. By leveraging the Configuration (1 man-day) Mechanical Part Adaptation programmable nature of the FPGA, (1 man-week) Drive Integration/Verification Test Accelerator can support multiple types of (24 man-weeks) feedback devices without changing the Low-Cost Networking Customized Servo Host Interface physical hardware. High-Cost, High-Risk Networking Customized Servo Host Interface Accelerator Platform – Hardware Construction The Accelerator platform is pictured in Motion Profile/Sequencing System Integration Figure 3. It is rated to handle up to 1.5-KW Motion Profile/Sequencing System Integration output with a 300% overload for 1 second. Its continuous power rating is 230V/7Arms. Total Manpower Total Manpower Position feedback is implemented using an = 1.2 man-weeks = 105 man-weeks incremental encoder interface with an index marker pulse. Accelerator can support either Figure 5 - Servo-drive design process comparison 115 V or 230 V AC single- or three-phase inputs. The system is also equipped with a a block diagram illustrating configuration son to the traditional DSP-based approach. variety of protection circuits ranging from capability. Configuration switches are locat- The Accelerator system significantly over-current protection, short-current pro- ed at each control section. An induction reduces the development time of a servo tection, and over-temperature protection as machine, for example, can be configured by design by eliminating programming, well as over-voltage protection. enabling the slip-gain block and adjusting coding, debugging, and code maintenance. The Accelerator platform integrates the ID and IQ current feedback scaling gains. latest chipsets from International Rectifier – The Accelerator platform includes a Conclusion the IR2137 and the IR2175. The IR2137 is toolbox for designing control algorithms The Accelerator platform provides a low- a monolithic 600-V high-voltage gate driver using graphically connected control blocks. cost solution for servomotor drive designs with built-in over-current protection. The toolbox contains the Control Block and still maintains the levels required The IR2175 is a monolithic 600-V current- Library, which is a complete set of control for today’s high-performance, permanent- sensing IC in a SO8 package. These two primitives available in Simulink™. It can magnet, and induction machine control high-voltage ICs teamed with the Xilinx be expanded when needed to create unique systems. The platform is based on a Xilinx Spartan-II FPGA device simplify the com- peripheral blocks. The Accelerator platform FPGA device that allows flexibility for cus- plicated design task of analog and power also uses a unique Matlab™-to-Verilog tomized functions without compromising electronics circuits such as gate drivers, pro- Porter (MVP) tool, where the Verilog code the time-critical machine control functions. tection, and current-sensing functions. is generated, synthesized, and directly Low cost is achieved in two ways: downloaded into the Xilinx Spartan-II • DSP functions are implemented in System Design Flow and Configuration FPGA to configure functionality. This parallel using FPGA devices. This The Accelerator platform comes with all method relieves you of considerable manu- approach removes the need for using the hardware and software needed to design al translation or re-hosting effort. multiple standalone DSPs. a complete high-performance motor- Accelerator comes with a Verilog library • A proven, flexible hardware architec- control system. It supports an encoder- that contains servo-specific, parameterized, ture allows rapid development of com- based servo amplifier, resolver-based servo fully tested motion-peripheral circuit mod- plete systems, which drastically reduces amplifier, and a sensorless control algo- ules. A current-sensing interface module, the resources required for rapid system rithm. Each of these products can be encoder-feedback module, and PWM development. licensed from International Rectifier. waveform generator are examples of unique You can configure the control structure, motion peripheral modules. The Accelerator platform is available tune the regulator control loop, and choose Figure 5 shows the impact of the today directly from International Rectifier. various communication protocols without Accelerator platform on the resources needed Additional details can be found at rigorous programming effort. Figure 4 shows to develop a servo-drive system in compari- www.irf.com.

Summer 2003 Xcell Journal 85 XilinxXilinx FPGAFPGA BlastedBlasted intointo OrbitOrbit A radiation-hardened Xilinx FPGA gives the Australian FedSat satellite powerful reconfigurable computing capabilities.

by Peter Bergsman Associate Editor Xilinx, Inc. [email protected]

On the morning of December 14, 2002, the ground shook at the Yoshinobu Launch Range at the Tanegashima Space Centre, on the island of Tanegashima in southern Japan. The 170-foot H-IIA rocket streaked aloft, carrying with it a Xilinx XQR4062XL, part of the XC4000XL series FPGA. This radiation- hardened FPGA is the core of the high- performance computing (HPC-I) payload incorporated in the Australian scientific mission satellite FedSat (Figure 1). The spacecraft was developed by the Cooperative Research Centre for Satellite Systems (CRCSS) in Australia. The HPC-I payload (Figure 2) was developed for CRCSS at the Queensland University of Technology. FPGAs have flown in space before, but HPC-I is the first intentional use by CRCSS of reconfigurable computing technology (RCT) in the standard opera- Source: National Space Development Agency tion of a spaceborne computing system. of Japan (NASDA) 86 Xcell Journal Summer 2003 According to Anwar Dawood, CRCSS principal research scientist and program leader, “Traditional fixed computer hardware is designed to perform a diverse range of functions. This results in an efficient processing for some tasks and a slow processing for other tasks, especially the recur- sive and intensive computing jobs.” Furthermore, fixed computer hardware is inflexible and unable to adopt changes when newly created functions are required, he added. Dawood pointed out that RCT offers the promising alternative of flexible hardware, which can be reconfigured – either by remote command or dynamically through its own internal operations – to specialize its function to an arbitrary range of demanding applications. The Xilinx-based HPC-1 is the prototype with which Dawood and his team expect to establish the viability of RCT in Figure 1 - FedSat spacecraft prior to launch (courtesy FedSat Project Team) spaceborne computing – including the tolerance of the hardware to the intense radiation of outer space. • Satellite Autonomous Navigation The reconfigurability of Xilinx FPGAs System (SANS) deploys HPC technol- enables satellites to be rewired without hav- Second-Generation HPC-II ogy in conjunction with advanced GPS ing to be retrieved. This raises the promise Dawood and the HPC team are now devel- for onboard orbit determination for of adaptable spacecraft that could be recon- oping a second-generation HPC-II, which autonomous navigation. figured remotely to work around problems is built around the increased capacity and – or even be able to repair themselves. capability of a Xilinx FPGA. This second- Retired spacecraft might also be reconfig- Fail-Safe Design generation project will emphasize critical ured for new purposes. Avoiding catastrophic satellite failure is an space applications and onboard real-time An example of a catastrophic satellite loss equally compelling motive for remote data processing. was described by Mark Long in a February 5 reconfiguration. Entire satellite constella- Dawood has initiated several applica- article for e-inSITE (www.e-insite.net). In tions have been lost through tiny failures in tion projects to exploit the efficiencies of 1998, Hughes Space and Communications computing circuitry. space-based RCT, including: announced that electrical shorts were the most likely cause of a string of failures • Disaster Detection and Monitoring involving the spacecraft control processors System (DDMS) uses HPC technolo- (SCPs) onboard its 601 flight models. gy for real-time or near-real-time The SCPs controlled the satellites’ crit- image processing for detecting and ical functions, including propulsion monitoring natural disasters, for attitude control, solar wing posi- such as forest fires and volcanic tioning, and antenna pointing. plumes. Investigators finally traced the • Satellite-Based Broadband problem to a tin-plated latching Services (SBBS) utilizes relay that served as an on/off HPC technology to pro- switch within the SCPs. vide multimedia commu- Under certain combined con- nications, Internet access, ditions, the switch was shorted and education services to out by a tiny, crystalline both urban and rural Figure 2 - HPC-1 payload (courtesy FedSat Project Team) growth less than the width of a areas. human hair.

Summer 2003 Xcell Journal 87 If the satellite operators had the ability developed by TRW. The TRW processors Conclusion to reconfigure their SCP systems on the fly, have been designed to provide high-speed, The technology being developed by Xilinx they might have found a way around the onboard processing capabilities that will for space-based applications promises to electrical shorts that led to the untimely allow signals to pass directly between small further enhance the capabilities of next- demise of their satellite constellation. aperture terminals without requiring the generation satellites to act as broadband intervention of a gateway terminal. routers in the sky. Radiation-Hardened The potent combination of onboard For more information on Xilinx In the same article, Long pointed out digital signal processing, packet switch- radiation-hardened FPGAs, visit another potential application for radiation- ing, and spot-beam technologies is www.xilinx.com/products/military/ hardened Xilinx products in the onboard expected to enable single-hop connectivi- radhardv.htm. signal processing systems of advanced, next- ty throughout each of the system’s many To learn more about CRCSS, high- generation satellite computer platforms. beam coverage areas. performance computing, and the FedSat Later this year, Hughes will launch the Similar technology is also expected to satellite, go to www.crcss.bee.qut.edu.au/ first of its Spaceway satellite platforms. These fly on two Astrolink satellites being con- comp.shtml and www.crcss.csiro.au/. platforms will feature onboard processors structed by Liberty Media.

Radiation-Tolerant FPGAs in Space

Space is a hostile environment. Streams of high-energy particles constantly bombard any exposed object. The Earth’s atmosphere provides a strong, protective barrier that absorbs most of this radiation. Satellites, however, are located well outside this protective shield, and their electronic circuitry is especially vulnerable to damage that might lead to catastrophic failure. According to Howard Bogrow, marketing manager for the Xilinx Aerospace and Defense Products Division, high- energy particles can cause a secondary reaction in untreated silicon-based chips that can cause their circuits to latch up. To address this problem, the XQR4000XL devices utilize a 0.35 micron epitaxial CMOS process that provides latch-up immunity, high total-ionizing dose (TID) tolerance, and low probability of single event upsets (SEUs) induced by natural radiation in satellite and other space environments.

Xilinx is currently shipping radiation- System-Level Function Blocks hardened versions of two device families: •• DLLsDLLs Platform FPGA • 4000XL with up to 130,000 gates, •• HighHigh • Block RAM certified radiation tolerant to 60 Krads • Block RAM •• IPIP ImmersionImmersion •• 840840 MbpsMbps LVDSLVDS Platform for • TripleDES Programmable • Virtex™ FPGAs with up to one million • TripleDES Systems •• XCITEXCITE gates, certified to 100 Krads. 3.3V - 62K gates •• MultiplierMultiplier •• PowerPCPowerPC •• DCMDCM •• RocketIORocketIO 0.35µ XQR4000XL 60Krads(Si) Later this year, a radiation tolerant line of QPro™ Virtex-II series FPGAs with up to 2.5V - 1M gates six million gates will be released (Figure 3). 0.22µ To determine the radiation tolerance of 1.5V - 6M gates 0.18µ the company’s products, Xilinx conducts 100Krads(Si) 1.5V >10M gates 0.15µ extensive testing of their TID 5V tolerant buffers 0.13µ 3.3V tolerant buffers (www.xilinx.com/prs_rls/radhard.html) and TODAY 2003 2004 2004 SEU characteristics (www.support.xilinx.com/ support/techxclusives/1000-techX35.htm).

Figure 3 - Roadmap for radiation-tolerant FPGAs

88 Xcell Journal Summer 2003

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90 Xcell Journal Summer 2003 Xilinx Events and Tradeshows Xilinx participates in numerous trade shows and events throughout the year. These gatherings are excellent opportunities only to meet our world-class silicon and software experts, ask questions, $2995 see demonstrations of new products and technologies, network with peers, and share success stories with Xilinx products. Envisage a new For more information and the most up-to-date schedule, FPGA-design dimension visit www.xilinx.com/events/. Interested in seamlessly mixing Schematics and VHDL? How about tight integration of FPGAs with board-level designs? Experience how nVisage DXP delivers – live at Worldwide Events Schedule Programmable World 2003. OR download your free 30-day trial version at www.nvisage.com or call 800-470-2686 June 2-3 PCI-SIG Developers Conference San Jose, CA

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In the Spring 2003 issue of Xcell Journal, we asked our readers to find nine “diamonds” on the pages of the magazine. The task was to note the page number where each diamond was found, add up the page numbers of each diamond, and send the sum to us with a good clean joke. The top five winners with the correct number and a joke (that we could print) would each win a HandSpring™ Visor Pro™ PDA. For the record, the nine page numbers were 14, 17, 36, 45, 52, 61, 66, 96, and 110. The correct sum was 497. And the winners are: Scott Campbell Paul Newton Three engineers and three IRS agents are traveling by train to a A guy gets shipwrecked. When he wakes up, he’s on conference. At the station, the three IRS agents each buy tickets a beach. The sand is purple. and watch as the three engineers buy only a single ticket. He can’t believe it. “How are three people going to travel on only one ticket?” asks The sky is purple. He walks around a bit and sees that an agent. “Watch and you’ll see,” answers an engineer. there is purple grass, purple birds, and purple fruit on They all board the train. the purple trees. The IRS agents take their respective seats, but all three engineers He’s shocked when he finds that his skin is starting cram into a restroom and close the door behind them. to turn purple too ... Shortly after the train departed, the conductor comes around “Oh no!” he cries, “I think I’ve been marooned!” collecting tickets. He knocks on the restroom door and says, “Ticket, please.” Mohammad Al-Tahan The door opens just a crack and a single arm emerges with a ticket in hand. The conductor takes it and moves on. After explaining to a student with various lessons and examples, that: The agents saw this and agreed it was quite a clever idea. So after the conference, they decide to copy the engineers on the return trip lim 1 = ∞ and save some money. x 8 x – 8 When they get to the station, they buy a single ticket for the return I tried to check if she really understood trip. To their astonishment, the engineers do not buy a ticket at all. that, so I gave her a different example. “How are you going to travel without a ticket?” says one perplexed This was the result: IRS agent. 1 “Watch and you will see,” answers an engineer. When they board lim = 5 x 5 x – 5 the train, the three agents cram into a restroom and the three engineers cram into another one nearby. David Kutz The train departs. Shortly afterward, one of the engineers leaves his restroom and walks over to the restroom where the IRS agents Three engineering students were gathered together discussing are hiding. the possible designers of the human body. He knocks on the door and says, “Ticket, please.” One said, “It was a mechanical engineer. Just look at all the joints.” Another said, “No, it was an electrical engineer. The nervous Keith Dellinger system has many thousands of electrical connections.” How can you tell introverted engineers from extroverted engineers? The last one said, “Actually it was a civil engineer. Who else Introverted engineers look at their own shoes. Extroverted engineers would run a toxic waste pipeline through a recreational area?” look at your shoes.

Summer 2003 Xcell Journal 93 Xilinx Alliance EDA Celoxica Product Acceleration Inc. www.celoxica.com www.prodacc.com Members and Products C-level design creation, compilation, and FPGA symbol generation verification for Virtex-II and Virtex-II Pro (LiveComponent™) and automated pin FPGAs assignment optimization and PCB layer Alatek count control (DesignF/X) www.alatek.com Endeavor Hardware acceleration (HES) www.endeav.com Simucad Co-verification for Virtex-II Pro www.simucad.com Altium (CoSimple™) Verilog Simulator for FPGAs (Silos) www.altium.com/products/nvisage.htm Complete PCB/FPGA design flow EVE Synopsys (nVisage) targeting Spartan™ Series FPGAs www.eve-team.com www.synopsys.com RTL-level Simulator Accelerator (ZEBU) Virtex-II Pro multigigabit transceiver Apache Design support for high-speed PCB design www.apache-da.com/Products/nspice.htm Forte Design (HSPICE®); FPGA Compiler II™ RTL HSPICE®-compatible simulator using www.forteds.com synthesis for Virtex series FPGAs; actual S-parameter data (NSPICE) for HLL compiler to RTL (Cynlib Tool Suite); VCS™(MX)/Scirocco™(MX) simulators; Virtex-II Pro™ MGT-based PCB design timing specification and analysis tool Formality® formal verification, LEDA® (TimingDesigner) RTL linter, and PrimeTime™ static Aplus timing analysis; high-level design using www.aplus.com Future Design Automation CoCentric™ System C Compiler and Architecture-specific synthesis and layout www.future-da.com CoCentric System Studio optimization for Virtex™-II series FPGA ANSI-C algorithms to RTL models (PALACE™) (SystemCenter) Synplicity www.synplicity.com Aptix Hierarchical Design Inc. (HDI) RTL synthesis (Synplify®), debugger www.aptix.com www.hierdesign.com technology (Identify®), and physical ASIC emulation (Prototype Studio™) Hierarchical floorplanning and analysis synthesis (Amplify®) for all Xilinx FPGAs software for Virtex-II series FPGAs Atrenta Translogic www.atrenta.com Mentor Graphics www.translogiccorp.com RTL Linter technology for Virtex-II series www.mentor.com FPGA symbol generation for fast PCB FPGAs (SpyGlass®) Virtex-II Pro MGT support for high-speed design iterations (FPGA Connector™) PCB design (HyperLynx™, ICX™, for Virtex-II series FPGAs Cadence Design Systems Tau™); complete FPGA design flow using www.cadence.com/feature/fpga_design.html the ModelSim® family of simulators and Verplex Virtex-II Pro MGT support for high-speed Leonardo-Spectrum™/Precision® synthesis; www.verplex.com PCB design (SPECCTRAQuest®); NCSim Seamless® co-verification support for Formal verification technology for Virtex-II family for FPGA design simulation; SPW Virtex-II Pro series FPGAs (Conformal™ LEC) for DSP data path development on FPGAs Novilit www.novilit.com Design partitioning using ISE EDK (AnyWare) for Virtex-II series FPGAs

94 Xcell Journal Summer 2003 XILINX PARTNER YELLOW PAGES

Xilinx AllianceCORE Third-Party Digital Core Design Loarant Corporation www.dcd.pl/ www.loarant.com IP Providers and Products Microprocessor, microcontroller, Proprietary 16-bit RISC CPU; embedded floating point, and serial communication system design controller cores United States Alcatel Technology Licensing Group Poland www.ind.alcatel.com/emac/ MEET Ltd. Ethernet media access controller cores Dolphin Integration www.meet-electronics.com United States www.dolphin.fr/ IP cores dedicated to industrial Bus interface, processor, peripheral, servomotor control Amphion Semiconductor Ltd. and DSP cores; EDA software Switzerland www.amphion.com France DSP, wireless communications, and Memec Core multimedia cores Duma Video, Inc. www.memeccore.com United States www.dumavideo.com Peripheral, bus interfaces, encryption, Digital video, AES/EBU audio, MPEG and communications cores Barco-Silex and DCT cores; real-time MPEG-2 HD United States www.barco-silex.com and SD compression DSP cores, with a specialization in image- United States ModelWare, Inc. audio applications www.modelware.com Belgium eInfochips Pvt. Ltd. Datacom/telecom cores including ATM, www.einfochips.com HDLC, POS, IMA, UTOPIA, and bridges CAST, Inc. PCI, USB, 80186, multimedia, United States www.cast-inc.com and wireless cores General purpose IP for processors, United States NewLogic GmbH perhipherals, multimedia, networking, www.newlogic.at/ encryption, serial communications, Eureka Technology Cores for wireless applications including and bus interfaces www.eurekatech.com Bluetooth and 802.11 United States Cores for SoC designs based on PCI and Austria supporting PowerPC™, ARM, MIPS, Crossbow Technologies, Inc. ARC, and SH2/SH4 processors Paxonet Communications www.crossbowip.com United States www.paxonet.com System Interconnect IP for on-chip and Solutions for interworking metro chip-to-chip multiprocessing GV & Associates, Inc. networking technologies to SONET United States www.gvassociates.com United States Boards and expertise in DSP, processor, Deltatec S.A. software, analog, and RF design Perigee, LLC www.deltatec.be/ United States www.perigeellc.com IP and services for digital imaging, DSP, DSP and image processing cores; embedded multimedia, PCI, and datacom iCoding Technology, Inc. firmware, GUI, and application software Belgium www.icoding.com development Turbo Code-related error correction United States Derivation Systems, Inc. products including system design www.derivation.com United States RealFast Operating Systems AB www.realfast.se/ IP cores for high-assurance hardware/ Intrinsyc, Inc. Real-time systems and RTOS; operating software applications and embedded www.intrinsyc.com system cores systems products; 32-bit Java processor core Single board embedded computers Sweden United States (FPGA + external processor); peripheral IP United Kingdom SOC Solutions, L.L.C. Digital Communications Technologies, Ltd. www.socsolutions.com www.dctl.com Embedded uP and software; networking, Embedded JAVA solutions wireless, audio, GPS, and handheld; United Kingdom peripheral cores United States

Summer 2003 Xcell Journal 95 XILINX PARTNER YELLOW PAGES

SysOnChip, Inc. Reference Design Partners Infineon Technologies AG www.sysonchip.co.kr/ www.infineontechnologies.com IP and products for CDMA The Xilinx Reference Design Alliance Cellular/PCS/WLL modem, FEC, and Program builds partnerships with industry- Intel Corporation Bluetooth leading semiconductor manufacturers to developer.intel.com/design/network/ Republic of South Korea develop reference designs for accelerating our customer’s product and system time to Telecom Italia Lab S.p.A. market. The goal is to build a library of Intrinsity www.idosoc.com/soc/viplibrary/ high-quality, multicomponent system-level www.intrinsity.com/home.htm reference designs in the areas of networking, main.jsp?screen=viplibrary communications, image and video Cores for ATM, optical networking, processing, DSP, and emerging technolo- Micron Technology and switched digital video broadcast gies and markets. www.micron.com equipment Italy Motorola Agere Systems Tensilica, Inc. www.motorola.com www.agere.com www.tensilica.com Configurable processors cores and AMCC Octasic Semiconductor development tools www.amcc.com www.octasic.com United States

TurboConcept Analog Devices PMC-Sierra Inc. www.turboconcept.com www.analog.com www.pmc-sierra.com/index.html Turbo Code forward error correction solutions Bay MicroSystems SiberCore Technologies France www.baymicrosystems.com www.sibercore.com Virtual IP Group www.virtualipgroup.com BitBlitz Communications Teracross Cores for microcontrollers, telecommunica- www.bitblitz.com www.teracross.com/~web/ tion, datacom, PC peripherals, and bus interface standards Broadcom Corp. Texas Instruments United States www.broadcom.com www.ti.com Wipro, Ltd. TransSwitch Coporation www.wipro.com Centillium www.transwitch.com/index_flash.jsp IP building blocks for technologies www.centillium.com like IEEE 1394, USB, Bluetooth, and IEEE 802.11 Congnigine Corporation Velio Communications, Inc. United States www.cognigine.com www.velio.com

Xylon d.o.o. Vitesse www.logicbricks.com Cypress Semiconductor www.vitesse.com Human-machine interfaces and industrial www.cypress.com communication controllers Croatia IBM Microelectronics West Bay Semiconductor Inc. www.ibm.com/us/ www.westbaysemi.com Zuken, Inc. www.zuken.co.jp/soc/ IDT ZettaCom PCI2.2, 10/100 Ethernet, and gigabit www.zettacom.com Ethernet cores www.idt.com Japan Ignis Optics Xanoptix www.ignis-optics.com www.xanoptix.com

96 Xcell Journal Summer 2003 XILINX PARTNER YELLOW PAGES

XPERTS Partners Avnet Design Services Chess iT/Embedded www.ads.avnet.com www.chess.nl/ Embedded processing FPGA design Embedded hardware and software design of 3T BV services; Virtex-II Pro; high-speed products and services at the chip, board, www.3T.nl/ SERDES; IP Core integration; timing and system level Design services; measurement instruments; closure; RLDRAM; RapidIO™ fail-safe controlling; medical equipment, Colorado Electronic Product Design, Inc. communication, and computer peripherals Baranti Group Inc. www.cepdinc.com www.baranti.com Designing embedded systems with Accent S.r.l. Award-winning design/manufacturing firm; FPGAs for DSP; interfaces for medical, www.Accent.it/ expertise in digital video, FPGAs consumer, aerospace, and military Complex FPGAs; SoCs; PowerPCs; IP-platforms; software, PCB, and IC Comit Systems, Inc. foundry services, from concept to silicon Barco Silex www.barco-silex.com www.comit.com Total solutions consisting of IP, FPGA, High-end FPGA/SoC design services, ADI Engineering and board design including the integration of customer- www.adiengineering.com developed and third-party IP Reference designs; custom designs; design services focused on Intel IXA and XScale Benchmark Electronics Inc. www.bench.com ControlNet India Pvt Ltd. EMS/JDM team; product design, support, www.controlnetindia.com Advanced Electronic Designs, Inc. introduction, and launch into volume ASIC/SoC Analog/RF FPGA design www.aedbozeman.com production services; IP development; domains: Design services and manufacturing support; Ethernet, IEEE1394, USB, security, PCI, hardware and software design for embedded WLAN, Infiniband systems Birger Engineering, Inc. www.birger.com Development of algorithms, electronics, Convergent Design LLC Advanced Principles Group, Inc. and systems for digital imaging www.convergent-design.com www.advancedprinciples.com Audio/video design for professional/ Design services and consulting; software consumer products algorithm acceleration and application- BitSim AB specific computing systems www.bitsim.com Design services; DSP, video, 3G, and DATA Respons ASA WLAN designs; high-speed prototyping www.datarespons.com Alpha Data boards Professional design and development www.alpha-data.com services for embedded hardware/software PCI/PMC/CPCI FPGA boards; embedded Bottom Line Technologies Inc. solutions; FPGA/digital hardware applica- applications using HDL or System tion specialists Generator methodologies www.bltinc.com FPGA, product, and system design services; networking; data communications; Deltatec International Inc. AMIRIX Systems Inc. telecommunications; video; PCI; signal www.deltatec.be/ www.amirix.com processing; military; aerospace Design services; digital imaging applica- Design services for electronic product tions; broadcast video, image processing realization; high-performance digital boards; and image synthesis programmable logic; embedded software CES Design Services @ Siemens Program and System Engineering www.ces-designservices.com Digicom Answers Pty Ltd. Andraka Consulting Group, Inc. Platform-oriented SoC/FPGA/PCB and www.fpga.com.au/ www.andraka.com firmware design in telecom, industrial, and Design services; experienced FPGA Exclusively FPGAs for DSP since 1994; video processing; customized solutions; resources; design-on-demand; pre-design applications include radar, sonar, digital concept; verification; prototypes advice; reviews and problem solving communications, imaging, and video

CG-CoreEl Programmable Solutions P. Ltd. Digital Design Corporation (DDC) Array Electronics www.cg-coreel.com www.digidescorp.com www.array-electronics.de/ Design services; telecom, networking, and Design services and products; image pro- SoC/FPGA/PCB designs in telecom, Processor IP and designs; turnkey FPGA; cessing; video; communications; DSP; industrial, and DSPs; concepts; verification; RTL design/validation audio; automotive; controls; interfaces prototypes; cores

Summer 2003 Xcell Journal 97 XILINX PARTNER YELLOW PAGES

Dillon Engineering, Inc. ExaLinx Image Technology Laboratory Corporation www.dilloneng.com www.exalinx.com www.gazogiken.co.jp/ Design services; FPGA-based DSP Design services; ASIC emulation for high- Design services; FPGAs for image process- algorithms; high-bandwidth, real- speed communications and wireless appli- ing; design tools: EDK, System Generator, time digital signal and image processing cations; reference designs and Forge applications Fidus Systems Inc. INITEC AG DRS Tactical Systems West Inc. www.fidus.ca/ www.initec.ch/ (formally Catalina Research) Design services; FPGAs; communications; Design services for system design; FPGA www.catalinaresearch.com video; DSP; interface conversions; ASIC applications in telecommunication systems Design services; FPGAs for DSP, including verification; hardware; PCB layout; soft- and medical electronics the manufacturer of Virtex reconfigurable ware; SI/EMC computing boards Innovative Computer Technology First Principles Technology, Inc. ictconn.com Eden Networks, Inc. www.fptek.com Digital, analog, Xilinx FPGA, and software www.edennetworks.com Design/assembly/test services; FPGA + design solutions for customers in a wide Turnkey design services; telecom and net- PCB + DSP/processor + system; imaging; variety of industries throughout the United working designs (Ethernet, SONET, ATM, video; test; satellite telecom; control States VoIP) Flexibilis Oy iWave Systems Technologies Private Ltd. Edgewood Technologies, LLC www.flexibilis.com www.iwavesystems.com www.edgewoodtechnologies.com IP development; FPGA design services; Embedded hardware and software design; Design services; FPGAs for telecom, DSP, Linux device drivers board design; FPGA and ASIC develop- embedded processors ment services Flextronics Design Enea Data AB www.flextronics.com/design/ Liewenthal Electronics Ltd. www.enea.se/ Complete product design and development www.liewenthal.ee/ Telecommunication, data communication, services for high-speed communications; Embedded systems design services; develop- DSP, RTOS, automotive, defense, high- reconfigurable computing; imaging; ment of software and hardware including reliability, and consumer electronics design audio/video; military Virtex and Spartan FPGAs

Enterpoint Ltd. GDA Technologies, Inc. Logic Product Development www.enterpoint.co.uk/ www.gdatech.com www.logicpd.com Design services; development boards; video, A leading services company focused on Full-service product development, including telecommunications, military, and high- designing systems, SoC, ASIC, FPGA, industrial design, mechanical, electrical, and speed design and IP software engineering

ESD Inc. HCL Technologies M&M Consulting www.esdnet.com www.hcltech.com [email protected] Design services; FPGAs for embedded High-speed board, ASIC, and FPGA Design services; imaging; video, audio systems, software/hardware design, PCB design and verification services in avionics, designs; high-density ASIC emulation layout medical, networking/telecom, consumer electronics Memondo Graphics Evatronix S.A. www.memondo.com www.evatronix.pl/ Helion Technology Limited Implementation of digital signal processing, Design services; FPGA design (Virtex, www.heliontech.com communications, and image processing Virtex-E, Spartan-II); embedded systems; Design services and IP for FPGA with a solutions and algorithms over Xilinx FPGAs SoCs and SoPCs designs focus on data security, wireless, and DSP Mikrokrets AS Evermore Systems Inc. IDERS Inc. www.mikrokrets.no/ www.evermoresystems.com www.iders.ca/ FPGA development comprising telecom- Design services; FPGA designs for commu- Contract electronic engineering and EMS munication, network communications, and nications, audio/video, wireless, and home resource, providing complete product cycles embedded systems; PCB development networking ranging from specifications to production

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Millogic Ltd. NovTech Engineering Rapid Prototypes, Inc. www.millogic.com www.novtech.com www.FPGA.com Design services and synthesizable Board-level and IP cores; turnkey design Design services; high-performance reconfig- cores; expertise in PCI, video, imaging, services; imaging; communication; PCI urable FPGA applications requiring maxi- DSP, compression, ASIC verification, cores; encryption mum speed or density using physical design communications principles NUVATION Milstar Inc. www.nuvation.com RDLABS www.Milstar.co.il/ Design services; imaging and communica- www.rdlabs.com Design services and manufacturers tions for defense/security, medical, con- FPGA/ASIC design; wireless communica- (industrial and military specs); DSP; sumer, and datacom/telecom markets tions; 802.11b/a IP cores; Matlab, Sysgen, communication; video; audio; ModelSim; instruments HP1661A, high-speed boards Plextek Ltd. HP8594E, HP54520A www.plextek.com Misarc srl - Agrate Design services; FPGA, DSP, radio, RightHand Technologies, Inc. www.misarc.com microwave, and microprocessor technolo- www.righthandtech.com Design services and manufacturers; gies for defense and communications Design services; Virtex-II Pro FPGAs, telecommunications, SoC development, boards, and software for video gaming, and test equipment boards using FPGA POLAR-Design storage, medical, wireless solutions www.polar-design.de/ High-end FPGA design for telecom, Rising Edge Technology Inc. Multi Video Designs networking, and DSP applications www.risingedgetech.com www.mvd-fpga.com Complete design solutions from the ground Design services; DSP for video, telecom- Polybus Systems Corporation up; FPGA interface designs muications; SoC with Virtex-II/Pro and www.polybus.com Spartan (PowerPC/MicroBlaze™); Xilinx Test patterns; customizable in-system Riverside Machines Ltd. training FPGA test patterns; design services; net- www.riverside-machines.com working and communications Design services and project management; Multiple Access Communications Ltd. DSP, wireless, network, and processor www.macltd.com Presco, Inc. development; Verilog, VHDL, SystemC, Design services; products and consultancy; www.prescoinc.com Specman DSP for wireless communications Twenty-five years of experience in custom electronics design/manufacturing for high- Roke Manor Research Nallatech performance image processing, data com- www.roke.co.uk/ www.nallatech.com munications, inkjet Design services; IP, ATM, DSP, imaging, Embedded reconfigurable computers for radar, and control solutions for FPGAs high-performance applications in DSP, Productivity Engineering GmbH imaging, and defense; Xilinx Diamond www.pe-gmbh.com Roman-Jones, Inc. XPERTS Design services; PCI design; microproces- www.roman-jones.com sor cores; obsolete component replace- Design services; FPGAs for embedded NetQuest Corporation ments; ASIC prototyping microprocessors; PCI; DSP; low-cost 8051 www.netquestcorp.com softcore Turnkey engineering design and produc- Programall Technologies Inc. tion services in advanced high-speed www.ProgramallTechnologies.com Sapphire Computers, Inc. embedded communications Design services; embedded systems target- [email protected] ing Virtex, Spartan, Virtex-II, and Virtex-II Engineering design consulting; high-speed North Pole Engineering Inc. Pro FPGAs digital and FPGA design www.northpoleengineering.com Hardware and software design services for R&D Consulting Siemens AG, Electronic Design House FPGA, ASIC, and embedded systems 972-9-7673074 www.eda-services.com FPGA development; video; imaging; Design services; system-on-chip; ASICs; Northwest Logic graphics; DSP; communications FPGAs; IPs; DSPs; boards; EMC; www.nwlogic.com embedded software; prototypes PCI, PCI-X, and SDRAM controller IP; high-end FPGA design services

Summer 2003 Xcell Journal 99 XILINX PARTNER YELLOW PAGES

Silicon & Software Systems Ltd. (S3) Syntera AB V-Integration www.s3group.com www.syntera.se/ www.V-Integration.com World-class electronics design company Design services; FPGAs for radar, digital Providing first-pass success in complex uniquely combining IC, FPGA, software, communications, telecom automotive, FPGA designs; applications include imag- and hardware design expertise aerospace, and DSP ing, communications, and interface design

Silicon Interfaces America Inc. Tachyon Semiconductor Williams Consulting, Inc. www.siliconinterfaces.com www.tachyonsemi.com [email protected] Design services; develops IP in areas of Design services for portable computing, Embedded systems hardware and software; networking, wireless, optical, datacom, networking, and embedded systems video; MPEG; control interconnect, and microcontrollers Tao of Digital, Inc. Zaiq Technologies, Inc. Silicon System Solutions P/L www.taoofdigital.com www.zaiqtech.com www.silicon-systems.com High-speed, large-gate-count SoC designs Design; partitioning and timing conver- Design services; FPGAs for very high-speed using IP cores for maximum modularity gence; VIP; platform experts for embedded applications including communications and and efficiency computer, networking, wireless, and DSP applications instrumentation Technolution B.V. Siscad S.p.A. www.technolution.nl/ www.siscad.it/ Innovative hardware and software solutions Xilinx FPGA design services; IP development and integration Millogic IP is Thales Airborne Systems Xilinx Proven! www.thalesgroup.com/airbornesystems Smart Logic, Inc. • PCI-X, VME, 12C, www.smart-logic.com Provider and integrator with high expertise Video, LZS, PS2 Design services; FPGAs for rapid in FPGA design for radars, DSP, and com- • Design Services prototyping including imaging, compres- munications • Prototyping sion, and real-time control • Xilinx Xperts TietoEnator R&D Services AB SoleNet, Inc. www.TietoEnator.com Millogic, Ltd. www.solenet.net European design services for telecom, 6 Clocktower Place Maynard, MA 01754 FPGA, board, and system designs for wire- industrial IT, and automotive; Xilinx exclu- 978.461.1560 less, telecommunications, consumer, and sive training provider in Scandinavia [email protected] reference design applications www.millogic.com so-logic electronic consulting www.so-logic.net Embedded systems (PowerPC, MicroBlaze); system-level design (Forge, SystemGenerator, Handel-C); Xilinx training centers (Austria, Eastern Europe)

Styrex AB www.styrex.se/ Synplicity offers a wide range of software products for FPGA and ASIC designers. Design services for embedded systems; Synplicity products are fast, easy-to-use, and most importantly, provide the best Quality of programmable logic, hardware develop- Results. Synplicity's products support ment, and microprocessor programming industry-standard languages (VHDL and Verilog) and run on most popular platforms.

Synopsys Professional Services Visit us at: www.synopsys.com www.synplicity.com Design services to solve your design or send an e-mail to: challenges in system-level design, RTL [email protected] to learn more design, and physical design

100 Xcell Journal Summer 2003 Will the RealDigital™ CPLD please stand up.

If you are not using the latest breakthrough in dividing the clock off-chip. Best of all, RealDigital CPLDs CPLD technology, you are not getting the most out of your CPLD. Only the deliver all this performance in the smallest, most secure new 1.8V CoolRunner-II RealDigital CPLD from Xilinx, offering a 100% digital design package available. core, gives you the performance, low power, and features you are looking for Get the new CoolRunner-II Design Kit with no price premium. Get started now with the new CoolRunner-II Design Kit, The best system performance in the industry including a populated board, programming cable, design guide, plus software and CoolRunner–II RealDigital CPLDs feature 1.8V CORE VOLTAGE CPLD COMPETITIVE CHART resource CDs… all for under fifty dollars! the most I/O per macrocell, as well as advanced Manufacturer Xilinx Lattice Altera Just contact your local Xilinx distributor or I/O interfacing that includes HSTL and SSTL. Device Family CoolRunner-II ispMACH4000C ispMACH4000Z None visit www.xilinx.com/coolrunner2 Plus, they deliver system performance in Standby Current 12 µA 1,800 µA 20 µA N/A to order your kit today. And don’t forget Internal Performance 500 MHz 400 MHz 265 MHz N/A excess of 500 MHz with the industry’s lowest the new CoolRunner-II RealDigital CPLDs Clock Divider/Doubler YES/YES NO/NO NO/NO N/A dynamic and standby current as low as 12 µA Max Density (Macrocells) 512 512 128 N/A are fully supported by the easy-to-use — lower than any other 1.8V device! The I/O Standards Support LVTTL, LVCMOS, LVTTL, LVCMOS LVTTL, LVCMOS N/A ISE WebPACK™ tool, which you can HSTL, SSTL unique Clock Divider also means no more download FREE right now. I/O Banks (max) 4 2 2 N/A

www.xilinx.com/realcpld

© 2003, Xilinx Inc. All rights reserved. The Xilinx name and the Xilinx logo are registered trademarks, CoolRunner, WebPACK are trademarks, and The Programmable Logic Company is a service mark of Xilinx Inc. All other trademarks and registered trademarks are the property of their respective owners. Spartan-3 1.2V FPGA Family: R Introduction and Ordering Information DS099-1 (v1.0) April 14, 2003 Advance Product Specification

Introduction - Densities as high as 74K logic cells The 1.2V Spartanª-3 family of Field Programmable Gate - 325 MHz system clock rate Arrays is specifically designed to meet the needs of high - Three separate power supplies for the core (1.2V), volume, cost-sensitive consumer electronic applications. I/Os (1.2V to 3.3V), and special functions (2.5V) The eight-member family offers densities ranging from ¥ SelectIOª signaling 50,000 to five million system gates, as shown in Table 1. - Up to 784 I/O pins The Spartan-3 family builds on the success of the earlier - 622 Mbps data transfer rate per I/O Spartan-IIE family by increasing the amount of logic - Seventeen single-ended signal standards resources, the capacity of internal RAM, the total number of - Six differential signal standards including LVDS I/Os, and the overall level of performance as well as by - Termination by Digitally Controlled Impedance improving clock management functions. Numerous - Signal swing ranging from 1.14V to 3.45V enhancements derive from state-of-the-art Virtexª-II tech- - Double Data Rate (DDR) support nology. These Spartan-3 enhancements, combined with ¥ Logic resources advanced process technology, deliver more functionality - Abundant, flexible logic cells with registers and bandwidth per dollar than was previously possible, set- - Wide multiplexers ting new standards in the programmable logic industry. - Fast look-ahead carry logic Because of their exceptionally low cost, Spartan-3 FPGAs - Dedicated 18 x 18 multipliers are ideally suited to a wide range of consumer electronics - JTAG logic compatible with IEEE 1149.1/1532 applications, including broadband access, home network- standards ing, display/projection, and digital television equipment. ¥ SelectRAMª hierarchical memory The Spartan-3 family is a superior alternative to mask pro- - Up to 1,872 Kb of total block RAM grammed ASICs. FPGAs avoid the high initial cost, the - Up to 520 Kb of total distributed RAM lengthy development cycles, and the inherent inflexibility of ¥ Digital Clock Manager (up to four DCMs) conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement - Clock skew elimination necessary, an impossibility with ASICs. - Frequency synthesis - High-resolution phase shifting Features ¥ Eight global clock lines and abundant routing ¥ Very low cost, high-performance logic solution for ¥ Fully supported by Xilinx ISE development system high-volume, consumer-oriented applications - Synthesis, mapping, placement and routing

Table 1 Ð Summary of Spartan-3 FPGA Attributes CLB Array Maximum (One CLB = Four Slices) System Logic Distributed Block RAM Dedicated Maximum Differential Device Gates Cells Rows Columns Total CLBs RAM (bits1) (bits1) Multipliers DCMs User I/O I/O Pairs XC3S50 50K 1,728 16 12 192 12K 0 0 0 124 56 XC3S200 200K 4,320 24 20 480 30K 216K 12 4 173 76 XC3S400 400K 8,064 32 28 896 56K 288K 16 4 264 116 XC3S1000 1M 17,280 48 40 1,920 120K 432K 24 4 391 175 XC3S1500 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221 XC3S2000 2M 46,080 80 64 5,120 320K 720K 40 4 565 270 XC3S4000 4M 62,208 96 72 6,912 432K 1,728K 96 4 712 312 XC3S5000 5M 74,880 104 80 8,320 520K 1,872K 104 4 784 344 Notes: 1By convention, one Kb is equivalent to 1,024 bits.

©2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

102 Xcell Journal Summer 2003 R Spartan-3 1.2V FPGA Family: Introduction and Ordering Information

Architectural Overview ¥ Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, The Spartan-3 family architecture consists of five funda- delaying, multiplying, dividing, and phase shifting clock mental programmable functional elements: signals. ¥ Configurable Logic Blocks (CLBs) contain RAM-based These elements are organized as shown in Figure 1. A ring Look-Up Tables (LUTs) to implement logic and storage of IOBs surrounds a regular array of CLBs. Those devices elements that can be used as flip-flops or latches. ranging from the XC3S200 to the XC3S2000 have two col- CLBs can be programmed to perform a wide variety of umns of block RAM embedded in the array. The XC3S4000 logical functions as well as to store data. and XC3S5000 devices have four RAM columns. Each col- ¥ Input/Output Blocks (IOBs) control the flow of data umn is made up of several 18 Kb RAM blocks; each block between the I/O pins and the internal logic of the is associated with a dedicated multiplier. The DCMs are device. Each IOB supports bidirectional data flow plus positioned at the ends of the outer block RAM columns, three-state operation. Twenty-three different signal making up a total of four. The XC3S50, the lowest cost standards, including six high-performance differential member of the family, has neither block RAM, nor dedicated standards, are available as shown in Table 2. Double multipliers, nor DCMs. Data Rate (DDR) registers are included. The Digitally The Spartan-3 family features a rich network of traces and Controlled Impedance (DCI) feature provides automatic switches that interconnect all five functional elements, on-chip terminations, simplifying board designs. transmitting signals among them. Each functional element ¥ Block RAM provides data storage in the form of 18 Kb has an associated switch matrix that permits multiple con- dual-port blocks. nections to the routing. ¥ Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product.

DS099-1_01_032703 Notes: 1. The two additional block RAM columns of the XC3S4000 and XC3S5000 devices are shown with dashed lines. The XC3S50 device does not have any block RAM, multipliers, or DCMs.

Figure 1 Ð Spartan-3 Family Architecture

Summer 2003 Xcell Journal 103 R Spartan-3 1.2V FPGA Family: Introduction and Ordering Information

Configuration The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, Spartan-3 FPGAs are programmed by loading configuration which includes XCF00S PROMs for serial configuration data into robust static memory cells that collectively control all and XCF00P PROMs for parallel configuration. functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a I/O Capabilities PROM or some other nonvolatile medium either on or off the board. After applying power, the configuration data is written The SelectIO feature of Spartan-3 devices supports 17 to the FPGA using any of five different modes: Master single-ended standards and six differential standards as Parallel, Slave Parallel, Master Serial, Slave Serial and listed in Table 2. Table 3 shows the number of user I/Os Boundary Scan (JTAG). The Master and Slave Parallel as well as the number of differential I/O pairs available for modes use an 8-bit wide SelectMAPª Port. each device/package combination.

Table 2 Ð Signal Standards Supported by the Spartan-3 Family Standard Category Description VCCO (V) Class Symbol Single-Ended GTL Gunning Transceiver Logic N/A Terminated GTL Plus GTLP HSTL High-Speed Transceiver Logic 1.5 I HSTL_I III HSTL_III 1.8 I HSTL_I_18 II HSTL_II_18 III HSTL_III_18 LVCMOS Low-Voltage CMOS 1.2 N/A LVCMOS12 1.5 N/A LVCMOS15 1.8 N/A LVCMOS18 2.5 N/A LVCMOS25 3.3 N/A LVCMOS33 LVTTL Low-Voltage Transistor/Transistor Logic 3.3 N/A LVTTL PCI Peripheral Component Interconnect 3.0 33 MHz PCI33_3 SSTL Stub Series Terminated Logic 1.8 N/A SSTL18_I 2.5 I SSTL2_I II SSTL2_II Differential LDT Lightning Data Transport 2.5 N/A LDT_25 (HyperTransportª) LVDS Low-Voltage Differential Signaling Standard LVDS_25 Bus BLVDS_25 Extended Mode LVDSEXT_25 Ultra ULVDS_25 RSDS Reduced-Swing Differential Signaling 2.5 N/A RSDS_25

104 Xcell Journal Summer 2003 R Spartan-3 1.2V FPGA Family: Introduction and Ordering Information

Table 3 Ð Spartan-3 User I/O Chart Available User I/Os and Differential (Diff) I/O Pairs VQ100 TQ144 PQ208 FT256 FG456 FG676 FG900 FG1156 Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff XC3S50 63 TBD 97 46 124 56 ------XC3S200 63 TBD 97 46 141 62 173 76 ------XC3S400----1416217376264116------XC3S1000 ------17376333149391175---- XC3S1500 ------333149487221---- XC3S2000 ------489221565270-- XC3S4000 ------633300712312 XC3S5000 ------633300784344 Notes: 1. All device options listed in a given package column are pin-compatible. Product Ordering and Availability Table 4 shows all valid device ordering combinations of range parameters for the Spartan-3 family as well as the device density, speed grade, package, and temperature availability status of those combinations.

Table 4 Ð Spartan-3 Device Availability Package Type: VQFP TQFP PQFP FTBGA FBGA No. of Pins: 100 144 208 256 456 676 900 1156 Code: VQ100 TQ144 PQ208 FT256 FG456 FG676 FG900 FG1156 Device Speed Grade XC3S50 Commercial devices (C, I) (C, I) (C, I) - - - - - offered in the -4 and -5 XC3S200 (C, I) (C, I) (C, I) (C, I) - - - - speed grades; industrial XC3S400devices offered in the -4 - - (C, I) (C, I) (C, I) - - - speed grade. XC3S1000 - - - (C, I) (C, I) (C, I) - - XC3S1500 - - - - (C, I) (C, I) - - XC3S2000 - - - - - (C, I) (C, I) - XC3S4000 ------(C, I) (C, I) XC3S5000 ------(C, I) (C, I) Notes: ° ° ° ° 1. C = Commercial: TJ = 0 to +85 C; I = Industrial: TJ = Ð40 C to +100 C. 2. Parentheses indicate that a given product is not yet released. Contact sales for availability information.

Summer 2003 Xcell Journal 105 REFERENCE

Xilinx Virtex FPGA Products

Virtex-II Pro Package Configurations with Virtex-II Pro (1.5V) Virtex-II (1.5V) Available RocketIO Transceiver Blocks XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125 XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000

Package XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125 Pins Body Size I/O’s 204 348 396 564 692 804 852 996 1164 1200 88 120 200 264 432 528 624 720 912 1104 1296 FG256 44 Chip Scale Packages — wire-bond chip-scale BGA (0.8 mm ball spacing) FG456 448 144 12 x 12 mm 88 92 92 FG676 888 BGA Packages (BG) — wire-bond standard BGA (1.27 mm ball spacing) FF672 448 575 31 x 31 mm 328 392 408 FF896 888 728 35 x 35 mm 516 FF1152 8 8 12 16 FGA Packages (FG) — wire-bond fine-pitch BGA (1.0 mm ball spacing) FF1148 0* 0* 256 17 x 17 mm 140 140 88 120 172 172 172 FF1517 16 16 456 23 x 23 mm 156 248 248 200 264 324 FF1704 20 20 24 676 27 x 27 mm 404 416 416 392 456 484 FF1696 0* 0* FFA Packages (FF) — flip-chip fine-pitch BGA (1.0 mm ball spacing) 672 27 x 27 mm 204 348 396 Note: * FF1148 and FF1696 packages support higher number of user I/O and 896 31 x 31 mm 396 556 556 432 528 624 zero RocketIO multi-gigabit transceivers 1152 35 x 35 mm 564 644 692 692 720 824 824 824 1148* 35 x 35 mm 804 812 1517 40 x 40 mm 852 964 912 1104 1108 1704 42.5 x 42.5 mm 996 1040 1040 1696* 42.5 x 42.5 mm 1164 1200 BFA Packages (BF) — flip-chip fine-pitch BGA (1.27 mm ball spacing) 957 40 x 40 mm 624 684 684 684

Note: Within the same family, all devices in a particular package are pin-out (footprint) compatible. Virtex-II packages FG456 and FG676 are also footprint compatible. Virtex-II packages FF896 and FF1152 are also footprint compatible. * The FF1148 and FF1696 packages support higher number of user I/O and zero RocketIO™ multi-gigabit transceivers. Important: Verify all Data with Device Data Sheet (http://www.xilinx.com/partinfo/databook.htm)

Numbers indicated in the matrix are the maximum number of user I/Os for that package and device combination; I/Os for RocketIO MGTs are not included in this table.

CLB Resources Memory Resources DSP Clock Resources I/O Features Speed Transceiver Blocks Transceiver ™ System Gates (see note 1) (Row X Col) Array CLB Number of Slices Logic Cells (see note 2) CLB Flip-Flops Max. Distributed RAM Bits(kbits) # 18 kbits Block RAM Block RAM (kbits) Total Dedicated Multipliers # 18x18 (min/max) DCM Frequency # DCM Blocks (see note 3) Digitally Controlled Impedance Maximum Differential I/O Pairs Max. I/O I/O Standards Commercial Speed Grades (slowest to fastest) Industrial Speed Grades (slowest to fastest) Serial PROM Family System ACE Config. Memory (Bits) RocketIO PowerPC Processor Blocks PowerPC Series EasyPath Virtex-II Solution (see note 4) Virtex-II Pro Family — 1.5 Volt .13um Nine Layer Copper Process XC2VP2 * 16 x 22 1,408 3,168 2,816 44 12 216 12 24/420 4 YES 100 204 LDT-25, LVDS-25, LVDSEXT-25, -5 -6 -7 -5 -6 1.31M 4 0 XC2VP4 * 40 x 22 3,008 6,768 6,016 94 28 504 28 24/420 4 YES 172 348 BLVDS-25, ULVDS-25, LVPECL-25, -5 -6 -7 -5 -6 3.01M 4 1 XC2VP7 * 40 x 34 4,928 11,088 9,856 154 44 792 44 24/420 4 YES 196 396 LVCMOS25, LVCMOS18, -5 -6 -7 -5 -6 4.49M 8 1 XC2VP20 * 56 x 46 9,280 20,880 18,560 290 88 1,584 88 24/420 8 YES 276 564 LVCMOS15, PCI33, LVTTL, -5 -6 -7 -5 -6 8.21M 8 2 XC2VP30 * 80 x 46 13,696 30,816 27,392 428 136 2,448 136 24/420 8 YES 372 644 LVCMOS33, PCI-X, PCI66, GTL, -5 -6 -7 -5 -6 11.36M 8 2 ✔ ISP

XC2VP40 * 88 x 58 19,392 43,632 38,784 606 192 3,456 192 24/420 8 YES 396 804 GTL+, HSTL I (1.5V,1.8V), -5 -6 -7 -5 -6 ISP/OTP 15.56M 0**or 12 2 ✔ XC2VP50 * 88 x 70 23,616 53,136 47,232 738 232 4,176 232 24/420 8 YES 420 852 HSTL II (1.5V,1.8V), -5 -6 -7 -5 -6 19.02M 0**or 16 2 ✔ XC2VP70 * 104 x 82 33,088 74,448 66,176 1,034 328 5,904 328 24/420 8 YES 492 996 HSTL III (1.5V,1.8V), -5 -6 -7 -5 -6 25.60M 16 or 20 2 ✔ XC2VP100 * 120 x 94 44,096 99,216 88,192 1,378 444 7,992 444 24/420 12 YES 572 1,164 HSTL IV (1.5V,1.8V), SSTL2I, -5 -6 -7 -5 -6 33.65M 0**or 20 2 ✔ XC2VP125 * 136 x 106 55,616 125,136 111,232 1,738 556 10,008 556 24/420 12 YES 644 1,200 SSTL2II, SSTL18 I, SSTL18 II -5 -6 -7 -5 -6 42.78M 0**,20, or 24 4 ✔ Virtex-II Family — 1.5 Volt .15um Eight Layer Metal Process XC2V40 40K 8 x 8 256 576 512 8 4 72 4 24/420 4 YES 44 88 LDT-25, LVPECL-33, -4 -5 -6 -4 -5 0.4M XC2V80 80K 16 x8 512 1,152 1,024 16 8 144 8 24/420 4 YES 60 120 LVDS-33, LVDS-25, -4 -5 -6 -4 -5 0.6M Platform FPGAs XC2V250 250K 24 x16 1,536 3,456 3,072 48 24 432 24 24/420 8 YES 100 200 LVDSEXT-33, LVDSEXT-25, -4 -5 -6 -4 -5 1.7M XC2V500 500K 32 x 24 3,072 6,912 6,144 96 32 576 32 24/420 8 YES 132 264 BLVDS-25, ULVDS-25, -4 -5 -6 -4 -5 2.8M XC2V1000 1M 40 x 32 5,120 11,520 10,240 160 40 720 40 24/420 8 YES 216 432 LVTTL, LVCMOS33, -4 -5 -6 -4 -5 4.1M

XC2V1500 1.5M 48 x 40 7,680 17,280 15,360 240 48 864 48 24/420 8 YES 264 528 LVCMOS25, LVCMOS18, -4 -5 -6 -4 -5 ISP 5.7M ISP/OTP XC2V2000 2M 56 x 48 10,752 24,192 21,504 336 56 1,008 56 24/420 8 YES 312 624 LVCMOS15, PCI33, PCI66, -4 -5 -6 -4 -5 7.5M XC2V3000 3M 64 x 56 14,336 32,256 28,672 448 96 1,728 96 24/420 12 YES 360 720 PCI-X, GTL, GTL+, HSTL I, -4 -5 -6 -4 -5 10.5M ✔ XC2V4000 4M 80 x 72 23,040 51,840 46,080 720 120 2,160 120 24/420 12 YES 456 912 HSTL II, HSTL III, HSTL IV, -4 -5 -6 -4 -5 15.7M ✔ XC2V6000 6M 96 x 88 33,792 76,032 67,584 1,056 144 2,592 144 24/420 12 YES 552 1,104 SSTL2I, SSTL2II, SSTL3 I, -4 -5 -6 -4 -5 21.9M ✔ XC2V8000 8M 112 x 104 46,592 104,832 93,184 1,456 168 3,024 168 24/420 12 YES 554 1,108 SSTL3 II, AGP,AGP-2X -4 -5 29.1M ✔

Note: 1. System Gates include 20-30% of CLBs used as RAM 2. Logic cell = (1) 4 Input (LUT) Look Up Table + Flip Flop + Carry Logic. 3. DCM – Digital Clock Management 4. Virtex-II Series EasyPath solution available to provide a no risk, no effort cost reduction path for volume production. * System gate count not meaningful for Virtex-II Pro devices with immersed special blocks such as PowerPC processors and multi-gigabit transceivers. ** The FF1148 and FF1696 packages support higher numbers of user I/O and zero RocketIO multi-gigabit transceivers. Important: Verify all Data with Device Data Sheet (http://www.xilinx.com/partinfo/databook.htm)

106 Xcell Journal Summer 2003 REFERENCE

Xilinx Spartan FPGA Products PRODUCT SELECTION MATRIX

CLB Resources BLK RAM CLK Resources I/O Features Speed System Gates (see note 1) (Row X Col) Array CLB Number of Slices Logic Cells (see note 2) CLB Flip-Flops Max. Distributed RAM Bits # Block RAM Block RAM (kbits) # Dedicated Multipliers (min/max) DLL Frequency # DLL's Synthesis Frequency Phase Shift Digitally Controlled Impedance Number of Differential I/O Pairs Max. I/O I/O Standards Commercial Speed Grades (slowest to fastest) Industrial Speed Grades (slowest to fastest) Serial PROM Family Config. Memory (Bits) Spartan-IIE Family — 1.8 Volt .18/.15um Six Layer Metal Process XC2S50E 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/320 4 YES YES NA 83 182 LVTTL,LVCMOS2, -6 -7 -6 0.6M XC2S100E 100K 20 x 30 1,200 2,700 2,400 37K 10 40K NA 25/320 4 YES YES NA 86 202 LVCMOS18, PCI33, PCI66, -6 -7 -6 0.9M XC2S150E 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/320 4 YES YES NA 114 265 GTL, GTL+, HSTL I, HSTL III, -6 -7 -6 1.1M XC2S200E 200K 28 x 42 2,352 5,292 4,704 73K 14 56K NA 25/320 4 YES YES NA 120 289 HSTL IV,SSTL3 I, SSTL3 II, -6 -7 -6 1.4M XC2S300E 300K 32 x 48 3,072 6,912 6,144 96K 16 64K NA 25/320 4 YES YES NA 120 329 SSTL2 I, SSTL2 II,AGP-2X, -6 -7 -6 1.9M XC2S400E 400K 40 x 60 4,800 10,800 9,600 150K 40 160K NA 25/320 4 YES YES NA 172 410 CTT, LVDS, BLVDS, LVPECL -6 -7 -6 2.7M XC2S600E 600K 48 x 72 6,912 15,552 13,824 216K 72 288K NA 25/320 4 YES YES NA 205 514 -6 -7 -6 4.0M Spartan-II Family — 2.5 Volt .22/.18um Six Layer Metal Process XC2S15 15K 8 x 12 192 432 384 6K 4 16K NA 25/200 4 YES YES NA NA 86 LVTTL, LVCMOS2, -5 -6 -5 0.2M XC2S30 30K 12 x 18 432 972 864 13.5K 6 24K NA 25/200 4 YES YES NA NA 132 PCI33 (3.3V & 5V), -5 -6 -5 0.4M XC2S50 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/200 4 YES YES NA NA 176 PCI66 (3.3V), GTL, GTL+, -5 -6 -5 0.6M XC2S100 100K 20 x 30 1,200 2,700 2,400 37.5K 10 40K NA 25/200 4 YES YES NA NA 196 HSTL I, HSTL III, HSTL IV, -5 -6 -5 0.8M XC2S150 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/200 4 YES YES NA NA 260 SSTL3 I, SSTL3 II, SSTL2 I, -5 -6 -5 1.1M XC2S200 200K 28 x 42 2,352 5,292 4,704 73.5K 14 56K NA 25/200 4 YES YES NA NA 284 SSTL2 II, AGP-2X, CTT -5 -6 -5 1.4M Spartan-XL Family — 3.3 Volt XCS05XL 5K 10 x 10 100 238 200 3.1K NA NA NA NA NA NA NA NA NA 77 TTL, LVTTL, CMOS, -4 -5 -4 0.05M XCS10XL 10K 14 x 14 196 466 392 6.1K NA NA NA NA NA NA NA NA NA 112 LVMOS, PCI -4 -5 -4 0.09M XCS20XL 20K 20 x 20 400 950 800 12.5K NA NA NA NA NA NA NA NA NA 160 -4 -5 -4 0.18M ISP ISP ISP OTP OTP OTP XCS30XL 30K 24 x 24 576 1,368 1,152 18.0K NA NA NA NA NA NA NA NA NA 192 -4 -5 -4 0.25M XCS40XL 40K 28 x 28 784 1,862 1,568 24.5K NA NA NA NA NA NA NA NA NA 224 -4 -5 -4 0.33M Spartan-3 — 1.2 Volt 90nm Eight Layer Metal Process XC3S50 50K 16 x 12 768 1,728 1,536 12K ------YES 56 124 Single-ended -4 -5 -4 XCF01S 0.3M LVTTL, LVCMOS3.3/2.5/1.8/1.5/1.2, XC3S200 200K 24 x 20 1,920 4,320 3,840 30K 12 216K 12 25/325 4 YES YES YES 76 173 PCI 3.3V – 32/64-bit 33MHz, -4 -5 -4 XCF01S 1.0M XC3S400 400K 32 x 28 3,584 8,064 7,168 56K 16 288K 16 25/325 4 YES YES YES 116 264 SSTL2 Class I & II, SSTL18 Class I, -4 -5 -4 XCF02S 1.7M HSTL Class I, III, XC3S1000 1000K 48 x 40 7,680 17,280 15,360 120K 24 432K 24 25/325 4 YES YES YES 175 391 HSTL1.8 Class I, II & III, -4 -5 -4 XCF04S 3.2M XC3S1500 1500K 64 x 52 13,312 29,952 26,624 208K 32 576K 32 25/325 4 YES YES YES 221 487 GTL, GTL+ -4 -5 -4 XCF08P 5.2M XC3S2000 2000K 80 x 64 20,480 46,080 40,960 320K 40 720K 40 25/325 4 YES YES YES 270 565 Differential -4 -5 -4 XCF08P 7.7M XC3S4000 4000K 96 x 72 27,648 62,208 55,296 432K 96 1,728K 96 25/325 4 YES YES YES 312 712 LVDS2.5, Bus LVDS2.5, -4 -5 -4 XCF16P 11.3M Ultra LVDS2.5, LVDS_ext2.5, XC3S5000 5000K 104 x 80 33,280 74,480 66,560 520K 104 1,872K 104 25/325 4 YES YES YES 344 784 RSDS, LDT2.5 -4 -5 -4 XCF16P 13.3M

PACKAGE OPTIONS AND USER I/O

Spartan-IIE (1.8V) Spartan-II (2.5V) Spartan-XL (3.3V) Spartan-3 XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

Pins Body Size I/O’s 182 202 265 289 329 410 514 86 132 176 196 260 284 77 112 160 192 224 Pins Body Size I/O’s 124 173 264 391 487 565 712 784 PLCC Packages VQFP Packages (VQ) – very thin TQFP (0.5 mm lead spacing) 84 30 x 30 mm 61 61 100 16 x 16 mm 63 63 PQFP Packages (PQ) TQFP Packages (TQ) – thin QFP (0.5 mm lead spacing) 208 28 x 28 mm 146 146 146 146 146 132 140 140 140 140 160 169 169 144 22 x 22 mm 97 97 97 240 32 x 32 mm 192 192 PQFP Packages (PQ) – wire-bond plastic QFP (0.5 mm lead spacing) VQFP Packages (VQ) 208 30.6 x 30.6 mm 124 141 141 100 14 x 14 mm 60 60 77 77 77 77 FGA Packages (FT) – wire-bond thin BGA (1.0 mm ball spacing) TQFP Packages (TQ) 256 17 x 17 mm 173 173 173 144 20 x 20 mm 102 102 86 92 92 92 112 113 113 FGA Packages (FG) – wire-bond fine-pitch BGA (1.0 mm ball spacing) Chip Scale Packages — wire-bond chip-scale BGA (0.8 mm ball spacing) 456 23 x 23 mm 264 333 333 144 12 x 12 mm 86 92 112 113 676 27 x 27 mm 391 487 489 280 16 x 16 mm 192 224 900 31 x 31 mm 565 633 633 FGA Packages (FT) — wire-bond fine-pitch thin BGA (1.0 mm ball spacing) 1156 35 x 35 mm 712 784 256 17 x 17 mm 182 182 182 182 182 182 FGA Packages (FG) — wire-bond fine-pitch BGA (1.0 mm ball spacing) 256 17 x 17 mm 176 176 176 176 456 23 x 23 mm 202 265 289 329 329 329 196 260 284 Automotive products are highlighted: -40C to +125C junction temperature for FPGAs 676 27 x 27 mm 410 514 BGA Packages 256 27 x 27 mm 192 205

Note: 1. System Gates include 20-30% of CLBs used as RAM Important: Verify all Data with Device Data Sheet Numbers indicated in the matrix are the maximum number of user I/Os for 2. Logic Cell is defined as a 4 input LUT and a register (http://www.xilinx.com/spartan) that package and device combination.

Summer 2003 Xcell Journal 107 REFERENCE

Xilinx CPLD Products

PRODUCT SELECTION MATRIX I/O Features Speed Clocking System Gates Macrocells Product terms per Function Block Input Voltage Compatible Output Voltage Compatible Max. I/O I/O Banking Min. Pin-to-Pin Logic Delay (ns) Commercial Speed Grades (fastest to slowest) Industriall Speed Grades (fastest to slowest) Global Clocks Clocks per Term Product Function Block CoolRunner-II Family — 1.8 Volt

XC2C32 750 32 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 33 1 3.5 -3 -4 -6 -6 3 17

XC2C64 1500 64 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 64 1 4 -4 -5 -7 -7 3 17

XC2C128 3000 128 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 100 2 4.5 -4 -6 -7 -7 3 17 XC2C256 6000 256 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 184 2 5 -5 -6 -7 -7 3 17

XC2C384 9000 384 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 240 4 6 -6 -7 -10 -10 3 17

XC2C512 12000 512 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 270 4 6 -6 -7 -10 -10 3 17 CoolRunner XPLA3 Family — 3.3 Volt

XCR3032XL 750 32 48 3.3/5 3.3 36 5 -5 -7 -10 -7 -10 4 16

XCR3064XL 1500 64 48 3.3/5 3.3 68 6 -6 -7 -10 -7 -10 4 16

XCR3128XL 3000 128 48 3.3/5 3.3 108 6 -6 -7 -10 -7 -10 4 16 XCR3256XL 6000 256 48 3.3/5 3.3 164 7.5 -7 -10 -12 -10 -12 4 16

XCR3384XL 9000 384 48 3.3/5 3.3 220 7.5 -7 -10 -12 -10 -12 4 16 XCR3512XL 12000 512 48 3.3/5 3.3 260 7.5 -7 -10 -12 -10 -12 4 16 XC9500XV Family — 2.5 Volt

XC9536XV 800 36 90 2.5/3.3 1.8/2.5/3.3 36 1 5 -5 -7 -7 3 18

XC9572XV 1600 72 90 2.5/3.3 1.8/2.5/3.3 72 1 5 -5 -7 -7 3 18 XC95144XV 3200 144 90 2.5/3.3 1.8/2.5/3.3 117 2 5 -5 -7 -7 3 18 XC95288XV 6400 288 90 2.5/3.3 1.8/2.5/3.3 192 4 6 -6 -7 -10 -7 -10 3 18 XC9500XL Family — 3.3 Volt XC9536XL 800 36 90 2.5/3.3/5 2.5/3.3 36 5 -5 -7 -10 -7 -10 3 18 PACKAGE OPTIONS AND USER I/O XC9572XL 1600 72 90 2.5/3.3/5 2.5/3.3 72 5 -5 -7 -10 -7 -10 3 18

XC95144XL 3200 144 90 2.5/3.3/5 2.5/3.3 117 5 -5 -7 -10 -7 -10 3 18 CoolRunner-II CoolRunner XPLA3 XC9500XV XC9500XL XC95288XL 6400 288 90 2.5/3.3/5 2.5/3.3 192 6 -6 -7 -10 -7 -10 3 18 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL XC9536XV XC9572XV XC95144XV XC95288XV XC9536XL XC9572XL XC95144XL XC95288XL Body Size XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512 PLCC Packages (PC) 44 16.5 x 16.5 mm 33 33 36 36 34 34 34 34 PQFP Packages (PQ) 208 28 x 28 mm 173 173 173 164 172 180 168 168 VQFP Packages (VQ) 44 12 x 12 mm 33 33 36 36 34 34 34 34 64 12 x 12 mm 36 52 100 16 x 16 mm 64 80 80 68 84 TQFP Packages (TQ) *JTAG pins and port enable are not pin compatible in this package for this member of the family. 100 14 x 14 mm 72 81 72 81 144 20 x 20 mm 100 118 118 108 120 118* 117 117 117 117 Important: Verify all Data with Device Data Sheet and Product Availability with your local Chip Scale Packages (CP) — wire-bond chip-scale BGA (0.5 mm ball spacing) Xilinx Rep 56 6 X 6 mm 33 45 48 132 8 X 8 mm 100 106 Chip Scale Packages (CS) — wire-bond chip-scale BGA (0.8 mm ball spacing) 48 7 x 7mm 36 40 36 38 36 38 144 12 x 12 mm 108 117 117 280 16 x 16 mm 164 192 192 BGA Packages (BG) — wire-bond standard BGA (1.27 mm ball spacing) 256 27 x 27 mm 192 FGA Packages (FT) — wire-bond fine-pitch thin BGA (1.0 mm ball spacing) Automotive products are highlighted: 256 17 x 17 mm 184 212 212 164 212 212 -40C to +125C ambient temperature for CPLDs FBGA Packages (FG) — wire-bond Fineline BGA (1.0 mm ball spacing) 256 17 x 17 mm 192 192 324 23 x 23 mm 240 270 220 260

108 Xcell Journal Summer 2003 REFERENCE

Xilinx IQ Solutions

Part Number Speed Package Voltage Description Part Number Speed Grade Package Voltage Description

XC9500XL CPLD Spartan-XL

XC9536XL 10 ns/100 MHz VQ44, VQ64 3.3V 36 Macrocells (800 Gates), ISP, JTAG, Bus Hold XCS05XL -4 VQ100 3.3V Low cost FPGA with power down pin, 5V tol I/O, & I/P Hysteresis 5,000 Gate, 238 logic cells, 100 CLBs.

XC9572XL 10 ns/100 MHz VQ64, TQ100 3.3V 72 Macrocells (1,600 Gates), ISP, JTAG, Bus Hold XCS10XL -4 VQ100 3.3V Low cost FPGA with power down pin, 5V tol I/O, & I/P Hysteresis 10,000 Gate, 466 logic cells, 196 CLBs. CoolRunner XPLA3 XCS20XL -4 TQ144, PQ208 3.3V Low cost FPGA with power down pin, 5V tol I/O, 20,000 Gate, 950 logic cells, 400 CLBs. XCR3032XL 10 ns/100 MHz VQ44 3.3V 32 Macrocells (800 Gates), Low Power, Slew Rate Control, ISP & JTAG XCS30XL -4 TQ144, PQ208 3.3V Low cost FPGA with power down pin, 5V tol I/O, 30,000 Gate, 1,368 logic cells, 576 CLBs. XCR3064XL 10 ns/100 MHz VQ44, VQ100 3.3V 64 Macrocells (1,600 Gates), Low Power, Slew Rate Control, ISP & JTAG XCS40XL -4 PQ208, BG256 3.3V Low cost FPGA with power down pin, 5V tol I/O, 40,000 Gate, 1,862 logic cells, 784 CLBs. XCR3128XL 10 ns/100 MHzVQ100, TQ144 3.3V 128 Macrocells (3,200 Gates), Low Power, Slew Rate Control, ISP & JTAG Spartan-II

XCR3256XL 10 ns/100 MHz TQ144, PQ208 3.3V 256 Macrocells (6,400 Gates), Low Power, XC2S15 -5 TQ144 2.5V High volume FPGA, on-chip RAM, 16 I/O Slew Rate Control, ISP & JTAG standards, 15,000 Gate, 432 logic cells, XCR3384XL 10 ns/100 MHz PQ208 3.3V 384 Macrocells (9,600 Gates), Low Power, 96 CLBs, 4 block RAM blocks, 4 DLLS. Slew Rate Control, ISP & JTAG XC2S30 -5 TQ144, PQ208 2.5V High volume FPGA, on-chip RAM, 16 I/O XCR3512XL 10 ns/100 MHz PQ208 3.3V 512 Macrocells (12,800 Gates), Low Power, standards, 30,000 Gate, 972 logic cells, Slew Rate Control, ISP & JTAG 216 CLBs, 6 block RAM blocks, 4 DLLS.

CoolRunner-II XC2S50 -5 TQ144, PQ208, 2.5V High volume FPGA, on-chip RAM, 16 I/O FG256 standards, 50,000 Gate, 1,728 logic cells, XC2C32 6 ns/145 MHz VQ44 1.8V 32 Macrocells (800 Gates), 6 I/O Standards, 384 CLBs, 8 block RAM blocks, 4 DLLs. Slew Rate Control, Clock Doubler, Bus Hold, I/P Hysteresis. Ultra low power. XC2S100 -5 TQ144, PQ208, 2.5V High volume FPGA, on-chip RAM, 16 I/O FG256 standards, 100,000 Gate, 2,700 logic cells, XC2C64 7.5 ns/127 MHz VQ44, VQ100 1.8V 64 Macrocells (1,600 Gates), 6 I/O Standards, 600 CLBs, 10 block RAM blocks, 4 DLLs. Slew Rate Control, Clock Doubler, Bus Hold, XC2S150 -5 PQ208, FG256 2.5V High volume FPGA, on-chip RAM, 16 I/O I/P Hysteresis. Ultra low power. standards, 150,000 Gate, 3,888 logic cells, XC2C128 7.5 ns/127 MHz VQ44, VQ100 1.8V 128 Macrocells (3,200 Gates), 9 I/O Standards, 864 CLBs, 12 block RAM blocks, 4 DLLs. Slew Rate Control, Clock Doubler, Clcok Divider, XC2S200 -5 PQ208, FG456 2.5V High volume FPGA, on-chip RAM, 16 I/O CoolClock, DataGate, Bus Hold, I/P Hysteresis. standards, 200,000 Gate, 5,292 logic cells, Ultra low power. 1,176 CLBs, 14 block RAM blocks, 4 DLLs. XC2C256 7.5 ns/127 MHz VQ100, TQ144 1.8V 256 Macrocells (6,400 Gates), 9 I/O Standards, Spartan-IIE Slew Rate Control, Clock Doubler, Clcok Divider, CoolClock, DataGate, Bus Hold, I/P Hysteresis. XC2S50E -6 TQ144, PQ208, 1.8V High volume FPGA, on-chip RAM, 19 I/O Ultra low power. FT256 standards, 50,000 Gate, 1,728 logic cells, 384 CLBs, 8 block RAM blocks, 4 DLLs. XC2C384 10 ns/100 MHz TQ144, PQ208 1.8V 384 Macrocells (9,600 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok Divider, XC2S100E -6 TQ144, PQ208, 1.8V High volume FPGA, on-chip RAM, 19 I/O CoolClock, DataGate, Bus Hold, I/P Hysteresis. FT256 standards, 100,000 Gate, 2,700 logic cells, Ultra low power. 600 CLBs, 10 block RAM blocks, 4 DLLs.

XC2C512 10 ns/100 MHz PQ208 1.8V 512 Macrocells (12,800 Gates), 9 I/O Standards, XC2S150E -6 PQ208, FT256 1.8V High volume FPGA, on-chip RAM, 19 I/O Slew Rate Control, Clock Doubler, Clcok Divider, standards, 150,000 Gate, 3,888 logic cells, CoolClock, DataGate, Bus Hold, I/P Hysteresis. 864 CLBs, 12 block RAM blocks , 4 DLLs. Ultra low power. XC2S200E -6 PQ208, FT256 1.8V High volume FPGA, on-chip RAM, 19 I/O standards, 200,000 Gate, 5,292 logic cells, 1,176 CLBs, 14 block RAM blocks, 4 DLLs.

XC2S300E -6 PQ208, FG456 1.8V High volume FPGA, on-chip RAM, 19 I/O standards, 300,000 Gate, 6,912 logic cells, 1,536 CLBs, 16 block RAM blocks, 4 DLLs.

XC2S400E -6 FT256, FG456, 1.8V High volume FPGA, on-chip RAM,19 I/O FG676 standards, 400,000 Gate,10,800 logic cells, 2,400 CLBs, 40 block RAM blocks, 4DLLs.

XC2S600E -6 FG456, FG676 1.8V High volume FPGA, on-chip RAM,19 I/O standards, 600,000 Gate,10,800 logic cells, 3,456 CLBs, 72block RAM blocks, 4DLLs.

Summer 2003 Xcell Journal 109 REFERENCE

Xilinx Defense and Aerospace Products

QPRO Device SMD Voltage System Gates Logic Cells RAMbits CFG Bits MULTs DLLs Flip-Flops Max I/Os Packages XC3020* 5962-89948 5 1500 256 - 14779 - - 256 64 PG84, CB100 XC3030* None 5 2000 360 - 22176 - - 360 80 PG84 XC3042* 5962-89713 5 3000 480 - 30784 - - 480 96 PG84, PG132, CB100 XC3064* None 5 4500 688 - 46064 - - 688 120 PG132 XC3090* 5962-89823 5 6000 928 - 64160 - - 928 144 PG175, CB164 XC4005* 5962-92252 5 9K 466 6272 151960 - - 616 112 PG156, CB164 XC4010* 5962-92305 5 20K 950 12800 283424 - - 1120 160 PG191, CB196 XC4013* 5962-94730 5 30K 1368 18438 393632 - - 1536 192 PG223, CB228 XQ4005E 5962-97522 5 9K 466 6272 95008 - - 616 112 PG156, CB164 XQ4010E 5962-97523 5 20K 950 12800 178144 - - 1120 160 HQ208, PG191, CB196 XQ4013E 5962-97524 5 30K 1368 18438 247968 - - 1536 192 HQ240, PG223, CB228 XQ4025E 5962-97525 5 45K 2432 32768 422176 - - 2560 256 PG299, CB228 XQ4028EX 5962-98509 5 18K-50K 2432 32768 668184 - - 2560 256 HQ240, BG352, PG299, CB228 XQ4013XL 5962-98513 3.3 10-30K 1368 18K 393632 - - 1536 192 PQ240, BG256, PG223, CB228 XQ4036XL 5962-98510 3.3 22-65K 3078 42K 832528 - - 3168 288 HQ240, BG352, PG411, CB228 XQ4062XL 5962-98511 3.3 40-130K 5472 74K 1433864 - - 5376 384 HQ240, BG432, PG475, CB228 XQ4085XL None 3.3 55-180K 7448 100K 1924992 - - 7185 448 HQ240, BG432, CB228 XQV100 None 2.5 108904 2700 40K 781248 - 4 2400 180 PQ240, BG256, CB228 XQV300 5962-99572 2.5 322970 6912 64K 1751840 - 4 6144 316 PQ240, BG352, BG432, CB228 XQV600 5962-99573 2.5 661111 15552 96K 3608000 - 4 13824 512 HQ240, BG432, CB228 XQV1000 5962-99574 2.5 1124022 27648 128K 6127776 - 4 24576 512 BG560, CG560 XQV600E None 1.8 986K 15552 288K 3961632 - 8 13824 512 BG432, CB228 XQV1000E None 1.8 1569K 27648 384K 6587520 - 8 24576 660 BG560, CG560 XQV2000E None 1.8 2542K 43200 640K 10159648 - 8 38400 804 BG560, FG1156 XQ2V1000 TBD 1.5 1000K 11520 720 4082592 40 8 10240 432 FG456, BG575 XQ2V3000 TBD 1.5 3000K 32256 1728 10494368 96 12 28672 720 BG728 XQ2V6000 TBD 1.5 6000K 76032 2592 21849504 144 12 67584 1104 FF1152

* Not for new designs. QPRO RT DEVICE NOMENCLATURES XC = Qualified Prior to QML Certification

Device Voltage System Gates Logic Cells RAMbits CFG Bits MULTs DLLs Flip-Flops Max I/Os Packages Ionizing Total Dose (TID) in KRADs XQVR XQR4013XL 3.3 10-30K 1368 18K 393632 - - 1536 192 CB228 60 Qualified after QML XQR4036XL 3.3 22-65K 3078 42K 832528 - - 3168 288 CB228 60 Certification Radiation Tolerant XQR4062XL 3.3 40-130K 5472 74K 1433864 - - 5376 384 CB228 60 Virtex/Virtex-E XQVR300 2.5 322970 6912 64K 1751840 - 4 6144 316 CB228 100 XQVR600 2.5 661111 15552 96K 3608000 - 4 13824 512 CB228 100 XQR2V XQVR1000 2.5 1124022 27648 128K 6127776 - 4 24576 512 CG560 100 XQR2V1000 1.5 1000K 11520 720 4082592 40 8 10240 432 BG575 150 Virtex-II XQR2V3000 1.5 3000K 32256 1728 10494368 96 12 28672 720 CG717 150 Radiation Tolerant XQR2V6000 1.5 6000K 76032 2592 21849504 144 12 67584 1104 FC1144 150

QPRO CONFIGURATION PROMS Device SMD Voltage System Gates Logic Cells RAMbits CFG Bits MULTs DLLs Flip-Flops Max I/Os Packages Ionizing Total Dose (TID) KRADs XC1736D None 5 - - - 32768 - - - - DD8 - XC1765D 5962-94717 5 - - - 65536 - - - - DD8 - XC17128D None 5 - - - 131072 - - - - DD8 - XC17256D 5962-95617 5 - - - 262144 - - - - DD8 - XQ1701L 5962-99514 5 - - - 1048576 - - - - SO20, CC44 - XQ17V16 TBD 3.3 - - - 16777216 - - - - VQ44, CC44 - XQR1701L - 5 - - 1048576 - - - - SO20, CC44 60 XQR18V04 - 3.3 - - 4194304 - - - - VQ44, CC44 40 XQR17V16** - 3.3 - - 16777216 - - - - VQ44, CC44 TBD

**Under development.

110 Xcell Journal Summer 2003 REFERENCE FG676 (1.0mm) 27.0x27.0mm BG728 BF957 (1.27mm) FF1517 (1.0mm) (1.27mm) 35.0x35.0mm 40.0x40.0mm 40.0x40.0mm FG456 (1.0mm) 23.0x23.0mm FF1152 (1.0mm) 35.0x35.0mm BG575 (1.27mm) FG1156 (1.0mm) FG324 (1.0mm) 31.0x31.0mm 35.0x35.0mm 23.0x23.0mm FG256 (1.0mm) 17.0x17.0mm FF896 (1.00mm) 31.0x31.0mm FG900 BG256 (1.0mm) (1.27mm) 31.0x31.0mm 27.0x27.0mm FT256 (1.0mm) 17.0x17.0mm CAVITY-UP BGA’S CAVITY-UP FF672 (1.0mm) 27.0x27.0mm FLIP-CHIP BGA’S BG560 FG680 (1.27mm) (1.0mm) 42.5x42.5mm 40.0x40.0mm CS280 (0.8mm) 16.0x16.0mm CAVITY-DOWN BGA’S CAVITY-DOWN (with copper Heatslug) (0.5mm) HQ/PQ240 34.6x34.6mm CS144 (0.8mm) 12.0x12.0mm (0.5mm) VQ100 16.0x16.0mm PC84 TQ144 (0.5mm) (0.05in) 1.19x1.19in 22.0x22.0mm CS48 (0.8mm) 7.0x7.0mm VQ64 (0.5mm) 12.0x12.0mm CP132 (0.5mm) 8.0x8.0mm (0.5mm) HQ/PQ208 30.6x30.6mm TQ100 (0.5mm) PC44 (0.05in) 16.0x16.0mm VQ44 CP56 0.69x0.69in (0.8mm) (0.5mm) 12.0x12.0mm CHIP-SCALE BGA 6.0x6.0mm VERY THIN QUAD FLAT PACK THIN QUAD FLAT VERY THIN QUAD FLAT PACK THIN QUAD FLAT PLASTIC QUAD FLAT PACK PLASTIC QUAD FLAT PLASTIC QUAD FLAT PACK PLASTIC QUAD FLAT

Summer 2003 Xcell Journal 111 REFERENCE

Xilinx Configuration Storage Solutions Memory Density Number of Components Space Min Board Compression FPGA Config. Mode Multiple Designs Storage Software Removable IRL Hoods Max Config. Speed Media Non-Volatile SystemACE CF up to 8 Gbit 2 25 cm2 No JTAG Unlimited Yes Yes Yes 30 Mbit/sec CompactFlash SystemACE MPM 16 Mbit 1 12.25 cm2 Yes SelectMAP AMD 32Mbit 152 Mbit/sec Flash Memory 64 Mbit Slave-Serial (up to 8 FPGA chains) SystemACE SC 16 Mbit 3 Custom Yes SelectMAP Up to 8 No No Yes 152 Mbit/sec AMD 32 Mbit (up to 4 FPGA) Flash memory 64 Mbit Slave-Serial (up to 8 FPGA chains)

I/O Voltage VCCJ VCCO (V) Density PD8 VO8 SO20 PC20 PC44 VQ44 Core Voltage 2.5V 3.3V PROM Solution VO20 FS48 VCC (V) Platform Flash PROMs In-System Programming (ISP) Configuration PROMs XC3S50 XCF01S Y 3.3 1.8 - 3.3 1.8-3.3 XC18V512 512Kb Y Y Y 3.3V Y Y XC3S200 XCF01S Y 3.3 1.8-3.3 1.8-3.3 XC18V01 1Mb Y Y Y 3.3V Y Y XC3S400 XCF02S Y 3.3 1.8-3.3 1.8-3.3 XC18V02 2Mb Y Y 3.3V Y Y XC3S1000 XCF04S Y 3.3 1.8-3.3 1.8-3.3 XC18V04 4Mb Y Y 3.3V Y Y XC3S1500 XCF08P Y 1.8 1.5-3.3 1.5-3.3 One-Time Programmable (OTP) Configuration PROMs XC3S2000 XCF08P Y 1.8 1.5-3.3 1.5-3.3 XC17V01 1.6Mb Y Y Y 3.3V Y Y SC3S4000 XCF16P Y 1.8 1.5-3.3 1.5-3.3 XC17V02 2Mb Y Y Y 3.3V Y Y XC3S5000 XCF16P Y 1.8 1.5-3.3 1.5-3.3 XC17V04 4Mb Y Y Y 3.3V Y Y XC2S50E XCF01S Y 3.3 1.8-3.3 1.8-3.3 XC17V08 8Mb Y Y 3.3V Y Y XC2S100E XCF01S Y 3.3 1.8-3.3 1.8-3.3 XC17V16 16Mb Y Y 3.3V Y Y XC2S150E XCF02S Y 3.3 1.8-3.3 1.8-3.3 XC2S200E XCF02S Y 3.3 1.8-3.3 1.8-3.3 I/O XC2S300E XCF02S Y 3.3 1.8-3.3 1.8-3.3 Voltage XC2S400E XCF04S Y 3.3 1.8-3.3 1.8-3.3 Xilinx Home Page XC2S600E XCF04S Y 3.3 1.8-3.3 1.8-3.3 FPGA PROM Solution PD8 VO8 SO20 PC20 PC44 VQ44 Core Voltage 2.5V 3.3V http://www.xilinx.com OTP Configuration PROMs for Spartan-II/IIE XC2VP2 XCF02S Y 3.3 1.8-3.3 1.8-3.3 XC2VP4 XCF04S Y 3.3 1.8-3.3 1.8-3.3 XC2S50E XC17S50A Y Y Y 3.3V Y Y XC2VP7 XCF08P Y 1.8 1.5-3.3 1.5-3.3 XC2S100E XC17S100A Y Y Y 3.3V Y Y Xilinx Online Support XC2VP20 XCF16P Y 1.8 1.5-3.3 1.5-3.3 XC2S150E XC17S200A Y Y Y 3.3V Y Y http://www.xilinx.com/support/support.htm XC2VP30 XCF16P Y 1.8 1.5-3.3 1.5-3.3 XC2S200E XC17S200A Y Y Y 3.3V Y Y XC2VP40 XCF16P Y 1.8 1.5-3.3 1.5-3.3 XC2S300E XC17S300A Y 3.3V Y Y XC2VP50 XCF32P Y 1.8 1.5-3.3 1.5-3.3 XC2S15 XC17S15A Y Y Y 3.3V Y Y Xilinx IP Center XC2VP70 XCF32P Y 1.8 1.5-3.3 1.5-3.3 XC2S30 XC17S30A Y Y Y 3.3V Y Y http://www.xilinx.com/ipcenter/index.htm XC2VP100 XCF32P Y Y 1.8 1.5-3.3 & 1.8-3.3 XC2S50 XC17S50A Y Y Y 3.3V Y Y + XCF01S Y Y & 3.3 & 3.3 1.5-3.3 XC2S100 XC17S100A Y Y Y 3.3V Y Y XC2VP125 XCF32P Y 1.8 1.5-3.3 1.8-3.3 XC2S150 XC17S150A Y Y Y 3.3V Y Y Xilinx Education Center + XCF16P 1.8-3.3 XC2S200 XC17S200A Y Y Y 3.3V Y Y http://www.xilinx.com/support/ XC2V40 XCF01S Y 3.3 1.8-3.3 1.8-3.3 I/O education-home.htm XC2V80 XCF01S Y 3.3 1.8-3.3 1.8-3.3 Voltage XC2V250 XCF02S Y 3.3 1.8-3.3 1.8-3.3 XC2V500 XCF04S Y 3.3 1.8-3.3 1.5-3.3 Xilinx Tutorial Center FPGA PROM Solution PD8 VO8 SO20 PC20 PC44 VQ44 Core Voltage 3.3V 5.0V 1.5-3.3 XC2V1000 XCF04S Y 3.3 1.8-3.3 OTP Configuration PROMs for Spartan-XL http://www.xilinx.com/support/techsup/ 1.5-3.3 XC21500 XCF08P Y 1.8 1.5-3.3 XCS05XL XC17S05XL Y Y 3.3V Y Y 1.5-3.3 tutorials/index.htm XC2V2000 XCF08P Y 1.8 1.5-3.3 XCS10XL XC17S10XL Y Y 3.3V Y Y 1.5-3.3 XC2V3000 XCF16P Y 1.8 1.5-3.3 XCS20XL XC17S20XL Y Y 3.3V Y Y 1.5-3.3 XC2V4000 XCF16P Y 1.8 1.5-3.3 XCS30XL XC17S30XL Y Y 3.3V Y Y Xilinx WebPACK 1.5-3.3 XC2V6000 XCF32P Y 1.8 1.5-3.3 XCS40XL XC17S40XL Y Y 3.3V Y Y XC2V8000 XCF32P Y 1.8 1.5-3.3 http://www.xilinx.com/sxpresso/webpack.htm

112 Xcell Journal Summer 2003 REFERENCE

Xilinx Software

Feature ISE WebPACK ISE BaseX ISE Foundation ISE Alliance Devices Virtex™Series Virtex-E: V50E – V300E Virtex: V50 – V300 ALL ALL Virtex-II: 2V40 – 2V250 Virtex-E: V50E – V300E Virtex-II Pro: 2VP2 Virtex-II: 2V40 – 2V250 Virtex-II Pro: 2VP2 Spartan™ Series Spartan-II/IIE: Spartan-II/IIE: ALL Spartan-II/IIE: ALL Spartan-II/IIE: ALL ALL (except XC2S400E and XC2S600E) Spartan-3: 3S50 Spartan-3: 3S50 and 3S200 Spartan-3: ALL Spartan-3: ALL CoolRunner™ XPLA3 / CoolRunner-II ALL ALL ALL ALL XC9500™ Series ALL ALL ALL ALL Services Educational Services Yes Yes Yes Yes Design Services Sold as an Option Sold as an Option Sold as an Option Sold as an Option Support Services Web Only Yes Yes Yes Design Entry Schematic Editor Yes Yes PC Only No HDL Editor Yes Yes Yes Yes State Diagram Editor Yes Yes PC Only No CORE Generator System No Yes Yes Yes PACE (Pinout and Area Constraint Editor) Yes Yes Yes Yes Architecture Wizards Yes Yes Yes Yes DCM – Digital Clock Management MGT – Multi-Gigabit Transcievers 3rd Party RTL Checker Support Yes Yes Yes Yes Xilinx System Generator for DSP No Sold as an Option Sold as an Option Sold as an Option Embedded GNU Embedded Tools No Yes (Available with optional EDK) Yes (Available with optional EDK) Yes (Available with optional EDK) System Design GCC – GNU Compiler GDB – GNU Software Debugger WindRiver Xilinx Edition Development Tools No Sold as an Option Sold as an Option Sold as an Option Diab C/C++ Compiler SingleStep Debugger visionPROBE II target connection Synthesis Xilinx Synthesis Technology (XST) Yes Yes Yes No Synplicity Synplify/Pro Integrated Interface Integrated Interface Integrated Interface (PC Only) Integrated Interface (PC Only) Synplicity Amplify Physical Synthesis Support Yes Yes Yes Yes Leonardo Spectrum Integrated Interface Integrated Interface Integrated Interface Integrated Interface Synopsys FPGA Compiler II EDIF Interface EDIF Interface EDIF Interface EDIF Interface ABEL CPLD CPLD CPLD (PC Only) No Implementation FloorPlanner Yes Yes Yes Yes Constraints Editor Yes Yes Yes Yes Timing Driven Place & Route Yes Yes Yes Yes Modular Design Yes Yes Yes Yes Timing Improvement Wizard Yes Yes Yes Yes Programming iMPACT Yes Yes Yes Yes System ACE Configuration Manager Yes Yes Yes Yes Board Level IBIS Models Yes Yes Yes Yes Integration STAMP Models Yes Yes Yes Yes LMG SmartModels Yes Yes Yes Yes HSPICE Models* Yes Yes Yes Yes Verification HDL Bencher™ Yes Yes PC Only No ModelSim® Xilinx Edition (MXE II) ModelSim XE II Starter** ModelSim XE II Starter** ModelSim XE II Starter** ModelSim XE II Starter** Static Timing Analyzer Yes Yes Yes Yes ChipScope Pro No Sold as an Option Sold as an Option Sold as an Option FPGA Editor with Probe No Yes Yes Yes ChipViewer Yes Yes Yes Yes XPower (Power Analysis) Yes Yes Yes Yes 3rd Party Equivalency Checking Support Yes Yes Yes Yes SMARTModels for PPC and Rocket I/O No Yes Yes Yes 3rd Party Simulator Support Yes Yes Yes Yes Platforms PC (MS Windows 2000/MS Windows XP) PC Only (MS Windows 2000/MS Windows XP) PC (MS Windows 2000/MS Windows XP)Sun Solaris, Linux PC (MS Windows 2000/MS Windows XP)Sun Solaris, Linux IP/CORE For more information on the complete list of Xilinx IP products, visit the Xilinx IP Center at http://www.xilinx.com/ipcenter

* HSPICE Models available at the Xilinx Design Tools Center at www.xilinx.com/ise. ** MXE II supports the simulation of designs up to 1 million system gates and is sold as an option. For more information, visit the Xilinx Design Tools Center at www.xilinx.com/ise

Summer 2003 Xcell Journal 113 REFERENCE

Xilinx Global Services

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114 Xcell Journal Summer 2003

Introducing the SPARTAN ™-3 Platform FPGAs. The New Generation of Low Cost Solutions.

The world’s lowest-cost FPGAs

The first devices ever manufactured in 90nm process technology, our new Spartan-3 FPGAs deliver unbeatable price and performance. Packing a ton of I/Os, with densities ranging from 50K to 5 Million gates, you’ve got the lowest cost per pin and lowest cost per gate in the industry— and it’s all in the most cost-efficient die size available.

All the density and I/O you need . . . at the price you want

The new Spartan-3 FPGAs allow you to take your design idea from the white board to the circuit board in a huge range of applications. With cost savings in manufacturing, easy integration of soft core processors, superior DSP performance and full I/O support with total connectivity solutions, you get all you need at the price you want. The Spartan-3 Platform FPGAs are ready for a new generation of designs...are you?

MAKE IT YOUR ASIC

The Programmable Logic CompanySM

For more information visit www.xilinx.com/spartan3

PN 0010726