Multi-Pole Bandwidth Enhancement Technique for Transimpedance Amplifiers Behnam Analui and Ali Hajimiri California Institute of Technology, Pasadena, CA 91125 USA Email: [email protected]

Abstract quencies. Capacitive peaking [3] is a variation of the A new technique for bandwidth enhancement of ampli- same idea that can improve the bandwidth. fiers is developed. Adding several passive networks, A more exotic approach to solving the problem was which can be designed independently, enables the control proposed by Ginzton et al using distributed amplification of and frequency response behavior. [4]. Here, the gain stages are separated with transmission Parasitic of cascaded gain stages are iso- lines. Although the gain contributions of the several lated from each other and absorbed into passive net- stages are added together, the parasitic capacitors can be works. A simplified design procedure, using well-known absorbed into the transmission lines contributing to its filter component values is introduced. To demonstrate the real part of the characteristic impedance. Ideally, the feasibility of the method, a CMOS transimpedance ampli- number of stages can be increased indefinitely, achieving fier is implemented in 0.18mm BiCMOS technology. It an unlimited gain bandwidth product. In practice, this achieves 9.2GHz bandwidth in the presence of 0.5pF will be limited to the loss of the transmission line. Hence, photo diode and a trans-resistance gain of the design of distributed amplifiers requires careful elec- 0.6kW, while drawing 55mA from a 2.5V supply. tromagnetic simulations and very accurate modeling of transistor parasitics. Recently, a CMOS distributed 1. Introduction amplifier was presented [7] with unity-gain bandwidth of The ever-growing demand for higher information trans- 5.5 GHz. fer rates has resulted in a rapid emergence of highly inte- This work introduces a new multi-pole bandwidth grated communication systems. Silicon integrated enhancement technique for wide-band amplifier design. circuits are the only candidate that can achieve the It is based on turning the entire amplifier into a low-pass required level of integration with reasonable speed, cost, filter with a well-defined pass-band characteristic and and yield and have thus been pursued to a great degree in cut-off frequency. The inevitable parasitic capacitances recent years. In particular, full silicon-based integration of the transistors are absorbed as part of the low-pass fil- of optical-fiber-based data communication systems, such ter and hence, affect the bandwidth of the amplifier in a as 10-GB/s (OC192) and 40-GB/s (OC768) SONET or controlled fashion. gigabit ethernet systems, can be of great interest for these In the rest of the paper, we first discuss the details of reasons. However, silicon-based integrated circuits the bandwidth enhancement technique starting with a implementing such systems face serious challenges due brief background and following with the design method- to the inferior parasitic characteristics in silicon-based ology. Then, we show implementation of CMOS trans- technologies, complicating the procedure for a wide-band impedance amplifier as a design example and conclude design. this paper with its measurement results. Wide-band amplifiers are one of the most critical build- 2. Bandwidth Enhancement Theory ing blocks at the electro-optical interface on both receiver The limitation on the gain bandwidth product (GBW) of and transmitter sides. Wideband operation is an insepara- conventional amplifier structures has been known for ble part of any baseband communication system such as over half a century [9]. It was first studied in the context non-return-to-zero (NRZ) amplitude shift keying (ASK) of broadband matching, where lossless passive networks common to optical fiber communications due to the sig- are used to optimally match specific loads to source nal’s spectral content down to very low frequencies. Par- impedances over a wide range of frequencies. Bode has ticularly, all amplifiers in the path should have enough shown that there exists a maximum GBW product for bandwidth with minimum variations in the and such a system regardless of the network used [8]. Fano constant group-delay to avoid distortion in the signal. and Youla, further generalized the theory for a larger The inherent parasitic capacitors of the transistors are class of load impedances. The same theory can be applied the main cause of bandwidth limitation in wideband to a simple single-stage amplifier, with the unilateral amplifiers. Several bandwidth enhancement methods small signal model and a passive load impedance have been proposed in the past. First order shunt peaking Zj()w shown in Fig. 1a. For such an amplifier, it can be is used to introduce a resonant peaking at the output when shown that [5] the maximum gain bandwidth product is the amplitude starts to roll-off at high frequencies [1][2]. given by: Traditionally it has been done by adding a series inductor with the output load that increases the effective load gm ()GBW = ------(1) impedance as the capacitive reactance drops at higher fre- max p × C (a) vin g v Z(jw) Av1 H (w) Av2 Av3 m in 1 H2(w) H3(w)

S (b) Log(A ) Z1(w) Z2(w) Z3(w) v gm1 gm2 gm3

Fig. 1 (a) A general small signal model of an amplifier with an arbitrary passive load (b) isolation of cascaded passive Log(w) networks Fig. 2 Stagger tuning for designing wideband amplifiers where gm is the device transconductance and C is defined as: imation for the transistors. If some number of stages with the same simple model of Fig. 1a are placed in series, 1 C = lim æö------(2) gain stages separate different networks due to the internal w¥® èøjwZ isolation of the active devices. Using parameters in Fig. However, the upper-bound in (1) is not valid for amplifi- 1b, the over all transfer function can be written as: ers, where the load does not satisfy the conditions of an Av()jw = Gm × Z21()jw (4) impedance function1. In other words, if the overall trans- fer function of an amplifier is of the form: where:

G = g ××g g (5) Av()jw = gm × Zj()w (3) m m 1 m2 m3 and Zj()w is not an impedance function, then Bode-Fano Z21()jw = Z211, ()jw ××Z212, ()jw Z213, ()jw (6) limit in (1) need not be satisfied. It will be shown that dis- and Z21, i()jw 's are the forward impedance parameters of tributing passive structures between gain stages can result the two- networks and can be designed indepen- in such transfer function. Therefore, the GBW product dently. From (4) and (6) it is clear that Z21()jw is the can potentially be higher. This is one of the major contri- product of three different impedance functions and there- butions of this paper. fore need not be an impedance function itself. For

A more rigorous study on broadband matching circuits instance, Z21()jw is still a rational function, but the for amplifiers is developed in [10]. There, the matching numerator polynomial can be more than one degree networks exist at the input and output of a single stage higher than the denominator one. As a result, although (4) amplifier simultaneously. Although, this can result in is in form of the overall gain in (3), it is not limited by the larger GBW products than (1), the need for the amplifier upper-bound set in (1). two-port parameters complicates the proposed design One design approach for such cascaded transfer func- method. Moreover, the procedure emphasizes single tions is stagger tuning of the frequency responses, such as stage, two-port amplifiers, which limits its applications. the one shown symbolically in Fig. 2. An early amplitude Based on these methods, passive structures have been roll-off due to a low frequency pole in one structure can, used for input broadband matching and bandwidth then, be compensated for, with a peaking in the next enhancement [12]. stage. Similarly, the overall phase response of passive A. Methodology structures can be properly controlled. However, this Practical amplifiers are more complicated than the requires careful calculation of exact transfer functions model in Fig. 1a. They have several stages with more based on the component values that can be used as design nodes controlling the transfer function shape. The new equations. If not accurate, undesirable peaking may be technique introduced in this paper, proposes deploying introduced to the overall transfer function. distributed passive networks in between the gain stages In the design of such networks, well-known low-pass of the amplifier to tailor the frequency response shape. filter structures with known response characteristics can The distribution of the passive networks will result in a be used instead. Since, in this procedure, it is desired to frequency dependent transfer function which need not be achieve a particular response shape, which resembles in form of an impedance function as in (3). Therefore, the low-pass filter responses with known characteristics, the Bode-Fano limit does not apply to the complete amplifier same component values as the ones in the filter can be and can be overcome in practice. used for the passive network elements. Therefore, the Fig. 1b shows small signal model of cascaded transistor design procedure will be much more simplified. Addi- gain stages and passive networks using unilateral approx- tionally, absorbing the capacitive parasitic components of the gain stages (transistors) into the passive networks will turn the transistor into a gain stage with infinite band- 1. An impedance function in the complex frequency domain, is a ratio- width. Thus, the frequency-dependent behavior will com- nal function (ratio of two polynomials with real coefficients) of fre- quency with no singularities in the interior of the right half-plane. pletely rely on the passive structures. In his approach one Additionally, the numerator polynomial should be of at most one degree can resort to passive networks with low sensitivity to higher than the denominator one. The conditions for impedance func- component values. The design procedure based on this tion can be found in [5]. new practical technique will follow. Passive Network RL RD L2 L4 L6 Parasitic Capacitances V V L4 V R B B Out V G V F In M In R1 C C3 C CN R L 1 5 2 L2 3 L1 AV Buffer IIn CPD Added Network Fig. 3 Inserting a ladder structure between the gain stages Fig. 4 Simplified schematic of the TIA with parasitic capacitances and additional inductors. B. Design Procedure This expression can be used as a guideline in designing Different passive structures can be inserted between the amplifier, before adding the passive network. For gain stages. However, using a standard network configu- instance, adjusting for larger d with proper choice of load ration for which the component value equations are will result in a better bandwidth enhancement already known, will simplify the design. A small-signal ratio after inserting the network. model of two cascaded gain stages is shown in Fig. 3 If the analysis is to be carried out for the input stage of after adding a standard ladder configuration. By choosing a transimpedance amplifier with a current input signal, R1 the desired frequency response shape and hence the filter is infinity due to the large equivalent resistance of the type, the element values can be generated using standard reverse biased photo diode. However, it can be shown network synthesis methods [11]. The order of the passive from (11) that for fixed C1, C2, and R2, there exists a network, n, is an additional design parameter. Using value R1 (i.e., R1 = 2.05R2 resulting in d = 0.7 ) that higher orders will improve the response; however, the maximizes the BWER for the input stage. Therefore, the components will take some impractical values and the same procedure can be used, without including R1 in the number of inductors will also increase resulting in an network. Enhancement ratio in (11) should also be modi- unrealistic design. As an example, to achieve a maxi- fied for the input passive structure as: mally flat frequency response for a 3rd order ladder net- 1 R2 C1 + C3 work, such as the one in Fig. 3, values from butterworth BWER = ------××------(12) 1 – d R C1 filter components can be used as follows: 1 1 3. Design example and simulation results C1 = ------(7) R1(1 – d)wc To demonstrate the effectiveness of the developed methodology, a CMOS transimpedance amplifier (TIA) 2 (8) is designed. The simplified schematic of the circuit L2 = ------2 2 (1 – d + d )w××c C1 including the added passive components is shown in Fig. 4. It is a single-ended design consisting of three gain 1 C3 = ------(9) stages. The first stage is a shunt-shunt feedback transim- R2(1 + d )wc pedance stage that provides a low input impedance. This where d is an indication of impedance transformation will reduce the dominant effect of the input pole due to between R1 and R2 and is defined as: the large photo diode junction capacitance (CPD). The next two stages are cascode configuration and are iso-

R1 – R2 lated using a source follower buffer. d = n ------(10) Four passive networks are inserted in the critical nodes R1 + R2 of the structure to relocate the poles and therefore, and wc is the 3-dB cut-off frequency of the network. Note enhance the bandwidth. The input network, separates the that C1 and C3 are the transistor parasitic capacitances photo diode capacitance and the parasitic capacitance of absorbed into the passive structure. The design procedure the input stage. Adding one inductor will turn it into a 3rd is to first optimize the original amplifier with no addi- order ladder structure, which can be designed as tional components. As a result, component values for R1, explained in the previous section. The next two networks R2, C1, and C3 will be known. Using either of (7) or (9), are also of 3rd order and are placed between the cascoded the new value for wc can be derived. Then, the value of transistors. The output network isolates the load resis- the inductor can be calculated form (8), knowing all the tance from the last stage and is a 2nd order network. other parameters. If the analysis is done for the output However, adding explicit capacitors (including bonding- structure, R2 should be replaced with RL which is the load pad capacitance) can turn it into a 3rd order structure. resistance. With this choice of networks, only inductors are to be If we define the bandwidth enhancement ratio (BWER) added to the configuration. The capacitors (as shown as the ratio between the old (before adding any passive with dotted line in Fig. 4) are the parasitics from the component) and new 3-dB bandwidth of the amplifier, devices. A final optimization is done to include the bilat- we can show: eral effects. Note that the output network is different from a conventional shunt-peaking approach. For a photo wc, new 1 R C + C BWER º ------= ------××------2 ------1 3 (11) diode capacitance of 0.5pF, circuit achieves over 9GHz wcold, 1 – d R1 + R2 C1 60 R 50 trans ]

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-30 0.1 1 10 Frequency [GHz] Fig. 5 Trans-resistance gain of the TIA with 0.5pF photo diode capacitance Fig. 7 The die photo of the 10GHz Trans-impedance Amplifier. 0 transistors can be absorbed into passive networks, -90 inserted between the gain stages. The component values can be calculated based on standard low-pass filter struc- -180 tures. A prototype CMOS TIA implemented using the

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e s a -450 h Acknowledgments P -540 The authors would like to thank Conexant Systems for fabricating the chip and M. Racanelli, S. Stetson, and A. -630 Karroy for their support. They also acknowledge I. Aoki, H. Hashemi, D. Ham, S. Kee, and H, Wu from Caltech’s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency [GHz] CHIC group for useful discussions. We also thank Lee Fig. 6 Phase response of the TIA center for advanced networking the support of this project. bandwidth. This is 2.4 times larger than the bandwidth achieved using same circuit with no additional passives. References [1] S. Mohan, et. al., “Bandwidth extension in CMOS with optimized 4. Measurement results on-chip inductors,” IEEE JSSC, vol. 35, no.3, pp. 346-355, March The transimpedance amplifier was implemented using 2000. [2] N. Ohkawa, “Fiber-optic multigigabit GaAs MIC front-end circuit 0.18mm MOS transistors in a BiCMOS process technol- with inductor peaking,” J. Lightwave Tech., vol. 6, no.11, pp. ogy. It draws 55mA from a 2.5V power supply. The 1665-1671, Nov. 1988. amplitude and phase response of the implemented TIA, [3] F. Chien and Y. Chan, “Bandwidth enhancement of transimped- ance amplifier by a capacitive-peaking design,” IEEE JSSC, vol. extracted from measurement data are shown in Fig. 5 and 34, no. 8, pp. 1167-1170, Aug. 1999. Fig. 6. Here he photo-detector capacitance is CPD=0.5pF. [4] E. Ginzton, et. al., “Distributed Amplification,” Proc. of IRE, pp. The bandwidth is 9.2GHz and the transimpedance gain is 956-969, Aug. 1948. [5] T. Wong, Fundamentals of Distributed Amplification, 1st ed., 54dBW. This is the fastest 0.18mm CMOS transimped- Boston: Artech House, 1993. ance amplifier to this date to the authors’ knowledge. The [6] K. Kobayashi, R. Esfandiari, and A. Oki, “A novel HBT distrib- uted amplifier design topology based on attenuation compensation input reflection coefficient, S11, remains below -10dB up techniques,” IEEE Trans. Micro. Theory and Techniques, vol. 42, to 7GHz. The dip in the frequency response of the tran- No.12, pp. 2583-2589, Dec. 1994. simpedance can be traced back to a resonance mode [7] B. Ballweber, R. Gupta, and D. Allstot, “A fully integrated 0.5-5.5 GHz CMOS distributed amplifier,” IEEE JSSC, vol. 35, No.2, pp. between the on-chip supply by-bass capacitor and wireb- 231-239, Feb. 2000. ond and supply line as changing those param- [8] H. Bode., Network Analysis and Feedback Amplifier Design, Prin- eters directly affects its depth and frequency. Simulated ceton: D. Van Nostrand company, 1945. [9] W. Hansen, “On maximum gain-band width product in amplifi- average equivalent input noise current is 17pA /.Hz ers,” J. Applied Phys., vol. 16, pp. 528-534, 1945. This results in total input noise current of 1.6mA. The [10] W. Ku and W. Petersen, “Optimum gain-bandwidth limitations of 2 transistor amplifiers as reactively constrained active two-port net- amplifier core occupies 0.8´ 0.8mm of area as shown works,” IEEE Tran. Circ. and Syst., vol. CAS-22, pp. 523-533, in Fig. 7. June 1975. [11] W. Chen, Theory and Design of Broadband Matching Networks, 5. Conclusions Oxford: Pergamon Press, 1976 [12] H. Kim, S. Chandrasekhar, C. Burrus, J. Bauman, “A Si BiCMOS In this paper, we address the gain-bandwidth (GBW) lim- Trans-impedance Amplifier for 10Gb SONET receiver, Symp. itation problem and introduce a new practical methodol- VLSI circuits, 2000, pp. 170-172. ogy that can be used to design wide-band amplifiers with specified desired characteristics for its transfer function. In a simple design procedure, parasitic capacitances of