Flexnoc Physical™ Arteris Flexnoc Physical Interconnect IP

® Arteris FlexNoC Physical™

Arteris FlexNoC Physical Interconnect IP

Arteris FlexNoC Physical interconnect fabric IP is the first physically-aware commercial network-on- chip IP. It builds upon the already layout-friendly FlexNoC IP to shorten the time required for P&R. LEARN MORE FlexNoC Physical IP uses the SoC interconnect architecture to both accelerate timing closure and www.Arteris.com improve QoR by using less slack to meet timing, further reducing SoC silicon area and improving performance.

ACCELERATE TIMING CLOSURE AND P&R

Automated Pipeline Configuration and Optimization HIGHLIGHTS FlexNoC Physical interconnect IP enhances layout QoR and productivity by importing user-defined and production (LEF/DEF) floorplans, automatically configuring pipelines to meet timing closure,  Adds physical- and separating the FlexNoC interconnect IP instances at a physical level so they can be routed awareness to already separately from the rest of the SoC. layout-friendly FlexNoC IP: Minimum wires, fine- grained pipeline placement, distributed IP placement.

 Reduces timing closure and P&R effort by provid- ing better netlists and floorplans to back-end teams, earlier.

 Advanced Technology: Additional configurable hardware IP, visualization cockpit, timing estimation engine, automatic pipeline placement and configuration. BENEFITS  Reduces or eliminates excessive P&R iterations – To resolve timing closure errors on  Additional inputs are NoC long paths, SoC designers often have to iterate over multiple P&R runs, which can take weeks. architecture, SoC floor- Optimizing the NoC interconnect IP early, prior to full SoC P&R, reduces the likelihood of tim- plan and technology ing closure issues during layout. process information.

 Eliminates trial-and-error timing closure with automated pipeline configuration –  Links to EDA Tools: By analyzing the interconnect IP in the front-end design phase and automatically configuring Outputs LEF/DEF floorplan pipeline stages as appropriate, the front-end teams hand over to the back-end team a netlist information, RTL, con- that will close timing by design. straints and TCL scripts for easy use by industry-  Optimizes Quality-of-Results (QoR) – SoC teams often over-design their chips in the leading SP&R tools from front-end stage to avoid timing problems in the back-end. FlexNoC Physical IP intelligently Synopsys and Cadence. estimates and predicts in the front-end phase where timing issues will occur in the back-end, allowing design teams to implement the minimum number of pipeline stages to achieve de- sired frequencies, while also minimizing latencies and power consumption.

® Arteris FlexNoC Physical™

 Separates the FlexNoC interconnect physical IP from the rest of the SoC – FlexNoC ADVANTAGES Physical offers features to separate the interconnect IP at the physical level the same way that it allows such isolation at the architectural level. Users can now generate interconnect  Easier and faster timing floorplan outlines and treat the interconnect as a separate IP to be independently placed and closure. routed by itself. Such a separation simplifies the job of the layout team.  Fewer place and route iterations.  Automated pipeline configuration can save months of manual work.  Less likelihood of overdesign or under-design.  Visualize and under- stand architecture and topology issues earlier in the design process.

REDUCE TIME-TO-MARKET ANALYST PERSPECTIVE FlexNoC Physical IP decreases the effort and time to reach timing closure while reducing the likelihood of overdesign by intelligently configuring pipeline registers and allowing the NoC interconnect “Arteris is solving an im- to be optimized and routed separately from the rest of the SoC. portant set of back-end problems with technology FlexNoC that works earlier in the SoC design flow. USER SUCCESS “Our successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and FlexNoC Physical IP has implement sophisticated SoCs in less time and with better power consumption and performance.” the potential to signifi- Fares Bagh, Vice President of R&D, Freescale cantly decrease timing issues experienced in the “Arteris interconnect IP offers us a layout stage, reducing convenient solution to handle the high speed communication need- P&R iterations and engi- ed between our SoC and external “After a complete evaluation of available interconnect fabric IP neering change orders modem IC. Our customers will products, Arteris FlexNoC was the clear choice. We are pleased ARTERISbenefit from the lower BOM cost with the increased productivity our design team has experi- (ECOs) and saving cost and power consumption as a enced using FlexNoC.” and schedule time.” result of this IP. We look forward Ty Garibay, Vice President of Silicon Systems Develop- CUSTOMERto Arteris’ interconnect IP helping ment, Altera Mike Demler, Senior Analyst, us shorten development sched- SUCCESSules and lower risks associated The Linley Group with compatibility.” Thomas Kim, Vice President, HiSilicon uses Arteris FlexNoC fabric IP as the backbone in- SoC Platform, Samsung terconnect for multiple mobility SoC product lines.

ABOUT ARTERIS LEARN MORE Arteris invented Network on Chip interconnect technology, offering the world’s first commercial solution in 2006. Arteris connects the IP blocks in semiconductors from Altera, Samsung, TI, Freescale, HiSilicon, www.Arteris.com Spreadtrum, RDA, Renesas Electronics, NTT Electronics, Toshiba, LG and many others.