Path to co-packaged photonic I/O for large- scale Chip-to-Chip interconnect

SEMICON West 2020 July 20-23, 2020 Thomas Liljeberg Intel - Silicon Photonics Products Division Intel silicon photonics

2016 2017 2018 Launched First Product Expanded Portfolio Ramped Hyper-scale Cloud Customers

100G CWDM4-OCP Demonstrated 400G

Award Winning 100G CWDM4 2km First High Volume Integrated Silicon Photonics Transceiver

100G PSM4 100G CWDM4 10km New 100G Transceiver for 5G Wireless Infrastructure

>3M 100G transceivers shipped -- 2M/yrrun-rate

3 photonics At Silicon Scale Laser Fabrication Silicon Integration Silicon Scale

Silicon (device) wafer Indium phosphide Optical die

Plasma activation and bonding: InP die are bonded & transferred Electrical in parallel to device wafer

Advanced CMOS manufacturing at Intel fabs on 300mm wafers InP substrate removal: only active RF epi layers remain on device wafer Capable of multiple InP optical wavelengths and integration of Comprehensive, automated Silicon multiple optical on-wafer optical, electrical, and Hybrid laser >90% coupling efficiency components high-speed test capabilities

3 Growth of switch bandwidth

102.4T 100T 2x bandwidth / 2yrs 100G, 200G? Increasing power overhead ? Increasing SI complexity ? 51.2T 50T 100G (x512) 64x 800G 2RU

25.6T 100G (x256) 25T 32x 800G 1RU

Switch bandwidth 12.8T I/O 50G (x256) 12.8T Pluggable solution 32x 400G Form factor 1RU

2019 2025 Directional, based on Intel estimates

Silicon Photonics Product Division 4 Optical switch I/O: key to network growth Problem Solution Network BW must match data center traffic High BW optics move close to the switch to growth, but growth rates are mismatched eliminate need for retimers and reduce power

Years for BW to double Conventional switch

Data center Switch IC SerDes I/O Front 25.6T ▪ Front panel optical modules traffic throughput speed panel switch ▪ Standardization Optical Retimers 2 2 3 modules Optical switch with external laser Increasing SerDes I/O count and speed 25.6T ▪ Power savings increase power and signal routing difficulty switch ▪ Density and serviceability Impact of increasing switch I/O System System System Co-packaged optics switch 25.6T ▪ Lowest system power power density cost Lasers switch ▪ Highly integrated lasers deliver best density at lowest cost

Silicon Photonics Product Division 5 Silicon Photonics Co-Packaged Switch

Switch package

Photonic Engine Optical Interface

Integration for Power and Performance scaling • Lower-loss channel → lower-power I/O Silicon Photonics • No on-board retimers → lower system power and cost Optical • Higher density • Reduced cost of photonics ($/Gbps) through integration Components • Reduced cost (system) through simpler systems and deployment → Enable bandwidth scalability: break constraint of copper and front-plate pluggable 6 Silicon Photonics Product Division Enabling Technologies –Hybrid Laser

• On-chip laser vs. external “optical power supply” - Total power - Cost - Thermal solution - Reliability

Laser Power Reliability / Laser Cost Thermal Dissipation Serviceability Requires low laser Lowest ~+10% power in On-chip 1 FIT (wafer-scale mfg) package (or redundancy) ~1.7x High Higher FIT, but External Coupling loss Lower (Laser packaging) field serviceable (+5% system) Intel estimates

Silicon Photonics Product Division 7 Enabling technologies -Silicon Photonics hybrid Laser Platform

80°C 20°C 90°C 100°C 1310nm 25 110°C

20 Advanced CMOS manufacturing process in Intel fabs 120°C

on 300mm wafers 15

MQW gain 130°C 10

Output Power (mW) Power Output 140°C 5 Hybrid laser supports wafer scale fabrication with 150°C extra flexibility for design optimization 0 0 20 40 60 80 100 120 140 160 180 Drive Current (mA) Pierre Doussiere, GROUP IV PHOTONICS, 2017

Silicon Photonics Product Division 8 ReliabilItyof HYBRID III-V/Si wafer bonded laser

III-V / Si Hybrid Laser, 80C HTOL Process qual 80C HTOL 50 50 40 40 Sample size = 231 lasers 30 Sample size = 30 lasers 30 20 20 10 10 0 0 -10 -10 -20 -20

Ibias Ibias change (%) -30 -30 1310nm 1310nm (%)Ibiasin Change -40 -40 -50 -50 0 5 10 15 20 25 0 2000 4000 6000 8000 10000 Aging time (khrs) Aging time (hrs)

23,500 hours at 80C and 2x typical operating Bias Increase vs. Aging Time for 150C, 150mA aging test current 50 40 ▪ Excellent long-term stability (average drift ~1%), over 30 2.7 years (>15 yrs @ 65C laser) 20 10 Process Qual: 231 devices / 10khrs 0

-10 Norm (%) Ibias Accelerated test: 3000hrs corresponds to 15 yrs -20 at 70C case temperature -30 0 500 1000 1500 2000 2500 3000 Field data (laser): ~2 FIT Aging time (hrs) R. Herrick, OFC 2019 invited talk

Silicon Photonics Product Division 9 Intel Silicon Photonics Ring Modulators

ER = 4.6 dB TDECQ = 1.2 dB

With FIR

Carrier depletion ring modulators • 10um ring radius • Integrated silicon heaters for bias-point control • <20mW/pi tuning efficiency • >50GHz bandwidth • 6dB ER @ 2Vpp • Stable performance over temperature – tested error free over 80C range and 45C/min temperature change

Silicon Photonics Product Division 10 16ch Integrated Silicon photonics Transmitter • Test-chip: 16-channel (1.6Tbps) PSM transmitter PIC • On-die integrated lasers • 112G ring-resonator modulators 16x 16x Mode • Mode-converters and V-grooves for cost- 2x 16-laser array V-groove effective HVM packaging MRR 2x1 conv • Fully integrated Tx optics enables wafer- level test → KGD • Supports redundant lasers

Key Components (DR4) Additional for WDM (FR4) • 16x channels • 16 mode-converters with • 4x (4:1) Muxes • Multi-wavelength laser array • 32x lasers integrated V-groove • 4x (1:4) Demuxes • 16x MZIs • >30cm of WG routing • 16x Ring Modulators • >500 bumped pads • 48x GeMPDs and Heaters • 4x Temperature sensors

Silicon Photonics Product Division 11 Enabling technologies –Packaging • On-chip spot-size converter • 0.5dB coupling loss +/-0.2dB over O-band • 0.3dB penalty for +/- 1um alignment

• Passive alignment in etched V-grooves • Demonstrated average coupling loss ~1.1dB

• High-speed, low-loss LGA socket • Compatible with XSR channel • Future point of standardization • Enables testability

Silicon Photonics Product Division 12 integrated photonics performance

100G pluggable module

1.6T photonic engine Optical eye diagram of 8-channels of 106Gbs integrated Silicon Photonics transmitter • Compact, fully integrated optical network interfaces through advanced packaging technology • Design targets and performance compliant with applicable optical interface standards • Photonic Integrated Circuits realized as 16-channel by 100Gbps in Intel Silicon Photonics high-volume manufacturing platform • Scalable to 3.2Tbs and beyond

Integrated receiver performance at 106Gbps

13 Silicon Photonics Product Division Co-packaged Silicon Photonics + 12.8Tbps Tofino 2 Ethernet switch

• Barefoot Tofino 2 12.8T P4- programmable Ethernet switch Bare fiber to MTP ribbon connector panel • Co-packaged with integrated photonic

engines Switch ASIC heatsink removed to show details • Compliant with applicable standards for I/O interfaces • Designed for 25.6T and 51.2T switch generations Electrical fly-over cables for half the ports • Technology platform developed for volume manufacturability • Live 400G Ethernet traffic enabled by fully functional switch platform with co-packaged optics ports in single MTP front faceplate connectors switch package • Demonstrated compliant interop with commercial ToR switch + QSFP-DD DR4 module

Silicon Photonics Product Division Market adoption

Pilot at 25T – learn and refine Full scale deployment at 50T Ubiquitous, enabling at 100T 102.4T 100T 100G or 200G? ? ? 51.2T Pluggable model broken 50T 100G (x512) Scale enabled by co-packaging 64x 800G 2RU Re-timers for all ports? 25.6T Power: Module and total system 100G (x256) 25T 32x 800G Significant value of co-package ($,W) 1RU

Switch bandwidth 12.8T Re-timers for larger systems I/O 50G (x256) Power density of 800G 12.8T Pluggable solution 32x 400G Cost and system power savings with co-packaging Form factor 1RU

2019 2025 Directional, based on Intel estimates

Silicon Photonics Product Division 15 summary • Ethernet switches facing scalability challenge from I/O constraints - Increasing power overhead - I/O port count and package escape • Pluggable solutions can enable the next 2 generations of switches, but… - at increasing cost in terms of power and density - Co-packaged optics at lower cost with volume • Co-packaging of optical I/O addresses challenge with improved power, density, and cost - Core technologies required for co-packaging exist now: Technology demonstration of Co-packaged optics + Tofino-2 Ethernet Switch - Ethernet traffic and interop with commercial switch-system and 400G-DR4 pluggable modules

Silicon Photonics Product Division 16 Thank you! Intel.com/siliconphotonics

DCG Connectivity Group 17