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Grand Challenges and Timelines for Electronic-Photonic Integration Grand Challenges and Timelines for Electronic-Photonic Integration Lionel C. Kimerling Director, MIT Microphotonics Center AIM Integrated Photonics MEPTEC 2016, San Jose 1 Key Points § silicon learning curve carries huge leverage § system func3on over device emphasis § Ge-on-Si: a pleasant surprise § everything gets be;er with integraon § manufacturing is the key silicon advantage The Informa(on Age is becoming the Learning Age. A technology transi(on to distributed systems that gather and process informa(on, and actuate responses. 2 Computing Systems 100x / 20 yr Per-CPU Chip: 100x/10yr Per-System: 1000x/10 yr ~50-60% (2x/18 mo.) – falling ~100% (2x/yr) ~ steady System parallelism: fundamental physics of power-efficiency (lower clock frequency) 6 PF server of 2010: ~2.5M fiber connects @10 Gb/s Budget of $20–40M for optical transceivers in one machine! Alan Benner, IBM Pervasive Silicon Photonics § The number of photonic components deployed in IT systems is increasing. § The contribution of photonics to system cost is becoming significant. § Manufacturing cost reduction is directly related to the number of units produced. § If a common manufacturing platform is shared across the industry, one can expect that cost reduction will scale with manufacturing volume. § Integrated Silicon Microphotonics is today the only platform capable of high volume production (>10 million units) and high levels of integration. 4 Design Rule: photonics at BxD=1Tb/s x cm $0.01/Gbps $0.1/Gbps $1/Gbps cost and margins decrease, TAM and integration increase $/Gbps ê25%/yr unit count x100/interface energy ÷100/interface Monolithic, chip-level photonic integration: solution to cost, energy bandwidth density. output Electronic-Photonic ‘CMOS’ PD1 (L = 160 µm) CMOS FET-Photonic Integration Scenarios photon PD2 (L = 80 µm) Si CMOS FEOL BEOL SiGe <450 <550 750* SiGe 900 Silicon is the only materials system capable of high density electronic-photonic integration. Ge-on-Si High Efficiency Photonic Devices Waveguide Integrated Devices in CMOS λ n SiGe Ge n+ contact 50 nm Si p p+ contacts Two Step Ge-on-Si CVD Butt coupler Ge “Damascene λ Vertical I/O couplers Waveguides & Ge growth, CMP & Contacts & Interconnect Vertical Coupler Top electrode vertical butt α-Silicon coupler coupler CVD-SiO2 xtal-Silicon n+ region n+ region SiGe 0.6um p+ region p+ region SOI BOX λ in λ out Silicon Edge View Side View Edge View Everything improves with integration: speed, power efficiency and functionality. The GOPS Gap Performance (GOPS) The 1000 GOPS 100 Gap 10 SMT, FGMT, CGMT OOO 1 Superscalar Why the GOPS Gap? Pipelining § Performance 0.1 § Power efficiency § Programmability 0.01 1992 1998 2002 2006 2010 time Agarwal, MIT 5 ATAC: All-to-All Computing Parallelism has replaced clock speed as the scaling paradigm. Programming – Power Efficiency - Performance sending core receiving core multi-wavelength source waveguide modulator data waveguide modulator filter transimpedance driver photodetector amplifier flip-flop flip-flop Electronic-photonic ‘CMOS’ Optical power and data buses Engineering parallelism is the most important frontier in information hardware. Optical Path Switching IP to circuit switching for large files • 103 reduction in cost • 103 increase in data rate • no need to match data rates • congestion reduction • multiple access by broadcast VICTORIES Project, AIST Japan 10 Package evolution: tighter integration Chip on Carrier or MCM Assembly Verdiell, Samtec, Inc. Silicon Interposer 3D Assembly Scaling cycles for System-in-Package electronic-photonic synergy 11 Integrated Silicon Microphotonics manufacturing and performance Scaling with a standard, modular platform: • increases: yield, reliability, density • reduces: cost, time to market, power, latency 12 Commercial Entry of Silicon Photonics Board-level photonic interconnection: 2017 Interconnect Time Reach BW BW Density Energy Frame (G/cm2) (pJ/bit) Rack ~2000 20-100m 40-200 G ~100 1000 à 200 Chassis ~2005 2-4 m 20-100 G ~100-400 400 à 50 Backplane ~2010 1-2 m 100-400 G ~400 100 à 25 Board ~2017 .01-1 m 0.3 – 1T ~1250 25 à 5 Module ~2020 1-10 cm 1 – 4 T >10000 1 à .1 Chip ~2025 0.1-3 cm 2-20T >40000 .1à.01 § Initial penetration is in HPC and Core Routers, then to Datacenters § Factors of speed, energy, density come together for optical solution at board level. CTR III TWG Report, Semicon West (2013), Roe Hemenway, Photonic Controls 13 Strategy: Photons Closer to the Chip 14 MIT Converged E-P Chip Package BGA electronic + edge optical pin Single-mode fiber with 0.25 mm pitch Up to 80 WDM optical pins per edge for a 2 cm × 2 cm chip High Bandwidth Packaging BGA Power and I/O Allocation htt p:/ / m ph - ro ad m ap .mi t.e du Vertically Integrated Firms no longer exist Consortia and Open Source Platform Standardization Majorca@MIT: Massimiliano Salsi, Juniper 17 The IPSR OBO Project • Quantify performance of SiPh-based on-board interconnect. Understand BER vs data rate with n-connector daisy chains. Understand power dissipation trade-offs Understand compatibility with Telcordia GR-1435, IEC-60529, IP5X/IP6X Understand relative issues in SiPh vs VCSEL implementations • Understanding design tradeoff in SiPh-based on-board interconnect system. Understand impact of EP connectors on power budget. Understand impact of molded plastic optics at ~ 1550 nm WDM wavelengths Understand impact of EP connectors on temp, humidity, vibration stability Understand impact of EP connectors on dust tolerance. Understand cost benefit of relaxed mechanical tolerances of EP connectors Improve understanding of pigtailed vs connectorized module trade-offs. Improve understanding of fly-over vs PCB-embedded optical media trade-offs. 18 Current IPSR OBO Project Participants • 3M-Terry Smith (Proposal Co-Leader) • 3MTS • Corning • Celestica • MACOM • Molex • Promex Industries • US Conec • US Competitors-John MacWilliams (Proposal Co-Leader) 19 Manufacturing Grand Challenges Industry-wide adoption of scalable platform(s) r Standardization: materials, design, packaging, functionality r Performance: defined by cost and system requirements r Platform tradeoffs: supporting cross-market applications Scaling Cost r simplicity, integration, packaging and production volume r known good die, photonic test, reliability and redundancy r 2020 target: Si transceiver chip <$0.01/Gb/s (excluding laser) Scaling Power-per-Function r reduce functional latency with ASIC/receiver/photonics co-design r employ self-aware, self-regulating circuits and networks r scale speed with parallelism; network reconfiguration, bulk flows Scaling Bandwidth Density r scale data rate; I/O port count; spectral bandwidth More detailed guidance is available in the IPSR Roadmap document and in the scheduled TWG meetings. 20 Electronic Photonic Design Automation Compatibility: digital/analog CAD tools and design rules § validated PDK models for photonic circuits § models for hybrid ASIC-on-optical interposer § compatibility with evolution of SM, DP, multilevel coding, ... § foundry infrastructure: IP licensing/indemnification • look-up database; licensing fees Performance scaling path § validated PDK models for electronic-photonic circuits § validated chip-level thermo-mechanical models § validated package-level thermo-mechanical models § single electronic-photonic IC/package design platform Integrated Photonic Systems Roadmap 2016 21 Test, Assembly, and Optical Packaging Minimize Part Count and Assembly Steps: Integration § Replacement for fiber pigtails § Improved design and process tool software § Comprehensive material properties data base § Low cost: on-chip/off-chip and on-board parallelism § Performance/cost tradeoffs: SM/CWDM, cable/backplane § Board substrate/waveguide: rigid/flex/fly-over/embedded § “Optical Pin” connector for package-to-board § Aggregate data rates of 5-128 Tb/s/chip § Scale system packaging architecture: CPU/ASIC to I/O Integrated Photonic Systems Roadmap 2016 22 Test, Assembly, and Optical Packaging Leverage electronics investment in complex 3D-SiP § design and simulation tools for heterogeneous integration § low cost electronic/photonic package substrates § increased parallelism in manufacturing processes § supply chain for low cost package production Reliability and Redundancy § known failure modes § standard hermetic and thermal test under operation § fault tolerant design § built-in self-test Integrated Photonic Systems Roadmap 2016 23 Test, Assembly, and Optical Packaging Heterogeneous SM functional blocks: minimal assembly § sub-micron tolerances with rigid mechanical stability § dimensional consistency of parts § fiducially registered parts High Throughput Assembly § fast curing adhesives § compatible electronic/photonic bonding processes § assembly equipment: 0.05 micron, 6 dimension accuracy r Rapid set up § low cost, high accuracy parts supply chain Integrated Photonic Systems Roadmap 2016 24 Silicon Microphotonics § The transceiver is the near term driver for silicon microphotonics. § Silicon is the only material platform capable of supporting a standard cross-market, high-volume transceiver in the long term. § A WDM standard of ~25Gb/s per channel will optimize the tradeoff between power efficiency and aggregate bandwidth density. § An independent optical power supply will be the dominant architecture in the near term. CTR II TWG Report, 2009 25 Interconnection and Packaging § Optical pins will be needed within the next decade to address EMI and pin count issues. § WDM will be necessary to meet off-chip bandwidth needs by 2020: single-mode,
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