applied sciences

Review Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

Lee Carroll *, Jun-Su Lee, Carmelo Scarcella, Kamil Gradkowski, Matthieu Duperron, Huihui Lu, Yan Zhao, Cormac Eason, Padraic Morrissey, Marc Rensing, Sean Collins, How Yuan Hwang and Peter O’Brien

Photonic Packaging Group, Tyndall National Institute, Lee Maltings Complex, Cork T12R5CP, Ireland; [email protected] (J.-S.L.); [email protected] (C.S.); [email protected] (K.G.); [email protected] (M.D.); [email protected] (H.L.); [email protected] (Y.Z.); [email protected] (C.E.); [email protected] (P.M.); [email protected] (M.R.); [email protected] (S.C.); [email protected] (H.Y.H.); [email protected] (P.O’B.) * Correspondence: [email protected]; Tel.: +353-21-234-6434

Academic Editor: Paolo Minzioni Received: 7 November 2016; Accepted: 5 December 2016; Published: 15 December 2016

Abstract: Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

Keywords: photonics packaging; silicon photonics; integrated optics; optoelectronics; photonic integrated circuits (PICs)

1. Introduction The last decade has seen Si-photonics promoted as a platform for potentially revolutionary advances in the fields of Telecommunications, Data Communications, Medical Technology, Security, and Sensing [1–3]. The main driving force behind Si-photonics is the potential to realize small, highly integrated, photonic sub-systems that leverage off the decades of fabrication experience, technology, and scalability already developed for CMOS (complementary metal-oxide semiconductor) electronics [4]. Ultimately, the goal is the development of low-cost high-volume photonic integrated circuits (PICs) with integrated electronics, to simultaneously access the full potential of the silicon platform—i.e., Si-photonics for high-speed signaling and sensing, and CMOS-electronics for subsequent logical operations and computations [5]. An impressive array of Si-photonic elements has been demonstrated by researchers, and are now available as qualified ‘building blocks’ in the multi-project wafer (MPW) runs offered by several silicon foundries [6–8]. These include one-dimensional (1D) and two-dimensional (2D) grating-couplers, broadband edge-couplers, strip/rib waveguides and crossings, multi-mode-interference (MMI) splitters, echelon and arrayed waveguide (AWG) multiplexers/de-multiplexers, thermally-tunable

Appl. Sci. 2016, 6, 426; doi:10.3390/app6120426 www.mdpi.com/journal/applsci Appl. Sci. 2016, 6, 426 2 of 21 Appl. Sci. 2016, 6, 426 2 of 20 micro-ringtunable micro resonators,‐ring resonators, high-speed high Ge‐speed photodiodes, Ge photodiodes, thermo-optic thermo phase‐optic shifters, phase electro-absorption shifters, electro‐ modulatorsabsorption modulators (EAMs), etc. (EAMs), Literally etc. thousands Literally thousands of these photonic of these elements, photonic andelements, perhaps and dozens perhaps of simpledozens Si-PIC of simple (photonic Si‐PIC integrated (photonic circuit) integrated designs, circuit) can bedesigns, laid-out can on be the laid single‐out MPW on the ‘block’ single (usually MPW 10–30‘block’ mm (usually2) that 10–30 is typically mm2) used that byis typically academic used researchers by academic and small-to-medium researchers and enterprises small‐to‐medium (SMEs) asenterprises their test-bed (SMEs) for as photonic their test designs.‐bed for photonic However, designs. developing However, innovative developing PICs, innovative and demonstrating PICs, and theirdemonstrating functionality their in functionality a laboratory environment,in a laboratory either environment, on an optical-bench either on an or optical in a probe-station,‐bench or in isa onlyprobe the‐station, first step is only towards the first realizing step towards useful devices realizing that useful can attract devices investment that can attract and generate investment interest and andgenerate value interest in the market. and value Very in often, the market. the technical Very challenges often, the associatedtechnical withchallenges transferring associated an Si-PIC with fromtransferring the laboratory an Si‐PIC to afrom device the are laboratory underestimated, to a device or even are underestimated, completely overlooked or even at completely the Si-PIC designoverlooked phase, at leadingthe Si‐PIC to design significant phase, performance leading to penaltiessignificant and performance unnecessarily penalties high fabrication and unnecessarily costs in first-generationhigh fabrication prototypes. costs in first‐generation prototypes. ‘Photonic Packaging’ is the catch-allcatch‐all term used to describe the range of techniques and technical competencies needed to make the optical, electrical, thermal, mechanical (and sometimes chemical) connections between a a PIC PIC and and the the outside outside world world [9–12]. [9–12 ].While While Fiber Fiber-to-PIC‐to‐PIC coupling coupling is perhaps is perhaps the thebest best-known‐known aspect aspect of photonic of photonic packaging, packaging, the field the also field includes also includes the integration the integration of laser of‐chips, laser-chips, micro‐ micro-optics,optics, electronic electronic-chips,‐chips, and micro and‐fluidics micro-fluidics on PICs; onthe PICs;high‐speed the high-speed (25 Gbps) routing (25 Gbps) and routing impedance and‐ impedance-matchingmatching of transmission of transmission-lines‐lines from external from connectors external to the connectors microscopic to the photonic microscopic components photonic on componentsthe PIC; and onthe the efficient PIC; and thermal the efficient cooling thermal and thermal cooling‐stabilization and thermal-stabilization needed to keep needed the PIC to within keep the its PICoperational within its range—see operational Figures range—see 1 and Figures2. 1 and2. While satisfying satisfying any any one one of of these these photonic photonic packaging packaging requirement requirement can canbe trivial, be trivial, especially especially with withthe tools the toolsand resources and resources a laboratory a laboratory environment, environment, they can they be can difficult be difficult to realize to realizein a robust, in a robust,stand‐ stand-alonealone device device for prototyping for prototyping in the in thefield. field. This This is especially is especially the the case case in in more more advanced advanced photonic devices, where where there there is is the the simultaneous simultaneous need need for several for several different different varieties varieties of packaging, of packaging, i.e., multi i.e.,‐ multi-channelchannel Fiber‐ Fiber-to-PICto‐PIC coupling, coupling, a vertically a vertically integrated integrated driver driver-chip,‐chip, and a and high a‐ high-speedspeed connection, connection, and anda thermo a thermo-electric‐electric cooler cooler [12]. [To12]. ensure To ensure that thatthese these devices devices are fully are fully-functional‐functional when when fabricated fabricated and andassembled assembled requires requires the adoption the adoption of packaging of packaging design design rules rules (PDRs) (PDRs) up front, up front, at the at Si the‐PIC Si-PIC design design stage. stage.This article This article provides provides a review a review of the of thedifferent different optical, optical, electrical, electrical, and and thermal thermal considerations considerations for successful photonic packaging, as a PDR ‘primer’ that also highlights some current trends that are helping to scale packaging to commercial volumesvolumes ofof photonicphotonic devices.devices.

Figure 1.1. SchematicSchematic of of a Si-PICa Si‐PIC (photonic (photonic integrated integrated circuit) circuit) packaged packaged with with a multi-channel a multi‐channel quasi-planar quasi‐ coupledplanar coupled (QPC) fiber-array,(QPC) fiber a‐array, hybrid-integrated a hybrid‐integrated laser source laser basedsource on based a micro-optic on a micro bench‐optic (MOB), bench a(MOB), vertically a vertically integrated integrated electronic electronic integrated integrated circuit (EIC), circuit and (EIC), a thermo-electric and a thermo cooler.‐electric Electrical cooler. connectionsElectrical connections between between the PIC andthe PIC PCB and (printed PCB (printed circuit circuit board) board) are made are made by wire-bonds, by wire‐bonds, while while the connectionsthe connections between between the PICthe PIC and and EIC EIC are madeare made using using copper copper pillar pillar bumps bumps (CPBs). (CPBs). Appl. Sci. 2016, 6, 426 3 of 21 Appl. Sci. 2016, 6, 426 3 of 20

(a) (b)

(c)

(d)

Figure 2. ExamplesExamples of of packaged packaged photonic photonic modules; modules; ( (aa)) Single Single-channel‐channel PIC PIC with with side side-by-side‐by‐side electronic electronic integration; (b (b) )Optical Optical Network Network Unit Unit (ONU) (ONU) of the of FP7 the‐FABULOUS FP7-FABULOUS project; project; (c) Single (c)‐ Single-channelchannel in/out photonicin/out photonic module modulewith vertically with vertically integrated integrated electronic electronic chip; (d) chip;8‐Channel (d) 8-Channel Transceiver Transceiver for the FP7 for‐ PLAT4Mthe FP7-PLAT4M project. project.

2. Optical Packaging 2. Optical Packaging As an indirect‐gap semiconductor, Si offers very low direct‐gap recombination for diode‐laser As an indirect-gap semiconductor, Si offers very low direct-gap recombination for diode-laser emission. Therefore, the light signal needed to drive Si‐photonics must come from an external laser emission. Therefore, the light signal needed to drive Si-photonics must come from an external laser source, either indirectly (i.e., the fiber‐coupling of light from a discrete laser‐device), or directly (i.e., source, either indirectly (i.e., the fiber-coupling of light from a discrete laser-device), or directly (i.e., the the hybrid/heterogeneous integration of a III–V device/material on the Si‐PIC). Many applications hybrid/heterogeneous integration of a III–V device/material on the Si-PIC). Many applications exist for exist for both the indirect and direct coupling of laser light to the PIC, and each approach can be both the indirect and direct coupling of laser light to the PIC, and each approach can be further broken further broken down by the employed coupling scheme, i.e., grating‐coupling, edge‐coupling, down by the employed coupling scheme, i.e., grating-coupling, edge-coupling, evanescent-coupling, evanescent‐coupling, etc. Generally, Fiber‐to‐PIC coupling (indirect) is used for telecom and datacom etc. Generally, Fiber-to-PIC coupling (indirect) is used for telecom and datacom applications, because applications, because it allows for the transfer of information over fiber networks, while integrated it allows for the transfer of information over fiber networks, while integrated sources (direct) are used sources (direct) are used for security and sensing applications. for security and sensing applications.

2.1. Fiber Fiber-to-PIC‐to‐PIC Coupling The main challenge associated with transferring light between a telecom single-modesingle‐mode fiberfiber (SMF)(SMF) and the the typical typical waveguides waveguides on on a Si a‐PIC Si-PIC is the is large the large difference difference between between the mode the‐ mode-fieldfield diameter diameter (MFD) (MFD)of the two of the material two material systems. systems. At telecom At telecom wavelengths wavelengths (1260–1650 (1260–1650 nm), nm),the MFD the MFD in the in thefiber fiber is approximatelyis approximately 10 μ 10m µandm and circularly circularly symmetric, symmetric, while while in the inPIC the it is PIC typically it is typically elliptical elliptical and 0.5 × and 0.3 μ0.5m ×in 0.3sizeµ m[13]. in Consequently, size [13]. Consequently, in addition in to additionan order to of an magnitude order of difference magnitude in difference the mode in sizes the betweenmode sizes the between two waveguides, the two waveguides, there can also there be a can strong also polarization be a strong dependent polarization loss dependent (PDL), if lossthe (PDL),unknown if the and unknown unstable and direction unstable of directionthe electric of‐ thefield electric-field in the SMF in‐mode the SMF-mode does not align does notwith align the withfundamental the fundamental polarization polarization of the PIC of the waveguide PIC waveguide (usually (usually TE (transverse TE (transverse-electric)‐electric) for telecoms for telecoms and datacomsand datacoms applications, applications, and TM and (transverse TM (transverse-magnetic)‐magnetic) for sensing for sensing applications). applications). As a result, As a result, it is often it is necessaryoften necessary to implement to implement some some form form of ‘polarization of ‘polarization management’ management’ to to ensure ensure stable stable Fiber Fiber-to-PIC‐to‐PIC coupling—either directly in the coupler coupler-element‐element itself (as in the case of a 2D grating grating-coupler‐coupler [14]), [14]), or at a later stage in the PIC (such as a wave-guidewave‐guide element that filtersfilters and rotates the polarization as necessary [15]). [15]). As As more more fully fully described described in the in thefollowing following three three sub‐sections, sub-sections, there there are essentially are essentially three approachesthree approaches to Fiber to Fiber-to-PIC‐to‐PIC coupling—edge coupling—edge-coupling,‐coupling, grating grating-coupling,‐coupling, and and most most recently evanescentevanescent-coupling—each‐coupling—each having their own performance advantages and limitations, and so suiting particular photonic applications. A summary of the typical insertion insertion-loss,‐loss, bandwidth, and alignment tolerance for these different Fibre-to-PICFibre‐to‐PIC coupling approachesapproaches isis givengiven inin TableTable1 .1.

2.1.1. Edge‐Coupling Edge‐coupling is a well‐established approach for the commercial packaging of laser‐chips [16], but has not been widely adopted in the field of Si‐photonics, despite being able to deliver broadband, Appl. Sci. 2016, 6, 426 4 of 20 polarization‐agnostic insertion‐losses of better than −1 dB after careful alignment [17]. A typical edge‐ coupler for a Si‐PIC consists of an inverted taper (with a length of 100–300 μm) embedded in an integrated nitride‐based spot‐size‐converter (SSC), or a post‐process deposited polymer‐based SSC, to increase the effective MFD of the on‐PIC waveguide mode to approximately 3 × 3 μm [18,19]. This creates good modal‐overlap with either lensed SMF‐28 fibers or ultra‐high numerical aperture Appl.(UHNA) Sci. 2016 fibers, 6, 426 for Fiber‐to‐PIC coupling—see Figure 3. 4 of 21 Since the back‐end deposition and etching of a 3–5 μm SiON‐layer needed to create an integrated mode‐adapter has proven difficult to add as a standard building block (mainly because of the high 2.1.1. Edge-Coupling strain introduced to the wafers by the SiON layer), edge‐couplers are only slowly being introduced to theEdge-coupling MPW runs being is a offered well-established by the Si‐ approachPhotonic foundries. for the commercial Adding an packaging edge‐coupler of laser-chips onto a Si‐ [PIC16], alsobut has increases not been post widely‐fabrication adopted processing in the field costs, of Si-photonics, because it despite calls beingfor either able toaccurate deliver dicing broadband, and polarization-agnosticpolishing of the PIC edges, insertion-losses or an additional of better deep than‐etch− (>601 dB μ afterm) lithography careful alignment to create [ 17a high]. A‐quality typical facetedge-coupler for low for insertion a Si-PIC‐ consistslosses [6]. of an Deep inverted etching taper techniques (with a length can of 100–300even beµ m)taken embedded further, in anto simultaneouslyintegrated nitride-based create a facet spot-size-converter and v‐grove in (SSC), which or the a post-processfiber can be passively deposited aligned polymer-based with respect SSC, to theincrease on‐PIC the waveguides effective MFD [20]. of theThe on-PIC principle waveguide draw‐back mode of this to approximately approach is that 3 × the3 µ mv‐grooves [18,19]. Thiscan occupycreates gooda significant modal-overlap fraction with the Si either‐PIC lensedfootprint SMF-28 that would fibers orotherwise ultra-high be numerical available for aperture the active (UHNA) part offibers the forphotonic Fiber-to-PIC device. coupling—see Figure3.

Figure 3. FiberFiber-to-PIC‐to‐PIC edge edge-coupling;‐coupling; ( a) Kovar ‘butterfly’‘butterfly’ package for edge-coupling.edge‐coupling. Kovar has the same thermal expansion coefficient coefficient as glass, so the Fiber-to-PICFiber‐to‐PIC alignment can be maintained, when the ambientambient temperaturetemperature changes; changes; (b ()b Microscope) Microscope image image of anof edge-couplingan edge‐coupling to a III-Vto a laser-chipIII‐V laser using‐chip usinga lensed a lensed fiber. The fiber. fiber The is fiber mounted is mounted into a metal into a ferule, metal so ferule, it can so be it laser-welded can be laser‐ towelded the kovar to the butterfly kovar package;butterfly (package;c) Schematic (c) ofSchematic edge-coupling of edge to a‐coupling Si-PIC using to a lensed-fiberSi‐PIC using and a spot-sizelensed‐fiber converter and spot (SSC),‐size or convertermode-converter (SSC), (MC), or mode to help‐converter bridge (MC), the gap to between help bridge the mode-size the gap between in the fiber the and mode on-PIC‐size waveguide.in the fiber and on‐PIC waveguide. Since the back-end deposition and etching of a 3–5 µm SiON-layer needed to create an integrated Most often, edge‐coupling is carried‐out between a PIC and a lensed‐fiber. The lensing of the mode-adapter has proven difficult to add as a standard building block (mainly because of the high fiber facet creates a 3 μm diameter ‘hot‐spot’ of light that better matches the fiber‐mode to the MFD strain introduced to the wafers by the SiON layer), edge-couplers are only slowly being introduced to of the on‐PIC SSC. The 1 dB alignment tolerance for such an edge‐coupler is typically sub‐micron the MPW runs being offered by the Si-Photonic foundries. Adding an edge-coupler onto a Si-PIC also (approximately ±500 nm), and so requires careful active alignment to minimize insertion‐losses increases post-fabrication processing costs, because it calls for either accurate dicing and polishing of [18,19]. Given that this alignment tolerance is comparable to the fabrication tolerance of multi‐channel the PIC edges, or an additional deep-etch (>60 µm) lithography to create a high-quality facet for low fiber‐arrays, edge‐coupling is almost always applied only to single‐channel Fiber‐to‐PIC coupling. In insertion-losses [6]. Deep etching techniques can even be taken further, to simultaneously create a facet addition, laser‐welding of the lensed‐fiber (mounted in a metallic ferrule) and the PIC to a kovar and v-grove in which the fiber can be passively aligned with respect to the on-PIC waveguides [20]. package is usually necessary to ensure that the small displacements caused by thermal The principle draw-back of this approach is that the v-grooves can occupy a significant fraction the expansion/contraction do not impact the Fiber‐to‐PIC coupling (kovar is a Fe‐Ni‐Co alloy designed Si-PIC footprint that would otherwise be available for the active part of the photonic device. to have a thermal expansion coefficient that matches the glass in the fiber)—see Figure 3. In addition, Most often, edge-coupling is carried-out between a PIC and a lensed-fiber. The lensing of the this metal‐to‐metal bond is less prone to the small alignment‐drift that sometimes occurs in epoxy‐ fiber facet creates a 3 µm diameter ‘hot-spot’ of light that better matches the fiber-mode to the MFD bonds due to age or environmental effects [16]. Clearly, the alignment tolerance and material of the on-PIC SSC. The 1 dB alignment tolerance for such an edge-coupler is typically sub-micron requirements of current state‐of‐the‐art edge‐coupling are too high to credibly satisfy medium‐to‐ (approximately ±500 nm), and so requires careful active alignment to minimize insertion-losses [18,19]. high volumes (106–107 devices per year). Given that this alignment tolerance is comparable to the fabrication tolerance of multi-channel fiber-arrays, edge-coupling is almost always applied only to single-channel Fiber-to-PIC coupling. In addition, laser-welding of the lensed-fiber (mounted in a metallic ferrule) and the PIC to a kovar package is usually necessary to ensure that the small displacements caused by thermal expansion/contraction do not impact the Fiber-to-PIC coupling (kovar is a Fe-Ni-Co alloy designed to have a thermal expansion coefficient that matches the glass in the fiber)—see Figure3. In addition, this metal-to-metal bond is less prone to the small alignment-drift that sometimes occurs in epoxy-bonds Appl. Sci. 2016, 6, 426 5 of 21 due to age or environmental effects [16]. Clearly, the alignment tolerance and material requirements of current state-of-the-art edge-coupling are too high to credibly satisfy medium-to-high volumes (106–107 devices per year). Edge-coupling is often used for non-linear applications in Si-photonics, where high optical powers (on the order of 1 W) are needed to drive four-wave mixing and other non-linear interactions. The broadband nature of the edge-coupler means that the relative strengths of the pump, signal and idler channels can be measured accurately (because all three wavelengths experience the same insertion-loss), and this allows the non-linear conversion efficiencies to be calculated precisely. To prevent damage to the mode-adapter, modules for non-linear applications with edge-couplers must be fabricated in a hermetically sealed package. Otherwise, the electric-field gradient of the ‘hot-spot’ formed by the high optical power being focused by the lensed fiber can result in an optical tweezer effect that attracts micro-particles and organic contaminants in the air to the facet of the mode-adapter. If these contaminants absorb a significant fraction of the optical-power, then it can give rise to a catastrophic failure of the mode-adapter, due to localized heating of the facet. Such failures are more common for SU-8 and PMMA mode-adapters, rather than for integrated SiON mode-adapters, because the dielectric material is more resistant to thermal decomposition than the polymer photoresists. A number of research groups and companies are working to develop schemes that reduce the alignment tolerance of edge-coupling [21,22]. The aim is to relax the alignment tolerance (or strengthen the fabrication tolerance [23]) to a level that supports multi-channel edge-coupling for telecom and datacom applications. This activity is motivated by the lower insertion losses and more broadband coupling that would be offered by these edge-coupler arrays, compared to the current (dominant) alternative of grating-coupler arrays. The losses and bandwidth of current MPW grating-couplers are routinely identified by companies and standardization bodies as significant barriers to the commercial adoption of photonic devices.

2.1.2. Grating-Coupling The most common alternative to edge-coupling is grating-coupling, where a sub-µm periodic structure is lithographically etched into the waveguide-layer of the PIC, to create a coherent interference condition that diffractively couples the fiber-mode into the PIC waveguide [24,25]—see Figure4. The 10 × 10 µm footprint of the grating-coupler is chosen to match the 8–10 µm MFD of a standard telecom fiber, and consists of a (periodic) array of ≈20 trenches partially-etched into the 220 nm Si-layer [12]. A simple relation exists between the peak wavelength of the coupler (λ), the pitch of the trenches (P), the effective index of the grating-coupler region (ne), the index of the oxide-layer (no), and the angle-of-incidence (θ) of the fiber-mode: λ = P (ne – no sin θ), where the value of ne is determined by the etch-depth and duty-cycle of the trenches, as well as the polarization of the fiber-mode. Typically, a near-normal angle-of-incidence (θ ≈ 10◦) is used, to provide directionality to the coupled-mode, and to reduce back-reflections into the fiber. However, from a packaging perspective, Fiber-to-PIC coupling at near-normal incidence—i.e., ‘pigtailing’—can lead to a bulky device with poor mechanical performance. To address this issue, a ‘quasi-planar’ approach has been developed for Fiber-to-PIC coupling, where the fiber facet is polished to ≈40◦ to create a total internal reflection condition the directs the fiber-mode onto the grating-coupler at the correct angle of 10◦ [26,27]—see Figure5. This geometry creates an almost ‘2D’ package in which it is easier to respect the minimum-turn-radius of the telecom fibers (≈5 cm), while maintaining a reasonable device footprint. Appl. Sci.Appl.2016 Sci. ,20166, 426, 6, 426 6 of 20 6 of 21 Appl. Sci. 2016, 6, 426 6 of 20

FigureFigure 4. Fiber-to-PIC 4. Fiber‐to‐PIC grating-coupling; grating‐coupling; (a) Side-view(a) Side‐view schematic schematic of aof silicon-on-insulator a silicon‐on‐insulator (SOI) (SOI) grating- coupler,gratingFigure with ‐coupler,4. a Fiber 2 µm ‐withto bottom-oxide‐PIC a 2 μgratingm bottom‐coupling; (BOX)‐oxide layer. (BOX)(a) TheSide layer.‐≈view10 Theµ schematicm ≈10 MFD μm MFD (mode-field of a(mode silicon‐field diameter)‐on ‐diameter)insulator fiber-mode fiber(SOI)‐ is mode is incident on the grating‐coupler with a ≈10° angle‐of‐incidence; (b) Top‐view schematic of a incidentgrating on the‐coupler, grating-coupler with a 2 μm withbottoma ≈‐oxide10◦ angle-of-incidence; (BOX) layer. The ≈10 μ (bm) Top-view MFD (mode schematic‐field diameter) of a 1D fiber focusing‐ 1D focusing grating‐coupler. The footprint of the coupler matches the MFD of the fiber‐mode; (c,d) grating-coupler.mode is incident The on footprint the grating of‐ thecoupler coupler with matchesa ≈10° angle the‐of MFD‐incidence; of the (b fiber-mode;) Top‐view schematic (c,d) Microscope of a Microscope1D focusing images grating of‐coupler. one‐dimensional The footprint (1D) andof the two coupler‐dimensional matches (2D) the grating MFD of‐couplers, the fiber respectively.‐mode; (c,d) images of one-dimensional (1D) and two-dimensional (2D) grating-couplers, respectively. Microscope images of one‐dimensional (1D) and two‐dimensional (2D) grating‐couplers, respectively.

Figure 5. Quasi‐planar Coupling (QPC) geometry to allow for the ‘horizontal’ Fiber‐to‐PIC grating‐ coupling;Figure 5. (Quasia) Single‐planar‐channel Coupling in/out (QPC) QPC fiber geometry‐coupling to allow to a Si for‐PIC, the with ‘horizontal’ an inset showingFiber‐to‐ PICa schematic grating‐ Figure 5. Quasi-planar Coupling (QPC) geometry to allow for the ‘horizontal’ Fiber-to-PIC grating- ofcoupling; the polished (a) Single fiber‐ channelfacet; (b )in/out QPC fiberQPC‐ fibercoupling‐coupling using to a amulti Si‐PIC,‐channel with anfiber inset‐array. showing a schematic coupling;of the ( apolished) Single-channel fiber facet; in/out (b) QPC QPC fiber fiber-coupling‐coupling using to a multi a Si-PIC,‐channel with fiber an‐ insetarray. showing a schematic of theGrating polished couplers fiber facet; offer (b significantly) QPC fiber-coupling more relaxed using aalignment multi-channel tolerance fiber-array. than an edge‐coupler, typicallyGrating ±2.5 μcouplersm of in‐ planeoffer misalignmentsignificantly more for a 1dBrelaxed penalty alignment [13]. Grating tolerance‐couplers than can an alsoedge be‐coupler, placed at any point on the PIC surface, not just at the edge of the chip, do not require any post‐processing Gratingtypically ±2.5 couplers μm of in offer‐plane significantly misalignment more for a 1dB relaxed penalty alignment [13]. Grating tolerance‐couplers than can also an edge-coupler,be placed steps, such as precision dicing and polishing of the PIC, thereby facilitating wafer‐scale testing and typicallyat any± point2.5 µ onm the of in-planePIC surface, misalignment not just at the for edge a of 1 the dB chip, penalty do not [13 require]. Grating-couplers any post‐processing can also characterizationsteps, such as precision of PIC dicingbefore and dicing polishing and packaging.of the PIC, therebyHowever, facilitating until recently, wafer‐scale these testing practical and be placed at any point on the PIC surface, not just at the edge of the chip, do not require any advantagescharacterization have beenof PIC somewhat before dicingoffset byand minimum packaging. insertion However,‐losses untilthat are recently, higher thanthese those practical that post-processingcanadvantages be achieved steps,have demonstratedbeen such somewhat as precision by offset edge dicing by‐couplers. minimum and polishing Fortunately, insertion of‐ thelossesrecent PIC, that advances thereby are higher facilitatingin grating than those‐coupler wafer-scale that testingdesigncan and be characterizationhaveachieved started demonstrated to close of PIC this beforeby performance edge dicing‐couplers. andgap, Fortunately, packaging. with reports However,recent of 1.6 advances dB until and recently, 1.2in gratingdB (measured) these‐coupler practical advantagesinsertiondesign have‐losses beenstarted from somewhat touniform close this offsetand performance apodized by minimum grating gap, insertion-losses with‐couplers reports in theof that1.6 silicon dB are and‐ higheron‐ insulator1.2 dB than (measured) thoseplatform that can be achieved[28,29].insertion More demonstrated‐losses advanced, from uniform though by edge-couplers. andless commerciallyapodized Fortunately, grating‐scalable‐couplers grating recent in‐ advancescouplerthe silicon designs, in‐on grating-coupler‐insulator where a platformmetallic design haveback[28,29]. started‐reflector More to close advanced,layer this is performance added though in lessa post gap, commercially‐processing with reports‐scalable step, of 1.6allows grating dB andfor‐coupler insertion 1.2 dB designs, (measured)‐losses where of 0.6 insertion-losses a dB metallic [30], fromshowingback uniform‐reflector that and bestlayer apodized‐in is‐class added grating grating-couplers in a‐ couplerspost‐processing offer in the the step, same silicon-on-insulator allows level forof performanceinsertion‐losses platform as theof 0.6 best [28 dB, 29edge [30],].‐ More couplers, while still offering relatively relaxed alignment tolerances. advanced,showing though that best less‐in commercially-scalable‐class grating‐couplers grating-coupleroffer the same level designs, of performance where a metallic as the best back-reflector edge‐ couplers,Standard, while or still ‘1D’ offering grating relatively‐couplers relaxed usually alignment exhibit a tolerances.strong polarization sensitivity, which can layer is added in a post-processing step, allows for insertion-losses of 0.6 dB [30], showing that makeStandard, them unsuitable or ‘1D’ grating telecom‐couplers and datacom usually exhibitconnections, a strong due polarization to the unknown sensitivity, and which unstable can best-in-class grating-couplers offer the same level of performance as the best edge-couplers, while still polarizationmake them stateunsuitable from telecom telecom fibers. and Onedatacom solution connections, is 2D grating due‐ coupler,to the unknownwhich is formed and unstable by the offeringsuperpositionpolarization relatively state of relaxed two from orthogonally alignmenttelecom fibers. orientated tolerances. One solution 1D grating is 2D‐couplers, grating‐ coupler,and can whichaccept isa formedfiber‐mode by theof anyStandard,superposition polarization or ‘1D’ of‐ state,two grating-couplers orthogonallydiffracting it intoorientated usually a pair exhibit of1D on grating‐PIC a strong waveguides‐couplers, polarization andthat canare sensitivity, bothaccept TE a‐polarized fiber which‐mode [31]. can of make themRecentany unsuitable polarization work on telecom 2D‐state, grating anddiffracting‐coupler datacom it optimization into connections, a pair of for on ‐SiPIC due‐photonics waveguides to the has unknown predictedthat are and both insertion unstable TE‐polarized losses polarization of [31]. 1.0 stateRecent from telecom work on fibers. 2D grating One‐coupler solution optimization is 2D grating-coupler, for Si‐photonics which has predicted is formed insertion by the superposition losses of 1.0 of two orthogonally orientated 1D grating-couplers, and can accept a fiber-mode of any polarization-state, diffracting it into a pair of on-PIC waveguides that are both TE-polarized [31]. Recent work on 2D Appl. Sci. 2016, 6, 426 7 of 20 Appl. Sci. 2016, 6, 426 7 of 21

dB and 2.0 dB for designs with and without back‐reflectors and polarization dependent losses as low grating-coupleras 0.3 dB [32,33]. optimization for Si-photonics has predicted insertion losses of 1.0 dB and 2.0 dB for designsFor with many and telecom without and back-reflectors datacom applications, and polarization it is useful dependent to have losses multiple as low channels as 0.3 packaged dB [32,33]. to the Forsame many PIC, telecom with current and datacom projects applications, targeting even it is useful 128 and to have 256 multiplechannels. channels Instead packaged of aligning to theindividual same PIC, channels, with current it is possible projects targetingto use an even ‘optical 128 shunt’ and 256 to channels. simultaneously Instead align of aligning each fiber individual with a channels,matching it grating is possible‐coupler to use [34]. an In ‘optical this approach, shunt’ to a precision simultaneously fiber‐array align is each constructed, fiber with consisting a matching of a grating-couplerglass‐plate in which [34]. In a thisseries approach, of parallel a precision v‐groves fiber-array are precision is constructed,‐etched, typically consisting with of a a pitch glass-plate of 127 inμm which or 250 a series μm, to of match parallel the v-groves diameter are of precision-etched, standard telecom typically fibers, and with a aflat pitch glass of 127‘lid’—seeµm or Figure 250 µm, 6. toOnce match the the fibers diameter are inserted of standard into the telecom v‐groove fibers, channels, and a flat and glass the ‘lid’—see lid is applied, Figure the6. Oncethree‐ thepoint fibers‐contact are insertedcondition into ensures the v-groove the precise channels, position and and the spacing lid is applied, of the different the three-point-contact channels. The conditionnominal centricity ensures theof the precise inner position‐cores of and the spacing fibers in of these the different fiber‐arrays channels. is ±0.5 The μm, nominal which is centricity well within of the the inner-cores ±2.5 μm 1 ofdB thealignment fibers in tolerance these fiber-arrays of the grating is ±0.5‐couplers.µm, which Therefore, is well within when thethe± first2.5 µandm 1 last dB alignmentgrating‐couplers tolerance are ofconnected the grating-couplers. by a shunt waveguide, Therefore, a when single the active first alignment and last grating-couplers of the fiber‐array are that connected maximizes by the a shunt shunt waveguide,transmission a singlealso aligns active all alignment intermediate of the fiber fiber-array‐channels thatwith maximizes respect to their the shunt grating transmission‐couplers (with also a aligns±0.5 μ allm intermediatetolerance). Once fiber-channels the single‐ withor multiple respect‐channel to their grating-couplers Fiber‐to‐PIC alignment (with a ±has0.5 beenµm tolerance).made, it is Oncelocked the into single- place or using multiple-channel a low‐shrinkage Fiber-to-PIC index‐matched alignment ultraviolet has been (UV) made,‐cured it epoxy. is locked into place using a low-shrinkage index-matched ultraviolet (UV)-cured epoxy.

Figure 6. Optical shunt to support the active‐alignment of a multi‐channel fiber‐array to a Si‐PIC; (a) Figure 6. Optical shunt to support the active-alignment of a multi-channel fiber-array to a Si-PIC; Microscope image of an optical‐shunt and three intermediate couplers—2 × 1D grating‐couplers, and (a) Microscope image of an optical-shunt and three intermediate couplers—2 × 1D grating-couplers, 1 × 2D grating‐coupler); (b) Schematic of a multi‐channel fiber‐array showing how three‐point contact and 1 × 2D grating-coupler); (b) Schematic of a multi-channel fiber-array showing how three-point allows for precise alignment of the fibers in the v‐grooves; (c) The transmission spectrum of the contact allows for precise alignment of the fibers in the v-grooves; (c) The transmission spectrum of theoptical optical-shunt,‐shunt, showing showing the the bandwidth bandwidth of of the the grating grating-couplers.‐couplers. As As the the shunt shunt is symmetricsymmetric andand has has negligiblenegligible waveguide-losses, waveguide‐losses, thethe insertion-loss insertion‐loss (IL)(IL) inin units units of of dB dB is is simply simply half half of of the the optical-shunt optical‐shunt transmissiontransmission in in units units of of dB. dB.

Although shunt alignment helps reduce the per‐channel cost of Fiber‐to‐PIC packaging, it still Although shunt alignment helps reduce the per-channel cost of Fiber-to-PIC packaging, it still involves a single active‐alignment step, while a credible route to scalable packaging calls for a passive involves a single active-alignment step, while a credible route to scalable packaging calls for a passive Fiber‐to‐PIC alignment scheme. The recent demonstration of ‘flip‐chip’ Fiber‐to‐PIC alignment is one Fiber-to-PIC alignment scheme. The recent demonstration of ‘flip-chip’ Fiber-to-PIC alignment is one promising approach [35]. Here, a beam‐splitter system is used to visually align the inner‐cores in a promising approach [35]. Here, a beam-splitter system is used to visually align the inner-cores in fiber‐array to the matching grating‐couplers on a PIC, with a tolerance of ±1 μm, without active a fiber-array to the matching grating-couplers on a PIC, with a tolerance of ±1 µm, without active alignment. Since this is within the 1dB alignment tolerance of the grating‐couplers, this approach still alignment. Since this is within the 1 dB alignment tolerance of the grating-couplers, this approach offers low insertion‐loss, but is at least one order of magnitude faster than active alignment. still offers low insertion-loss, but is at least one order of magnitude faster than active alignment. Alternative schemes for passive alignment involving large‐footprint (30 μm × 30 μm) grating‐ Alternative schemes for passive alignment involving large-footprint (30 µm × 30 µm) grating-couplers couplers that offer relaxed 1dB alignment tolerances of ±10 μm are also under investigation. Here, that offer relaxed 1 dB alignment tolerances of ±10 µm are also under investigation. Here, the principle the principle drawback is a reduction in the spectral bandwidth, which can exclude this approach for drawback is a reduction in the spectral bandwidth, which can exclude this approach for wavelength wavelength division multiplexing applications. division multiplexing applications.

Appl. Sci. 2016, 6, 426 8 of 20 Appl. Sci. 2016, 6, 426 8 of 21 2.1.3. Evanescent‐Coupling 2.1.3.A Evanescent-Coupling new approach to Fiber‐to‐PIC coupling, termed ‘evanescent coupling’ was first applied to Si‐ PhotonicsA new by approach IBM‐Zurich to Fiber-to-PICin 2015 [36]. In coupling, this scheme, termed as in ‘evanescent edge‐coupling, coupling’ an inverted was first‐taper applied is used to toSi-Photonics efficiently extract by IBM-Zurich the mode in from 2015 the [36 ].PIC In waveguide. this scheme, However, as in edge-coupling, instead of being an inverted-taper captured by an is onused‐PIC to SSC, efficiently the mode extract evanescently the mode fromcouples the into PIC a waveguide. second waveguide However, on insteada different of being optical captured‐chip, that by isan in on-PIC very close SSC, face the‐ modeto‐face evanescently proximity with couples the PIC—see into a second Figure waveguide 7. The refractive on a different index and optical-chip, MFD on thethat optical is in very‐chip close can then face-to-face be easily proximity matched to with that the of PIC—seestandard SMF Figure fibers,7. The allowing refractive for indexa two‐ andstep (FiberMFD‐ onChip the‐PIC) optical-chip coupling can process. then be Currently, easily matched chip‐ to‐ thatchip ofevanescent standard SMFcoupling fibers, has allowing only been for a demonstratedtwo-step (Fiber-Chip-PIC) between a Si coupling‐PIC and process. a polymer Currently,‐based chip-to-chipoptical‐chip, evanescent but there is coupling no clear has reason only why been thisdemonstrated approach betweencannot be a Si-PICtransferred and a to polymer-based glass‐ or SiON optical-chip,‐based optical but‐chips there isfor no more clear robust reason photonic why this devices.approach cannot be transferred to glass- or SiON-based optical-chips for more robust photonic devices.

Figure 7. Evanescent coupling from an optical-chip to a Si-PIC; (a) Schematic of the evanescent coupling Figurescheme, 7. showing Evanescent the inverted-tapercoupling from onan theoptical Si-PIC‐chip and to the a Si wave-guiding‐PIC; (a) Schematic region of thethe optical-chipevanescent coupling(high-index scheme, polymer showing core the surrounded inverted‐taper by a on low-index the Si‐PIC polymer and the wave cladding);‐guiding (b )region Mode of propagation the optical‐ chipand 3D-FDTD(high‐index (finite polymer difference core surrounded time domain) by a simulations low‐index polymer illustrate cladding); the transfer (b) of Mode light propagation between the andoptical-chip 3D‐FDTD and (finite Si-PIC. difference time domain) simulations illustrate the transfer of light between the optical‐chip and Si‐PIC. Evanescent coupling is attractive, because it offers all the characteristic advantages of Evanescent coupling is attractive, because it offers all the characteristic advantages of edge‐ edge-coupling, such as low insertion-loss, broadband coupling, and low sensitivity to polarization, coupling, such as low insertion‐loss, broadband coupling, and low sensitivity to polarization, as well as well as the relaxed alignment tolerances typical of grating-coupling [36]. Additionally, unlike as the relaxed alignment tolerances typical of grating‐coupling [36]. Additionally, unlike edge‐ edge-coupling, the inverted-taper of the evanescent coupler does not need to be located at the edge of coupling, the inverted‐taper of the evanescent coupler does not need to be located at the edge of the the PIC, and does not depend on precision dicing and polishing of the PIC edges, further reducing its PIC, and does not depend on precision dicing and polishing of the PIC edges, further reducing its cost to implement at volume. cost to implement at volume. 2.2. Laser-to-PIC Integration 2.2. Laser‐to‐PIC Integration For many sensing applications in photonics, it is desirable to locally generate either a continuous For many sensing applications in photonics, it is desirable to locally generate either a continuous wave or modulated light signal on the Si-PIC. Since there is no monolithically integrable laser-diode wave or modulated light signal on the Si‐PIC. Since there is no monolithically integrable laser‐diode available for CMOS, this necessitates either (i) the heterogeneous integration of III–V material on the available for CMOS, this necessitates either (i) the heterogeneous integration of III–V material on the Si-PIC; or (ii) the hybrid integration of a III–V device on the Si-PIC. Si‐PIC; or (ii) the hybrid integration of a III–V device on the Si‐PIC. Heterogeneous integration refers to the bonding of III-V material with optical gain onto the Si-PIC Heterogeneous integration refers to the bonding of III‐V material with optical gain onto the Si‐ (either directly or with an intermediate polymer adhesive layer), followed by the etching of material to PIC (either directly or with an intermediate polymer adhesive layer), followed by the etching of create a cavity condition for lasing. The cavity can be formed between two etched facets, two Bragg material to create a cavity condition for lasing. The cavity can be formed between two etched facets, reflectors, or with a micro-ring, depending on the application [37,38]. The resulting laser emission is two Bragg reflectors, or with a micro‐ring, depending on the application [37,38]. The resulting laser then evanescently coupled into the on-PIC waveguide. Heterogeneous integration can be regarded emission is then evanescently coupled into the on‐PIC waveguide. Heterogeneous integration can be as a post-processing step, rather than photonic packaging, and is often used to create semiconductor regarded as a post‐processing step, rather than photonic packaging, and is often used to create amplifiers (SOAs), which provide optical gain to offset the insertion-loses and waveguide losses on semiconductor amplifiers (SOAs), which provide optical gain to offset the insertion‐loses and the Si-PIC [39]—see Figure8. The optical gain from these integrated SOAs has a strong (Arrhenius) waveguide losses on the Si‐PIC [39]—see Figure 8. The optical gain from these integrated SOAs has thermal dependence, and so requires temperature stabilization for stable performance. a strong (Arrhenius) thermal dependence, and so requires temperature stabilization for stable performance. Appl. Sci. 2016, 6, 426 9 of 21 Appl. Sci. 2016, 6, 426 9 of 20

HybridHybrid integration integration involves involves the the coupling coupling of of light light from from a discrete a discrete III-V III laser‐V laser device device onto onto the Si-PIC,the Si‐ eitherPIC, either directly directly or by using or by a µ usingOpto-Electro-Mechanical a μOpto‐Electro‐Mechanical (µOEM) stage. (μOEM) Hybrid stage. integration Hybrid schemes integration tend toschemes have lower tend integration to have lower densities integration than heterogeneous densities than integration heterogeneous schemes, integration but have schemes, the advantage but have of deployingthe advantage only of ‘known deploying good only devices’, ‘known which good leads devices’, to higher which yields leads and tighterto higher performance yields and profiles. tighter Twoperformance promising profiles. hybrid laserTwo promising integration hybrid schemes laser are theintegration micro-optical schemes bench, are andthe micro direct‐ verticaloptical bench, cavity surfaceand direct emitting vertical laser cavity (VCSEL) surface integration. emitting laser (VCSEL) integration.

FigureFigure 8.8. III–V semiconductor optical amplifiers amplifiers (SOAs) integrated on a Si-PIC;Si‐PIC; (a) ImageImage ofof aa packagedpackaged SOA module, with with Fiber Fiber-to-PIC‐to‐PIC grating grating-coupling‐coupling of of the the input input and and output output channels channels in the in theQPC QPC configuration, configuration, to toevaluate evaluate the the optical optical gain gain of of the the SOA; SOA; (b (b) )Microscope Microscope image image of the packagedpackaged SOASOA showingshowing thethe QPCQPC Fiber-to-PICFiber‐to‐PIC coupling,coupling, andand thethe thermistorthermistor usedused toto provideprovide feedbackfeedback forfor thethe integratedintegrated thermo-electricthermo‐electric coolercooler (TEC)(TEC) mounted mounted under under the the PIC. PIC.

TableTable 1. 1.Typical Typical insertion insertion loss, loss, bandwidth, bandwidth, polarizationpolarization sensitivity,sensitivity, alignmentalignment tolerances,tolerances, andand MPWMPW (multi-project(multi‐project wafer) wafer) availability availability for for different different Fiber-to-PIC Fiber‐to‐PIC (photonic (photonic integrated integrated circuits) circuits) couplers. couplers.

InsertionInsertion 11 dB dB Polarization 1dB Alignment CouplerCoupler Type Type 1 dB Alignment ToleranceMPW MPW Availability Availability LossLoss BandwidthBandwidth Sensitivity Tolerance ±2.5 μm (in‐plane) [13] & 1D‐GC 1 1.6dB [28] 40 nm [13] TE 1/TM 1 ±2.5 µm (in-plane) [13]& CEA‐Leti &Imec 1D-GC 1 1.6 dB [28] 40 nm [13] TE 1/TM 1 CEA-Leti &Imec 1010 μmµm (out (out-of-plane)‐of‐plane) [26] [26] 2D‐GC 1 3.2dB [32] 35 nm [32] TE & TM ±2.5 μm (in‐plane) [32] CEA‐Leti & Imec 2D-GC 1 3.2 dB [32] 35 nm [32] TE & TM ±2.5 µm (in-plane) [32] CEA-Leti & Imec 200 nm TE & Edge Coupler 1.2dB [17] 200 nm TE & TE & TM ±0.5 μm (in‐plane) [17] Imec (taper only) Edge Coupler 1.2 dB [17] 150 nm TM [17] TE & TM ±0.5 µm (in-plane) [17] Imec (taper only) Evanescent 150 nm TM [17] 1.0 dB [36] >>40 nm [36] TE & TM ±2.5 μm (in‐plane) [36] Imec (taper only) EvanescentCoupler 1.0 dB [36] >>40 nm [36] TE & TM ±2.5 µm (in-plane) [36] Imec (taper only) Coupler 1 1D1 1D-GC‐GC = =one one-dimensional‐dimensional grating grating-coupler,‐coupler, 2D 2D-GC‐GC == two-dimensionaltwo‐dimensional grating-coupler, grating‐coupler, TE TE = = transverse-electric, transverse‐electric, andand TM TM = =transverse transverse-magnetic.‐magnetic.

2.2.1.2.2.1. Micro-OpticalMicro‐Optical BenchBench BothBoth Luxtera Luxtera and and the the Tyndall Tyndall National National Institute Institute have have demonstrated demonstrated micro‐ micro-opticaloptical bench (MOB) bench (MOB)[40,41]. [ 40These,41]. MOBs These consist MOBs consistof an AlN of an (or AlN Si) sub (or Si)‐mount sub-mount on which on whichan edge an‐emitting edge-emitting laser‐chip, laser-chip, a ball aμLens ball µ forLens collimating for collimating and focusing, and focusing, and a andmirror a mirror (or a total (or a internal total internal reflection reflection element) element) for beam for‐ beam-steering,steering, are mounted—see are mounted—see Figure Figure 9. The9 .hermetically The hermetically-sealed‐sealed Luxtera Luxtera MOB also MOB includes also includes a micro a ‐ micro-opticaloptical isolator isolator to reduce to reduce feedback feedback to the to laser the‐ laser-chip.chip. The MOB The MOB functions functions by re by‐imaging re-imaging light light from from the theedge edge-emitting‐emitting laser laser onto onto the the grating grating-coupler‐coupler on on the the surface surface of of the the PIC PIC with with the the required required near-normalnear‐normal angle-of-incidence.angle‐of‐incidence. Standard Standard 1D 1D grating-couplers grating‐couplers on theon PICthe canPIC be can used, be butused, custom but grating-couplerscustom grating‐ designedcouplers designed to better match to better the match elliptical the spotelliptical from spot the MOBfrom offerthe MOB even offer lower even insertion-losses. lower insertion‐losses. InIn the Tyndall Tyndall MOB, MOB, the the 300 300 μmµ mball ball μLensµLens self self-aligns‐aligns in a inprecision a precision laser‐ laser-drilleddrilled hole, and hole, which and whichthen provides then provides a fixed a fixed reference reference-point‐point for forthe thealignment alignment and and mounting mounting of of the the μµPrism reflectionreflection element.element. TheThe overall overall footprint footprint of the of MOBthe MOB is approximately is approximately 1 × 1 mm, 1 with× 1 themm, individual with the components individual ofcomponents laser-chip, ofµLens, laser‐ andchip,µ μPrismLens, having and μ aPrism maximum having dimension a maximum of 300 dimensionµm. Once of assembled,300 μm. Once the assembled, the MOB is actively aligned with respect to the grating‐coupler on the Si‐PIC, and has a 1 dB alignment tolerance comparable to that of Fiber‐to‐PIC coupling (±2.5 μm). Without adequate Appl. Sci. 2016, 6, 426 10 of 21

MOB is actively aligned with respect to the grating-coupler on the Si-PIC, and has a 1 dB alignment Appl. Sci. 2016, 6, 426 10 of 20 tolerance comparable to that of Fiber-to-PIC coupling (±2.5 µm). Without adequate thermal-sinking, the laser-chipthermal‐sinking, on the MOBthe laser is‐ likelychip on to the overheat, MOB is leadinglikely to tooverheat, reduced leading performance to reduced or performance burning-out. or Good thermalburning contact‐out. between Good thermal the MOB contact and between the PIC, the as MOB well asand thermo-electric the PIC, as well cooler as thermo (TEC),‐electric are neededcooler for stable(TEC), operation are needed of the for MOB stable [42 operation]. of the MOB [42]. Appl. Sci. 2016, 6, 426 10 of 20

thermal‐sinking, the laser‐chip on the MOB is likely to overheat, leading to reduced performance or burning‐out. Good thermal contact between the MOB and the PIC, as well as thermo‐electric cooler (TEC), are needed for stable operation of the MOB [42].

FigureFigure 9. Tyndall 9. Tyndall micro-optical micro‐optical benchbench (MOB); (MOB); (a) ( aSchematic) Schematic of the of MOB the MOBshowing showing the laser the‐chip, laser-chip, ball ball lens,lens, andand micro-prism;micro‐prism; ( (bb)) COMSOLCOMSOL‐software-software thermal thermal model model of the of theMOB MOB showing showing the elevated the elevated temperaturetemperature of the of laser-chipthe laser‐chip during during CW CW operation; operation; ((c,d) ZemaxZemax rayray-tracing‐tracing applied applied to the to MOB the MOB shows shows

howhow emission emission from from the the laser-chip laser‐chip is is re-imaged re‐imaged onto the the grating grating-coupler‐coupler on onthe thesurface surface of the of PIC. the PIC. UnlikeFigure a fiber 9. Tyndall‐mode, micro the re‐optical‐imaged bench spot (MOB); is elliptical, (a) Schematic just like of the the mode MOB showingform the the laser laser‐chip.‐chip, ball Unlike alens, fiber-mode, and micro the‐prism; re-imaged (b) COMSOL spot‐ issoftware elliptical, thermal just model like the of modethe MOB form showing the laser-chip. the elevated 2.2.2. VCSELtemperature Integration of the laser ‐chip during CW operation; (c,d) Zemax ray‐tracing applied to the MOB shows 2.2.2. VCSELhow Integration emission from the laser‐chip is re‐imaged onto the grating‐coupler on the surface of the PIC. DirectUnlike integration a fiber‐mode, of verticalthe re‐imaged cavity spot surface is elliptical, emitting just like lasers the mode (VCSELs) form the is laser also‐chip. a promising avenue Directfor hybrid integration integration. of verticalHere, the cavity significantly surface reduced emitting footprint lasers of (VCSELs) a VCSEL chip is also (250 a × promising 250 μm) over avenue for hybridthe 2.2.2.MOB integration. VCSEL (1 × 1 mm) Integration Here, allows the for significantly very high integration reduced densities. footprint Planar of a VCSEL VCSEL‐ chipto‐PIC (250 integration× 250 µ hasm) over the MOBbeen (1demonstrated,×Direct1 mm) integration allows where of for verticalphotoresist very cavity high based integrationsurface ‘wedges’ emitting densities. are lasers used (VCSELs) to Planar refract is VCSEL-to-PIC alsothe aVCSEL promising mode integrationavenue onto the has beengrating demonstrated,for hybrid‐coupler integration. with where the photoresistHere, required the significantly near based‐normal ‘wedges’ reduced angle footprint‐ areof‐incidence used of a to VCSEL refract[43]. chip Alternatively, the (250 VCSEL × 250 μ m) modea overgrating onto‐ the the MOB (1 × 1 mm) allows for very high integration densities. Planar VCSEL‐to‐PIC integration has grating-couplercoupler can withbe designed the required to couple near-normal the VCSEL angle-of-incidence‐mode into a pair of [ opposing43]. Alternatively, waveguides, a grating-coupler which can thenbeen be recombineddemonstrated, into where a single photoresist‐channel, based after ‘wedges’ phase ‐arecompensation used to refract [44]. the A VCSEL tilted ‐modeVCSEL onto approach the can be designed to couple the VCSEL-mode into a pair of opposing waveguides, which can then be can gratingalso be‐coupler used, withwhere the the required VCSEL near is ‐normaldirectly angle flip‐‐chippedof‐incidence onto [43]. the Alternatively, PIC with an a asymmetricgrating‐ recombined into a single-channel, after phase-compensation [44]. A tilted-VCSEL approach can also distributioncoupler can of besolder designed balls to [45]—see couple the Figure VCSEL 10.‐mode By intocontrolling a pair of opposingthe contact waveguides, area of the which bond can‐pads then be recombined into a single‐channel, after phase‐compensation [44]. A tilted‐VCSEL approach be used,available where for the solder VCSEL wetting, is directly the tilt flip-chipped‐angle of the onto VCSEL the PICcan be with optimized. an asymmetric This tilted distribution‐VCSEL of can also be used, where the VCSEL is directly flip‐chipped onto the PIC with an asymmetric solderapproach balls [45 allows]—see for Figure passive 10 flip. By‐chip controlling alignment the to the contact PIC for area rapid of assembly the bond-pads at commercial available volumes. for solder distribution of solder balls [45]—see Figure 10. By controlling the contact area of the bond‐pads wetting, the tilt-angle of the VCSEL can be optimized. This tilted-VCSEL approach allows for passive available for solder wetting, the tilt‐angle of the VCSEL can be optimized. This tilted‐VCSEL flip-chipapproach alignment allows to thefor passive PIC for flip rapid‐chip alignment assembly to at the commercial PIC for rapid assembly volumes. at commercial volumes.

Figure 10. Tilted vertical cavity surface emitting laser (VCSEL) to Si‐PIC integration; (a) Schematic of the Figuretilted‐VCSEL 10. Tilted geometry, vertical cavity showing surface the emitting VCSEL laserpositioned (VCSEL) above to Si‐ PICthe integration;grating‐coupler (a) Schematic on the Si of‐PIC, Figure 10. Tilted vertical cavity surface emitting laser (VCSEL) to Si-PIC integration; (a) Schematic of andthe the tilted tilt being‐VCSEL provided geometry, by showing the solder the VCSELballs; ( bpositioned) SEM (scanning above the electron grating ‐micrsoscope)coupler on the imageSi‐PIC, of a the tilted-VCSELtiltedand VCSEL the tilt geometry, onbeing the provided Si‐PIC; showing by(c) theMicroscope thesolder VCSEL balls; image (b positioned) SEM of a(scanning tilted above‐VCSEL electron the on grating-coupler micrsoscope) the Si‐PIC, image showing on of the a the Si-PIC, and theelectrical tilttilted being ‐VCSELtracks provided andon theon ‐PICSi‐ byPIC; waveguides the (c) solderMicroscope used balls; imagefor ( brouting) SEMof a tiltedthe (scanning electrical‐VCSEL on electronand the optical Si‐PIC, micrsoscope) signals. showing the image of a tilted VCSELelectrical‐ ontracks the and Si-PIC; on‐PIC ( cwaveguides) Microscope used imagefor routing of the a tilted-VCSEL electrical and optical on the signals. Si-PIC, showing the electrical-tracks and on-PIC waveguides used for routing the electrical and optical signals. Appl. Sci. 2016, 6, 426 11 of 21

3. Electronic Packaging Appl. Sci. 2016, 6, 426 11 of 20 For telecom and datacom applications, photonic devices are required to operate at high speeds and with3. Electronic very high Packaging bandwidths. In many cases, this involves the (de-)multiplexing of several 25 Gbps electrical-channels to/from a single N × 25 Gbps optical-channel, with N = 4, 6, 12, etc. The efficient, For telecom and datacom applications, photonic devices are required to operate at high speeds low-reflection,and with artifact-free,very high bandwidths. routing In of many these cases, high-speed this involves electrical the (de signals‐)multiplexing from a of centimeter-scale several 25 Gbps SMA (SubMiniature,electrical‐channels version to/from A) /SMK a single (SubMiniature, N × 25 Gbps optical version‐channel, K) connector with N = to4, 6, the 12, microscopic etc. The efficient, structures on the PIClow‐reflection, can present artifact a design‐free, routing challenge. of these If a high very‐speed high numberelectrical ofsignals electrical from a connections centimeter‐scale to the PIC are needed,SMA (SubMiniature, or if precise (sub-ns) version A) control /SMK of (SubMiniature, switching is version needed K) on connector multiple to channels, the microscopic then vertical integrationstructures of a customon the PIC electronic can present integrated a design challenge. circuit (EIC) If a very driver-chip high number may of also electrical be needed. connections to the PIC are needed, or if precise (sub‐ns) control of switching is needed on multiple channels, then 3.1. High-Speedvertical integration Routing of a custom electronic integrated circuit (EIC) driver‐chip may also be needed. High-speed3.1. High‐Speed SMA Routing (18–25 GHz) and SMK (46 GHz) connectors have a ≈1 cm2 footprint on the PCB, whileHigh the pitch‐speed of SMA the (18–25 electrical GHz) bond-padsand SMK (46 onGHz) a PIC connectors is typically have a ≈ 1001 cmµ2m. footprint Therefore, on the thePCB, pitch of the high-speedwhile the pitch 50 Ω oftransmission the electrical bond lines‐pads must on be a PIC reduced is typically by two 100 μ orders-of-magnitudem. Therefore, the pitch betweenof the the connectorhigh and‐speed the 50 PIC, Ω transmission while maintaining lines must the be path-length reduced by oftwo different orders‐of electrical-channels‐magnitude between to the preserve signal timings.connector This and the usually PIC, while results maintaining in PICs surrounded the path‐length by of circular different or electrical semi-circular‐channels PCBs, to preserve with an area signal timings. This usually results in PICs surrounded by circular or semi‐circular PCBs, with an that increases proportional to the square of the number of electrical channels—see Figure 11. area that increases proportional to the square of the number of electrical channels—see Figure 11.

(a) (b) (c)

(d) (e)

Figure 11. Examples of electrical‐routing structures needed for high‐speed photonic packages; (a) Figure 11. Examples of electrical-routing structures needed for high-speed photonic packages; (a) Image Image of the semi‐circular PCB‐to‐PIC routing needed to ensure that multiple signals arrive at the of the semi-circularsame time; (b) Microscope PCB-to-PIC image routing of a pitch needed‐reducing to ensure ceramic that interposer multiple used signals to match arrive the atminimum the same‐ time; (b) Microscopepitch on a image standard of ahigh pitch-reducing‐dielectric PCB ceramic (300 μm) interposer to the bond used‐pad pitch to match on the the PIC minimum-pitch (100 μm); (c) on a standardMicroscope high-dielectric image PCBof the (300 ‘tape’µm) or to ‘ribbon’ the bond-pad wire‐bonds pitch used on to the connect PIC (100 theµ PCBm); (cto) Microscopethe ceramic image of the ‘tape’interposer; or ‘ribbon’ (d,e) On wire-bonds‐PIC high‐speed used transmission to connect thelines PCB in the to theco‐planar ceramic ground interposer;‐signal‐ground (d,e) On-PIC high-speedgeometry. transmission lines in the co-planar ground-signal-ground geometry.

On standard high‐dielectric PCB (DK ≈ 10), the minimum feature size limits the pitch of 50 Ω Ontransmission standard high-dielectriclines to about 300 μ PCBm, which (DK ≈ is 10),a factor the of minimum three greater feature than the size bond limits‐pad pitch the pitch on the of 50 Ω transmissionPIC. This lines ‘gap’ to can about be bridged 300 µ bym, a which pitch‐reducing is a factor multi of‐level three ceramic greater interposer, than the designed bond-pad using pitcha on the PIC.finite This element ‘gap’ mode can (FEM) be bridged high frequency by a pitch-reducing structural simulator multi-level (HFSS). The ceramic interposer interposer, offers smaller designed feature sizes and higher manufacturing tolerances than those possible for PCBs. The electrical using a finite element mode (FEM) high frequency structural simulator (HFSS). The interposer offers connection between the interposer and the bond‐pads on the PIC are made using 10–20 μm diameter smallerAu feature wire‐bonds. sizes andFor DC higher (direct manufacturing current) connections, tolerances circular than cross those‐section possible wire‐bonds for PCBs. are used, The but electrical connectionfor high between‐speed connections the interposer ‘ribbon’ and or the ‘tape’ bond-pads wire‐bonds on are the preferred. PIC are made Ribbon using wire‐ 10–20bonds haveµm diameter a Au wire-bonds.higher surface For area DC‐per (direct‐unit‐ current)volume, which connections, offers lower circular resistance cross-section to high‐speed wire-bonds signals, because are used, of but for high-speedthe skin effect. connections ‘ribbon’ or ‘tape’ wire-bonds are preferred. Ribbon wire-bonds have a higher surfaceTo reduce area-per-unit-volume, induction effects, all whichwire‐bonds offers should lower be as resistance short and tostraight high-speed as possible. signals, This often because of means that the PIC should be recessed into the PCB, to allow for a ‘flush’ wire‐bond. Once connected the skin effect. To reduce induction effects, all wire-bonds should be as short and straight as possible. This often means that the PIC should be recessed into the PCB, to allow for a ‘flush’ wire-bond. Once connected Appl. Sci. 2016, 6, 426 12 of 21 to the PIC, wire-bonds are very sensitive to any shearing force, and so the PIC, interposer, and PCB must be rigidly connected in the the mechanical package. ‘Glob top’ encapsulation of the wire-bonds Appl. Sci. 2016, 6, 426 12 of 20 with silicone or epoxy can offer further protection, but can only be used in packages where it will not interfereto the with PIC, Fiber-to-PIC wire‐bonds are coupling, very sensitive or other to any integrated shearing components. force, and so the PIC, interposer, and PCB Oncemust be transferred rigidly connected to the PIC, in the the the high-speed mechanical package. signals must ‘Glob be top’ routed encapsulation from the of bond-pads the wire‐bonds to/from the relevantwith silicone on-PIC or epoxy components. can offer further Although protection, different but can cross-section only be used geometries in packages where are possible it will not on the PCB andinterfere interposer with Fiber (micro-strip,‐to‐PIC coupling, strip-line, or other and integrated co-planar components. transmission-lines), Si foundry design rules typically restrictOnce transferred the high-speed to the PIC, transmission the high‐speed lines signals to a co-planar must be routed geometry. from Tothe avoid bond‐pads significant to/from losses and reflections,the relevant HFSSon‐PIC must components. be used Although to optimize different these cross on-PIC‐section transmission geometries are lines possible within on the the boundary PCB and interposer (micro‐strip, strip‐line, and co‐planar transmission‐lines), Si foundry design rules conditions of the very specific materials and layer-thicknesses available at the Si foundry [6–8]. typically restrict the high‐speed transmission lines to a co‐planar geometry. To avoid significant losses 3.2. Verticaland reflections, Integration HFSS must be used to optimize these on‐PIC transmission lines within the boundary conditions of the very specific materials and layer‐thicknesses available at the Si foundry [6–8]. Monolithic integration of photonic and electronic functionalities onto a single chip is often promoted3.2. Vertical as the Integration ultimate goal for large-scale Si photonics [4]. However, at low-to-medium volumes 4 5 (10 –10 chipsMonolithic per year), integration the vertical of photonic integration and electronic of the electronic functionalities and photonic onto a functionalitiessingle chip is often onto two separatepromoted Si chips as canthe ultimate bring an goal economic-advantage, for large‐scale Si photonics because [4]. it allowsHowever, for at the low mixing‐to‐medium of different volumes CMOS technology(104–105 nodes. chips per Specifically, year), the thevertical fabrication integration tolerances of the electronic of PICs can and be photonic satisfied functionalities by the 45 nm onto node on relativelytwo separate low-cost Si chips 200 mm can wafers,bring an whileeconomic high-performance‐advantage, because cost-effective it allows for the electronic-ICs mixing of different (EIC) may needCMOS the 14 technology nm node nodes. on 300 Specifically, mm wafers. the The fabrication footprint tolerances of a PIC of PICs (10–30 can mm be satisfied2) is usually by the quite45 nm large node on relatively low‐cost 200 mm wafers, while high‐performance cost‐effective electronic‐ICs (EIC) compared to a typical EIC, because of large photonic components (AWGs, delay-lines, etc.) and the may need the 14 nm node on 300 mm wafers. The footprint of a PIC (10–30 mm2) is usually quite space reserved for Fiber-to-PIC coupling, so not ‘wasting’ this space on the more expensive CMOS large compared to a typical EIC, because of large photonic components (AWGs, delay‐lines, etc.) and nodethe can space bring reserved a significant for Fiber reduction‐to‐PIC coupling, in overall so not cost. ‘wasting’ this space on the more expensive CMOS Thenode verticalcan bring integrationa significant reduction of an EIC in overall on a PICcost. can be made using either solder-ball-bump (SBBs) orThe copper-pillar-bump vertical integration of (CPBs) an EIC interconnects, on a PIC can be whichmade using provide either an solder electrical,‐ball‐bump mechanical, (SBBs) or and thermalcopper interface‐pillar‐bump between (CPBs) the interconnects, two chips [ 46which,47]. provide In particular, an electrical, vertical mechanical, integration and improves thermal the high-speedinterface electronic between the interface two chips to [46,47]. the PIC, In particular, because it vertical acts to integration replace long improves (100–500 the highµm)‐speed possibly curved,electronic wire-bonds interface with to the short PIC, (because≈10 µm) it acts SBB to or replace CPB long interconnects, (100–500 μm) which possibly minimizes curved, wire parasitic‐ inductionbonds effects with short [48– 50(≈10]—see μm) FigureSBB or 12CPB. In interconnects, addition to high-speed, which minimizes high-density parasitic electronic induction integration,effects [48–50]—see Figure 12. In addition to high‐speed, high‐density electronic integration, the mechanical the mechanical connection offered by SBBs and CPBs also allows for the bridging of different connection offered by SBBs and CPBs also allows for the bridging of different functional technologies, functional technologies, such as MEMS (micro-electro-mechanical systems), III-V, non-CMOS ASIC such as MEMS (micro‐electro‐mechanical systems), III‐V, non‐CMOS ASIC (application‐specific (application-specificintegrated circuit), integrated etc. [3]. circuit), etc. [3].

(a) SMT (b) FrontEnd Fibre Electronics Array CPBs

Printed Circuit Board Tracks

(c) EIC DC Cu Lines Solder 25µm RF Cu Lines PIC Figure 12. Vertical integration of an electronic integrated circuit (EIC) driver‐chip on top of a Si‐PIC; Figure 12. Vertical integration of an electronic integrated circuit (EIC) driver-chip on top of a Si-PIC; (a) Image of an EIC integrated on a PIC, with RF (radio frequency) and DC (direct current) signals (a) Image of an EIC integrated on a PIC, with RF (radio frequency) and DC (direct current) signals routed from the front‐end electronics on the PCB across the surface of the PIC; (b) Microscope image routed from the front-end electronics on the PCB across the surface of the PIC; (b) Microscope image of of the EIC integrated onto the PIC using several hundred discrete copper‐pillar‐bumps (CPBs); (c) the EICFurther integrated zoomed onto‐in microscope the PIC using image several of the hundred CPB interconnects discrete copper-pillar-bumps between the EIC and (CPBs); PIC. Solder (c) Further zoomed-inreflow microscopebonding with image a “no of clean” the CPB flux interconnectsallows for very between well aligned the EICCPB and interconnects PIC. Solder with reflow minimal bonding with a“solder “no clean” squeezing”. flux allows for very well aligned CPB interconnects with minimal “solder squeezing”. Appl. Sci. 2016, 6, 426 13 of 21

CPBs typically have a diameter of 20–30 µm, and are formed by Cu electro-plating of under-bump metal-padsAppl. Sci. on 2016 the, 6, 426 PIC and EIC, followed by the deposition of a (lead-free) Sn-Ag-Cu13 solder-cap. of 20 The PIC and EIC are vertically integrated by aligning the matching pairs of CPBs on both chips using CPBs typically have a diameter of 20–30 μm, and are formed by Cu electro‐plating of under‐ the beam-splitterbump metal‐ camerapads on the of a PIC flip-chip and EIC, system; followed bringing by the deposition the two chips of a (lead into‐ contact;free) Sn‐Ag and‐Cu then solder applying‐ a thermo-compressioncap. The PIC and EIC or solder-refloware vertically integrated cycle to fuseby aligning together the the matching paired pairs solder-caps. of CPBs on These both solder-capschips will beusing coated the by beam a native-oxide‐splitter camera layer of a that flip must‐chip system; be removed bringing to ensurethe two a chips good into electrical contact; and and mechanical then interconnectapplying is a formed thermo‐compression [51]. The traditional or solder‐reflow solder-fluxes cycle to fuse used together in electronic the paired packaging solder‐caps. are These generally not applicablesolder‐caps in will photonic be coated packaging, by a native‐ becauseoxide layer they that can must leave be removed chemical to ensure residue a good that electrical contaminates the opticaland mechanical interfaces interconnect for Fiber-to-PIC is formed coupling. [51]. The traditional This can solder lead to‐fluxes increased used in insertion electronic packaging losses and also are generally not applicable in photonic packaging, because they can leave chemical residue that a weakening of the mechanical Fiber-to-PIC bond. Instead, a ‘no clean’ flux should be used during contaminates the optical interfaces for Fiber‐to‐PIC coupling. This can lead to increased insertion the solder-reflowlosses and also bonding. a weakening This of the flux mechanical is VOC-free Fiber (volatile‐to‐PIC bond. organic Instead, compounds) a ‘no clean’ flux and should activates be and evaporatesused during at the melting-pointthe solder‐reflow of bonding. the solder This [52 flux], so is it VOC does‐free not (volatile require organic a post-bonding compounds) solvent-rinse and that canactivates contaminate and evaporates the PIC at [ 53the,54 melting]. ‐point of the solder [52], so it does not require a post‐bonding Aftersolvent the‐rinse alignment that can contaminate of the EIC the and PIC PIC [53,54]. in a flip-chip system, and applying a ‘no clean’ flux solder-reflowAfter cycle the alignment (typically of 250 the◦ EICC for and 30 PIC s), it in is a possible flip‐chip tosystem, achieve and an applying excellent a ‘no bond clean’ between flux the top- andsolder bottom-side‐reflow cycle CPBs. (typically A variety 250 °C of for diagnostics—electrical 30 s), it is possible to achieve resistance an excellent measurements, bond between destructive the top‐ and bottom‐side CPBs. A variety of diagnostics—electrical resistance measurements, destructive tear-off tests, and X-ray microscopy—can be used to assess the quality of the CPB interconnect. tear‐off tests, and X‐ray microscopy—can be used to assess the quality of the CPB interconnect. An An alignment of better than ±1 µm can be achieved, with little-to-no ‘solder squeezing’, which would alignment of better than ±1 μm can be achieved, with little‐to‐no ‘solder squeezing’, which would have thehave potential the potential to lead to lead to electricalto electrical shorts shorts between between adjacent adjacent interconnects—see interconnects—see Figure Figure 13. 13.

PIC PIC

(b) hotonic0IC

EIC PIC EIC EIC

Figure 13. Analysis of the copper‐pillar‐bumps (CPBs) for vertical integration; (a,b) SEM images of Figure 13. Analysis of the copper-pillar-bumps (CPBs) for vertical integration; (a,b) SEM images the ‘top’ and ‘bottom’ CPBs that form the vertical interconnect between the PIC and EIC before solder‐ of thereflow ‘top’ andbonding. ‘bottom’ The asymmetric CPBs that pairing form the of the vertical CPBs helps interconnect to reduce between slippage theduring PIC the and flip EIC‐chip before solder-reflowalignment; bonding. (c) Side‐view The image asymmetric of the PIC pairing + EIC assembly of the CPBsafter a helps‘grind and to reduce polish’ has slippage been used during to the flip-chipexpose alignment; approximately (c) Side-view 70 CPBs; (d image,e) X‐ray of microscope the PIC + images EIC assembly of the PIC+EIC after assembly, a ‘grind allowing and polish’ the has been usedoperator to expose to ‘see through’ approximately the EIC, 70 and CPBs; identify (d,e the) X-ray position microscope of the CPBs. images This diagnostic of the PIC+EIC allows assembly,the allowingoperator the operator to non‐destructively to ‘see through’ identify the missing EIC, andor grossly identify malformed the position CPBs. of the CPBs. This diagnostic allows the operator to non-destructively identify missing or grossly malformed CPBs. 4. Thermal Management of PICs 4. ThermalPhotonic Management elements, of such PICs as integrated semiconductor optical amplifiers (SOAs) and micro‐ring resonators, exhibit a strong temperature‐dependence that is many times greater than that of CMOS Photonicelectronics. elements, A temperature such variation as integrated of 20 °C semiconductor is often sufficient optical for a PIC amplifiers to drift out (SOAs) of its operational and micro-ring resonators,profile exhibit [55,56]. aGlobal strong thermal temperature-dependence stabilization of the PIC thatin a photonic is many device, times greaterusually with than a that thermo of CMOS‐ electronics.electric A cooler temperature (TEC), is variationessential for of 20prototypes◦C is often that sufficientneed to be for tested a PIC in tothe drift field, out where of its seasonaloperational profiletemperature [55,56]. Global swings thermal of ±10 °C stabilization are common. ofThe the added PIC global in a photonic stability from device, the TEC usually allows with for more a thermo- electricefficient cooler and (TEC), better is reproducibility essential for in prototypes the local temperature that need‐tuning to be testedof individual in the photonic field, where elements seasonal (e.g., micro‐ring resonators, thermo‐optic phase‐shifters, etc.) on the PIC. Increasing the coefficient of temperature swings of ±10 ◦C are common. The added global stability from the TEC allows for more performance (CoP) of the TEC in these modules is an important consideration for lowering the efficientoperational and better cost reproducibility of deployed photonics. in the local temperature-tuning of individual photonic elements (e.g., micro-ringFigure 14 resonators, shows a schematic thermo-optic of the typical phase-shifters, ‘thermal stack’ etc.) for ona module the PIC. with Increasing a PIC and integrated the coefficient of performanceEIC. The electrical (CoP) power of the is TEC delivered in these to the modules EIC, where is anit evolves important into thermal consideration power (H for= dQ/dt lowering) via the operational cost of deployed photonics. Appl. Sci. 2016, 6, 426 14 of 21

Figure 14 shows a schematic of the typical ‘thermal stack’ for a module with a PIC and integrated

EIC. TheAppl. electrical Sci. 2016, 6, 426 power is delivered to the EIC, where it evolves into thermal power (H =14 dQ/dtof 20 ) via Joule-heating, and then flows into the PIC through the SBB or CPB interconnect layer. From there, the heatJoule conducts‐heating, into and athen heat-spreading flows into the plate,PIC through and reaches the SBB the or CPB ‘cold interconnect side’ of the layer. TEC, From before there, reaching the baseplatethe heat conducts of the module, into a heat where‐spreading it is plate, lost and to the reaches ambient the ‘cold environment, side’ of the TEC, either before through reaching passive the baseplate of the module, where it is lost to the ambient environment, either through passive convection/conduction, or ‘rack-based’ forced-convection cooling. convection/conduction, or ‘rack‐based’ forced‐convection cooling.

Figure 14. Thermal imaging of a photonic module and PIC; (a,b) A comparison of optical and thermal Figureimaging 14. Thermal of the optical imaging network of a photonic unit (ONU) module packaged and for PIC; the (FP7a,b‐)FABULOU A comparison project. of Once optical powered and thermal‐ imagingup, of both the opticalthe EIC network and PIC unit experience (ONU) a packaged significant for increase the FP7-FABULOU in temperature project. (34 °C Once and powered-up,20 °C, ◦ ◦ both therespectively); EIC and PIC (c) Schematic experience of the a significant ‘thermal stack’ increase in the inONU, temperature showing the (34 conductionC and 20 pathC, from respectively); the (c) SchematicEIC to to ofthe the baseplate; ‘thermal (d) stack’Thermal in microscopy the ONU, of showing the EIC and the PIC conduction on the ONU. path Silicon from is thetransparent EIC to to the baseplate;in the ( d3–5) Thermal μm wavelength microscopy range of at thewhich EIC the and sensor PIC operates, on the ONU. allowing Silicon the user is transparent to ‘see through’ in the the 3–5 µm wavelengthEIC substrates range at and which image the the sensor metallic operates, structures allowing on the surface the userof the to EIC ‘see and through’ PIC. the EIC substrates and image the metallic structures on the surface of the EIC and PIC. The effect of unchecked Joule‐heating can be illustrated by powering‐up the EIC while the TEC is powered‐down, as shown in Figure 15. Here, 1.1 W of power is applied to the EIC in a Si photonic Theoptical effect network of unchecked unit (ONU), Joule-heating developed for can the be the illustrated EU‐FP7 ‘FABULOUS’ by powering-up project the [57], EIC which while results the TEC is powered-down,in a temperature as shown increase in of Figure 34 °C and 15 .20 Here, °C for 1.1 EIC W and of PIC, power respectively. is applied These to themeasurements EIC in a Si were photonic opticalmade network using unita thermal (ONU), microscope, developed which for allows the the for EU-FP7 accurate, ‘FABULOUS’ non‐contact temperature project [57 measurements,], which results in a temperatureboth of the increase PIC (100 of μ 34m◦C‐scale) and 20and◦ Cthe for full EIC photonic and PIC, module respectively. (10 cm‐ Thesescale). measurementsThese dynamic were temperature measurements provide quantitative information on both the heat‐conduction and heat‐ made using a thermal microscope, which allows for accurate, non-contact temperature measurements, capacity of the thermal stack. Broadly speaking, the ‘kinks’ in these dynamic measurements µ both ofcorrespond the PIC (100 to them-scale) time taken and for the the fullheat photonic to ‘fill’ the module different (10 blocks cm-scale). of material These in the dynamic stack, though temperature measurementsproper modelling provide and quantitative data‐fitting information is needed to fully on both extract the the heat-conduction quantitative details. and In heat-capacity contrast, the of the thermalsteady stack.‐state Broadly temperature speaking, difference the ‘kinks’ between in the these EIC dynamicand PIC (∆ measurementsT = 13.8 °C) provides correspond a very direct to the time takenmeasure for the heatof the to thermal ‘fill’ the resistance different (RT) blocks of the CPB of material interconnect in the layer stack, through, though RT = ∆ properT/H. The modelling thermal and data-fittingresistance is needed of the full to fullyCPB layer extract is then the quantitative 12.5 K/W = 13.2 details. °C/1.1 In W. contrast, Given that the the steady-state interconnect temperature layer 3 differenceconsists between of 484 individual the EIC and CPBs, PIC this (∆ Timplies = 13.8 a ◦resistanceC) provides of 6.1 a very× 10 directK/W per measure interconnect. of the The thermal dynamic and steady‐state information from the thermal microscopy measurements can be used to resistance (RT) of the CPB interconnect layer through, RT = ∆T/H. The thermal resistance of the full validate current thermal models, and also to show how future designs can be optimized. CPB layer is then 12.5 K/W = 13.2 ◦C/1.1 W. Given that the interconnect layer consists of 484 individual Once the TEC is powered‐up, the PIC rapidly stabilizes to the set‐point temperature (TSP) 3 CPBs,programmed this implies into a resistance the external of proportional 6.1 × 10 K/W‐integral per‐differential interconnect. (PID) Thecontroller. dynamic A micro and‐bead steady-state or informationsurface‐ frommountable the thermaltechnology microscopy (SMT) thermistor measurements is placed in can close be thermal used toproximity validate to currentthe PIC, thermalto models,provide and also feedback to show to the how PID controller. future designs For the can ONU be from optimized. the ‘FABULOUS’ project, the PIC stabilizes Onceto TSP the± 0.1 TEC °C in is30 powered-up,s, and TSP ± 0.01 the°C in PIC 60 s. rapidly In this steady stabilizes‐state, where to the 1.1 set-point W of electrical temperature power is (TSP) programmedapplied to into the EIC, the externalthe TEC needs proportional-integral-differential to draw 0.5 W to recover the PIC to (PID) a room controller.‐temperature A micro-beadset‐point or surface-mountableof 18 °C. This implies technology a CoP of (SMT) 2.2 = 1.1 thermistor W/0.5 W, and is placed shows inthat close thermal thermal management proximity accounts to the for PIC, to provide feedback to the PID controller. For the ONU from the ‘FABULOUS’ project, the PIC stabilizes Appl. Sci. 2016, 6, 426 15 of 21

◦ ◦ to TSP ± 0.1 C in 30 s, and TSP ± 0.01 C in 60 s. In this steady-state, where 1.1 W of electrical power isAppl. applied Sci. 2016 to, 6 the, 426 EIC, the TEC needs to draw 0.5 W to recover the PIC to a room-temperature set-point15 of 20 ◦ ofAppl. 18 Sci.C. 2016 This, 6, implies426 a CoP of 2.2 = 1.1 W/0.5 W, and shows that thermal management accounts15 of for 20 30% == 0.5 W/0.5W/0.5 W W + 1.1 1.1 W W of the operational power-budgetpower‐budget for the module. Increasing the CoP ofof TE-cooling30%TE‐cooling = 0.5 W/0.5 for for PICs, PICs, W + by by1.1 improving improving W of the howoperational how heat heat can can power be be distributed distributed‐budget andfor and the dissipated dissipated module. across Increasing across the the module, themodule, CoP is an ofis activeTEan ‐activecooling topic topic for of research. PICs,of research. by Finite-elementimproving Finite‐element how simulations heat simulations can be in distributedCOMSOL in COMSOL canand be candissipated used be used to test across to andtest the optimizeand module, optimize new is stackannew active designs,stack topic designs, which of research. arewhich then Finite are experimentally ‐thenelement experimentally simulations validated using invalidated COMSOL the dynamic using can be temperaturethe used dynamic to test measurements andtemperature optimize fromnewmeasurements thermalstack designs, microscopy—see from thermalwhich aremicroscopy—see Figure then 16experimentally. Figure 16. validated using the dynamic temperature measurements from thermal microscopy—see Figure 16.

Figure 15.15. TemperatureTemperature changes changes of of the the EIC EIC and and PIC PIC in the in FP7-FABULOUS the FP7‐FABULOUS optical optical network network unit (ONU) unit fromFigure(ONU) the 15.from thermal Temperature the thermal microscope microscopechanges analysis; of theanalysis; (a EIC) The and ( increasea) The PIC increase in in the EIC FP7 in and EIC‐FABULOUS PIC and temperature, PIC temperature, optical when network thewhen ONU unit the is(ONU)ONU powered-up, is from powered the and thermal‐up, the and TEC microscope the (thermo-electric TEC analysis;(thermo cooler) ‐(electrica) The is increase cooler) not activated. inis EICnot and Afteractivated. PIC 30 temperature, s, theAfter PIC 30 temperature s, when the PICthe reachesONUtemperature is a powered steady-state reaches‐up, a at andsteady 20 ◦theC‐state aboveTEC at (thermo the 20 ambient;°C ‐aboveelectric ( bthe) cooler) Once ambient; the is TECnot (b) isactivated.Once activated the TECAfter (in Cooling#1),is 30 activated s, the PIC the(in hottemperatureCooling#1), PIC rapidly the reaches returnshot PIC a tosteady rapidly the ambient‐state returns at set-point20 to °Cthe above ambient temperature, the set ambient;‐point reaching temperature, (b) Once±0.1 ◦theC reaching of TEC the set-pointis ±0.1activated °C in of 30 the(in s. InCooling#1),set Cooling#2,‐point in the30 the s. hot In ONU PICCooling#2, andrapidly TEC the returns are ONU powered-up to and the TEC ambient at are the powered set same‐point moment,‐ uptemperature, at the and same the reaching PIC moment, never ±0.1 and exceeds °C the of PIC the set-pointsetnever‐point exceeds byin 30 more thes. In thanset Cooling#2,‐point 5 ◦C. by morethe ONU than and 5 °C. TEC are powered‐up at the same moment, and the PIC never exceeds the set‐point by more than 5 °C.

Figure 16. COMSOL thermal simulations of the EIC and PIC in the FP7‐FABULOUS ONU; (a–c) For Figureaccurate 16. convergent COMSOL models,thermal the simulations simulation of meshthe EIC must and span PIC infrom the the FP7-FABULOUSFP7 10‐FABULOUS cm‐scale of ONU;the full ( amodule–c) For accurate(including convergent TEC and models,baseplate) the to simulation the 10 μ meshm‐scale must of spanthe CPB from interconnects. the 10 cm-scalecm‐scale The of theresults full of module these (including(includingsimulations TEC can be and validated baseplate) against toto thethe thermal 1010 μµm-scalem‐imaging,‐scale ofof and thethe used CPBCPB to interconnects.interconnects. test new designs The for results better of cooling these simulationsof the EIC and can PIC be validatedin the photonic against module. thermal-imaging,thermal ‐imaging, and used to test new designs for better cooling of the EIC and PIC in the photonic module. 5. Emerging Technologies for Photonics Packaging 5. Emerging Technologies for Photonics Packaging 5. EmergingIn addition Technologies to the established for Photonics technologies Packaging described in the previous sections, it is interesting to look Inat additionemerging to technologies the established and technologies how they describedmay impact in thephotonic previous packaging sections, in it isthe interesting future. For to lookexample, atat emerging emerging the same technologies technologies polymer waveguide and and how how they technology they may may impact impactthat photonic has photonic been packaging used packaging to in demonstrate the future. in the For future.evanescent example, For theexample,coupling same can polymerthe alsosame be waveguidepolymer combined waveguide technologywith electrical technology that FR4 has (fire been that‐resistant, usedhas been to version demonstrate used 4)to PCBsdemonstrate evanescent to create evanescent a couplingplatform cancouplingcapable also of be can routing combined also be electrical combined with electrical and with optical electrical FR4 signals (fire-resistant, FR4 from (fire external‐resistant, version connectors 4) version PCBs toto4) createsinglePCBs to aor platformcreate multiple a platform capable Si‐PICs capable[36]. Here, of routingthe main electrical advantages and opticalover glass signals interposers from external is improved connectors cost‐ effectivenessto single or multiple and processing Si‐PICs [36].flexibility Here, ofthe the main polymer advantages waveguides over glass (i.e., interposers direct laser is‐writing improved or photolithography),cost‐effectiveness and especially processing for flexibilitylarge areas. of The the anticipatedpolymer waveguides propagation (i.e., distances direct laserin these‐writing ‘optical or PCBs’photolithography), is in the range especially of 10s of cm,for largeso the areas. principle The anticipatedchallenge to propagation be overcome distances is reducing in these waveguide ‘optical PCBs’ propagation is in the lossesrange toof 10sbelow of cm, 0.1 sodB/cm. the principle Another challengehighly innovative to be overcome solution is reducingfor PIC‐to waveguide‐PIC [58] and propagation multi‐core losses Fiber to‐to below‐PIC [59]0.1 dB/cm. Another highly innovative solution for PIC‐to‐PIC [58] and multi‐core Fiber‐to‐PIC [59] Appl. Sci. 2016, 6, 426 16 of 21 of routing electrical and optical signals from external connectors to single or multiple Si-PICs [36]. Here, the main advantages over glass interposers is improved cost-effectiveness and processing flexibility of the polymer waveguides (i.e., direct laser-writing or photolithography), especially for large areas. The anticipated propagation distances in these ‘optical PCBs’ is in the range of 10s of cm, so the principle challenge to be overcome is reducing waveguide propagation losses to below 0.1 dB/cm. Another highly innovative solution for PIC-to-PIC [58] and multi-core Fiber-to-PIC [59] optical connectivity is that offered by the photonic wire bonds (PWBs) developed at the Karlsruhe Institute of Technology. These PWBs are formed by tightly focused femtosecond laser pulses that expose photoresist along a freeform 3D path connecting two optical interfaces (e.g., inverted-tapers on a Si-PIC to the inner-core of a single-mode fiber). Since the shape of the PWBs can be easily adapted, there is no need for high-precision mechanical alignment between connected PICs and fibers, which is an advantage for future scale-up. Writing PWBs is currently a serial process, and it remains to be seen if it can be economically implemented at the wafer-level, where thousands or tens-of-thousands of PWBs are needed per wafer. There are also many innovations around the basic grating-coupler designs, including replacing single-line trenches with sub-wavelength lithographic features that allow for a high degree of index engineering. In some cases, these sub-wavelength features are designed to create an apodized structure that almost perfectly matches the profile of the incident fiber-mode [60], and so allows for very low (sub-decibel) insertion losses. An alternative strategy is to use the sub-wavelength lithographic features to create a region with highly non-linear patterning that creates a patch of meta-material in the SOI (silicon-on-insulator)-layer [61]. When the pattern in this meta-material is properly optimized it can couple light from free-space into the SOI-waveguide, and can even couple light of different polarizations, in analogy to 2D grating-couplers. The efficiency of these meta-material couplers each device is at least comparable to more standard grating-couplers, and can offer a broader bandwidth, because multiple guided modes are responsible for the coupling, which makes the meta-material coupler less sensitive to wavelength shifts. The principle disadvantages of both of these sub-wavelength coupler schemes is that they can normally only be fabricated by e-beam lithography, because they require feature-sizes on the order of 100 nm, which are not readily accessible using the 193 nm deep-UV lithography typically used in the Si-Photonic foundries. Until the performance of these sub-wavelength couplers can be transferred to a scalable UV lithographic process, they cannot be developed into standardized building blocks for commercial photonic devices. In addition to Fiber-to-PIC coupling, grating-couplers can be used for optical proximity coupling or interlayer coupling [62–64], which allows for efficient vertical chip-to-chip and even board-to-chip connections (in conjunction with optical-PCBs mentioned above). Combined with low-loss waveguides for horizontal distribution, this vertical chip-to-chip optical connection allows for the possibility of true 3D integrated routing of light across optical-motherboards to multiple Si-PICs. Even though the bandwidth of Fiber-to-PIC grating-couplers is typically rather narrow (normally, the 1 dB bandwidth is 30–40 nm), the same gratings in an optical proximity configuration will offer broadband coupling, because a near-field interaction between the gratings mediates the coupling. For the same reason, the insertion-loss between two adjacent grating-couplers is not simply the sum of two equivalent Fiber-to-PIC interfaces; it can be much lower, on the order of a single Fiber-to-PIC interface. These optical proximity couplers are expected to have a large impact on wafer-level packaging, because they allow for the flip-chip alignment and/or wafer-bonding of different photonic systems for advanced hybrid photonic devices.

6. Discussion of Trends in Photonics Packaging The high-cost and low-speed of photonic packaging is probably the most significant bottleneck in developing competitive photonic devices. As spin-out companies work to take devices to market, and large multi-nationals enter the Si-photonics space, there is a growing need to develop automated packaging processes to enable higher volume production. The clear trend is for more compact photonic Appl. Sci. 2016, 6, 426 17 of 21 designs with lower insertion-loss, higher levels of integration (electrical and MEMs), scalability to many multiples of 25 Gbps channels, and efficient (ideally passive) thermal stabilization. To meet this challenge, researchers in photonic packaging are transitioning from a legacy of individually customized prototypes towards developing standardized and scalable solutions. While these technology innovations of passive Fiber-to-PIC alignment, more precise flip-chip vertical integration, and better thermal-stack design all play an important role, ‘soft’ developments, such as the publication and adoption of packaging standards, as well as the growth and consolidation of the material and component supply-chain, are equally important. The need to create standardized design rules and standards for photonic packaging is slowly gaining recognition in the Si-photonics community. This shift is driven by the benefit of removing application-specific design-burdens from researchers/engineers, and streamlining the design-to-device process. Photonic packaging groups are now working with industry partners to establish packaging design kits (PDKs) and rules (PDRs) that support non-expert users in developing Si-PICs that are compatible with best-practice photonic packaging. This helps new users avoid problems and avoid costly and time-consuming PIC re-designs. Examples of important PDR parameters that are often overlooked by new users are (i) the pitch of grating-coupler arrays on the Si-PIC (which should match the dimensions of the fiber-channels, i.e., 127 µm or 250 µm); (ii) the minimum pitch of the electrical bond-pads should be >100 µm for DC-connections (to maximize yield of wire-bonding) and >300 µm for RF-connections (to eliminate the need for costly ceramic pitch-reducing interposers); and (iii) the need for an ‘exclusion zone’ around grating-coupler array, where no electrical connections or phase-sensitive components are placed, in case of epoxy overflow. Although currently at an early stage of development, it is expected that these PDRs will be extended and formalized into standards over time, and rolled in to the design rule checking (DRC) at Si-foundries. Simple photonic packaging PDKs have already been implemented at a software level in the PIC design tools of PhoeniX BV (OptoDesigner) and Luceda (IPKISS) [65,66].

7. Conclusions Photonic packaging is an essential step in realizing highly integrated Si photonic devices for both small-scale prototyping and commercial mass-production. The packaging of a photonic device is often the most expensive element of the overall module fabrication, and can involve major technical challenges that need to be addressed at the PIC design stage. Simultaneously satisfying the optical, electrical, and thermal design considerations for a PIC requires a ‘joined up’ approach that goes well beyond the most widely recognized issue of Fiber-to-PIC coupling. Researchers in packaging are increasingly working with advanced design tools, and evolving packaging equipment, to meet these challenges. As photonic devices and technologies transition out of the laboratory and into the market, photonic packaging is also maturing to keep pace—its focus is shifting from testing and prototyping towards standardized and scalable commercial implementation.

Acknowledgments: This review paper includes Photonic Packaging developed under several European and Irish research calls, including: FP7-PLAT4M (318178), FP7-FABULOUS (318704), H2020-TIPS (644453), H2020-CARDIS (644798), and SFI/12/RC/2276 and SFI/14/ADV/RC2761 from Science Foundation Ireland. In addition, the authors would like to thank Noreen Nudds, Ken Rogers, and Tony Compagno for their technical assistance in assembling and imaging samples and modules. Author Contributions: This review paper collects the results and contributions from many projects and procedures developed by the Photonic Packaging Group at the Tyndall National Institute in Ireland. L.C. and P.O’B. prepared the review manuscript; J.-S.L. made the grating-coupler measurements; C.S. developed the high-speed electronic interconnects; K.G. made the thermal measurements; M.D. made the Zemax simulations; H.L. developed the VCSEL flip-chip; Y.Z. made the grating-coupler flip-chip measurements; C.E. made the COMSOL simulations; P.M. designed the high-speed transmission lines; M.R. developed the flip-chip and wire-bonding; S.C. prepared the SolidWorks imagery; H.Y.H. developed the Lumerical simulations for evanescent-coupling. Conflicts of Interest: The authors declare no conflict of interest. Appl. Sci. 2016, 6, 426 18 of 21

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