Silicon CMOS-Integrated Nano-Photonics for Computer and Data Communications Beyond 100G

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BEYOND 100G OPTICAL COMMUNICATIONS Silicon CMOS-Integrated Nano-Photonics for Computer and Data Communications Beyond 100G

Yurii A. Vlasov, IBM T. J. Watson Research Center

ABSTRACT dictated by tremendous growth of data traffic in networks due to bandwidth-intensive applica- Five criteria that are usually considered by tions such as virtualization, video on demand, IEEE standards committees for development of the need for massive storage, and the rise of next generation standards are broad market social networking. To meet these demands, the potential, distinct identity, and compatibility, as concept of warehouse-scale datacenters (WSCs) well as technical and economic feasibility. We is being developed [2] with large numbers of consider these criteria separately and show that commodity servers interconnected by massive the new emerging large-volume markets loosely numbers of high-bandwidth optical links [3]. defined as Computercom will demand new stan- While performance, reliability, power efficiency, dards and new technologies. We discuss how the and the like are very important attributes, the balance between single-channel bit rate, and main driving force for wide acceptance of high- number of wavelength multiplexed and spatially bandwidth optical interconnects in WSC data- multiplexed optical channels can help to satisfy centers is the cost efficiency. Novel technologies the need for huge total bandwidth, while keep- like silicon complementary metal oxide semicon- ing cost low and power efficiency high. Silicon ductor (CMOS) integrated nanophotonics CMOS-integrated photonics holds promise to promise to slash transceiver cost from the cur- become a technology of choice for wide deploy- rent few dollars per gigabit per second of ment of low-power and cost-effective optical input/output (I/O) bandwidth to less than a few interconnects for these new markets, and to cents per gigabit per second. These technologies, become a single solution addressing distances if developed in time, will be prone to dominate spanning from just a meter to 10km. the market. The second area, HPCS, is also becoming BROAD MARKET POTENTIAL ready for wide acceptance of massively parallel optical interconnects [4–7]. This is mostly neces- At least two markets are becoming poised for sitated by the ever increasing mismatch between wide deployment of broadband optical commu- computational operations currently reaching 10 nications — burgeoning Internet data centers Peta-floating point operations per second (flops) (IDCs) and high-performance computing sys- and available memory bandwidth that is limited tems (HPCSs). Both are experiencing in recent by severe constraints in providing high-band- years sustainable growth in volumes, revenues width electrical I/O links on cards and between and performance that is envisioned to be limit- racks [5–7]. With this tendency likely to extend ed, among other constraints, by availability of to the next decade, massive numbers of parallel cost-effective and power-efficient optical inter- optical links, on the order of 100 million, is connects [1]. In addition, if a cost-effective opti- expected in the HPCS that will be used to con- cal solution can become readily available, the nect racks, boards, modules, and chips together high-end and mid-range servers market will also [5, 6]. In order to be massively deployed in benefit from understanding that optical intercon- HPCS, optical links must provide reliable com- nects can be a viable business solution for munication while maintaining extremely low replacement of costly and bulky electrical cables power dissipation, on the order of just a few and backplanes. These new opportunities, with pico-Joules per transmitted bit. It is worth men- potential market volumes on the order of mil- tioning that, besides accounting for just electri- lions of parts per year, are forming a new appli- cal-to-optical (EO) and optical-to-electrical The views expressed in cation area that can be loosely called, as a (OE) conversion in transceivers, this power bud- this document are those of follow-up to the more traditional telecom and get should also include all electrical high-speed the author and do not datacom markets, a Computercom. serial (HSS) circuitry required to provide high- necessarily represent the Although these markets’ needs are similar, integrity electrical signaling on a card or module views of IBM Corpora- they are dictated by different economic drivers. for the I/O link. As with cost efficiency, the tion. The expansion of datacenter businesses is mostly power efficiency numbers required for wide

adoption of optical interconnects in the HPCS of HSS links supports 10 Gb/s data rates and, With the new are approximately 20–50 times lower than avail- with the maturation of scaled CMOS technology, able with today’s technology. 28 Gb/s HSS links were developed. However, generation of MM further bandwidth scaling is severely limited by fibers, it is possible DISTINCT IDENTITY CMOS device performance even in the advanced to envision that 28 nm CMOS node, as well as by increasingly AGGREGATE BANDWIDTH difficult and power-hungry equalization that is traditional With the recent adoption of new IEEE 802.3ba required to restore signal integrity and retime at VCSEL/MM links standards for 40 Gb/100 Gb Ethernet [8], some the end of the on-card HSS link even for very of these growth areas are covered, and technolo- short distances of a few inches. Besides consider- can be extended gies and solutions are being currently developed. able additional power dissipation, the retiming beyond current However, it is quite possible that actual growth increases the link latency, which for some appli- 100 m; however, in network traffic will demand earlier deploy- cations is highly undesirable. Therefore, it is ment of WSC datacenters [1–3]. In addition, the likely that the line rates for HSS links will not it is difficult to growth in network traffic will put serious stress increase significantly beyond 25 Gb/s, and the expect the reach on the capability of network switches and routers required IO bandwidth has to be provided to keep up with the pace, and will stress the abil- instead by an increasing degree of paralleliza- approaching 1000m. ity of current backplane architectures to provide tion. necessary connectivity [9]. Current plans for the development of the next generation HPC sys- WAVELENGTH-DIVISION MULTIPLEXING tems that can deliver performance at the Exaflops level (1018 FLOPs) by the end of the To satisfy the bandwidth demands, the degree of decade are also under consideration by govern- WDM has to increase beyond the current four ments in the United States and Japan, followed WDM channels of the 100 GbE standard. WDM by China, Russia, and India. All of these trends technology can potentially provide the terabit will soon call for new standardization cycles for bandwidth offered by an SM fiber, especially 400 Gb and 1 Tb optical interconnects, and will promising at relatively short distances of just a demand an investment in the development of few kilometers where dispersion penalties do not novel technologies that can provide 10–50 times yet play a significant role. However, the number improvement in cost and power efficiency to of WDM channels and, correspondingly, the meet these new market demands [9]. Although it channel spacing will most likely be limited to less is expected that further development of next- than 10 due to cost and power limitations associ- generation optical transceivers based on tradi- ated with the technical solutions that can pro- tional multimode optical fibers and directly vide reliable uncooled operation and a high modulated vertical cavity surface-emitting laser degree of integration. (VCSEL)/multimode (MM) might provide some of this scaling, serious difficulties are envisioned LINK BUDGET to meet aggressive power and cost savings Maintaining the link integrity at longer distances required for future WSC and HPCS, while simul- is always more difficult, and requires more opti- taneously maintaining reliability. cal power and extended link budget than for short-reach interconnects. Since the deployment REACH of a new generation of optical links will happen The current 100GbE standard regulates either in a controlled environment of a large datacen- short-reach VCSEL/MM-based links for less ter or, even better, in controlled buildings specif- than 100 m distances or single-mode (SM) links ically designed to host HPCSs, the 6–11 dB link serving over 10 km distances. For WSC and budget typical for 100 GbE long reach applica- Exascale HPCS markets, intermediate distances tions might be excessive and not economically are of interest covering distances from a few viable. Even assuming the optimistic power slope meters up to 2 km [10]. Growth in these markets efficiency of the next generation DFB laser has already been identified as a gap needing to arrays exceeding 20–30 percent and assuming be filled by new standards and new technologies 3–5 dBm of laser power per channel, the inser- [9]. With the new generation of MM fibers, it is tion loss for transmitter and receiver would most possible to envision that traditional VCSEL/MM likely reduce the budget to a moderate 2–3 dB links can be extended beyond the current 100 m; [10]. Cost-effective packaging can be a dominat- however, it is difficult to expect the reach to ing factor for improvement of the link budget approach 1000 m. New technologies are needed since it will be mostly limited by coupling losses to fill this gap that starts to appear, including from the DFB laser to the photonic integrated directly modulated SM VCSELs, directly modu- circuit chip. lated (DML) distributed feedback (DFB) lasers, and silicon photonics [11]. SILICON CMOS-INTEGRATED LINE RATE ANOPHOTONICS ECHNOLOGY The bandwidth bottleneck characteristic for both N T : WSC datacenters and Exascale HPCS first TECHNICAL FEASIBILITY occurs at the edge of the card. The application- specific integrated circuit (ASIC) or high-perfor- New technology is rising that holds a strong mance processor chips send high-bandwidth I/O promise to revolutionize short-reach optical signals through the HSS links to the card edge interconnects: silicon CMOS-integrated photon- where optical transceivers are responsible for the ics [12–23]. This promise is connected with the EO-OE data conversion. The current generation benefits of monolithic integration of optical and

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electrical circuitry on a single silicon die utilizing mature CMOS semiconductor IC technology. If successful, such integration might result in signif- WDM DFB arrays icant cost reduction and highly increased integration density of optical interconnects based on λ λ λ 0 1 N Y times spatial multiplexing very-low-power and highly reliable CMOS-inte- Coupler grated optical transceivers. Various approaches REFCLK have been explored lately from building optical 25G circuits like modulators and photodetectors in TXN CDR DRV MZI the CMOS front-end of the line (FEOL) [12–15] 25G SMF to adding additional low-temperature processing TX1 CDR DRV MZI WDM

N :1 MUX SMF 25G steps at the back-end of the line (BEOL) after TX0 CDR DRV MZI SMF completion of the CMOS process [16]. Several products utilizing some of these approaches are Single Si nonophotonics chip already appearing, mostly targeting the active CDR 25G Ge PD optical cable market [12]. RXN TIA/LA Over the last several years, IBM has devel- 25G PSR SMF RX1 oped a variant of silicon photonics technology CDR TIA/LA Ge PD WDM SMF 25G Y times fiber ribbon called CMOS-integrated silicon nanophotonics RX0 CDR TIA/LA Ge PD N :1 DeMUX SMF [13, 14]. This technology allows monolithic integration of deeply scaled optical circuits into the Control IO FEOL of a standard sub-100-nm CMOS process. Micro-controller The infrared light signals propagate inside silicon waveguides with submicron dimensions on a silicon-on-insulator (SOI) die. These optical circuits share the same silicon device layer with the bodies of nearby metal oxide semiconductor Figure 1. Potential implementation of a single die CMOS-integrated silicon field effect transistors (MOSFETs). Several pro- nanophotonics WDM transceiver. N wavelength channels are muxed/demuxed cessing modules have been developed and added in a single SM fiber. The polarization splitter and rotator (PSR) on the receiver into a standard CMOS FEOL processing flow. side allows signals to be received from SM fiber having random polarization. For example, to build a high-performance Ge Splitting the laser power Y times or additional Y laser arrays allows the total photodetector, a “Ge-first” integration module bandwidth to be increased 25G × N × Y times. was developed using a rapid melt growth tech- nique concurrent with the source-drain anneal CMOS TECHNOLOGY NODE: step [17]. These modules require a minimal number of additional unique masks and process- PHOTONICS SCALING ing steps, while sharing most mask levels and Most current demonstrations and existing prod- processing steps with the rest of the convention- ucts utilizing silicon photonics are using relative- al CMOS flow. For example, passive optical ly old technology nodes like 130 nm [12–14] or waveguides and thermo-/electro-optic modula- even older nodes [23]. Some work has been tors require only the addition of a single addi- done in advanced CMOS nodes such as 32 nm tional mask to the process flow, since they share [15]; however, they are limited, at the moment, the same silicon device layer with the CMOS to early exploratory demonstrations. The choice positive channel FETs (pFETs) and negative of the best technology node for development of channel FETs (nFETs). next-generation optical transceivers based on Utilization of advanced scaled CMOS tech- CMOS-integrated nanophotonics is dictated by nology for fabrication of nanophotonics circuits consideration of development and manufactur- allows the control of optical nanophotonics ing costs, as well as the resulting performance waveguide dimensions to within a few nanome- limitations due to the corresponding CMOS gen- ters, opening the way to build very dense opti- eration. cal circuitry. Indeed, the demonstrated optical Obviously, the development of a derivative devices, such as wavelength-division multiplex- technology such as silicon photonics is less costly ers [18], high-speed electro-optical modulators in the relatively old and mature CMOS technol- [19], germanium photodetectors [17], and fiber ogy nodes. The feature size of scaled silicon pho- edge couplers [20], are all working close to the tonic waveguides, around 400–500 nm, is large optical diffraction limit. Silicon CMOS-integrat- enough that even relatively old 248 nm lithogra- ed nanophotonics have shown on-die densities phy tools can easily resolve it. However, old below 0.5 mm2/channel, enabling the develop- technology nodes lack the advanced control over ment of terabit-per-second-class transceivers such lithographically defined critical dimensions with up to 40 parallel transceiver channels pro- (CDs) that is required for high yield of silicon viding 25 Gb/s bandwidth each that can all be photonics devices and circuits. The variability of integrated on a single CMOS die with an area CDs has the strongest impact on WDM silicon as small as 5 × 5 mm2. However, electrical I/O photonics devices based on light interference, routing issues for the whole package also have such as arrayed waveguide gratings [21], Echellet to be considered, as discussed later. With such gratings [18], and ring resonators, the perfor- integration density, the area occupied by optical mance of which is strongly affected by the result- circuitry is becoming comparable to or some- ing random phase (path length difference) times even smaller than that occupied by errors. Indeed, 3σ variation of CDs of just 10 accompanying analog and digital CMOS cir- nm results in unacceptably high crosstalk levels cuits. between WDM channels, necessitating the intro-

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for silicon nanophotonics transceivers. As men- 1.0 tioned above, line rates around 25 Gb/s are envi- 2 1mm sioned to dominate the Computercom markets for the foreseeable future; therefore, sub-100-nm

40 Four-channel LAN WDM size (mm) CMOS technologies starting from 90 nm and above should be considered. CMOS technology beyond 90 nm can provide respectable FT above 140 GHz, high enough to yield AMS circuits working above 20 Gb/s [22]. However, the very substantial benefits of CMOS scaling for digital 2 25 0.25mm 25G 0.5 CMOS devices do not necessarily translate into benefits for the AMS circuits. Although the further increase in FT makes the design of fast broadband amplifiers easier and more robust, CMOS LA line rate (Gb/s) the footprint and power scaling of the AMS cir- 10G cuits is significantly slower than those of their 10 0.04mm2 digital counterpart. From these considerations, 0.1 the technology nodes beyond 65 nm might not necessarily provide the expected returns in performance and power scaling, and the benefits of 180 130 90 65 3245 more advanced technology nodes therefore are CMOS technology node (nm) countered by significantly increased development and manufacturing costs. Figure 2. Choice of CMOS technology node for implementation of silicon CMOS-integrated nanophotonics transceivers. The CMOS AMS circuit’s line LASER SOURCE rate scales with a technology node reaching 25 Gb/s around a 90–65 nm node. One of the integral parts of optical transceivers The photonics circuit area scales down to a diffraction-limited footprint based on silicon photonics is the compact and around 90–65 nm and stays constant. For comparison, a four-channel LAN cost-efficient laser. Traditional VCSEL lasers WDM device based on cascaded MZI filters is chosen. In this case the mini- are very difficult to couple to in-plane photonics mal waveguide width and minimal bending radius that both can yield in a cor- circuits, and most commercial devices are MM, responding CMOS node define the device footprint. which makes it very difficult to utilize in WDM systems. As opposed to traditional transceivers based on directly modulated VCSELs or DML duction of active thermal tuners to compensate DFB lasers, the laser source for integrated sili- for such fabrication errors [21]. Utilization of con photonics is considered instead as an opti- 193 nm lithography in advanced CMOS nodes cal power supply [12–14]. In direct analogy to allows for minimization of the effects of phase the electrical power supply that provides electri- errors on WDM crosstalk, and results in an cal energy to other parts of the system, the opti- increase in the yield of photonic devices with cal power supply is a source of constant light acceptable die-to-die and wafer-to-wafer vari- power coupled to the silicon photonics chip. ability. Porting the silicon photonics technology Although several recent developments indicate to more advanced CMOS nodes will decrease that such a laser can be integrated on a silicon significantly the effect of random phase errors photonics chip using advanced bonding tech- and increase the yield even further. niques [23], the manufacturability in CMOS These benefits of advanced CMOS technolo- foundry, its power efficiency, temperature stabil- gy nodes can, however, be completely negated by ity and reliability all remain grossly unexplored. significantly increasing development and manu- Instead, the DFB laser that is separate from the facturing costs (masks, process development, CMOS die is usually considered to be the best step charges, etc.). On the other hand, the choice. Either it resides in a separate package advantages of standard CMOS scaling, such as and is coupled to the silicon photonics transceiv- shrinking of the electronic circuit footprint and er via a fiber, or alternatively, it can be co- decreasing power consumption, are not necessar- assembled with the silicon photonics die in the ily extendable to scaled silicon nanophotonics same package [12]. However, the market growth circuits. The footprint of silicon nanophotonics demands more advanced schemes in which mul- devices based on dielectric confinement is not tiple-wavelength light sources enable simultane- scalable below the diffraction limit, and the ous operation of multiple WDM channels. power dissipation is almost independent of the Although arrays of DFB lasers with up to 12 size. Therefore, there is a range of CMOS tech- channels are commercially available [24], fur- nologies that can be considered as optimal for ther significant development is needed to adopt development of silicon nanophotonics that on this technology for implementation in terabit- one hand utilize the advanced CD control per-second-class silicon photonics-based offered by 193 nm lithography, and on the other transceivers. offer reduced costs. PACKAGING CMOS TECHNOLOGY NODE: CMOS SCALING Integration of optical components on a single The radio frequency (RF) performance of broad- silicon die using mature CMOS technology in a band analog and mixed signals (AMS) CMOS mature commercial CMOS foundry allows for circuits like TIA/LA amplifiers and modulator significant decrease in the cost of optical com- drivers is probably the main consideration for ponents in the total bill-of-material (BOM) the choice of the best CMOS technology node costs for optical transceivers. As a result, the

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cost of the final transceiver solution will mostly standards have to be adopted that might not be defined not by the BOM, but rather pre- necessarily be compatible with already deployed CMOS-integrated sili- dominantly by the cost of packaging and test- technologies and might expand into different ing. Active alignment and part-by-part assembly wavelength bands. con nanophotonics of many discrete components into a single pack- technology can age, as widely done in the optoelectronics ON-BOARD ELECTRICAL enable this new gen- industry today, must therefore be avoided. INTERCONNECTS DENSITY Instead, adoption of pick-and-place automated eration of optical packaging practices utilized in the microelec- The on-chip integration density might not neces- interconnects. Once tronics industry for packaging of silicon chips sarily directly translate into a reduction in form must be considered to make the resulting factor of a packaged transceiver. Indeed the ulti- mature, the silicon transceiver solution cost effective. For example, mate integration density for Si CMOS nanopho- photonics-based flip-chip bonding techniques can be adopted. tonics is limited by the pitch in the BGA array, optical links can With a Pb-free solder reflow, the silicon which for scaled CMOS nodes, can be less than nanophotonics transceiver chip terminated with 0.2 mm. The 40-channel flip-chip bonded pack- serve a variety of a standard ball grid array (BGA) can be flip- aged transceiver that can provide a total of 1 markets, from those chip bonded directly onto a laminate PCB Tb/s bidirectional bandwidth can therefore offer board, very much like all other surface-mount- on-board densities on the order of 0.5 mm2/chan- requiring 2–5 km of ed electrical components. nel. However, clearly, in order to realize such a reach to optical concept the transceiver should be at least as reli- backplanes covering OMPATIBILITY able as other more expensive parts of the net- C work interface card (NIC) or the PCB board distances as short as In general, the multitier legacy network was itself. Therefore, such pitch density can be just a meter. always a serious barrier for deployment of new achievable only in systems where cost effective- technologies and adoption of new standards. ness is the priority, while reliability can be to The adoption of Si CMOS-integrated nanopho- some extent mitigated. Otherwise, optical tonics can be severely limited, and its perfor- transceivers have to be developed as field mance and cost benefits can be negated by replaceable units (FRUs), hence making the several important technology attributes that form factors be driven now by the available land are incompatible with existing legacy infra- grid array (LGA) pitch, which is typically around structure. 1–2 mm. With the 1 mm LGA pitch, the pin-limited area to provide 40 high-bandwidth electrical SINGLE-MODE FIBER CABLES AND differential pairs is something like 15 × 15 mm2, CONNECTORS limiting the on-board areal density to 6 mm2/channel. If the standard 2 mm pitch LGA Current parallel optical interconnects are mostly substrates are used, the PCB area needed for based on multimode fiber technology. Not only the transceiver grows to 30 × 30 mm2 with areal does this technology operate in the 850–950 nm density 20 mm2/channel. This is about 40 times wavelength range, but it is also serial, and requires larger than that given by the technology itself. a large number of parallel MM fiber cables and multicore fiber connectors for further bandwidth ONCLUSION scaling. Silicon photonics is an inherently single- C mode technology and, as such, requires a mature New emerging markets of WSC datacenters and ecosystem that can provide ribbonized SM fiber HPCSs produce a demand for medium-reach cables and cost-effective SM multicore connec- single-mode WDM optical links capable of deliv- tors. Although these technologies are already ering high-bandwidth traffic beyond 100GbE. commercially available today, they need to CMOS-integrated silicon nanophotonics technol- become more mature to be able to provide the ogy can enable this new generation of cost-effec- expected large volumes with significantly reduced tive and low-power optical interconnects. Once costs and increased reliability. mature, the silicon photonics-based optical links can serve a variety of markets, from those requir- OPERATING WAVELENGTH ing 2–5 km of reach to optical backplanes cover- Currently explored silicon CMOS-integrated ing distances as short as just a meter. photonics solutions are utilizing laser sources developed for the fiber to the home (FTTH) ACKNOWLEDGMENTS market; hence, the wavelength of choice is usual- The author gratefully acknowledges numerous ly 1490 nm [12]. A moderate number of parallel fruitful discussions with long-term collaborators optical channels can be powered by a single laser and colleagues at IBM Watson Research Center operating at this wavelength, thus optimizing the — William Green, Solomon Assefa, Tymon Bar- power efficiency. With further development of wicz, Alan Benner, Alexander Rylyakov, Clint silicon photonics WDM transceivers, the choice Schow, Joe Cahill, Dan Dreps, and many, many of center wavelength and spacing between chan- others. Special thanks to Jonathan Proesel, nels will be dictated by the choice of cost-effec- Jessie Rosenberg, and Douglas Gill for careful tive DFB laser arrays and the availability of reading of the manuscript. cost-effective cooling solutions. Backward compatibility with the 100 Gb-LR4 components REFERENCES would require adopting a LAN WDM or coarse [1] S. Lawson, “Facebook Sees Need for Terabit Ethernet,” WDM (CWDM) wavelength grid centered IDG News Service, Feb. 02, 2010, http://www.network- around 1310 nm wavelength. However, with the world.com/news/2010/020310-facebook-sees-need-for- increase of WDM parallelization, new channel terabit.html.

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Green et al., “CMOS integrated Silicon also was, for over a decade, a research scientist with the Nanophotonics: Enabling Technology for Exascale Com- Ioffe Institute of Physics and Technology in St. Petersburg, putational Systems,” Proc. SEMICON, Chiba, Japan, Russia, working on semiconductor nanophotonics since Dec. 1–3, 2010, available: http://www.research.ibm. 1988. He received his M.S. from the University of St. com/photonics. Petersburg (1988) and his Ph.D. from the Ioffe Institute [14] S. Assefa et al., “CMOS Integrated Silicon Nanopho- (1994), both in physics. He has published over 100 journal tonics: Enabling Technology for Exascale Computational papers, filed over 40 U.S. patents, and delivered over 150 Systems,” Opt. Fiber Commun. Conf., Los Angeles, CA, invited and plenary talks in the area of nanophotonic struc- 2011, Paper OMM6. tures. He served on numerous organizing committees of [15] J. S. Orcutt and R. J. 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