L13 X86 History

Binghamton CS-220 University Spring 2019 X86 An Historical Perspective Computer Systems: Section 4.1 Binghamton CS-220 University Spring 2019 ISA Compatibility • It’s nice to have the same software run on different hardware • It’s nice to have the apps I wrote for iPhone6 run on iPhoneX • But different hardware has different capabilities • I can do more things on an iPhoneX than an iPhone6 • How can we manage this change? Binghamton CS-220 University Spring 2019 Backward Compatibility • If something is backward compatible • It will do everything it used to do • It may be able to do more iPhone X iPhone 6 iPhone 6 • Implications … • Things can only get more complex • Every “mistake” made early propagates forever • Eventually, things get really complicated Binghamton CS-220 University Spring 2019 Intel Microprocessor Milestones Date Chip Data Width Transistors Clock Rate Usage 1972 8008 8 3.5K 0.8 MHz Monitors, Controllers 1974 8080 8 (some 16) 6K 2 MHz + Calculators 1978 8086 16 29K 10 MHz IBM PC/DOS – First x86 1985 80386 32 275K 40 MHz IBM PC-AT - Windows+Linux 1993 Pentium P5 32 3.1M 66 MHz IBM Personal Computer 2004 Pentium 4F 64 125M 3.8 GHz IBM ThinkCenter 2008 Core i7 64 731M 3.33 GHz Lenovo Thinkpad 2014 Core i7 extreme 64 1.4B 3.5 GHz Lenovo Ultrabook Binghamton CS-220 University Spring 2019 1972 Intel 8008, 8 bit word - Calculators 16 Origin 8 %ax %ah %al Accumulate %cx %ch %cl Counter %dx %dh %dl Data %bx %bh %bl Base Binghamton CS-220 University Spring 2019 1978 Intel 8086, 16 bit word – Vanilla PC 16 Origin 8 %ax %ah %al Accumulate %cx %ch %cl Counter %dx %dh %dl Data %bx %bh %bl Base %si Source Index %di Destination Index %sp Stack Pointer %bp base Pointer Binghamton CS-220 University Spring 2019 1985 - 80386 32 bit word - PC/XT 32 16 Origin 8 %eax %ax %ah %al Accumulate %ecx %cx %ch %cl Counter %edx %dx %dh %dl Data %ebx %bx %bh %bl Base %esi %si Source Index %edi %di Destination Index %esp %sp Stack Pointer %ebp %bp base Pointer Binghamton CS-220 University Spring 2019 ~2000 – AMD AMD64 – 64 bit word 64 32 16 Origin 8 %rax %eax %ax %ah %al Accumulate %rcx %ecx %cx %ch %cl Counter %rdx %edx %dx %dh %dl Data %rbx %ebx %bx %bh %bl Base %rsi %esi %si Source Index %rdi %edi %di Destination Index %rsp %esp %sp Stack Pointer %rbp %ebp %bp base Pointer Binghamton CS-220 University Spring 2019 41 Years of Intel x86 Evolution Architectures Intel Processors X86-16 8086 1978 80286 1982 X86-32/IA-32 80386 1985 80486 t 1989 Pentium i 1993 MMX Pentium II m 1997 SSE Pentium III 1999 SSE2 e Pentium 4 2000 Pentium M 2003 SSE3 Pentium 4F 2004 Core 2 Duo 2006 SSE4 Core i7 2008 X86-64 / EM64t Sandy Bridge 2011 Sky Lake 2015 Xeon Phi 2016 Coffee Lake 2018 Binghamton CS-220 University Spring 2019 Assembly Programmer’s View of x86 CPU Memory • Programmer-Visible State Addresses • IP: Instruction Pointer Registers RIP “Stack” • Address of next instruction Data • “%rip” (x86-64) Condition Instructions • Register file Codes ALU Object Code • Heavily used program data Program Data • Condition codes OS Data • Store status information about most recent arithmetic operation • Used for conditional branching • Memory • Arithmetic/Logic Unit (ALU) • Byte addressable array • Performs Instructions • Code, user data, (some) OS data • Includes stack used to support procedures.

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