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Ez80f91 MCU Product Brief

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Ez80f91 MCU Product Brief ® eZ80Acclaim! Flash Microcontrollers eZ80F91 MCU Product Brief PB013505-0607 Product Block Diagram • IrDA-compatible infrared encoder/decoder • Two universal asynchronous receiver/ eZ80F91 MCU transmitter (UARTs) with independent baud rate generators 256 KB Flash + 32-Bit GPIO 2 512 B Flash • Inter-integrated circuit (I C) and serial peripheral interface (SPI) with independent 10/100 Mbps clock rate generator 8 KB SRAM Ethernet MAC • Four counter/timers with prescalers supporting 8 KB Frame Buffer event counting, input capture, output compare, Infrared and Pulse Width Modulator (PWM) modes Encoder/ 2 UART I2C SPI • Watchdog Timer (WDT) with internal RC Decoder clocking option Real Time • Real time clock (RTC) with on-chip 32 KHz 4 PRT WDT oscillator, selectable 50/60 Hz input, and Clock separate RTC_VDD pin for battery backup 4 CS JTAG ZDI PLL • Glueless external memory interface with 4 + WSG Chip-Selects/Wait-State Generators and external WAIT input pin. It also supports Intel® and Motorola® buses Key Features • JTAG and ZiLOG Debug Interface (ZDI) sup- The eZ80F91 MCU is a member of ZiLOG’s porting emulation features ® eZ80Acclaim! product family which offers • Low-power PLL and on-chip oscillator on-chip Flash versions of ZiLOG’s eZ80® processor core. The eZ80F91 MCU offers the • Programmable-priority vectored interrupts, following features: non-maskable interrupts, and interrupt controller • 50 MHz high-performance eZ80® CPU • New DMA-like eZ80® CPU instructions • 256 KB Flash Program Memory and extra 512 B device configuration Flash Memory • Power management features supporting HALT/SLEEP modes and selective peripheral • 32 bits of General-Purpose Input/Output power-down controls (GPIO) • 144-pin BGA package or 144-pin LQFP • 16 KB total on-chip high-speed SRAM: package – 8 KB for general-purpose use • 3.0 V to 3.6 V supply voltage with 5 V – 8 KB for 10/100 BaseT Ethernet Media tolerant inputs Access Controller (EMAC) high-speed frame buffer Copyright ©2007 by ZiLOG, Inc. All rights reserved. www.zilog.com eZ80F91 MCU Product Brief 2 • Operating temperature ranges: • Endurance, 10,000 write cycles (typical) – Standard, 0 ºC to +70 ºC • The data can be retained for more than – Extended, –40 ºC to +105 ºC 100 years at room temperature In addition, 16 KB of high-speed, relocatable General Description SRAM is available and 8 KB is for general- The eZ80F91 MCU is industry’s first MCU purpose use. Another 8 KB is used by the EMAC featuring a high-performance 8-bit microcontroller for Ethernet operation, but is also user-accessible with an integrated 10/100 BaseT EMAC. It is a when Ethernet functionality is not required. power-efficient, optimized pipeline architecture General-Purpose Input/Output microcontroller with a maximum operating speed of 50 MHz. Offering on-chip Flash Memory, There are 32 bits of GPIO. All GPIO pins are SRAM, Ethernet MAC, and rich peripherals, the individually programmable and support the eZ80F91 is well-suited for industrial, communica- following I/O modes: input, output, open drain, tion, automation, security, and embedded Internet open source, level-triggered interrupts (High or applications. Low), edge-triggered interrupts (High or Low), dual edge-triggered interrupts, and alternate eZ80® CPU Core function. Eight of the output pins can drive 10 mA each (Port A), while 16 other pins feature ® The eZ80 CPU operates either in Z80-compatible Schmitt-trigger input buffers (Port B and Port C). (64 KB) mode or full 24-bit (16 MB) addressing mode. Considering both the increased clock speed 10/100 BaseT Ethernet MAC and processor efficiency, the processing power of The eZ80F91 MCU features an integrated IEEE eZ80® competes with the performance of 16-bit 802.3 Ethernet controller with 8 KB of microprocessors. The eZ80® improves on the dynamically-configurable Tx/Rx frame buffer. It world-famous Z80® architecture. Like Z80® , supports speed of 10 Mbps and 100 Mbps, full eZ80® CPU features dual bank registers for fast duplex operation, and an industry-standard Media context switching. Independent Interface (MII) for simple connection to an external Physical Layer interface (PHY) eZ80F91 MCU Peripherals device. The eZ80F91 delivers high performance Description and overall cost effectiveness as an embedded network microcontroller. The peripherals of eZ80F91 MCU includes the following: High performance is achieved by optimizing the internal bus design of the eZ80® CPU with shared On-Chip Memory memories, dedicated Ethernet Tx/Rx DMAs, and The eZ80F91 device offers 256 KB of Flash Tx/Rx FIFOs. This bus design provides the highest Program Memory. A separate page of 512- bytes data throughput over the Ethernet interface, yet Flash Memory is available for general device requires minimum eZ80® CPU intervention and configuration data. Other on-chip memory features minimizes system loading. include: Infrared Encoder/Decoder • Single power supply operation • Supports IrDA SIR format • Page erase feature, 2048 bytes/page • Operates seamlessly with on-chip UART • Fast page erase and byte program operation • Interfaces with IrDA-compliant transceivers • 78 ns minimum read cycle • Supports transmit/receive to 115 Kbps PB013505-0607 eZ80Acclaim!® Flash Microcontrollers eZ80F91 MCU Product Brief 3 Universal Asynchronous Receiver/Transmitter action of the WDT is user-programmable for either Each of the two UART channels contains a a hardware reset or a non-maskable interrupt to the ® transmitter, a receiver, control logic/registers, and a eZ80 CPU. The source of action taken after a Baud Rate Generator (BRG). WDT time-out is indicated by a WDT status bit. • The BRG produces a lower-frequency bit clock Real Time Clock from the system clock. All standard baud rates The RTC allows counting of seconds, minutes, up to 115 Kbps (and higher) are supported. hours, day-of-the-week, day-of-the-month, month, • The UART module implements the logic year, and century. Alarms and interrupts can be set required to support asynchronous communica- for seconds, minutes, hours, and day-of-the-week. tions, hardware flow control, and 9-bit charac- The RTC input is taken either from the on-chip ter format. The module also contains separate 32 KHz oscillator or from a 50/60 Hz input. The 16-byte-deep transmit and receive FIFOs. RTC operates from an isolated RTC_VDD pin to allow constant operation from a battery. Inter-Integrated Circuit The I2C channel contains control registers and a Chip-Select/Wait State Generator and WAIT Pin clock rate generator. The I2C interface operates in Four independent chip selects facilitate glueless four modes: Master Transmit or Receive and Slave interface to system memory and external devices. Transmit or Receive. A standard and fast I2C speed Each chip-select can be configured for up to 7 wait of 100 kbps and 400 kbps are supported. states and supports either memory or I/O space. Memory chip selects can be individually Serial Peripheral Interface programmed on a 64 KB boundary. I/O chip The SPI channel contains control registers and a selects can choose a 256 byte section of I/O space. clock rate generator. The SPI is a synchronous The WAIT input pin allows interface with slow serial interface allowing multiple SPI devices to be peripherals. It also supports Z80® , Intel®, and interconnected. The SPI interface is configured to Motorola® bus modes. function either as a master or a slave. JTAG Interface Programmable Reload Timers An IEEE 1149.1-compatible five-pin test access The eZ80F91 MCU provides four independent port (TAP) is provided to interface with on-chip Programmable Reloadable Counter Timers (PRT) test logic defined by IEEE standard. The TAP also to handle complex timing functions. Each timer is includes Boundary Scan functions and is used to a 16-bit downcounter and offers a 4-bit clock control on-chip emulation/debugging capabilities. prescaler with four selectable taps for CLK ÷ 4, Some features include software break points, CLK ÷ 16, CLK ÷ 64 and CLK ÷ 256. The timers 64-word trace buffer, complex break points using operates in basic mode supporting SINGLE-PASS address and data masks, and cascadable triggers. or CONTINUOUS count. Additional features include 4 input captures, 4 output compares, PLL and On-Chip Crystal Oscillator 2 external event counters, and 4 PWMs that can The eZ80F91 MCU features a low-power, operate independently or in unison. Any one of the programmable PLL that can be selected to generate input capture pins can be programmed as master the system clock. Taking the input from the PWM power-trip inputs. on-chip crystal oscillator, the PLL generates system clock speed up to 50 MHz from low-cost, Watchdog Timer low-frequency external crystals in the range of The WDT features four programmable time-out 1 MHz to 10 MHz. periods. It operates either from the main system clock, the on-chip 32 KHz oscillator (from the RTC), or the internal RC oscillator. The time-out PB013505-0607 eZ80Acclaim!® Flash Microcontrollers eZ80F91 MCU Product Brief 4 ZiLOG Debug Interface Electrical Features Summary The ZiLOG Debug Interface (ZDI) incorporates • Power supply, 3.3 V ± 0.3 V the functions of an in-circuit emulator. ZDI allows you to single-step code, change registers, edit • Standard temperature, 0 ºC to 70 ºC programs, and view status of the internal registers. • Extended temperature, –40 ºC to +105 ºC Block Transfer Instructions • Supply current at 50 MHz; 50 mA (typical) Block transfer instructions with expanded repeat ® • Supply current in HALT mode with peripherals capability are added to the eZ80 CPU. They powered down; <5 mA (typical) provide high-performance data transfer similar to hardware DMAs. • Supply current in SLEEP mode; <50 µA (typical) Power Management Support Tools The eZ80F91 MCU supports several power management features. Two peripheral The following development tools are available to Power-Down Registers allow independent clock program and debug the eZ80F91 MCU: gating of on-chip peripherals under software Hardware control while operating under normal conditions.
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