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Hardware Design with VHDL Hardware Design with VHDL Hardware Design with VHDL An Introduction (created by Ronald Hecht) Henning Puttnies and Eike Schweißguth University of Rostock Institute of Applied Microelectronics and Computer Engineering April 4, 2016 Hardware Design with VHDL Outline Outline 1 Introduction 2 VHDL for Synthesis 3 Simulation with VHDL 4 Frequent Mistakes 5 Advanced Concepts Hardware Design with VHDL Introduction Outline 1 Introduction 2 VHDL for Synthesis 3 Simulation with VHDL 4 Frequent Mistakes 5 Advanced Concepts Hardware Design with VHDL Introduction Hardware Description Languages What are HDLs? Modeling language for electronic designs and systems VHDL, Verilog PALASM, ABEL Net list languages such as EDIF, XNF Test languages such as e, Vera SystemC for hardware/software co-design and verification Hardware Design with VHDL Introduction Hardware Description Languages HDL for . Formal description of hardware Specification on all abstraction layers Simulation of designs and whole systems Design entry for synthesis Standard interface between CAD tools Design reuse Hardware Design with VHDL Introduction Hardware Description Languages Design methodology Design Entry Test Development Functional Simulation Synthesis Place & Route Timing Simulation Hardware Design with VHDL Introduction Hardware Description Languages Pros and Cons of HDLs Pros Speeds up the whole design process Powerful tools Acts as an interface between tools Standardized Design reuse Cons Learning curve Limited support for target architecture Hardware Design with VHDL Introduction Abstraction Levels Design Abstraction Levels Performance Specifications Behavior Test Benches Sequential Descriptions State Machines Register Transfers Abstraction Data Flow Level Selected Assignments Synthesizable Arithmetic Operations Boolean Equations Structure Hierarchy Physical Information Behavior Sequential statements, implicit registers Data flow Register transfer level (RTL), Parallel statements, explicit registers Structure Design hierarchy, Wiring components Hardware Design with VHDL Introduction Abstraction Levels HDL Abstraction Levels Abstraction Level PLD Language Verilog VHDL SystemC Hardware Design with VHDL VHDL for Synthesis Outline 1 Introduction 2 VHDL for Synthesis 3 Simulation with VHDL 4 Frequent Mistakes 5 Advanced Concepts Hardware Design with VHDL VHDL for Synthesis A First Example A First Example Multiplexer library ieee ; use ieee . std logic 1164 . all ; entity mux is port ( a[3:0] 0 a, b : in std logic vector (3 downto 0); o[3:0] s : in std logic ; b[3:0] 1 o : out std logic vector (3 downto 0)); end mux; s architecture behavior of mux is begin −− behavior o <= a when s = '0' else b; end behavior; Hardware Design with VHDL VHDL for Synthesis A First Example Library library ieee ; use ieee . std logic 1164 . all ; Makes library ieee visible Use objects within the library Use package std logic 1164 Makes std logic and std logic vector visible Hardware Design with VHDL VHDL for Synthesis A First Example Entity entity mux is port ( a, b : in std logic vector (3 downto 0); s : in std logic ; o : out std logic vector (3 downto 0)); end mux; Defines the name of the module Describes the interface Name of the ports Direction Type Hardware Design with VHDL VHDL for Synthesis A First Example Architecture architecture behavior of mux is begin −− behavior o <= a when s = '0' else b; end behavior; Implements the module Behavior Structure RTL description Entity and architecture are linked by name (mux) Name of architecture (behavior) More than one architecture per entity allowed Hardware Design with VHDL VHDL for Synthesis Combinational Logic Parallel Processing Half Adder a library ieee ; s use ieee . std logic 1164 . all ; b entity half adder is co port ( a, b : in std logic ; s, co : out std logic ); end half adder ; Implicit gates Signals are used to wire architecture rtl of half adder is gates begin −− rtl s <= a xor b; Computes signals s and co <= a and b; co from a and b in parallel end rtl ; Hardware Design with VHDL VHDL for Synthesis Combinational Logic Full Adder entity full adder is ci port ( a s2 a, b, ci : in std logic ; s b s1 s, co : out std logic ); c2 end full adder ; co c1 architecture beh par of full adder is signal s1, s2, c1, c2 : std logic ; begin −− behavior All statements are processed −− half adder 1 s1 <= a xor b; in parallel c1 <= a and b; A signal must not be driven −− half adder 2 s2 <= s1 xor ci; at two places c2 <= s1 and ci; −− evaluate s and co Order of statements is s <= s2; irrelevant co <= c1 or c2; end beh par; Hardware Design with VHDL VHDL for Synthesis Combinational Logic Sequential Processing { Processes All statements are architecture beh seq of full adder is processed sequential begin −− beh seq Sensitivity list (a, b, ci) add: process (a, b, ci ) variable s tmp, c tmp : std logic ; Multiple variable begin −− process add assignments are allowed −− half adder 1 s tmp := a xor b; Order of statements is c tmp := a and b; −− half adder 2 relevant c tmp := c tmp or (s tmp and ci ); Variables are updated s tmp := s tmp xor ci ; −− drive signals immediately s <= s tmp; Signals are updated at the co <= c tmp; end process add; end of a process end beh seq; Try to avoid multiple signal assignments Hardware Design with VHDL VHDL for Synthesis Combinational Logic Parallel versus Sequential Processing p1: process (a, b) begin −− process p1 −− sequential statements process p1, process p2 and o are −− ... −− drive process outputs processed in parallel x <= ... Statements within processes are end process p1; sequential p2: process (c, x) begin −− process p2 Inter-process communication −− sequential statements with signals −− ... −− drive process outputs Signal values are evaluated y <= ... recursively in zero time end process p2; Simulator uses delta cycles −− drive module outputs o <= x or y; Hardware Design with VHDL VHDL for Synthesis Combinational Logic Real time and delta cycles ∆ Delta time Real time t/ns Hardware Design with VHDL VHDL for Synthesis Combinational Logic Signals and Variables Signals Inside and outside processes Communication between parallel statements and processes Only the last assignment within a process is evaluated Signal is updated at the end of a process Signals are wires Variables Inside processes only For intermediate results Multiple assignments allowed Immediate update Hardware Design with VHDL VHDL for Synthesis Structural Description Structural Description Module composition Wiring of Modules Design Hierarchy \Divide and conquer" ci a s s_out half s1 adder c2 a_in a s b co half co_out adder c1 b_in b co Hardware Design with VHDL VHDL for Synthesis Structural Description architecture structural of full adder is component half adder port ( a, b : in std logic ; s, co : out std logic ); end component; signal s1, c1, c2 : std logic ; begin −− structural Make module half adder half adder 1 : half adder known with component port map ( a => a in, b => b in, declaration s => s1, co => c1); Module instantiation half adder 2 : half adder Connect ports and signals port map ( a => ci, b => s1, s => s out, co => c2); co out <= c1 or c2; end structural ; Hardware Design with VHDL VHDL for Synthesis Storage Elements Register entity reg is port ( d, clk : in std logic ; dq q : out std logic ); end reg; clk architecture rtl of reg is begin −− rtl Sensitivity list only contains the reg: process (clk) clock begin −− process reg if rising edge (clk) then Assignment on the rising edge q <= d; of the clock end if ; end process reg; Not transparent end rtl ; Hardware Design with VHDL VHDL for Synthesis Storage Elements Latch entity latch is port ( d, le : in std logic ; dq q : out std logic ); end latch ; le architecture rtl of latch is begin −− rtl Sensitivity list contains latch latch : process ( le , d) enable and data input begin −− process latch if le = '1' then Assignment during high phase q <= d; of latch enable end if ; end process latch ; Transparent end rtl ; Hardware Design with VHDL VHDL for Synthesis Storage Elements Register with Asynchronous Reset architecture rtl of reg areset is begin −− rtl dq reg : process (clk , rst ) rst begin −− process reg if rising edge (clk) then q <= d; end if ; Sensitivity list contains clock if rst = '0' then and reset q <= '0'; Reset statement is the last end if ; end process reg; statement within the process Reset has highest priority end rtl ; Hardware Design with VHDL VHDL for Synthesis Storage Elements Register with Synchronous Reset architecture rtl of reg sreset is begin −− rtl Sensitivity list only contains reg : process (clk) clock begin −− process reg if rising edge (clk) then Reset statement is the last q <= d; statement within the clock if rst = '0' then statement q <= '0'; end if ; Should be used if target end if ; architecture supports end process reg; synchronous resets end rtl ; Hardware Design with VHDL VHDL for Synthesis Storage Elements Register with Clock Enable architecture rtl of reg enable is begin −− rtl reg : process (clk , rst ) dq begin −− process reg en if rising edge (clk) then if en = '1' then rst q <= d; end if ; end if ; Enable statement around signal if rst = '0' then assignment q <= '0'; end if ; Use this semantic! end process reg; end rtl ; Hardware Design with VHDL VHDL for Synthesis Storage Elements Storage Elements { Summary Before you start Register or latch? What kind of reset? Clock enable? When you code, be precise Sensitivity list Clock statement Enable semantic Reset order/priority Prefer registers with synchronous resets Check synthesis results Hardware Design with VHDL VHDL for Synthesis Register Transfer Level Register Transfer Level (RTL) A Module may consist of Pure combinational elements Storage elements Mixture of combinational and storage elements Use RTL for shift registers, counters Finite state machines (FSMs) Complex Modules o Transition State Output Logic Memory Logic i clk rst Hardware Design with VHDL VHDL for Synthesis Register Transfer Level Shift register library ieee ; use ieee .
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