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Control Data'" 7600 Computer System

Preliminary System Description November, 1968 @ 1968, Control Data Corporation Printed in the United States of America 7600 SYSTEM DESCRIPTION svnchronous internal locric with 27.5 /data for the attached in~utor out~ut (Preliminary) nanosecond clock period devices. The communic'ation between / PPU and equipment controller is then a Introduction CPU small core memory one record burst of data followed by a 65,536 words of coincident current The 7600 system is the result of relatively long period of inaction. The memory (60 bit 5 parity) a development program to provide + PPU is then able to time share its channel 32 independent banks tJ computing capacity substantially beyond to the CPU among a number of 2048 words per bank that of the 6600 systems. Central equipment controllers without storing 275 nanosecond read/write cycle time processor computation exceeds four more than one record of data in its own 27.5 nanosecond per word maximum times as fast as corresponding memory at any one time. transfer rate computation in the 6600 system. The 7600 system is designed to be machine Communication between a PPU and a CPU large core memory peripheral equipment controller is over code upward compatible with the 512,000 words of linear select memory 6400/6500/6600 systems in the area a 12 bit full duplex channel. Each (60 bit + 4 parity) channel has a 12 bit data path from PPU of central processor routines;; it is not 8 independent banks compatible on the machine code level to controller, and a separate 12 bit 64,000 words per bank data path from controller to PPU. These in the area of system programs or input- 1760 nanosecond read/write cycle time I output drivers. The 7600 system input- two data paths are independent and 8 words read simultaneously each may operate simultaneously. Each path t output provisions have been generalized reference and greatly expanded over those has two associated control lines carrying . 27.5 nanosecond per word maximum control information in the direction of provided in the 6400/6500/6600 systems. transfer rate ! Input-output data rates are not expected data flow. These lines carry a "word flag" f. to average substantially higher on a to indicate passage of each 12 bit word CPU input-output section 1 , per channel basis than the rates in the of data, and a "record flag" to indicate 15 independent channels (asynchronous) the completion of a record of data. Each 6600 systems. A much larger volume each channel full duplex (60 bit) of input-output data is handled in the path has one associated control line buffer areas of 64 or 128 words each carrying control information against the 7600 system by a much larger number channel of input-output channels. direction of data flow. This line carries 55 nanosecond per 60 bit word transfer a "word resume" signal to indicate rate The 7600 system contains a central receipt of a data word. processing unit (CPU) and a number of PPU computation section peripheral processing units (PPU). 12 bit internal word Communication between a PPU and the Some of the PPU are physically located binary computation in fixed point CPU is over a 12 bit full duplex channel with the CPU and others may be synchronous internal logic with 27.5 identical to that described above. The remotely located. The PPU communicate nanosecond clock period 12 bit data path from PPU to CPU with the CPU over high speed data includes a 60 bit assembly register at links with the data buffered at the CPU PPU core memory the CPU end of the data link. This register end of the data link. The PPU provide 4096 words of coincident current memory assembles five 12 bit words into a 60 a communication and message switching (12 bit + 1 parity) bit word for entry into the CPU memory. function between the CPU and individual two independent banks The 12 bit data path from CPU to PPU peripheral equipment controllers. Each 2048 words per bank includes a 60 bit disassembly register at PPU has a number of high speed data 275 nanosecond read/write cycle time the CPU end of the data link. This links to individual peripheral equipment register disassembles a 60 bit word from I controllers in addition to the data link PPU input-output section the CPU memory into five 12 bit words to the CPU. The PPU time shares the 8 independent channels (asynchronous) for transmission over the data link. data link to the CPU among the peripheral each channel full duplex (12 bit) equipment controllers on a record by A maximum of 15 PPU may be directly record basis. System communication connected to the CPU. Each CPU channel has assembly and disassembly registers The 7600 system is divided into a to convert from 60 bit to 12 bit word The 7600 system is designed to number of major sections which are length. All 15 CPU input-output channels accommodate multiple operating stations. interconnected as shown in figure 1. may be in operation at the same time. New peripheral equipment configurations All input data enters the system at a Data is transmitted to, or from, PPU on a are being developed which will operate programabie peripheral equipment record by record basis. The CPU program from programable equipment controllers controller. All output data leaves the is interrupted at the end of a record and are specifically intended for this system at a programable peripheral transmission to exchange control application. These controllers will be equipment controller. The PPU serve to information with the communicating PPU able to communicate with the PPU on gather input data from these peripheral or to initiate transmission of another a record by record basis at higher rates equipment controllers for delivery to the record. On very long records the CPU than the existing 6400/6500/6600 CPU for processing, and distribute equipment. program is interrupted at prescribed processed data to these equipment intervals in the buffer data. The frequency controllers for output devices. The of this interruption is a function of the 7600 system parameters communication between PPU and buffer size and may be preset individually CPU computation section equipment controller is generally limited for each CPU channel. 60 bit internal word by the rate at which the equipment binary computation in fixed point and controller can deliver or accept data. floating point format Most equipment controllers in the 7600 Operating system nine independent arithmetic units system will contain a core memory The 7600 hardware was designed with twelve word instruction stack buffer capable of holding one record of a particular software approach in mind. Equipment Controller or r Peripheral Equipment Equipment Controller PPU (12 bits) 4096 words 8 channels

Equipment Controller or Central Processing Unit (CPU) Peripheral Equipment PPU (12 bits) Equipment Controller 4096 words Computation LCM (60 bits) Section 512,000 words 8 banks

SCM (60 bits)

PPU (12 bits) 4096 words 8 channels

Fig. 1 7600 System Communication

This approach is an outgrowth of Central processing unit (CPU) readout of the 60 bit word. The total experience with the Chippewa and The CPU is a single integrated data read/write cycle time for a SCM bank is ten clock periods. It is thus possible SCOPE Operating Systems for the 6600. processing unit. It consists of a The 7600 system software will be computation section, small core memory, for a maximum of ten SCM banks to be in operation at one time. This maximum described in a following section of large core memory, and input-output this manual. section. These sections are all contained occurs during block copy instructions between SCM and LCM in which the in one main frame cabinet and operate addresses for sequential words cause System monitor in a tightly synchronous mode with a clock period of 27.5 nanoseconds. SCM bank conflicts. In random The system monitor is a CPU program CPU program in the 7600 system. This program is Communication with equipment outside of addressing of the SCM the main frame cabinet is asynchronous. data, CPU instructions, and input-output loaded with the operating system on a channel data, an average of four SCM machine "dead start" and remains in banks in operation at one time is more CPU core memory the CPU core memory as long as the normal. operating system is used. A portion of The CPU contains two types of internal the 'ystem Inonitorresides permanently core memory. One type, designated as, The SCM performs certain basic in the small core memory (SCM) section the core memory (SCM), is a functions in system operation which the of the CPU. This portion of the monitor many bank coincident current type LCM cannot effectively perform. These program is called the "resident monitor" memory with a total capacity of 64K functions are essentially ones requiring Program. The bulk the system Inonitor words of 60 bit length (K = 1024). The rapid random access to unrelated fields resides in the large core memory other type, designated as the large core of data. The first 4K addresses in SCM (LCM) Of the CPU- This portion Of memory (LCM) is a linear selection type are reserved for input-output buffer the monitor program is called piecemeal of memory in which eight 60 bit words and control areas. These areas are into the SCM for execution as overlays are addressed as a single unit. The LCM addressed by the CPU input-output on the resident monitor program. has a total capacity of 500K words of section as required to service the 60 bit length. These two types of internal communication channels to the PPU. Object program memory have significantly different CPU object programs do not have access ' An object program is defined in this system functions in the CPU. to these areas. The next 1K addresses manual to mean any CPU program other are reserved for the resident monitor than the system monitor program. This The SCM is arranged in 32 banks of 2K program. term is used to describe generally a job words each. Each bank is independent of oriented program. An object program the other 31 banks. Maximum data The remainder of the SCM is divided may be a machine language program transfer rate between the SCM as a unit between fields of CPU program code and such as a FORTRAN compiler, or it may and other parts of the system is one fields of data for the currently executing be a program which results from word each clock period. Each SCM bank program. compiling FORTRAN statements with has a four clock period access time a compiler. from arrival of the storage address to The LCM is arranged in eight banks of '64~words each. Each bank is the SCM. All data files are buffered Data may be directly addressed in independent of the other seven banks. A through LCM for the object programs. either the SCM or the LCM. The general storage reference to a LCM bank results Small object programs are generally information flow in this section is in a read/write cycle which takes 64 run to completion in SCM with the illustrated in figure 2. clock periods. Eight 60 bit words are complete input file in LCM at the read simultaneously from a LCM bank beginning of execution, and the complete Instruction word stack whenever a read/write cycle occurs. output file in LCM at the end of execution. The instruction word stack is a group These words are held in a 480 bit of twelve 60 bit registers in the CPU operand register for each LCM bank. The low order addresses in LCM are computation section which hold program Subsequent reference to a word reserved for monitor program overlays, instruction words for execution. The residing in one of these operand registers object time library, and compilers. instruction stack information is essentially allows either read or write function These areas require approximately 32K a moving window in the program code. without the delay of a bank read/write of the 500K available storage. The stack is filled two words ahead of cycle. Maximum data transfer rate The remainder of LCM is divided into the program address currently being between the LCM as a unit and other fields of the various operating executed. A small program loop may parts of the system is one word each stations in the system. frequently be entirely contained within clock period. This maximum transfer the instruction stack. When this happens Computation section rate occurs during block copy the loop may be executed repeatedly instructions between LCM and SCM. The computation section of the CPU without further references to SCM. LCM bank read/write cycles are contains nine segmented arithmetic units, anticipated in the block copy operation 24 operating registers, and a 12 word The current instruction word is contained to avoid a bank access delay. instruction stack. These units work in a special register in the CPU together to execute a CPU program computation section. This register is The LCM provides the basic working stored in the SCM. Data moves into, and designated the CIW register. Program storage for the CPU. All object programs out of, the computation section of the instruction words are read one at a time are assembled here for execution in CPU through the operating registers. from the instruction stack and are

lnstruction Word Stock (60bits) Functional I I I I I I Units

I 7 I I - Long Add I Floating Add I L I - I - Floating Multiply 1 I - Floating Divide 1 - Boolean I I Shift +vvv+vvC+vvv I Current Instruction Word Normalize 1 I I Population Count From SCM I-> Control l ncrement

A Regsten B registers X Reglsten (60bits) (18 bm) (18 bm) I 1 I I I J 1 I I I 1 1 1 I J 1 1 I

SCMI SCM LCM LCM Address Data Address Data Fig. 2 CPU Computation Section loo0 program. If an error condition occurs 16 16 I chainel 1 Channel Channel 17 Channel 17 during the execution interval the monitor input package output package program can determine the type of error 1 700 by analyzing the terminating exchange Channel 14 Channel 14 Channel 15 Channel 15 package parameters. Each bit in the PSD register has significance either as a input package output package mode selection or an error condition flag. Channel 12 Channel 12 Channel 13 Channel 13 600 CPU input-output section input package I output package + The CPU input-output section includes Channel 10 Channel 10 Channel 11 I Channel 11 the mechanism to buffer data to (or from) the directly connected PPU. Each PPU input package I output package communicates with the CPU over a 12 bit full duplex channel. Each channel Channel 6 Channel 6 Channel 7 Channel 7 has assembly and disassembly registers input package output package to convert the 12 bit channel data to 60 bit CPU words. The function of the CPU Channel 4 Channel 4 Channel 5 Channel 5 input-output section is to deliver these 60 bit words to the SCM for incoming input package output package input package I output package data, read 60 bit words from the SCM +---- Channel 2 Channel 2 Channel 3 Channel 3 for outgoing data, and interrupt the CPU program for monitor action on the buffer data as required.

-- - - Real time Channel 1 Channel 1 The input-output section is able to process a maximum of one 60 bit word package package input package output package I I each two clock periods. The effective 0 20 40 60 100 processing rate is somewhat lower than this because of bank storage conflicts in (octal addresses) SCM. Whenever a bank conflict occurs on an input-output section request, the Fig. 4 110 Section Exchange Packages in SCM communication path to the SCM is held up until the conflict is resolved. Channel (EEA) Error exit address -This is a job stack. It is possible to step through requests for a SCM word reference SCM absolute address for an exchange a program one instruction word at a are processed on a priority basis jump or error termination. time using an operator console to monitor whenever the I/O section is not able to the register values at each step. keep up with the channel requests. The (BPA) Breakpoint address -This is a priority is assigned in order by channel SCM relative address for breakpointing Error Exits number, with the lowest order channels an object program. Execution of an object program may be having the highest priority. terminated by an exchange jump to (PSD) Program status designation - the error exit address (EEA) under There are a total of 15 channels in the This is a register of control information. certain conditions. Some of these 1/0 section of the CPU. These channels conditions may be selected by mode are numbered in octal beginning with Program breakpoint declarations through the monitor 01 and ending with 17. Each channel An object program may be executed in program, and some are unconditional. has a SCM buffer area for incoming data small sections during a debugging phase In general, errors due to arithmetic and a separate SCM buffer for outgoing by using the breakpoint address register overflow, underflow, or indefinite results data. In addition each channel has an (BPA). This is a hardware register in the during computation may be allowed to exchange package for incoming data and computation section of the CPU which proceed through the calculation, or may an exchange package for outgoing data. is loaded from the object program cause an error exit, depending on Each buffer area is divided into two fields, exchange package. A coincidence test mode selection. Errors due to hardware a lower field and an upper field. Data is is made between (BPA) and the failure or program addressing out of entered (or removed) from the buffer program address register (P) as each an assigned field in storage cause area in a circular mode. The last word in program instruction word is read from unconditional error exits. In any error the lower field is followed by the first the IWS to the CIW register. When a exit case the monitor program has the word in the upper field. The last word in coincidence occurs the program ability to continue the object program the upper field is followed by the first execution is terminated with an exchange where the error can be corrected word in the lower field. Whenever a buffer jump to the error exit address (EEA). or ignored. area has been filled (or emptied) to the point where a field boundary is crossed, The monitor program controls the The error condition flags and mode the CPU is interrupted through the breakpoint address for debugging an selection flags are all contained in an associated exchange package to process object program by altering the exchange 18 bit program status designation (PSD) the buffer data. The channel continues to package for the object program before register. This register is loaded from the fill (or empty) the other buffer field while each execution interval. The monitor exchange package for each object the CPU is processing this buffer data. program receives instructions for program. The mode selections are made breakpoint control from an operator in the exchange package prior to the The I/O section exchange package areas console or from control cards in a execution interval by the monitor are permanently aesigned in the lowest order addresses of SCM. These areas are Real time interrupt message over the associated channel to arranged as shown in figure 4. The I10 The CPU clock period counter causes an the CPU. The interrupt occurs whenever section buffer areas are assigned in the interrupt of the CPU program every 3.6 a record flag arrives at the CPU input- next higher order address positions of milliseconds (approx.):This corresponds output section on an incoming data link. SCM. These areas may be changed both to the modulus of the 17 bit register in Interpretation of message content is a in size and order (wiring change) to the clock period counter. This interrupt function of the system monitor program. accommodate various types of channel causes an exchange jump to absolute volume. A typical arrangement for the address 20 in SCM. The real time System dead start buffer areas is shown in figure 5. Total exchange package at this SCM address The system is initially started through the I/O section space in SCM cannot exceed executes a CPU program in monitor mode maintenance control unit (MCU). This absolute address 10,000 octal. which advances the count in a 60 bit mechanism is used whenever power SCM storage location to continue the is turned on after an idle period or when Real time clock real time clock function of the clock the system is restarted after hardware CPU programs may be timed precisely by period counter. This program also tests failure. The MCU is essentially a PPU with using the CPU clock period counter. time limit for the currently active object specially adapted input-output channels. This counter is essentially a real time program. The real time interrupt flag is This unit is used exclusively for clock which is advanced one count each cleared at the end of the execution maintenance functions. clock period of 27.5 nanoseconds. Since interval for real time exchange package. the clock is advanced synchronously This flag is read as an 18th bit on an 016 The dead start sequence begins with a with the program execution, the program instruction in order to avoid erroneous deck of binary cards for the MCU may be timed to an exact number of timing indication where the reading of program. These cards are loaded through CPU clock periods. the clock period counter coincided with the MCU card reader and activate the the setting of the interrupt flag. This bit is MCU. The MCU program then dead starts The CPU clock period counter contains an indication that the counter has passed the CPU and all other PPU in sequence. a 17 bit register which can be read by its modulus but the interrupt to advance A bootstrap program is entered directly a CPU program with an 016 instruction. the SCM word has not yet occurred. into SCM from the MCU. The CPU This register contains the lowest order program is then initiated by the MCU 17 bits of the real time count. An overflow External interrupt through the MCU exchange package at of the highest order bit in this register The CPU computation may be interrupted absolute address zero in SCM. This sets a real time interrupt flag. This flag from an external source through the bootstrap program transmits a resident reads as an 18th bit on an 01 6 instruction. directly connected PPU. Each such PPU PPU program to all directly connected In addition, this flag causes an exchange has the ability to interrupt the execution PPU to initiate their activity. The system jump to the real time exchange package of an object program and call the is then loaded completely from a system at absolute address 20 in SCM. system monitor by sending a control library tape associated with one of the

10.000 Channel 15 Channel 15 Ch. 16 Ch. 16 Ch. 17 Ch. 17

input buffer output buffer input output input output 7000 Channel 13 Channel 13 Channel 14 Channel 14

input buffer output buffer input buffer output buffer 6000 . Channel 11 Channel 11 Channel 12 Channel 12

input buffer output buffer input buffer output buffer 5000 Channel 7 Channel 7 Channel 10 Channel 10

input buffer output buffer I input buffer output buffer 4000 Channel 5 Channel 5 Channel 6 Channel 6

input buffer output buffer input buffer output buffer 3000 Channel 3 Channel 3 Channel 4 Channel 4

input buffer output buffer input buffer output buffer 2000 , Channel 1 Channel 1 Channel 2 Channel 2

input buffer output buffer input buffer output buffer 1000 I Input - Output section exchange packages 400 1000

(octal addresses) Fig. 5 110 Section Buffer Areas in SCM system PPU. This library tape may be programs for execution. Organization of program handles all 110 section interrupt any tape in the system and may be CPU storage is illustrated in figure 6 on requests as well as object program 1 declared at dead start time through the the following page. The I10 section requests. The remaining portion of SCM maintenance console. storage areas are fixed by hardware beginning at octal address 12,000 and addressing in SCM. The remaining areas continuing to 200,000 is available for I System operation are strictly software organization. object program code and data. The operating system software cbnsists ' I of the CPU monitor program, with its The resident monitor program resides The low order addresses in LCM are used overlays, plus the PPU programs to drive immediately above the 110 section in for permanent storage of frequently the peripheral equipment. The operating SCM. This program is a permanent part used programs and overlays. The system I system forms a software framework in of the operating system and is never tables are kept here and are directly SCM and LCM to hold the object moved during system execution. This addressed by the monitor program.

SCM LCM

1'750'000

Current Object Data -Control Point No. 4 Field

Control Point No. 3 Field Current Object Program

L Control Point T No. 2 Field Resident Monitor Control Point Program No. 1 Field

Library Routines

110 Buffer Areas

FORTRAN Compiler

Monitor Overlays

110 exchange System packages I Tables I

(Octal addresses) Fig. 6 Operating System Storage Allocation 'Library routines and compiler code may when the output data has been delivered data 1,935bits vary with installation requirements. to the output file buffer in LCM and this post-am ble 66 bits Approximately 100,000 octal words of buffer has been emptied onto a disk pack, lndex 290 bits LCM are expected to be used for these tape, or disk file for listing. permanent storage requirements. Heads Parallel 16 The third phase consists of copying the Data/Sector/Head The remainder of LCM beginning at output file from the magnetic storage to Group octal address 100,000and continuing to a printer at the operating station. During (516 60 bit words) 30,960bits address 1,750,000is available for object this phase the LCM control point field Sectors/ Rev. 40 program code and data. This area is - has been rdleased for another job. Data/ Rev./ . divided into a number of control point Head Group 1,238,400bits fields. Each control ~ointfield contains Sy&em peripherals a single job oriented program code and Head Groups/Stack/ The Disk/Drum Subsystem consists of Unit 2 data. In addition, each control point one controller and one 7600 Disk File DevicesISystem 2 contains the necessary control (two storage units) or up to two 7600 information for continuity from one Total Storage/System 316,000,000bits I Drums. The 7600 Disk File contains two program to the next. These areas vary double-ended disk drive spindles (stacks) Data/Position/ in size as required for each job. When a which rotate asynchronously at 1,800 Stack/Unit 2,476,800bits job is completed and a new job is rpm, less inductive slip. Each of the four Positions/StacklUnit 512 track positions assigned to a control point, the storage half-spindles contains 18 disks (32 1,268,121,600 areas are readjusted by moving the data Data/Stack/Unit bits recording surfaces). There are two in each control point field through the Stacks/ Unit 2 hydraulic positioning access assemblies, I SCM as a buffer to a new LCM location. DataIUnit 2,536,243,200bits each one servicing a pair of half-spindles. Each of the two access assemblies is UnitsIRead-Write Job execution proceeds through the considered to be one file unit. Each Control 1 system in three phases. In the first phase access assembly contains two separate UnitsIDevice 2 cards are read at an operating station horizontally opposed groups of 16 head 5,072,486,400 and an input file is generated on a disk Total Storage Device bits arms, one group for each half spindle pack, tape unit, or disk file. This input file DeviceslSystem 1 (stack). Mounted on the end of each may physically reside at the operating Total Storage/System 5,072,486,400bits head arm are two head pads, .each of station or it may reside in a central which contains one readlwrite magnetic disk file. The 7600 Drum Unit consists of a rotating head. Thus, there is one head for each of drum coated with a magnetic material the 32 surfaces on a half-spindle. In the second phase the input file is and the associated read, write, and head Each unit is divided into 4 groups of copied into a control point field in LCM. select electronics. The drum is driven 16 heads each (2groups on each stack). If the input file is small the entire file may by an integral three-phase induction Each access can be moved to any of the then reside in LCM. If the input file is motor. The speed of the drum is 512 data positions on each stack or a I large the first portion of the file is copied 1,800rpm minus a maximum 5% into a buffer area in the control point field. non-data position (retract) via a position 128 function. There is only one data zone on induction slip. There are groups of The control cards in the input file are 16 heads. The nominal data rate of the the file. It has a nominal data rate of then interpreted by the monitor program drum is 380 nanoseconds per 16 bit word. and the necessary compiler or library 380 nanoseconds per 16 bit word. Since the PPU interface receivesltransmits Since the PPU interface receives/ routines are read from outside the LCM transmits 12 bit bytes, the nominal PPU if necessary for program execution. 12 bit bytes, the nominal PPU data rate of the disk system is 285 nanoseconds data rate of the drum system is When the control point information is 285 nanoseconds per 12 bit byte. ready for execution the program code is per 12 bit byte. The maximum latency is transferred to SCM. If the program and approximately 35.5ms.There are 512 positions on each of the two stacks. The Drum Characteristics associated data are too large to fit (approximate figures) entirely in SCM a portion of the data must positioning times are: be retained in LCM and directly Stack to stack position 15 msec. Bit capacity per track 85,400bits addressed there. This must be done by Adjacent position 25 msec. Sectors per track 40 sectors declaration at compile time in order to Random average position 100 msec. Bits/ head/sector 2,135bits designate certain arrays of data to reside Maximum position 145 msec. pre-amble 165 bits in LCM for execution. data 1,935bits Only one program at a time is executed in Head switching time does not exceed post-amble 35 bits SCM. The entire SCM object program 60 usec in the same stack. The recovery Index 1,000bits field may thus be used for each program. tiefor a read following a write is Heads-Parallel 16 60 usec. Data is read from the input file in LCM Data/Sectoc/ and results are stored in an output file in Head Group LCM. If the amount of input and output Disk File Characteristics (516 60 bit words) 30,960bits data is small the job may be run to (approximate figures) Sectors/Rev. 40 completion in one execution interval. Number of tracks/ Data/ Rev./ If job execution is delayed by buffer size disk or by intermediate file references the Head Group 1,238,000bits Bit capacity per track 86,930bits program code is returned to LCM and Head Groups/ another control point uses the SCM while Sectors per track 40 sectors StackIUnit 128 buffer data is transferred to (or from) BitsIheadJsector 2,166 bits Data/Position/ LCM. The second phase is completed preamble 165 bits Stack/Unit 158,000,000bits 1 Positions/Stack/Unit 1 larger number of peripheral equipments efficiently use computer resources while StacksIUnit 1 grouped as operating stations and used giving the user maximum flexibility in Data1Unit 158,000,000 bits primarily for user functions. program csnstruction. Units/Read-Write The system-oriented peripheral The COMPASS language allows all 11 control 1 equipments include a card reader and hardware CPU functions to be expressed

Units/Device 1 CRT display reserved for the ' symbolically. In addition, many features Total Storage/Device 158,000,000 bits maintenance function and used in are included which enable the conjunction with the MCU. Additionally, programmer to control the assembly The controller contains two,read/write one or more Disk/Drum Subsystems and process itself. COMPASS is executed control units. Each control unit can be a variable number of PPU are utilized for in the CPU. operated by two 7600 PPU on a system-oriented functions; of these, time-shared basis. Each PPU uses two one Disk Subsystem configured as two Features provided by COMPASS include: input-output channels (one for data and independent units and four PPU Free-field source format one for control) to operate the controller. constitute the minimum recommended Selective assembly of code sequences Each readlwrite control unit operates configuration. The configuration of the based upon assembly-time tests one disk file storage unit or one drum. operating stations will vary, and is Assembly-time access to symbol table The two PPU channels are identical, subject to continued refinement as information but the signals are defined differently. system operating experience Programmer control over local and The control channel transmits output accumulates. In general, both general common code blocks function codes and receives input status purpose and special purpose stations Subprogram linkage with external codes. After the necessary functions may be utilized; the latter typified by a symbols and entry points are issued on the control channel, the tape input-output station operated in Data generation deferred to load time data transfer takes place on the data conjunction with a centralized tape vault, Symbol equation and redefinition channel. The readlwrite control units do and the former by the configuration of Macro coding; both program and not contain any reservation logic for the Figure 7. Operating stations may be system defined two PPU interfaces. Thus, the PPU must located remote from the central complex Micro coding reserve control units with software. The through use of communications links Extensive listing control software ensures that only one channel of and interfaces, and when employing Thorough language diagnostics a read/write control unit is operating at programable equipment controllers, may one time. The only exception is that be utilized for a variety of FORTRAN: FORTRAN is a procedural status can be read at any time. A 16 bit CPU-independent processing. language designed for solving problems cyclic parity byte is generated by the of a mathematical or scientific nature. controller for the data field of each System software concepts CONTROL DATA 7600 FORTRAN utilizes record written on the peripheral unit. In general, 7600 software releases will an extremely fast compiler which is The parity byte is written on the storage provide source language compatibility compatible with FORTRAN IV and USASl unit at the end of the record. During a with their then current 6000 Series FORTRAN with extensions. Compilations read operation, the parity byte is read counterparts. Exceptions will be made may be produced simultaneously with and compared to the parity byte only in the interest of improved system other compilations or with execution of generated for the record being read. performance or compliance with other programs in the multi-programming If the parity does not compare the parity evolving language standards. mode. A program consisting of mixed error status bit sets. Small block data FORTRAN and COMPASS subprograms transfers can be accomplished by writing Product Set releases will provide an may be compiled, assembled and on alternate sectors and considering the increasing variety of user facilities, with executed as a unit. PPU as being reserved for one storage each retaining all capabilities of previous unit. For large block data transfers, releases. Facilities will include batch Emphasis is placed on efficiently two PPU can operate one storage unit in and time shared system operation, and producing relocatable binary output and a mode where PPU A operates on the comprehensive sub-systems for on USASl compatibility. Subprograms even-numbered sectors and PPU B information management, on-line are compiled independently, and a file operates on the odd-numbered sectors. diagnostics, and job or system resource consisting of relocatable binary Thus the transfer rate of one block accounting. Additionally, the system will subprograms is produced. Options are is twice as fast. emphasize fail safe methods for available to produce a source listing, recording and include automatic facility an object code listing, a cross reference Other 7600 peripherals include card for restart and recovery from a variety of listing, and a relocatable binary deck. readers and punches, tape transports, hardware and user errors. Specifications line printers, removable disk storage and schedules will be published The relocatable binary subprograms are drives, and CRT displays. These will separately, but will be consistent with processed by the 7600 loader. communicate with the system PPU the following general descriptions and through programable equipment will be oriented toward the use of The compiler can operate as a load-and- controllers. programable equipment controllers: go unit and produce machine language output. It operates as an independent Operating specifications will be Assembly languages, FORTRAN, and program under control of the operating comparable or identical to those of loader system and can be called to use only 3000 and 6000 Series peripherals. the storage required for compilation of a COMPASS: CONTROL DATA 7600 particular program. System configurations COMPASS is a COMPrehensive Typically, a 7600 system utilizes a small Assembly System which provides a 7600 LOADER: The 7600 CPU loader number of peripheral equipments used symbolic programming language for the performs the following functions: loads primarily for system functions, and a 7600 central processor. It is designed to absolute and relocatable binary I - PPU (12 bits) I 4096 words

Monitor Display LCM (60 bits) 512,000 words

Equipment Controller < SCM (60 bits)

Card punch

PPU (12 bits) 4096 words 1 8 channels I I I I I I

Fig. 7 Typical 7600 Operating Station I

programs, links separately compiled or without relocation for high-speed loading. Commercial data processing programs assembled programs, loads library There are several levels of overlays. The 7600 software product set includes subprograms and links them to user Segments are groups of subprograms in COBOL and a set of problem oriented programs, detects errors and provides relocatable form and are loaded and languages which allow the commercial diagnostics, outputs a memory map, unloaded as units. Each segment is data processing user to define, maintain, and generates overlays. assigned a level number when it is sort, and retrieve data from files. These loaded. Level zero is reserved for the programs adhere to USASl standards Three types of loading are performed: main segment. Loading a segment where applicable. The systems which normal, segment, and overlay. In normal displaces segments with level numbers comprise the commercial data loading, absolute or relocatable binary greater than ?r equal to its level processing product set include: subprograms which have been compiled number. Segments with level numbers or assembled independently are brought lower than the segment loaded are left COBOL together in LCM for execution in SCM. intact. When a segment is loaded, its SORT references are linked to subprograms Information System Table Generator Segments and overlays allow programs and common blocks of previously loaded Report Generator that exceed storage to be organized so segments. When a segment is displaced that portions or groups of programs may by another segment of equal or lower These s'ystems will be augmented by a be called, executed, and unloaded level number, the displaced segments are data mapager which will organize the as needed. delinked from the segments that are to transmission of data to and from remain. References left unsatisfied may peripheral devices. This provides the Overlays are subprograms in absolute be satisfied by entry points in a newly user with task flexibility, ease of form and are loaded at execution time loaded segment. definition for a range of problems, and efficient utilization of mainframe and INFORMATION SYSTEM: The performs the following functions for each: peripherals by centralization of I/O. information system is a set of problem 0 Monitors all lines connected to the oriented languages which enables the controller to which it is assigned. I DATA MANAGER: Although I10 requests user to create, amend, and retrieve data 17 Loads jobs for the central facility from can be made directly to a physical from data files. A feature of the system the remote station. record processor, the data manager is is the ability to retrieve data as a function Outputs data to the appropriate the lowest entry point in the hierarchy of several variables, either by control remote station. for generalized I10 requests. The data card command or in an interactive mode. Changes program parameters manager is logically divided into two When the requirement is to retrieve and (priority, run time, etc.) as requested segments - file manager and logical possibly structure large amounts of data by the remote operator. record processor. The file manager from sequential files, control cards are Monitors each remote job and, upon catalogs permanent files, allocates normally used. When, on the other hand, request, sends the status of the job storage, and performs label handling, the requirement is to retrieve limited to the remote station. security checks, and job accounting. The amounts of data from a random file, it Monitors the status of jobs at the logical record processor formats 1/0 and becomes advantageous to use an central facility so that remote output checkpoint requests, blocks and interactive mode with limited response is handled properly. deblocks logical records, provides time. access methods (e.g., sequential, The operator at the remote site initiates indexed sequential, and direct), and TABLE GENERATOR: A table, as the remote communication operation. accumulates data transfer statistics such interpreted by the table generator, is a By entering commands, the remote I as block counts, record counts, and multi-dimensional array, each dimension operator can interrogate the system for error counts. The data manager will have of which is defined by a single variable status information, change priorities and a modular structure such that only those or a number of catenated variables. times limits or terminate jobs. modules required will reside in core. The table generator is a generalized program which creates any number of EXPORTIIMPORT communicates with the COBOL: USASl standards separate the tables from a file consisting of fixed remote operator by informing him of language into a nucleus and a number and/or variable length records. Up to 25 status on the flow of jobs through the of modules each performing a specific record types may appear in any one system and certain error conditions. task. These modules are: file and may be structured into a hierarchy. The items or data fields within The software control program, IMPORT, Table Handling SORT a record may be alphanumeric codes or performs the following functions: Sequential Access Report Writer binary information, and they may be Inputs jobs from the card reader in Random Access Segmentation resequenced as desired. The resulting the same format as jobs loaded at ' Random Processing Library tables can assume a wide variety of local operating stations. output formats. Transmits card images via the communication equipment to EXPORT I The nucleus and each of the modules The system first retrieves the necessary at the central site. adhere to USASl specifications, and, information for the tables, sorts it into the as such, form a subset of 7600 COBOL. Receives the results of jobs from the desired sequence, and then prepares central site and outputs them on the Where no conflicts exist with these output in the form of table elements on a , specifications, COBOL is externally appropriate remote station set of files on a disk, tape, or equivalent peripheral device. compatible with 6000 COBOL. For medium. These files subsequently example, 7600 COBOL incorporates Communicates with EXPORT by serve as input to the report generator transmitting and receiving information INCLUDE and ENTRY statements, and program. other items currently utilized by 6000 concerning current job processing functions. COBOL. Many of the above modules are Remote Access Software I not restricted to COBOL. For example, CONTROL DATA 7600 EXPORT/ IMPORT During transmission of each data block, sequential and random access are a cyclic code word is generated. At handled by the file manager, while the programs allow multi-access to a 7600 computer from remotely located operating the receiving end, this code word is used SORT and report writer modules can in an error detection scheme; when an function as stand-alone systems. stations in a bat~hjob processing mode. Users at remote sites may submit jobs error-free data block js received, the and receive printed output in the same next data block is transmitted. This error SORT: 7600 SORT assumes wider way they would at stations local to the detection code word provides a responsibilities than its 6000 counterpart. computer. Each remote terminal connects reliability factor in excess of 99.9 percent. Run, file, and record attributes as well to the central computer via as control cards differ from 6000 SORT. communications lines. The EXPORT/IMPORT system is The user needs only to describe input connected to the central computer via and output files and sort keys. The voice grade or broad band The software for this remote system I system itself selects the most efficient consists basically of the Executive communication links, depending on the sorting algorithm and merging , Processor Of Remote Tasks (EXPORT), nature of the application being performed techniques. which resides in a Peripheral Processor at the remote station. assigned to remote communications at Additional products REPORT GENERATOR: A superset of the the central facility, and the Input/Output COBOL report writer module, the report Monitor for Processing Of Remote Tasks Additional software products will be generator formats raw data as it is being (IMPORT), which resides in each announced and specified at a later date. retrieved from files, establishes line remote operating station. These will include interactive terminal and page images, appends headings and access facilities, mathematical and page numbers, and selectively prints The software control program, EXPORT, simulation languages, PERT, APT, and data according to user furnished criteria. handles several remote stations and other technical applications packages. CONTROL DATl

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