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PARALLEL OPERATION in the CONTROL DATA 6600 James E

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PARALLEL OPERATION in the CONTROL DATA 6600 James E PARALLEL OPERATION IN THE CONTROL DATA 6600 James E. Thornton Control Data Corporation Minneapolis, Minnesota HISTORY survived early difficulties to become the basis for a nice jump in circuit performance. About four years ago, in the summer of 1960, Control Data began a project which cul­ SYSTEM ORGANIZATION minated last month in the delivery of the first 6600 Computer. In 1960 it was apparent that The computing system envisioned in that brute force circuit performance and parallel project, and now called the 6600, paid special operation were the two main approaches to attention to two kinds of use, the very large any advanced computer. scientific problem and the time sharing of This paper presents some of the consid­ smaller problems. For the large problem, a erations having to do with the parallel opera­ high-speed floating point central processor with tions in the 6600. A most important and access to a large central memory was obvious. fortunate event coincided with the beginning Not so obvious, but important to the 6600 of the 6600 project. This was the appearance system idea, was the isolation of this central of the high-speed silicon transistor, which arithmetic from any peripheral activity. 4096 WORD 4096 WORD 4096 WORD 4096 WORD CORE MEMORY CORE MEMORY ~ ~ CORE MEMORY CORE MEMORY PERIPHERAL PERIPHERAL PERIPHERAL PERIPHERAL & CONTROL & CONTROL & CONTROL & CONTROL PROCESSOR PROCESSOR PROCESSOR PROCESSOR 6600 CENTRAL MEMORY 4096 WORD 4096 WORD CORE MEMORY CORE MEMORY PERIPHERAL 6600 CENTRAL PROCESSOR PERIPHERAL & CONTROL & CONTROL PROCESSOR PROCESSOR 6600 CENTRAL MEMORY 4096 WORD 4096 WORD 4096 WORD 4096 WORD ~ CORE MEMORY - CORE MEMORY +- CORE MEMORY CORE MEMORY PHERIPHERAl PERIPHERAL PERIPHERAL PERIPHERAL & CONTROL & CONTROl. & CONTROL & CONTROL PROCESSOR PROCESSOR PROCESSOR PROCESSOR Figure 1. Control Data 6600. 33 From the collection of the Computer History Museum (www.computerhistory.org) 34 PROCEEDINGS-SPRING JOINT COMPUTER CONFERENCE, 1964 It was from this general line of reasoning instruction formats to provide for direct, in­ that the idea Of a multiplicity of peripheral direct, and relative addressing. Instructions processors was formed (FIg. 1). Ten such provide logical, addition, subtraction, shift, and peripheral processors have access to the central conditional branching. Instructions also pro­ memory on one side and the peripheral channels vide single word or block transfers to and from on the other. The executive control of the any of twelve peripheral channels, and single system is always in one of these peripheral word or block transfers to and from central processors, with the others operating on as­ memory. Central memory words of 60 bits signed peripheral or control tasks. All ten length are assembled from five consecutive processors have access to twelve input-output peripheral words. Each processor has instruc­ channels and may "change hands," monitor tions to interrupt the central processor and to channel activity, and perform other related monitor the central program address. jobs. These processors have access to central To get this much processing power with memory, and may pursue independent transfers reasonable economy and space, a time-sharing to and from this memory. design was adopted (Fig. 2). This design Each of the ten peripheral processors contains a register "barrel" around which is contains its own memory for program and moving the dynamic information for all ten buffer areas, thereby isolating and protecting processors. Such things as program address, the more critical system control operations in accumulator contents, and other pieces of in­ the separate processors. The central processor formation totalling 52 bits are shifted around operates from the central memory with relocat­ the barrel. Each complete trip around requires ing register and file protection for each program one major cycle or one thousand nanoseconds. in central memory. A "slot" in the barrel contains adders, assembly networks, distribution network, and intercon­ PERIPHERAL AND CONTROL PROCESSORS nections to perform one step of any peripheral The peripheral and control processors instruction. The time, to perform this step or, are housed in one chassis of the main frame. in other words, the time through the slot, is Each processor contains 4096 memory words / one minor cycle o:!'" one hundred nanoseconds. of 12 bits length. There are 12- and 24-bit Each of the ten processors, therefore, is allowed PROCESSOR TIME-SHARED PROCESSOR REGISTERS INSTRUCTION MEMORIES CONTROL READ PYRAM 10 CENTRAL CENTRAL MEMORY MEMORY (60) (60) (12) REAL TIME 1/0 CHANNELS EXTERNAL EQUIPMENT Figure 2. 6600 Peripheral and Control Processors. From the collection of the Computer History Museum (www.computerhistory.org) PARALLEL OPERATION IN THE CONTROL DATA 6600 35 one minor cycle of every ten to perform one of five references to be "nested" in each network its steps. A peripheral instruction may require during any major cycle. The central memory one or more of these steps, depending on the is organized in independent banks with the abil­ kind of instruction. ity to transfer central words every minor cycle. In effect, the single arithmetic and the The peripheral processors, therefore, introduce single' distribution and assembly network are at most about 2 % interference at the central made to appear as ten. Only the memories are memory address control. kept truly independent. Incidentally, the A. single real time clock, continuously memory read-write cycle time is equal to one running, is available to all peripheral proces­ complete trip around the barrel, or one thousand sors. nanoseconds. Input-output channels are bi-directional, CENTRAL PROCESSOR 12-bit paths. One 12-bit word may move in one direction every major cycle, or 1000 nano­ The 6600 central processor may be con­ seconds, on each channel. Therefore, a maxi­ sidered the high-speed arithmetic unit of the mum burst rate of 120 million bits per second system (Fig. 3). Its program, operands, and is possible using all ten peripheral processors. results are held in the central memory. It has A sustained rate of about 50 million bits per no connection to the peripheral processors ex­ second can be maintained in a practical operat­ cept through memory and except for two single ing system. Each channel may service several controls. These are the exchange jump, which peripheral devices and may interface to other starts or interrupts the central processor from systems, such as satellite computers. a peripheral processor, and the central program Peripheral and control processors access address which can be monitored by a peripheral central memory through an assembly network processor. and a dis-assembly network. Since five periph­ A key description of the 6600 central eral memory references are required to make processor, as you will see in later discussion, is up one central memory word, a natural assem­ "parallel by function." This means that a num­ bly network of five levels is used. This allows ber of arithmetic functions may be performed PERIPHERAL AND CENTRAL PROCESSOR CONTROL PROCESSORS 24 OPERATING REGISTERS 12 INPUT OUTPUT CHANNELS Figure 3. Block Diagram of 6600. From the collection of the Computer History Museum (www.computerhistory.org) 36 PROCEEDINGS-SPRING JOINT COMPUTER CONFERENCE, 1964 concurrently. To this end, there are ten func­ As an example,· a 15-bit instruction may call tional units within the central processor. These for an ADD, designated by the f and m octal are the two increment units, floating add unit, digits, from registers designated by the j and k fixed add unit, shift unit, two multiply units, octal digits, the result going to the register divide unit, boolean unit, and branch unit. In designated by the i octal digit. In this example, a general way, each of these units is a three the addresses of the three-address, floating add address unit. As an example, the floating add unit are only three bits in length, each address unit obtains two 60-bit operands from the cen­ referring to one of the eight floating point regis­ tral registers and produces a 60-bit result which ters. The 30-bit format follows this same form is returned to a register. Information to and but substitutes for the k octal digit an 18-bit from these units is held in the central registers, constant K which serves as one of the input of which there are twenty-four. Eight of these operands. These two formats provide a highly are considered index registers, are of 18 bits efficient control of concurrent operations. length, and one of which always contains zero. As a background, consider the essential Eight are considered address registers, are of difference between a general purpose device and 18 bits length, and serve to address the five read a special device in which high speeds are re­ central memory trunks and the two store cen­ quired. The designer of the special device can tral memory trunks. Eight are considered float­ generally improve on the traditional general ing point registers, are of 60 bits length, and purpose device by introducing some form of are the only central registers to access central concurrency. For example, some activities of memory during a central prograrn. a housekeeping nature may be performed sepa­ In a sense, just as the whole central proc­ rate from the main sequence of operations in essor is hidden behind central memory from separate hardware. The to,tal time to complete the peripheral processors, so, too, the ten func­ a job is then optimized to the main sequence tional units are hidden behind the central regis­ and excludes the housekeeping. The two cate­ ters from central memory. As a consequence, gories operate concurrently. a considerable instruction efficiency is obtained It would be, of course, most attractive to and an interesting form of concurrency is feasi­ provide in a general purpose device some gen­ ble and practical. The fact that a small number eralized scheme to do the same kind of thing.
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