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Performing the Shuffle with the PM2I and Illiac SIMD Interconnection Networks
Performing the Shuffle with the PM2I and Illiac SIMD Interconnection Networks Robert R. Seban Howard Jay Siegel Purdue University School of Electrical Engineering West Lafayette, Indiana 47907 Abstract—Three SIMD single stage interconnection networks which have been proposed and studied in the literature are the Illiac, PM2I, and Shuffle-Exchange. Here the ability of the Illiac and PM2I networks to per- form the shuffle interconnection in an SIMD machine with N processors is examined. A lower bound of 3\/N/2 transfers for the Illiac to shuffle data is derived. An algorithm to do this task in 2\/N-l transfers is given. A lower bound of log2N transfers for the PM2I to shuffle data has been published previously. An algo- rithm to do this task in log2N + l in transfers is presented here. 1. Introduction This paper extends SIMD interconnection network studies presented in [28, 31]. In particular, the ability of Fig. 1: PE-to-PE SIMD machine configuration, with the PM2I and Illiac single stage interconnection SIMD machine networks to perform the shuffle interconnection NPEs. is examined. In [28] it is shown that a lower bound on of configuration is shown in Fig. 1. It is called the PE- the number of transfers needed for the PM2I network to to-PE organization. The network is unidirectional and perform the shuffle is log2N, where N is the number of connects each PE to some subset of the other PEs. A processing elements in the SIMD machine. The algo- transfer instruction causes data to be moved from each rithm presented here requires only (log2N) + l transfers. -
Magnetic Peripherals Inc Storage Module Drive Vintage: C.1975 Synopsis: 14-Inch Cartridge Disk Drive
AccessionIndex: TCD-SCSS-T.20121208.028 Accession Date: 8-Dec-2012 Accession By: Tom Kearney Object name: Magnetic Peripherals Inc Storage Module Drive Vintage: c.1975 Synopsis: 14-inch cartridge disk drive. S/N: 652128. Description: Magnetic Peripherals Inc (MPI), of Minneapolis, Minnesota , was a joint venture formed by Control Data Corporation (CDC) and Honeywell Bull in 1975. CDC contributed their disk drive facilities at Normandale and Omaha, USA. Honeywell contributed its ex-GE disk plant at Oklahoma City and CII-Honeywell Bull’s plant at Heppenheim, Germany. Its early products were IBM-3330-like third generation disk drives, superceded by IBM-3340/3350/3370-like drives, all with IBM interfaces or Storage Module Device (SMD) interfaces. It became a major player in the hard disk drive market. It was the world wide leader in 14-inch disk drive technology in the OEM marketplace in the 1970s and early 1980s, especially with its SMD and CMD (Cartridge Module Drive) interfaces, and with its 24-hour/7-days-a-week plant at Brynmawr in South Wales, which celebrated the production of 1 million disks and 3 million magnetic tapes in Oct-1979. MPI was renamed Imprimus in 1988 and was bought by Seagate in 1989. The drive in this collection looks almost identical to a CDC9762 80MB disk drive, introduced in 1974 by CDC, see Figures 21 and 22. However, the drive in this collection was made in Portugal by Magnetic Peripherals Inc, and from the rear can be seen to have a different interface, which looks very like an SMD interface. -
Sperry Corporation, UNIVAC Division Photographs and Audiovisual Materials 1985.261
Sperry Corporation, UNIVAC Division photographs and audiovisual materials 1985.261 This finding aid was produced using ArchivesSpace on September 14, 2021. Description is written in: English. Describing Archives: A Content Standard Audiovisual Collections PO Box 3630 Wilmington, Delaware 19807 [email protected] URL: http://www.hagley.org/library Sperry Corporation, UNIVAC Division photographs and audiovisual materials 1985.261 Table of Contents Summary Information .................................................................................................................................... 3 Historical Note ............................................................................................................................................... 4 Scope and Content ......................................................................................................................................... 5 Arrangement ................................................................................................................................................... 6 Administrative Information ............................................................................................................................ 6 Related Materials ........................................................................................................................................... 7 Controlled Access Headings .......................................................................................................................... 8 Bibliography -
Online Sec 6.15.Indd
6.155.9 Historical Perspective and Further Reading Th ere is a tremendous amount of history in multiprocessors; in this section we divide our discussion by both time period and architecture. We start with the SIMD approach and the Illiac IV. We then turn to a short discussion of some other early experimental multiprocessors and progress to a discussion of some of the great debates in parallel processing. Next we discuss the historical roots of the present multiprocessors and conclude by discussing recent advances. SIMD Computers: Attractive Idea, Many Attempts, No Lasting Successes Th e cost of a general multiprocessor is, however, very high and further design options were considered which would decrease the cost without seriously degrading the power or effi ciency of the system. Th e options consist of recentralizing one of the three major components. Centralizing the [control unit] gives rise to the basic organization of [an] . array processor such as the Illiac IV. Bouknight et al. [1972] Th e SIMD model was one of the earliest models of parallel computing, dating back to the fi rst large-scale multiprocessor, the Illiac IV. Th e key idea in that multiprocessor, as in more recent SIMD multiprocessors, is to have a single instruction that operates on many data items at once, using many functional units (see Figure 6.15.1). Although successful in pushing several technologies that proved useful in later projects, it failed as a computer. Costs escalated from the $8 million estimate in 1966 to $31 million by 1972, despite construction of only a quarter of the planned multiprocessor. -
(U) NSA's Key Role in Major Developments in Computer Science
.............. -· ,.. , __ .,,...... ___ , _.,.._ ~ __ ....:" -..... .. Doc ID: 6586785 _ __ I 5 SSRFI;';'?Et U 'f'; !! i; I llJ l!llft, I dL& (U) NSA's Key Role in Major Developments in Computer Science PART ONE (U) Cryptology has historically entailed an intensive application of labor. But since the middle of the last century, automation has been used as a way to greatly ease the making and breaking of codes. The formation and maturation of the National Security Agency (NSA) and the evolution of its missions paralleled in large part the advent of the computer age. A!J a consequence, the NSA and its predecessor agencies have historically been at the forefront of computer development in the United States. {U) But the use of computational machines in American cryptology long predated the official birth ofNSA. During World War I, the military incorporated use of encryption equipment. During the 1930s, both the Army and Navy cryptologic components acquired devices from International Business Machines {IBM), which allowed them to sort large amounts of data. By the time World War II had broken out, all of the major combatants possessed sophisticated cipher machines for most of their communications generation and security programs. {U) As the war progressed, the U.S. military services placed many electronic accounting machines into the field in order to process a wide array of enemy signals. The services developed relationships with industry -- Bell Laboratories and Teletype Corporation in the case of the Army, and IBM, Eastman Kodak, and National Cash Register (NCR) in the case of the Navy. A prime example of the benefits of such relationships was the construction of the Navy's cryptanalytic "Bombe," a machine built by NCR to decipher messages from the German ENIGMA machine. -
SIMD1 Ñ Illiac IV
Illiac IV History Illiac IV n First massively parallel computer ● SIMD (duplicate the PE, not the CU) ● First large system with semiconductor- based primary memory n Three earlier designs (vacuum tubes and transistors) culminating in the Illiac IV design, all at the University of Illinois ● Logical organization similar to the Solomon (prototyped by Westinghouse) ● Sponsored by DARPA, built by various companies, assembled by Burroughs ● Plan was for 256 PEs, in 4 quadrants of 64 PEs, but only one quadrant was built ● Used at NASA Ames Research Center in mid-1970s 1 Fall 2001, Lecture SIMD1 2 Fall 2001, Lecture SIMD1 Illiac IV Architectural Overview Programming Issues n One CU (control unit), n Consider the following FORTRAN code: 64 64-bit PEs (processing elements), DO 10 I = 1, 64 each PE has a PEM (PE memory) 10 A(I) = B(I) + C(I) ● Put A(1), B(1), C(1) on PU 1, etc. n CU operates on scalars, PEs on vector- n Each PE loads RGA from base+1, aligned arrays adds base+2, stores into base, ● All PEs execute the instruction broadcast where “base” is base of data in PEM by the CU, if they are in active mode n Each PE does this simultaneously, giving a speedup of 64 ● Each PE can perform various arithmetic ● and logical instructions For less than 64 array elements, some processors will sit idle ● Each PE has a memory with 2048 64-bit ● words, accessed in less than 188 ns For more than 64 array elements, some processors might have to do more work ● PEs can operate on data in 64-bit, 32-bit, and 8-bit formats n For some algorithms, it may be desirable to turn off PEs n Data routed between PEs various ways ● 64 PEs compute, then one half passes data to other half, then 32 PEs compute, n I/O is handled by a separate Burroughs etc. -
Sperry Corporation, Univac Division Records 1825.I
Sperry Corporation, Univac Division records 1825.I This finding aid was produced using ArchivesSpace on September 14, 2021. Description is written in: English. Describing Archives: A Content Standard Manuscripts and Archives PO Box 3630 Wilmington, Delaware 19807 [email protected] URL: http://www.hagley.org/library Sperry Corporation, Univac Division records 1825.I Table of Contents Summary Information .................................................................................................................................... 4 Historical Note ............................................................................................................................................... 4 Scope and Content ......................................................................................................................................... 5 Administrative Information ............................................................................................................................ 7 Related Materials ........................................................................................................................................... 8 Controlled Access Headings .......................................................................................................................... 9 Appendices ..................................................................................................................................................... 9 Bibliography ................................................................................................................................................ -
VHSIC and ETA10
VHSIC and The First CMOS and Only Cryogenically Cooled Super Computer David Bondurant Former Honeywell Solid State Electronics Division VHSIC System Applications Manager ETA10 Supercomputer at MET Office - UK’s National Weather Forecasting Service Sources • “Very High Speed Integrated Circuits (VHSIC) Final Program Report 1980-1990, VHSIC Program Office”, Office of the Under Secretary of Defense for Acquisition, Deputy Director, Defense Research and Engineering for Research and Advanced Technology, September 30, 1990 • Carlson, Sullivan, Bach, and Resnick, “The ETA10 Liquid-Nitrogen-Cooled Supercomputer System”, IEEE Transactions on Electron Devices, Vol. 36, No. 8, August 1989. • Cummings and Chase, “High Density Packaging for Supercomputers” • Tony Vacca, “First Hand: The First CMOS And The Only Cryogenically Cooled Supercomputer”, ethw.org • Robert Peglar, “The ETA Era or How to (Mis-)Manage a Company According to Control Data Corp.”, April 17, 1990 Background • I graduated from Missouri S&T in May 1971 • My first job was at Control Data Corporation, the leading Supercomputer Company • I worked in Memory Development • CDC 7600 was in production, 8600 (Cray 1) was in development by Seymour Cray in Chippewa Falls, WI • Star 100 Vector Processor was in Development in Arden Hills • I was assigned to the development of the first DRAM Memory Module for a CDC Supercomputer • I designed the DRAM Module Tester Using ECL Logic Control Data Corporation Arden Hills • First DRAM Module was 4Kx32 using 128 1K DRAM Development Center - June 1971 Chips -
Vector Machines Vector Machines Today Introduction a Vector Processor Is a CPU That Can Run One Instructiononanentire Vector of Data
Hakam Zaidan Stephen Moore Outline Vector Architectures Properties Applications History Westinghouse Solomon ILLIAC IV CDC STAR 100 Cray‐1 Other Cray Vector Machines Vector Machines Today Introduction A Vector processor is a CPU that can run one instructiononanentire vector of data. The fetched number of instructions are small. They also achieve data parallelism in large scientific and multimedia applications. Styles of Vector Architectures Based on how the operands are fetched, vector processors can be divided into two categories: Memory‐Memory Architecture. Vector‐Register Architecture. Vector Processor Elements Vector Register: Fixed length, single vector, ports for reading and writing. Usually 8 to 32 registers of length 64 or 128 bits. Vector Functional Units (FUs): Usually 4‐8 functional units: FP mult, FP add, and FP divide, in addition to the integer add and logical shift Vector Load Store Unit (LSUs). Scalar registers. Cross‐bar. Vector Processor Properties Results are independent. Known pattern for memory access by the vector instructions. In pipelines, branches and branch problems are reduced. Single vector instruction indicate huge amount of calculations (e.g. loops). Disadvantages With scalar instructions: Relatively slow. Some difficulties in the implementation of the precise exceptions. High cost for on‐chip vector memory systems. Code complexity. Applications Lossy compression. Lossless compression. Multimedia Processing. Standard benchmarking kernels. Handwriting recognition. Speech recognition. Cryptography. Operating system and networking. Databases. Support of language run‐time. History In 1962, Illinois Automatic Computer series of super computers ILLIAC I, ILLIAC II, ILLIAC III, ILLIAC IV (with 64 ALUs 100‐ 150 Mflops). In 1973 TI’s Advance Scientific Computer (ASC) 20‐80 Mflops. -
PARALLEL OPERATION in the CONTROL DATA 6600 James E
PARALLEL OPERATION IN THE CONTROL DATA 6600 James E. Thornton Control Data Corporation Minneapolis, Minnesota HISTORY survived early difficulties to become the basis for a nice jump in circuit performance. About four years ago, in the summer of 1960, Control Data began a project which cul SYSTEM ORGANIZATION minated last month in the delivery of the first 6600 Computer. In 1960 it was apparent that The computing system envisioned in that brute force circuit performance and parallel project, and now called the 6600, paid special operation were the two main approaches to attention to two kinds of use, the very large any advanced computer. scientific problem and the time sharing of This paper presents some of the consid smaller problems. For the large problem, a erations having to do with the parallel opera high-speed floating point central processor with tions in the 6600. A most important and access to a large central memory was obvious. fortunate event coincided with the beginning Not so obvious, but important to the 6600 of the 6600 project. This was the appearance system idea, was the isolation of this central of the high-speed silicon transistor, which arithmetic from any peripheral activity. 4096 WORD 4096 WORD 4096 WORD 4096 WORD CORE MEMORY CORE MEMORY ~ ~ CORE MEMORY CORE MEMORY PERIPHERAL PERIPHERAL PERIPHERAL PERIPHERAL & CONTROL & CONTROL & CONTROL & CONTROL PROCESSOR PROCESSOR PROCESSOR PROCESSOR 6600 CENTRAL MEMORY 4096 WORD 4096 WORD CORE MEMORY CORE MEMORY PERIPHERAL 6600 CENTRAL PROCESSOR PERIPHERAL & CONTROL & CONTROL PROCESSOR PROCESSOR 6600 CENTRAL MEMORY 4096 WORD 4096 WORD 4096 WORD 4096 WORD ~ CORE MEMORY - CORE MEMORY +- CORE MEMORY CORE MEMORY PHERIPHERAl PERIPHERAL PERIPHERAL PERIPHERAL & CONTROL & CONTROl. -
TIME-SHARING CONTROL DATA® 3300/3500 Computer Systems
TIME-SHARING CONTROL DATA® 3300/3500 Computer Systems Equipment Bulletin Pub. No. 60156000 © 1965, Control Data Corporation November, 1965 Printed in United States of America CONTENTS 1. Introduction Relocation 4-2 Page Structure 4-2 2. Modular Description Address Relocation 4-4 3. Software Systems Program Address and MASTER 3-1 Program Address Group 4-4 Real-Time SCOPE 3-1 ISR and OSR 4-4 MSIO 3-2 Page Index File 4-8 File Manager 3-3 Page Index 4-9 Disk SCOPE 3-3 Partial Page Adder 4-12 Relocated Address 4-13 4. Multiprogramming Concepts Page Zero Considerations 4-13 Executive Mode 4-1 Instructions 4-13 Monitor State 4-1 3300 and 3500 Instruction List 4-14 Program State 4-1 FIGURES 2-1 3300 Computer System Console 2-2 4-7 Example of Page Index Refer- encing 4-8 4-1 Address Relocation Process 4-3 4-8 Page Index Format 4-9 4-2 Word Addressing 4-4 4-9 Relocation Chassis Display Panel 4-9 4-3 Character Addressing 4-4 4-10 Storage Address Buses 4-10 4-4 Program Address Group 4-5 4-11 Page Length Subdivisions 4'-10 4-5 Page Index File Address and Hardware Structure 4-6 4-12 Quarter Page in Relation to PP Designator 4-11 4-6 Relocation System illustrating Memory Protection with Fully 4-13 Starting Quarters versus Relative Expanded Memory (262K) 4-7 Quarters 4-12 iii BUSINESS AND INDUSTRY: ... .•• ... · .• ·• •. ·• • SPACE ... ... .. •• .. ..• TIME -SHARI NG SYSTEMS •• FOR BUSINESS, SCIENTIFIC • .. & REAL -TIME APPLICATIONS ..•• .• 1. -
Cray Supercomputers Past, Present, and Future
Cray Supercomputers Past, Present, and Future Hewdy Pena Mercedes, Ryan Toukatly Advanced Comp. Arch. 0306-722 November 2011 Cray Companies z Cray Research, Inc. (CRI) 1972. Seymour Cray. z Cray Computer Corporation (CCC) 1989. Spin-off. Bankrupt in 1995. z Cray Research, Inc. bought by Silicon Graphics, Inc (SGI) in 1996. z Cray Inc. Formed when Tera Computer Company (pioneer in multi-threading technology) bought Cray Research, Inc. in 2000 from SGI. Seymour Cray z Joined Engineering Research Associates (ERA) in 1950 and helped create the ERA 1103 (1953), also known as UNIVAC 1103. z Joined the Control Data Corporation (CDC) in 1960 and collaborated in the design of the CDC 6600 and 7600. z Formed Cray Research Inc. in 1972 when CDC ran into financial difficulties. z First product was the Cray-1 supercomputer z Faster than all other computers at the time. z The first system was sold within a month for US$8.8 million. z Not the first system to use a vector processor but was the first to operate on data on a register instead of memory Vector Processor z CPU that implements an instruction set that operates on one- dimensional arrays of data called vectors. z Appeared in the 1970s, formed the basis of most supercomputers through the 80s and 90s. z In the 60s the Solomon project of Westinghouse wanted to increase math performance by using a large number of simple math co- processors under the control of a single master CPU. z The University of Illinois used the principle on the ILLIAC IV.