A Potentiometric Analyser Based on the ZX81 Microcomputer
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Journal of Automatic Chemistry, Volume 5, Number 4 (October-December 1983), pages 174-181 A potentiometric analyser based on the ZX81 microcomputer S. W. Bateson, G. J. Moody and J. D. R. Thomas Applied Chemistry Department, Redwood Building, UWIST, Cardiff CF1 3XA, UK Introduction The Sinclair ZX81 microcomputer, with television, cassette- recorder and ZX printer, provides the necessary control and Automation can remove of the tedium and much labour from processing facilities. Besides being easily obtainable it has the titration, and the availability of personal computers permits advantages of a powerful Z80 microprocessor, a corrosion- efficient control and the for fast at a opportunity data-processing resistant membrane keyboard, and full access to all system lines low cost. In addition, the of the allows versatility computer at the rear-edge connector. It is programmed in BASIC and almost of any type potentiometric determination, including machine code. Gran's This describes a titration unit plot. paper controlled by a Various potentiometric electrode systems have been used, ZX81 microcomputer through a parallel bus interface system, and their potentials monitored by an Intersil-Datel 42X-digit which can also be used for calibrating electrodes with respect to millivoltmeter (Type 4101L) fitted with a differential high- ion concentration; this is illustrated for a precipitation titration impedance input buffer. of silver nitrate with bromide using a silver wire indicator A Bryans (J-J Instruments type PL3) X-Y recorder is used to electrode and glass reference electrode (Corning Model No. 33 make high-resolution plots of titration and derivative curves. 1070 030). With the standard program (obtainable from the authors) three plots (titration curve, second derivative, and calibration curve Instrumentation for direct potentiometry) are drawn on to A3 paper. The instrumentation layout is shown in figure 1. The titrator employs a Mettler DV11 digital burette, which is driven by a stepper motor, and which, when fitted with a 10cm cylinder assembly (Mettler DV210), can deliver titrant in mm (#1) A4 increments. Memory A15 Electrodes Decoder IC1,2 CPU Select Burette X-Y recorder Millivoltmeter Datalc4buffer 7/// 7///////// Interface '//////// Memory Interface system "/" routing Interface Memory TV ZX 81 Cassette monitor AO A -/////////////f///////////j'///////l/Ill Memory Partial decoding Interface Printer IC5 Fi#ure 1. Auto-titrator system Figure 2. Address decoder block diagram. 174 S. W. Bateson et al. A potentiometric analyser based on the ZX81 From ZX 81 edge connector 1N914 ROM CS IClc A15 13 9 A14 1 12 IC2 10 2 11 4 ICla,b 5 6 A5 ,11 SELECT 12 IC3 1 A13 WR .memory A12 All AIO WR interface A7 10 A6 12 RD interface WR 13 IC4 J,, DO 2 19 18- D1 17 BD1 Data D2 16 BD2 lines D3 15 BD3 IC1:74LS27 IC2." 74LS30 D4 1 14 BD4 IC3." 74 LS32 IC4." 74 LS245 =C 5 IC5-" 74 LS139 1 --,---ADC A3 3 DAC1 Address A2 bAC2 lines A1 AO AO Figure 3. ZX81 address decoder. 175 S. W. Bateson et al. A potentiometric analyser based on the ZX81 These units are connected via the interface system (figure (PEEK and POKE being BASIC commands to examine or alter, l)---the interface is a parallel bus-oriented system and com- respectively, the contents of specified memory locations). It parable to the IEEE 488 bus [1]. However, the complexity of the operates by redefining 16 memory-locations from 15552 to full IEEE standard was considered inappropriate, since this 15567 as interface addresses. The block diagram (figure 2) system was conceived as a highly cost-effective addition to the clarifies this. The circuit diagram is given in figure 3. existing data/address bus structure of a Z80-based microcom- When the correct combination appears on the address lines puter. The design and development of the interface is discussed (i.e. A 4, 5, 8, 9, 14, 15 LOW; A 6, 7, 10, 11, 12, 13 HIGH) the below. decoder (ICI, IC2) activates the 'SELECT' lines (figure 3). These then operate the routing circuit (IC3) and divert the RD and WR signals away from the memory and into the interface. (Note [a] The ZXS1 interface system the bars in RD and WR indicate that these lines go LOW when The design used was a memory-mapped interface: it is accessed active, a common feature of control lines, and [hi RD and WR by the CPU in the same way as any normal memory location. signals always appear shortly after the address is established.) The chief advantage of this method is that the circuitry can be This will occur regardless of the state of the lowest four address operated from BASIC via simple PEEK and POKE commands lines A0-A3, i.e. for 24 or 16 addresses. In this system, the BD3 20 1 BD2- 6 10 21 7 DAC resei BD1 3 15 22 6 = ailli'vo'ltreter hold BDO- ,2 4,13 16 23 5 C6 4 Pen lift IC8b IC8a 33k 33k 33k BC307 BC307 BC307 lk5 lk5 lk5 3) 9) BZY88C15 BZY88C15 BZY88C15 IC6 74LS75 IC7 74LS154 IC8 74LS02 Figure 4. Digitally controlled switch. 176 S. W. Bateson et al. A potentiometric analyser based on the ZX81 addresses from 15552 to 15567 are used. These addresses have In this design, a bidirectional tri-state buffer (IC4, figure 3) is been shared between four distinct circuit functions, as follows" used to isolate the external circuitry from the ZX81. Since the rest of the interface design consists either of inputs driven by the 15552-15555: analogue-to-digital converter (ADC) ZX81 or of tri-state outputs this may seem unnecessary; but 15556-15559: digital-to-analogue converter (DAC1) since in practice there is a limit to the number of device inputs 15560-15563: digital-to-analogue converter (DAC2) (and, due to capacitance effects, the length of wire) a Z80 CPU 15564-15567: digitally controlled switch (SW). can drive [2], this buffer was found essential. (Most microcom- These are selected by decoding A2 and A3 into four lines (IC5, puter systems are fully buffered as standard; the ZX81, for figure 3). This leaves A0 and A1 to control the circuit blocks. reasons of cost, is not.) The buffer normally isolates in both directions; when the millivoltmeter circuit is addressed it is switched to receive data (by IC5) and when any other part is Tri-state logic and buffering addressed, it sends data. The remaining circuit blocks are now So that data lines may be shared by all sections of a computer, described in order of complexity. 'tri-state' logic is used. Here, any part of the circuit which can send a signal to the bus has three possible outputs: low, high, and Digitally controlled switch high-impedance (isolated). Only one device is enabled at a time, A single 16-way switch, operated by any of the addresses 15564- thereby avoiding the possibility of two outputs conflicting. 15567, has been provided (figure 4). Devices are generally enabled under CPU control, via the IC6 (figure 4) is a four-bit latch which acts as a buffer when address and RD or WR lines etc. enabled, but holds its outputs when disabled. It is enabled when V ref (-1.26 V) to DAC2 lk2 +4V ZN423 IC9 15 14 Analogue BD3- 4 BD2 BD1 1Ok multiturn BDO 'Set zero' wR 9 10 11 813 lk2 +5V DAC1 L___] +4Vonf" 'L lOOl.lf DAC reset T IC 9 RS 7542 LlOOp, IC10; LF 351 Earth1Onf _ lk2 -5V Figure 5. Digital-to-analogue converter. 177 S. W. Bateson et al. A potentiometric analyser based on the ZX81 Table 1. Digital switch functions Thus, when the first DAC address is selected (DAC1 low, A0, A1 low) the first converter will expect the four least significant Function n IC7 pin bits to be present on the data bus when the WR (Write) line goes low; when the second address is selected (A0 high, rest as before) Normal (no function) 0 "1 the device will expect the middle four bits; similarly for the third Add 0.001 cm from burette 2 address and the four most significant bits. Add 0.1 cm from burette 2 3 is the data Refill burette 3 4 When the fourth address (A0, A1 high) selected, Lower chart recorder pen 4 5 lines are ignored and the data previously collected is transferred Hold millivoltmeter reading 5 6 to the 12-bit output register of IC9, from which the appropriate Reset D-A converters to zero 6 7 analogue voltage is derived. The CLEAR input (figure 5) can be used to reset the 12-bit register to zero, and is operated by the SW function described addressed, i.e. when WR and SW go low. Data is then passed to earlier. In the circuit offigure 5, the output voltage ranges from 0 IC7, a 4-to-16-1ine decoder. Addressing the circuit from BASIC to (-4095/4096)xVref, so the reference voltage must be by the instruction POKE 15567, n (n 0-15), causes output n of negative for a positive output range. The negative supply for the IC7 to go low, the others remaining high. The seven functions reference and output amplifiers is taken from the analogue-to- required in this application, together with values for n and digital converter (see below) which has an on-board supply output pin numbers for IC7, are given in table 1. inverter. The Mettler burette uses 18 V switching levels, which are driven from 5 V logic by the level-shifting circuits shown on IC7 pins 2, 3 and 4. Pin numbers for the Mettler multi-way connector Analogue-to-digital converter (ADC) are also shown.