PCI Development Backplane
User’s Guide
October 1998
Order Number: 278149-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 21285 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners. **ARM and StrongARM are trademarks of Advanced RISC Machines, Ltd.
PCI Development Backplane User’s Guide Contents
1 Introduction...... 1-1 1.1 Purpose ...... 1-1 1.2 Audience ...... 1-1 1.3 Manual Organization ...... 1-1 1.4 Conventions ...... 1-2 1.4.1 Caution ...... 1-2 1.4.2 Note...... 1-2 1.4.3 Numbering...... 1-2 1.4.4 Signal Notation ...... 1-2 1.5 Associated Documents...... 1-2 1.6 StrongARM and PCI...... 1-3 1.7 Key Features...... 1-4 2 Installation ...... 2-1 2.1 Delivered Items ...... 2-1 2.2 Preparation...... 2-1 2.3 Fitting the Board ...... 2-2 2.4 Connection of Power Supplies ...... 2-2 3 General Description...... 3-1 3.1 Overview ...... 3-1 3.2 Signal Lines...... 3-2 3.2.1 General...... 3-2 3.2.2 Interrupts ...... 3-3 3.2.3 Reset ...... 3-4 3.3 Arbitration ...... 3-4 3.4 System Clocks...... 3-4 3.5 System Slot Compatibility Issues ...... 3-5 4 Configuration...... 4-1 4.1 Backplane Variants ...... 4-1 4.1.1 EBSA-BPL-5V ...... 4-1 4.1.2 EBSA-BPL-3V3 ...... 4-1 4.2 Configuration Options...... 4-1 4.2.1 Etchlinks ...... 4-2 4.3 Configuring the Backplane ...... 4-3 4.3.1 Power Provision ...... 4-3 4.3.2 ID Select...... 4-4 4.3.3 Arbiter...... 4-4 4.3.3.1 Arbiter Source ...... 4-4 4.3.3.2 Lock...... 4-4 4.3.3.3 Arbiter Algorithm...... 4-4 4.3.4 Clock Frequency ...... 4-4 4.4 Quick Reference Configuration Tables ...... 4-5 A Technical Data ...... A-1 A.1 Electrical Data ...... A-1
PCI Development Backplane User’s Guide iii A.2 Mechanical Data ...... A-1 A.3 Construction ...... A-2 A.4 Test Points ...... A-2 B Layout and Circuit Diagrams...... B-1 B.1 Movable Keys...... B-3 C Bill of Materials...... C-1 Figures
1-1 The 21285 in an SA-110 System ...... 1-3 1-2 Backplane Block Diagram ...... 1-3 2-1 Backplane Dimensions...... 2-2 3-1 Backplane Layout...... 3-1 3-2 Backplane Block Diagram ...... 3-2 3-3 Backplane Implementation of PCI bus ...... 3-2 4-1 Example of Etchlink...... 4-2 4-2 Etchlink and Header Locations ...... 4-2 4-3 Power Connector Details ...... 4-3 B-1 Backplane Arrangement in a PC/AT Chassis ...... B-1 B-2 Jumper and Connector Locations ...... B-2 B-3 Circuit Diagram: System Slot ...... B-4 B-4 Circuit Diagram: Slot 1 ...... B-5 B-5 Circuit Diagram: Slot 2 ...... B-6 B-6 Circuit Diagram: Slot 3 ...... B-7 B-7 Circuit Diagram: Slot 4 ...... B-8 B-8 Circuit Details: Arbitration and System Clock Logic ...... B-9 B-9 Circuit Details: Power Connectors ...... B-10 C-1 Bill of Materials...... C-2 Tables
3-1 Interrupt Line Connections ...... 3-3 3-2 System Slot Arbiter: PCI Pinout (Request) ...... 3-5 3-3 System Slot Arbiter: PCI Pinout (Grant)...... 3-5 4-1 Power Connector Combinations ...... 4-5 4-2 IDSEL Configuration ...... 4-5 4-3 Selection of Arbiter Source ...... 4-5 4-4 Selection of Clock Frequency ...... 4-5
iv PCI Development Backplane User’s Guide Introduction 1
1.1 Purpose
This manual describes the features, installation and configuration of Intel’s custom PCI development backplane. The backplane allows a wide variety of StrongARM** (and mixed processor) topologies to be tested. Specifically, it will allow verification and evaluation of all 21285 PCI I/O support component and future PCI related StrongARM product line developments as system masters and intelligent devices in desktop/server environments.
1.2 Audience
The manual is intended for use by researchers, designers and developers who wish to experiment with or develop a variety of StrongARM-based system architectures using PCI as the primary interconnect mechanism.
1.3 Manual Organization
• Chapter 1, “Introduction”, introduces the PCI development backplane and identifies its key features. • Chapter 2, “Installation”, provides general information on installation and connection of power. • Chapter 3, “General Description”, provides an overview of the backplane, explains the implementation of signals and identifies compatibility issues. • Chapter 4, “Configuration”, identifies and describes the configurable options and provides tables of jumper settings. • Appendix A, “Technical Data”, provides electrical and mechanical information about the backplane. • Appendix B, “Layout and Circuit Diagrams”, provides layout and circuit diagrams for completeness and to explain configuration options. • Appendix C, “Bill of Materials”, provides a combined bill of materials for the EBSA-BPL-5V and EBSA-BPL-3V3 Development Backplanes.
PCI Development Backplane User’s Guide 1-1 Introduction
1.4 Conventions
This section defines product-specific terminology, abbreviations, and other conventions used throughout this manual.
1.4.1 Caution
Cautions indicate potential damage to equipment or loss of data.
1.4.2 Note
Notes emphasize particularly important information.
1.4.3 Numbering
All numbers are decimal or hexadecimal unless otherwise indicated. The prefix 0x indicates a hexadecimal number. For example, 19 is decimal, but 0x19 and 0x19A are hexadecimal. Otherwise, the base is indicated by a subscript; for example, 1002 is a binary number.
1.4.4 Signal Notation
In the circuit diagrams provided in Appendix B, active negative signals are indicated by a bar or overline; for example, FRAME. Active positive signals have no bar.
Multiple signals are indicated by a colon and square brackets. For example AD[7:0] refers to address and data lines 7, 6, 5, 4, 3, 2, 1 and 0.
In text, active negative signals are suffixed by a # character. For example, IRDY#. Active positive signals have no suffix. This is consistent with the signal naming convention used in the PCI Local Bus specification.
1.5 Associated Documents
The following associated documents may be required or helpful when using this manual: • PCI Local Bus Specification, Revision 2.1. • Cypress CY2260 datasheet (available from http://www.cypress.com). • Cypress application notes (Crystal Oscillator Topics, Jitter in PLL-based Systems, Layout and Termination Techniques). (all available from http://www.cypress.com) • Intel AP-523 application note; Pentium® Pro Processor Power Distribution Guidelines (available from http://www.intel.com under Pentium® Pro processors). This application note describes the VRM module. • Semtech MP60 VRM Module Specification (available from http://www.semtech.com).
1-2 PCI Development Backplane User’s Guide Introduction
1.6 StrongARM and PCI
The 21285 Core Logic Controller is part of Intel’s provision of PCI I/O support for the StrongARM product family. Specifically, it is a support device for the SA-110 StrongARM microprocessor, integrating an SDRAM memory controller, PCI bus, DMA engine, UART (data leads only), timers, interrupt control, boot ROM/Flash and low speed (X-bus) I/O in a single device. The chip supports an optional system arbiter, which shares pins with the X-bus control signals making it an either/or option. Figure 1-1 shows a diagram of the 21285 and SA-110 in a Host Bridge application. Figure 1-1. The 21285 in an SA-110 System
The 21285’s PCI interface can be statically configured in one of two modes: • As a device (configuration space enabled peripheral) on PCI • As the system master (Host Bridge)
An evaluation board (EBSA-285) supporting both modes is available. It can also operate standalone where PCI is not required.This manual describes Intel’s custom PCI backplane (Figure 1-2), which complements the EBSA-285 offering. The backplane allows a wide variety of StrongARM (and mixed processor) topologies to be tested. Specifically, it will allow verification and evaluation of the 21285 and future PCI related StrongARM product line developments as system masters and intelligent devices in desktop/server environments. Figure 1-2. Backplane Block Diagram aa002 4btPIsse slot system PCI 64-bit 4btPIso 2 slot PCI 64-bit 4btPIso 3 slot PCI 64-bit 4btPIso 1 slot PCI 64-bit 4btPIso 4 slot PCI 64-bit
Clocks Arbiter
64-bit PCI bus
PCI Development Backplane User’s Guide 1-3 Introduction
1.7 Key Features
The backplane provides the following: • Support for all features on the EBSA-285 module. • An environment for verification, evaluation and benchmarking of StrongARM PCI support with the widest possible range of PCI peripherals. For this reason, the standard PCI I/O form factor adopted by the PC industry is used. • The ability to use industry standard enclosures and PSUs. • An environment suitable for testing all of Intel’s current and future (standard form-factor assumed) PCI peripheral cards from the PPB, multimedia and communications business units with the StrongARM processor family. Of particular importance is interworking with the PCI bridge evaluation boards, allowing a wide variety of bridged bus topologies to be investigated and/or verified. • 64-bit support (for future-proofing of the design). • Two variants; EBSA-BPL-5V complying with the 5 V PCI signalling environment, and EBSA-BPL-3V3 with the 3.3 V PCI signalling environment. • Backplane provision of the PCI system clock and PCI arbitration. • Optional support of PICMG-style1 arbitration from the system slot. • Several link options have been provided to support different system configurations (see Section 4.2.1).
1. PICMG = PCI Industrial Computer Manufacturers Group. Please see their website (www.picmg.com) for more details.
1-4 PCI Development Backplane User’s Guide Installation 2
2.1 Delivered Items
You should have received: • This manual. • Either backplane EBSA-BPL-5V (5 V signal levels) or EBSA-BPL-3V3 (3.3 V signal levels). • A Voltage Reference Module (VRM). This may be separate, or it may be factory-fitted in connector J3.
With regard to installation, both boards are identical and will be installed in the same manner.
You will also need: • Either a PC/AT chassis, or standoffs for mounting the PCB • Either an AT-style PSU with +3.3 V output provision, or a standard AT-style PSU (+5 V, +12 V and -12 V only)1
Caution: If your PSU has a +3.3 V output that you wish to use, be sure to remove the VRM from the backplane BEFORE connecting power.
2.2 Preparation
The backplane offers several configuration options for selection by the user. The most likely of these have been preselected as defaults by links fabricated in the etch (etchlinks). It is expected that these will be used by the great majority of developers. Alternatives to the default options can be chosen by cutting the etchlinks and fitting header links as appropriate. As not all combinations of options may be fail-safe the user should read Chapter 4, “Configuration”, before modifying the board or applying power.
Caution: The backplane is a multilayer board. Take care not to damage etch or lower layers when cutting etchlinks. For more information, see Section 4.2.1.
1. The -5V and DC_OK pins are not connected on the backplane.
PCI Development Backplane User’s Guide 2-1 Installation
2.3 Fitting the Board
Caution: Observe proper antistatic precautions when handling the board.
The board can be fitted in any standard PC/AT enclosure. Alternatively, it can be installed on pillars on the workbench. Board dimensions are shown in Figure 2-1. Figure 2-1. Backplane Dimensions
8.65" (21.97mm) Bulkhead edge
+3.3V connector
+5V, +12V and -12V connector 7.0" (17.78mm)
Socket for +3.3V Voltage Regulator Module aa006
2.4 Connection of Power Supplies
The board can be powered by either of two methods. Use either one, but NOT both. • PC power supply with provision for +5 V, ±12 V and +3.3 V connected to J16 and J17. • Standard PC/AT supply with +5 V and ±12 V connected to J16, and a +3.3 V Voltage Reference Module (VRM)1 fitted in J3.
Note: J16 and J17 are standard PC motherboard power connectors. On J16, the -5 V and PWRGD pins are not connected.
Note: The current required by an EBSA-285 with 16 MB of SDRAM is typically 700 mA. This may be insufficient to reliably start some power supplies (PSUs). If you experience this problem, try increasing the load on the PSU by: — adding cards to the backplane configuration — attaching a disk to the PSU — attaching a suitable load resistor (5 to 10 Ω, rated at 10W) to the +5 V line of an available disk power harness. This should only be attempted by an appropriately qualified person.
1. Both backplanes are fitted with a connector to accept the supplied Voltage Reference Module (VRM). Backplane circuitry configures the installed VRM to 3.3 V.
2-2 PCI Development Backplane User’s Guide General Description 3
3.1 Overview
The backplane (Figure 3-1) is supplied in two versions; one for 5 V and one for 3.3 V signalling environments. The differences are: • The PCI connector keying • The voltage applied to the VIO power plane Figure 3-1. Backplane Layout
Power LEDs
+3.3V connector
+5V, +12V and -12V connector
Arbiter Socket for +3.3V Voltage Regulator Module aa003
PCI slots
Both boards are compliant with the standard PC/AT outline and are drilled with common mounting holes allowing it to be fitted in generic eight-slot desktop or deskside enclosures. Five full-length 64-bit PCI slots are provided.
Depending upon the backplane model purchased, the PCI slots will support either 5 V or 3.3 V cards. Both will support universal cards.
An onboard clock synthesizer provides separate PCI clocks for the five PCI slots and an onboard arbiter.
PCI Development Backplane User’s Guide 3-1 General Description
A block diagram of the backplane is shown in Figure 3-2. Figure 3-2. Backplane Block Diagram aa002 4btPIsse slot system PCI 64-bit 4btPIso 2 slot PCI 64-bit 4btPIso 3 slot PCI 64-bit 4btPIso 1 slot PCI 64-bit 4btPIso 4 slot PCI 64-bit
Clocks Arbiter
64-bit PCI bus
3.2 Signal Lines
This section describes the implementation of signal lines provided on the backplane.
3.2.1 General
The backplane provides all PCI signals except for JTAG boundary scan. The backplane implementation of the PCI bus is shown in Figure 3-3. Figure 3-3. Backplane Implementation of PCI bus
AD 31:00 AD 63:32 Address and Data C/BE 3:0# C/BE 7:4# 64-bit Address and Data PAR PAR64 Extension REQ64# FRAME# ACK64# IRDY# TRDY# LOCK# STOP# DEVSEL# IDSEL# INTA# INTB# SERR# INTC# PERR# INTD#
REQ# SBO# GNT# SDONE#
CLK# aa001 RST#
3-2 PCI Development Backplane User’s Guide General Description
All signal lines are bussed as parallel traces between all slots with the following exceptions: • The interrupt lines. • The request/grant arbitration lines. • DEVSEL to the PCI I/O slots (J4-J7). DEVSEL does not apply to the system slot. • PCI clocks. • PRSNT bits. These are ac coupled to 0 V on each of the I/O slots as additional ac grounds. • M66EN is tied to 0 V. The system is designed for 33 MHz operation only.
Pull-up resistors are provided on the following signals: • SBO# and SDONE# • REQ64# and ACK64# • FRAME#, IRDY#, TDY#, STOP#, LOCK#, and DEVSEL# • PERR# and SERR# • INTA#, INTB#, INTC# and INTD# • All arbiter request lines • All 64-bit address and data extension lines
DEVSEL may be optionally coupled via links and a resistor to a choice of AD lines as follows: • PCI I/O slot 1 - AD19 or AD31 (default AD19 via an etchlink) • PCI I/O slot 2 - AD18 or AD30 (default AD18 via an etchlink) • PCI I/O slot 3 - AD17 or AD29 (default AD17 via an etchlink) • PCI I/O slot 4 - AD16 or AD28 (default AD16 via an etchlink)
See also the note on line numbering in Section 4.3.2.
3.2.2 Interrupts
Interrupt connections are ORed in such a sequence that any add-in I/O board using INTA# can be uniquely recognized by the system.
The interrupt lines are interconnected as shown in Table 3-1.
Table 3-1. Interrupt Line Connections
pin6A pin7B pin7A pin8B
System slot INTA# INTB# INTC# INTD# I/O slot 1 INTB# INTC# INTD# INTA# I/O slot 2 INTC# INTD# INTA# INTB# I/O slot 3 INTD# INTA# INTB# INTC# I/O slot 4 INTA# INTB# INTC# INTD#
PCI Development Backplane User’s Guide 3-3 General Description
3.2.3 Reset
RESET# must be provided by the system bridge device. No provision is made on the backplane for an external reset of the PCI. The arbiter will be reset asynchronously using this signal.
3.3 Arbitration
Bus arbitration can be controlled by the backplane or from the system slot. The arbiter algorithm is compliant with the PCI Local Bus Specification, Revision 2.1. For flexibility, this is implemented via a socketed PLD (Programmable Logic Device). The backplane arbiter fitted is based on an Altera Max 7000* series device in a 68-pin PLCC package.
The following signals are routed to and from all slots to the arbiter: • A unique REQ# line for each slot with an external pullup • A unique GNT# to each slot • RESET# • FRAME# and IRDY# to identify the bus idle condition • LOCK# to identify resource lock cycles
In addition, the following backplane control inputs and monitoring outputs are provided: • A bank of programmable CONTROL bits (1 per slot) defaulted high via pull-up resistors. These static control bits can be used as part of a 2-level priority or masking algorithm for the arbiter, assuming algorithm support. The algorithm shipped as standard does not use these inputs. • An ARB_ENABLE# signal, which can be used to tri-state all outputs when an arbiter is provided by the system slot. • A LOCK_ENABLE signal to allow the arbiter to optionally lock the bus on LOCK# cycles. This allows systems to switch between bus locked and resource locked configurations assuming the correct device support (hardware and/or software). • Arbiter state monitoring outputs PCIARB[2:0] are brought out to a header for ease of connection to a logic analyzer etc.
3.4 System Clocks
System clocks are provided by a Cypress CY2260SC-3 clock synthesizer/driver and a 14.318 MHz crystal. The CY2260SC-3 has link options for 25 MHz, 27.5 MHz, 30 MHz and 33 MHz1 support. This device provides six PCI clocks with low jitter, slew limiting, and maximum skew of <250 ps in a 28-pin SOIC package. All other clock outputs are unused.
There are no provisions for 66 MHz clocking.
1. Default - via an etchlink.
3-4 PCI Development Backplane User’s Guide General Description
3.5 System Slot Compatibility Issues
Modules using the backplane arbiter must satisfy the following criteria: • Provide CONFIG cycles to configure the four I/O slots • Support the INT[A-D]# pins as inputs from the I/O slots as described in Table 3-1 • Provide PCI reset (RST#) for the system
In addition, modules providing PCI arbitration must use the system slot in the backplane and route the arbitration signals according to Table 3-2 and Table 3-3.
Table 3-2. System Slot Arbiter: PCI Pinout (Request)
Arbitrated slot REQ
I/O slot 1 18B REQ# (SYSCPU_REQ0) I/O slot 2 10B) Reserved (REQ2) I/O slot 3 19A Reserved (REQ3) I/O slot 4 9B PRSNT1# (REQ4)
Note: In the above table the first name is the name as specified in the PCI standard, the bracketed name is the signal name on the backplane.
Table 3-3. System Slot Arbiter: PCI Pinout (Grant)
Arbitrated slot GNT
I/O slot 1 17A GNT# (SYSCPU_GNT0) I/O slot 2 14A Reserved (GNT2) I/O slot 3 26A IDSEL (GNT3) I/O slot 4 11B PRSNT2# (GNT4)
Note: In the above table the first name is the name as specified in the PCI standard, the bracketed name is the signal name on the backplane.
Arbitration for the bus by the system slot module must occur within the card itself.
Note: The sharing of the grant pin and IDSEL can cause problems in systems that issue PCI configuration cycles in I/O slots. It is becoming common practice for intelligent I/O to interrogate the bus in this manner. System designs that use this backplane, and want to use system slot arbitration, must NOT tie the arbiter grant and IDSEL lines together on the module. It will not be possible for an I/O slot to interrogate the system slot with configuration cycles.
PCI Development Backplane User’s Guide 3-5
Configuration 4
4.1 Backplane Variants
Two variants with different PCI signalling voltages are available. Variant EBSA-BPL-5V provides 5 V signalling; variant EBSA-BPL-3V3 provides 3.3 V signalling. The choice of backplane purchased affects two features: • PCI connector polarization • VIO voltage level
Note: PCI signalling voltage is a factory set option. It is not user configurable.
4.1.1 EBSA-BPL-5V
On this backplane: • The PCI connectors are keyed at pin positions 62/63 and 50/51. • Soldered links W3 and W4 are fitted; W1 and W2 are not.
4.1.2 EBSA-BPL-3V3
On this backplane: • The PCI connectors are keyed at pin positions 62/63 and 12/13. • Soldered links W1 and W2 are fitted; W3 and W4 are not.
4.2 Configuration Options
Several backplane configuration options are available. These are related to: • Provision of a +3.3 V DC supply • ID Select standard • Arbiter source • Clock frequency
The last three of these options are selected by etchlinks (see the following section) or header links.
PCI Development Backplane User’s Guide 4-1 Configuration
4.2.1 Etchlinks
Etchlinks (links formed in the etch during fabrication) are used for selection of common defaults, with headers provided for jumper selection of other options. The etchlinks can be cut and jumpers fitted for verification modes, for example, switching between backplane and system-slot-based PCI arbitration. Figure 4-1 shows a general example. Figure 4-1. Example of Etchlink
Etchlink
Link default Signal
Other link option aa010
Header
Etchlinks are all on layer 1 with plenty of trace clearance to allow them to be cut without risk of accidentally damaging other inner layer traces.
The available options will now be described. Refer to Figure 4-2 for component layout and to Appendix B for circuit diagrams. A set of quick reference configuration tables is provided at the end of this chapter.
Caution: If you use header links to select your options, make sure the associated etchlinks have been cut. Figure 4-2. Etchlink and Header Locations
4-2 PCI Development Backplane User’s Guide Configuration
4.3 Configuring the Backplane
This section details the etchlinks to cut, and the jumpers to fit, for the desired method of operation.
4.3.1 Power Provision
Two mutually exclusive methods of power connection are available: • PC/AT PSU to J161 and a 3.3 V Voltage Regulator Module (VRM) on J3 • PC/AT PSU with standard and 3.3 V outputs. Standard to J161 and 3.3 V to J17
Caution: J16 and J17 are weakly keyed. Take care to use the correct connector; the keying mechanism can be easily overridden.
Layouts, pinouts and PSU sleeve colors are shown in Figure 4-3.
Note: The current required by an EBSA-285 with 16 MB of SDRAM is typically 700 mA. This may be insufficient to reliably start some power supplies (PSUs). If you experience this problem, try increasing the load on the PSU by: — adding cards to the backplane configuration — attaching a disk to the PSU — attaching a suitable load resistor (5 to 10 Ω, rated at 10 W) to the +5 V line of an available disk power harness. This should only be attempted by an appropriately qualified person. Figure 4-3. Power Connector Details
Corner of PCB
J16 J17
Orange - (nc) PWR GD 1 GND Red - +5V 2 GND Black Yellow - +12V 3 GND Blue - -12V 4 +3.3V GND 5 +3.3V GND 6 +3.3V Black - Brown GND 7 +3.3V GND 8 +3.3V White - (nc) -5V 9 +3.3V +5V 10 GND Red - +5V 11 GND Black
+5V 12 GND aa012
1. Industry standard connector supplying +5 V and ±12V (the -5 V and PWRGD pins are not connected).
PCI Development Backplane User’s Guide 4-3 Configuration
4.3.2 ID Select
On the PCI bus, AD19:16 are normally used for IDSEL#. However, the PICMG1 standard specifies AD31:28. Provision for both is made on the board. By default, AD19:16 are etchlinked to IDSEL#. If the etchlinks are cut for any reason, this same selection can be made by jumpering 2-3 on J11 to J14. For the PICMG standard, cut etchlinks EL1 to EL4, and install jumpers on J11 to J14, position 1-2.
Note: The PICMG standard specifies decrementing address line numbering with incrementing slot numbers. This is the convention adopted in the backplane labelling; however, it can be very confusing for those unaware of the issue when developing PCI configuration code.
4.3.3 Arbiter
The onboard arbiter allows the backplane to provide arbitration for the PCI bus.
4.3.3.1 Arbiter Source
Bus arbitration can be controlled from either the backplane arbiter (default) or the system slot.
Etchlinks on system-slot GNT# (EL7), system-slot REQ# (EL6) and ARB_ENABLE# (EL5) select the backplane arbiter. If the etchlinks are cut for any reason, this same selection can be made by jumpering 1-2 on J9, J10 and J15.
To use a system slot arbiter, cut etchlinks EL5-7 and fit jumpers on 2-3 of J9, J10 and J15. All three links (slot 0 grant routing, slot 0 request routing, and arbiter enable) need to be changed in unison.
4.3.3.2 Lock
LOCK_ENABLE is a control signal for the arbiter. It is pulled high by default.
4.3.3.3 Arbiter Algorithm
For developers who may wish to use their own arbitration algorithms, five optional control inputs (CNTRL 0 to 4) are made available for grounding on J1. All are pulled high by default.
4.3.4 Clock Frequency
S0 and S1 are the PCI clock speed select lines for the CY2260 clock synthesizer. Both have pullups. Options are 25 MHz, 27.5 MHz, 30 MHz and 33 MHz.
Etchlink EL8 grounds S1 (CLK_SEL 1), defaulting the bus clock to 33 MHz. If EL8 is cut, 33 MHz is selected by a jumper on header J1, CLK_SEL 1.
To select 25 MHz, cut the etchlink and fit jumpers on headers J1, CLK_SEL_0 and 1.
For 27.5 MHz, simply cut the etchlink.
For 30 MHz, cut the etchlink and fit a jumper on header J1, CLK_SEL 0.
1. PICMG = PCI Industrial Computer Manufacturers Group. Please see their website (www.picmg.com) for more details.
4-4 PCI Development Backplane User’s Guide Configuration
4.4 Quick Reference Configuration Tables
The following tables summarize the configurable options provided on the backplane. See Section 4.3 for a more detailed description.
Caution: ID select lines, arbiter source and clock frequency defaults are set by etchlinks. Do not use header links unless the associated etchlinks have been cut. Table 4-1 to Table 4-4 assume that the associated etchlinks have been cut.
Table 4-1. Power Connector Combinations
PSU type Connect to J16 Connect to J17 VRM on J3
PC/AT YES NO YES PC/AT with +3.3V YES YES NO provision
Table 4-2. IDSEL Configuration
Hdr Link in Position 1-2 Hdr Link in Position 2-3
J11 AD31 AD19 * J12 AD30 AD18 * J13 AD29 AD17 * J14 AD28 AD16 *
* Default - via EL1, 2, 3 and 4
Table 4-3. Selection of Arbiter Source
Arbiter J9 (ARB_ENABLE) J10 (REQ 0/1) J15 (GNT 0/1)
Backplane * Link position 1-2 Link position 1-2 Link position 1-2 System Link position 2-3 Link position 2-3 Link position 2-3
* Default - via EL5, 6 and 7
Table 4-4. Selection of Clock Frequency
Frequency CLK_SEL 0 CLK_SEL 1
25 MHz IN IN 27.5 MHz OUT OUT 30 MHz IN OUT 33 MHz * OUT IN
* Default - via EL8
PCI Development Backplane User’s Guide 4-5
Technical Data A
A.1 Electrical Data
The backplane complies with the PCI Local Bus Specification, Revision 2.x, thereby making the design as flexible as possible: • The larger connectors provide a 64-bit PCI environment. • 5 V or 3.3 V signalling versions available, with a VIO signal plane to provide the appropriate voltage to the connector VIO pins, the active logic, and associated pullups. • Programmable backplane arbiter provided on socket U1. This is implemented in an Altera MAX 7000* device operating at 5 V but with separate I/O power pins that can operate at 5 V or 3V3. • Low skew, slew limited system clocks to all slots and the backplane arbiter. The system clock generator is based on a Cypress CY2260-3 clock synthesizer/driver which provides six compliant PCI clock pins. The CY2260 can operate from 5 V or 3.3 V. • +5 V, +12 V and -12 V supplies from an industry standard PC/AT PSU are connected via J16. PowerOK and -5 V from the power supply are not used. • +3.3 V can either be supplied on industry standard connector J17 from a power supply unit, or it can be converted down from +5 V by a 3.3 V Voltage Reference Module (VRM) connected to J3. These two options are mutually exclusive. A warning to this effect is silk-screened onto the board.
A.2 Mechanical Data
The board is mechanically compliant with standard PC/AT outline (smaller size, using a subset of the mounting holes), allowing it to be fitted to generic 8-slot desktop or deskside enclosures. Five full-length 64-bit PCI slots are supported (no motherboard component restrictions). The PCI connectors support 5 V, 3.3 V or mixed voltage cards according to the backplane variant purchased. The five slots occupy an 8-slot AT card enclosure (reading from right to left as viewed from the rear of the enclosure) as follows: • slot 0 - empty - no connector • slot 1 - empty - no connector • slot 2 - system slot • slot 3 - PCI I/O slot 1 • slot 4 - PCI I/O slot 2 • slot 5 - PCI I/O slot 3 • slot 6 - empty - no connector • slot 7 - PCI I/O slot 4 This maximizes access to the component side of the system and one I/O slot for logic analyzer attachment, probing, daughtercards, etc.
Note: Due to the height of components, the EBSA-285 PCI Development Board occupies two slots of an AT motherboard. On the backplane, space is provided to the left of the system-slots and I/O4-slots to allow the EBSA-285 to be installed in either of these positions without sacrificing one of the other slots.
PCI Development Backplane User’s Guide A-1 Technical Data
A.3 Construction
The backplane is an 8-layer board with the following layer makeup: • Component side - pads, etchlinks and dispersion etch only • VIO - power plane • Signal layer 1 • +3.3 V plane • GND plane • Signal layer 2 • +5 V power plane • Solder side - pads only
A.4 Test Points
For ease of connection to power and ground planes, a range of through-plated holes to take 0.025 inch (0.635 mm) square-posts, is provided for the construction of test points. These are not shown on the schematics but are silk-screened on the etch. The following test point positions are provided: • GND TP1 to GND TP9 • VIO TP1 to VIO TP4 • VDD TP1 • 3V3 TP1
A-2 PCI Development Backplane User’s Guide Layout and Circuit Diagrams B
This appendix contains layout and circuit details of the PCI backplane.
Figure B-1. Backplane Arrangement in a PC/AT Chassis
PCI Development Backplane User’s Guide B-1 Layout and Circuit Diagrams
Figure B-2. Jumper and Connector Locations
B-2 PCI Development Backplane User’s Guide Layout and Circuit Diagrams
B.1 Movable Keys
In Figures B-3 through Figure B-7, the 3.3 V key, which is referenced as 3.3V Key, and the 5V key, referenced as 5V Key, allows the module to be configured for either 3.3V or 5V enviroments, but not both. The 3.3 V key is located between pins 106 and 107 on side 2, and pins 12 and 13 on side 1. The 5 V key is located between pins 144 and 145 on side 2, and 62 and 63 on side 1.
PCI Development Backplane User’s Guide B-3 Layout and Circuit Diagrams
Figure B-3. Circuit Diagram: System Slot System Slot: 64-Bit PCI -12V VIO 2-6,8
J4 2-6 2-6 +3.3V VDD +12V 2-6,8
BA +3.3V VDD 95 1 1
96 2 2 VIO INTD INTC INTB INTA 97 3 3 98 4 4
99 5 5 2-6 2-6 100 6 6 101 7 7 102 8 8 REQ4 103 9 47U C30 9 REQ2 104 10 10 GNT4 105 11 11 2 2 1 106 12 12 3.3V Key 107 13 13 108 14 14 GNT2 2 1 2 1 109 15 2-7 RESET 15 0.1UF C42
+3.3V PCICLK0 110 16 16 111 17 SYSCPU_GNT0 17 SYSCPU_REQ0 112 18 18 2 1 2 C25 1 113 19 REQ3 19 AD31 114 20 AD30 AD[63:0] 0.1UF 20 AD29 115 21 21 2-7 2-7 2-6 116 22 22 AD28 CBE[7:0] AD27 117 23 AD26 C18 47U 23 AD25 118 24 24 119 25 25 AD24 2 2 1 120 26 26 GNT3 AD23 121 27 27 122 28 AD22 GNT[4:2] REQ[4:2] 2-6 28 2 1 2 C63 1 AD21 123 29 29 AD20 0.1UF AD19 124 30 30 VDD 125 31 31 AD18 AD17 126 32 32 AD16 2 1 2 1 127 33 33 128 34 2-7 FRAME 0.1UF C1 34 CBE3 CBE2 IRDY 2-7 129 35 35 130 36 2-6 TRDY DEVSEL 36 2-6 131 37 C6 47U 37 132 38 38 2-6 STOP LOCK 2-6 133 39 39 2 2 1 PERR 2-6 134 40 2-6 SDONE 40 PICMG-STYLE FOR SLOT HEADERS SYSTEM USE FROM AND ARBITRATION LINKS CUT FOR CONNECTIONS DEFAULT ARBITRATION PROVIDE BACKPLANE ETCHLINKS NOTE PLEASE 135 41 2-6 SBO CBE7 CBE6 CBE5 CBE4 CBE0 CBE1 41 SERR 2-6 136 42 42 2 1 2 1 u thik n AL ik 2-3 links *ALL* and etchlinks ARBITER: Cut SLOT SYSTEM ARBITER: BACKPLANE 137 43 2-6 PAR 1-2 headers *ALL* and/or Etchlinks 43 0.1UF C11 138 44 AD15 44 VIO AD14 139 45 45 140 46 46 AD13 2 C47 1 2 1 AD12 141 47 47 AD11 AD10 142 48 0.1UF 48 143 49 49 AD9 144 50 50 5V Key 145 51 51 AD8 146 52 52 AD7 147 53 53 148 54 54 AD6
VIO AD5 149 55 55 AD4 AD3 150 56 56 12 1 12 1 1 12 1 12 151 57 57 AD2 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K R64 R70 R66 R67 R46 R49 R41 R38 AD1 152 58 58 AD0 153 59 59 2 2 2 2 ACK64 2-6 154 60 60 2-6 REQ64 155 61 61 156 62 62 Key SYSCPU_GNT0 SYSCPU_REQ0 157 63 157 63 63 158 64 INTD INTC INTB INTA SERR PERR ACK64 REQ64 64
159 65 65 VIO 160 66 66 161 67 67 2-6 PAR64 AD63 162 68 AD62 GNT1 GNT0 REQ1 REQ0 68 12
AD61 163 69 2.67K
69 R56 164 70 70 AD60 AD59 165 71 71 AD58 AD57 166 72 72
VIO 167 73 73 AD56 AD55 168 74 74 AD54 AD53 169 75 75 12 12 12 12 1 1 1 1 170 76 AD52 76 2 EL5 2 EL7 2 EL6 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K ETCHLINK2 ETCHLINK2 ETCHLINK2 R51 R55 R52 R48 R53 R50 R54 R47 AD51 171 77 77 AD50 AD49 172 78 78 1 1 1 2 2 2 2 173 79 79 AD48 AD47 174 80 80 AD46 AD45 175 81 81 176 82 82 AD44 J9 J15 AD43 177 83 83 AD42 3 2 1 3 2 1 3 2 1 AD41 178 84 84 J10 179 85 AD40 DEVSEL LOCK STOP IRDY TRDY FRAME SBO SDONE 85 AD39 180 86 AD38 86 ARB_ENABLE AD37 181 87 87 182 88 182 88 88 AD36 183 89 AD35 183 89 89 AD34 184 90 AD33 184 90 90 185 91 185 91 91 AD32 186 92 186 92 92
A6062-01 187 93 187 93 93 188 94 188 94 94
zz002
B-4 PCI Development Backplane User’s Guide Layout and Circuit Diagrams
Figure B-4. Circuit Diagram: Slot 1
-12V
VIO
+3.3V J5
+12V
VDD
BA +3.3V
VDD 95 1 1
96 2 2 VIO 97 3 3 98 4 4 99 5 5 100 6 6 101 7 7
1 2 2 1 102 8 8
C57 0.1UF 103 9 9 AD19 AD31
INTA INTD INTC INTB 104 10 10 105 11 11
1 2 2 1 106 12 12 3.3V Key
C53 0.1UF 107 13 13 108 14 14 AD[63:0] 109 15 15 RESET PCICLK1 110 16 16 111 17 17 GNT1 REQ1 112 18 18 113 19 19 AD31 114 20 AD30 20 2
ETCHLINK2 AD29 115 21 EL1 21 116 22 AD28 22
1 CBE[7:0] AD27 117 23 AD26 23 AD25 118 24 24 119 25 25 AD24 R57 120 26 26 IDSEL1 1122 47R5 AD23 121 27 27
3 2 1 122 28 28 AD22
J11 AD21 123 29 29 AD20 AD19 124 30 30 125 31 31 AD18 AD17 126 32 32 AD16 127 33 33 128 34 34 FRAME
CBE3 CBE2 IRDY 129 35 35 130 36 36 TRDY DEVSEL 131 37 37 132 38 38 STOP LOCK 133 39 39
47U C33 PERR 134 40 40 SDONE 135 41 SBO CBE7 CBE6 CBE5 CBE4 CBE0 CBE1 41 SERR 136 42 42
2 2 1 137 43 PAR 43 138 44 AD15 44 AD14 139 45
2 11 2 45 140 46 AD13 46
0.1UF C43 +3.3V AD12 141 47 AD11 47 AD10 142 48 48 143 49 49 AD9
2 11 2 144 50 50 5V Key
0.1UF C26 145 51 51 AD8 146 52 52 AD7 147 53 53
47U C19 148 54 54 AD6 AD5 149 55 55 AD4 AD3 150 56 150 56 56
2 2 1 151 57 AD2 151 57 57 AD1 152 58 AD0 152 58 58 153 59
1 2 2 1 59 154 60 154 60 60 REQ64
C64 0.1UF 155 61 VDD 61 156 62 62 64-Bit PCI IO Slot 1
ACK64 Key
2 11 2
0.1UF C2 157 63 157 63 63 158 64 158 64 64 159 65 159 65 65
C7 47U 160 66 66 161 67 PAR64 67 AD63 162 68 AD62 68
2 2 1 AD61 163 69 69 164 70 AD60 70 AD59 165 71 AD58
2 1 1 2 71 AD57 166 72 166 72 72
0.1UF C12 167 73 AD56 VIO 73 168 74 AD55 168 74 74 AD54 169 75 AD53 169 75 75
2 11 2 76 170 76 76 AD52
0.1UF C48 77 AD51 171 77 77 AD50 78 AD49 172 78 78 173 79 AD48 173 79 79 AD47 174 80 AD46 174 80 80 AD45 175 81 175 81 81 176 82 AD44 176 82 82 AD43 177 83 AD42 177 83 83 AD41 178 84 178 84 84 179 85 AD40 179 85 85 AD39 180 86 AD38 180 86 86 AD37 181 87 181 87 87 182 88 AD36 182 88 88 AD35 183 89 AD34 183 89 89 AD33 184 90 184 90 90 185 91 AD32 185 91 91 186 92 186 92 92 187 93 A6063-01 93 188 94 188 94 94
zz003
PCI Development Backplane User’s Guide B-5 Layout and Circuit Diagrams
Figure B-5. Circuit Diagram: Slot 2
VIO
-12V
+3.3V J6
+12V
VDD
BA +3.3V
VDD 95 1 1
96 2 2 VIO 97 3 3 98 4 4 99 5 5 100 6 6 101 7 7
1 2 2 1 102 8 8
C58 0.1UF 103 9 9 AD18 AD30
INTB INTA INTD INTC 104 10 10 105 11 11
1 2 2 1 106 12 12
C54 0.1UF 3.3V Key 107 13 13 108 14 14 AD[63:0] 109 109 15 15 RESET 110 PCICLK2 110 16 16 111 111 17 17 GNT2 REQ2 112 18 18 113 19 19
2
AD31 114 20 AD30 ETCHLINK2 20 EL2 115 21 AD29 21
116 22 1 22 AD28 CBE[7:0] 117 23 AD27 23 AD26 118 AD25 118 24 24 119 25 25 AD24 R58 120 26 26 IDSEL2 1122 47R5 AD23 121 27 27
3 2 1 122 28 28 AD22
J12 AD21 123 29 29 AD20 AD19 124 30 30 125 125 31 31 AD18 126 AD17 126 32 32 AD16 127 127 33 33 128 128 34 34 FRAME CBE3 CBE2 129 IRDY 129 35 35 130 130 36 36 TRDY 131 DEVSEL 131 37 37 132 132 38 38 STOP 133 LOCK 133 39 39 134 PERR 134 40 40 SDONE 135 41 SBO CBE7 CBE6 CBE5 CBE4 CBE0 CBE1 41 SERR 136 42
47U C34 42 137 43 PAR 43 138 44 AD15 44 2 2 1 AD14 139 45 45 140 46 AD13 46 AD12 141 47 AD11 47
2 1 1 2 AD10 142 48 48
0.1UF C27
+3.3V 143 49 143 49 49 AD9 144 50 50 5V Key 145 51 51
1 2 2 1 AD8 146 52 52 AD7 147 53
C44 0.1UF 53 148 54 54 AD6 AD5 149 55 55 AD4 AD3 150 56
C20 47U 56 151 57 151 57 57 AD2 152 58 AD1 152 58 58 AD0 2 2 1 153 59 153 59 59 154 60 64-Bit PCI to SLOT 2 154 60 60 REQ64 155 61 155 61 61
1 2 2 1 156 62 156 62 62
C65 0.1UF VDD ACK64 Key 157 63 157 63 63
1 2 2 1 158 64 158 64 64 159 65
C3 0.1UF 65 160 66 66 161 67 PAR64 67 AD63 162 68 AD62
C8 47U 68 AD61 163 69 69 164 70 AD60 70 2 2 1 AD59 165 71 AD58 71 166 72 AD57 166 72 72 167 73 167 73 73 AD56
1 2 2 1 168 74 AD55 168 74 74 AD54
0.1UF C49 169 75 AD53 169 75 75
VIO 170 76 170 76 76 AD52 171 77 AD51 171 77 77 AD50
1 2 2 1 172 78 AD49 172 78 78 173 79 AD48
C13 0.1UF 79 174 80 AD46 AD47 174 80 80 AD45 175 81 175 81 81 176 82 AD44 176 82 82 AD43 177 83 AD42 177 83 83 AD41 178 84 178 84 84 179 85 AD40 179 85 85 AD39 180 86 AD38 180 86 86 AD37 181 87 181 87 87 182 88 AD36 182 88 88 183 89 AD35 183 89 89 AD34 184 90 AD33 184 90 90 185 91 AD32 185 91 91 186 92 186 92 92 187 93 187 93 93 188 94 A6064-01 94
zz004
B-6 PCI Development Backplane User’s Guide Layout and Circuit Diagrams
Figure B-6. Circuit Diagram: Slot 3 -12V VIO
+3.3V J7 +12V VDD
BA +3.3V VDD 95 1 1
96 2 2 VIO 97 3 3 98 4 4 99 5 5 100 100 6 6 101 101 7 7 2 1 2 1 102 102 8 8 0.1UF C59 103 9 9 AD17 AD29 INTC INTB INTA INTD 104 10 10 105 11 11 2 1 2 1 106 12 12 3.3V Key 0.1UF C55 107 13 13 108 14 14 AD[63:0] 109 15 109 15 15 RESET 110 16 PCICLK3 110 16 16 111 17 111 17 17 GNT3 REQ3 112 18 18 113 19 19 AD31 114 20 AD30 20 2 ETCHLINK2 115 21 EL3 AD29 21 116 22 22 AD28 1 CBE[7:0] 117 23 AD27 23 AD26 118 24 AD25 118 24 24 119 25 25 AD24 R59 120 26 26 IDSEL3 1122 47R5 AD23 121 27 27 3 2 1 122 28 28 AD22 J13 AD21 123 29 29 AD20 AD19 124 30 30 125 31 125 31 31 AD18 126 32 AD17 126 32 32 AD16 127 33 127 33 33 128 34 128 34 34 FRAME CBE3 CBE2 129 35 IRDY 129 35 35 130 36 130 36 36 TRDY 131 37 DEVSEL 131 37 37 132 38 132 38 38 STOP 133 39 LOCK 133 39 39 134 40 PERR 134 40 40 SDONE 135 41 SBO CBE7 CBE6 CBE5 CBE4 CBE0 CBE1 41 136 42 SERR 136 42 42 137 43 PAR 43 138 44 138 44 44 AD15 C35 47U 139 45 AD14 139 45 45 140 46 140 46 46 AD13
2 2 1 141 47 AD12 141 47 47 AD11 AD10 142 48 48 143 49 143 49 49 AD9 2 1 2 1 144 50 50 5V Key
0.1UF C28 145 51
+3.3V 51 146 AD8 146 52 52 147 AD7 147 53 53 148 54 AD6 2 C45 1 2 1 54 149 AD5 149 55 55 AD4 0.1UF 150 56 AD3 150 56 56 151 57 151 57 57 AD2 152 58 AD1 152 58 58 AD0 47U C21 153 59 153 59 59
154 60 64-Bit PCI IO Slot 3 154 60 60 REQ64
2 2 1 155 61 155 61 61 156 62 62
ACK64 2 1C4 2 1 Key
0.1UF 157 63 157 63 63
VDD 158 64 64 159 65 65 160 66 2 1 2 1 66 161 67 PAR64 67 0.1UF C66 AD63 162 68 AD62 68 AD61 163 69 69 164 70 AD60 70 47U C9 AD59 165 71 AD58 71 AD57 166 72 166 72 72
2 2 1 167 73 167 73 73 AD56 168 74 AD55 168 74 74 AD54 169 75 AD53 169 75 75 2 1 2 1 170 76 170 76 76 AD52
0.1UF C50 171 77 AD51 171 77 77 AD50
VIO 172 78 AD49 172 78 78 173 79 AD48 173 79 79 AD47 174 80 AD46 2 C14 1 2 1 80 AD45 175 81 175 81 81 0.1UF 176 82 AD44 176 82 82 AD43 177 83 AD42 177 83 83 AD41 178 84 178 84 84 179 85 AD40 179 85 85 AD39 180 86 AD38 180 86 86 AD37 181 87 181 87 87 182 88 AD36 182 88 88 183 89 AD35 183 89 89 AD34 184 90 AD33 184 90 90 185 91 AD32 185 91 91 186 92 186 92 92 187 93 187 93 93 188 94
A6065-01 94
zz005-B
PCI Development Backplane User’s Guide B-7 Layout and Circuit Diagrams
Figure B-7. Circuit Diagram: Slot 4 64-Bit PCI IO Slot 4
-12V
VIO
+3.3V J8
+12V
VDD
BA +3.3V
VDD 95 1 1
96 2 2 VIO 97 3 3 98 4 4 99 5 5 100 6 6 101 7 7
2 1 1 2 102 8 8
0.1UF C60 103 9 9 AD16 AD28
INTD INTC INTB INTA 104 10 10 105 11 11
2 11 2 106 12 12
0.1UF C56 3.3V Key 107 13 13 108 14 14 AD[63:0] 109 15 15 RESET PCICLK4 110 16 16 111 17 17 GNT4 REQ4 112 18 18 113 19 113 19 19 AD31 114 20 AD30 20 2
ETCHLINK2 AD29 115 21 EL4 115 21 21 116 22 AD28 116 22 22
1 CBE[7:0] AD27 117 23 AD26 117 23 23 AD25 118 24 24 119 25 25 AD24 R60 120 26 26 IDSEL4 121 2 47R5 AD23 121 27 27
3 2 1 122 28 28 AD22
J14 AD21 123 29 29 AD20 AD19 124 30 30 125 31 31 AD18 AD17 126 32 32 AD16 127 33 33 128 34 34 FRAME
VIO
CBE3 CBE2 IRDY 129 35 35 130 36 36 TRDY
1 1 1 1 1 1 1 1 1 DEVSEL 131 37 37
2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K
R45 R36 R37 R39 R35 R34 R33 R32 R31 132 38 38 STOP LOCK 133 39 39
2 2 2 2 2 2 2 2 2 PERR 134 40 40 SDONE 135 41 SBO CBE7 CBE6 CBE5 CBE4 CBE0 CBE1 41 SERR 136 42 42
47U C36 137 43 PAR 137 43 43 138 44 AD15 138 44 44 AD14 139 45 2 2 1 45 140 46 AD13 46 CBE7 AD63 AD62 AD61 AD60 AD59 AD58 AD57 AD56 AD12 141 47 AD11 141 47 47
2 1 1 2 AD10 142 48 142 48 48 143 49 AD9
0.1UF C46 49
+3.3V 144 50 50 5V Key
145 51 51 VIO AD8 146 52 52
1 2 2 1 AD7 147 53 53 1 1 1 1 1 1 1 1 1
C29 0.1UF
148 54 AD6 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K
54 R44 R30 R28 R27 R25 R24 R22 R21 R19 AD5 149 55 55 AD4 AD3 150 56 56 2 2 2 2 2 2 2 2 2
C22 47U 151 57 57 AD2 AD1 152 58 58 AD0 153 59 2 2 1 59 154 60 60 REQ64 155 61 61
2 11 2 156 62 62
CBE6 AD55 AD54 AD53 AD52 AD51 AD50 AD49 AD48
0.1UF C67 ACK64
VDD
157 63 63 158 64 64
2 11 2 Key 159 65 65
0.1UF C5 160 66 66
161 67 67 PAR64 VIO AD63 162 68 68 AD62
C10 47U AD61 163 69 69
1 1 1 1 1 1 1 1 1 164 70 70 AD60
2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K
AD59 165 71 AD58 R43 R18 R16 R15 R13 R12 R11 R10
2 2 1
71 R9 AD57 166 72 72
2 2 2 2 2 2 2 2 2 167 73 73 AD56
2 11 2 AD55 168 74 74 AD54 AD53 169 75
0.1UF C51 75
VIO 170 76 76 AD52 AD51 171 77 77 AD50 AD49 172 78 78
1 2 2 1 173 79 AD48 79 CBE5 AD47 AD46 AD45 AD44 AD43 AD42 AD41 AD40
C15 0.1UF AD47 174 80 80 AD46 AD45 175 81 81 176 82 82 AD44
AD43 177 83 83 AD42 VIO AD41 178 84 84 179 85 85 AD40
1 1 1 1 1 1 1 1 1 1 AD39 180 86 86 AD38
2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K 2.67K
AD37 181 87 R40 R42
87 R8 R7 R6 R5 R4 R3 R2 R1 182 88 88 AD36 183 89 2 2 2 2 2 2 2 2 2 2 AD35 183 89 89 AD34 184 90 AD33 184 90 90 185 91 185 91 91 AD32 186 92 186 92 92 187 93 187 93 93 A6066-01 188 94 188 94 94
PAR64 CBE4 AD39 AD38 AD37 AD36 AD35 AD34 AD33 AD32
zz006
B-8 PCI Development Backplane User’s Guide Layout and Circuit Diagrams
Figure B-8. Circuit Details: Arbitration and System Clock Logic VIO VIO 1 2 1 2 1 2.67K lc rc decoupling trace Clock R68 0.1UF C82 HEAD8X2 15 13 11 9 7 5 3 1 J1 15 13 11 9 7 5 3 1 2 CLKSEL0 CLKSEL1
XTAL_IN zz007 2 1 2 C83 1 CLK_ENABLE XTAL_IN 0.1UF 16 14 12 10 16 14 12 10 8 8 6 6 4 4 2 2 1 2 C85 1 0.1UF 2 CLKSEL1 CLKSEL0 LOCK_ENABLE CNTRL4 CNTRL3 CNTRL2 CNTRL1 CNTRL0 ETCHLINK2 EL8 2 1 2 1 1 DEVICE=CY2260SC-3 13 GND;4,11,17,23 VIO;1,8,14,20,26 12 U2 13 12 14.31818MHZ 2 5 2 XTAL_SM 1 X1 0.1UF C84 5 OE S0 XTALIN P S1 NC1 2 3 CY2260 NC2 2 1 2 C80 1 N 4 0.1UF PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 CPUCLK2 CPUCLK1 CPUCLK0 XTALOUT PCICLK5 CPUCLK3 10 9 8 7 6 5 4 3 2 1 CLKB CLKA REF1 REF0 RPK20A 2 1 2 1 2 1 2 1 RNET 4.7K 22 21 19 18 16 15 10 9 7 6 27 28 25 25 24 3 21 19 18 16 15 9 7 6 27 28 3 22 10 10PF C69 E1 0.1UF C79 20 LA A O EFITTED BE NOT MAY - CLOAD 11 12 13 14 15 16 17 18 19 20 XTAL_OUT VIO XTAL_OUT REQ4 REQ3 REQ2 REQ1 REQ0 1 1 1 1 1 1 1 12 12 12 12 12 R71 R69 R65 R63 R62 R61 47R5 47R5 47R5 47R5 47R5 47R5 2 2 2 2 2 2 2 ARBCLK PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 LOCK_ENABLE ARB_ENABLE ARBCLK CNTRL4 CNTRL3 CNTRL2 CNTRL1 CNTRL0 RESET FRAME IRDY LOCK REQ4 REQ3 REQ2 REQ1 REQ0 VIO VIO 2 C78 1 1 2 1 1 Y20decoupling CY2260 10UF C40 10UF N;6,16,26,34,38,48,58,66 GND; 11,21,31,43,53,63 3,35 VIO; VDD; SOCKETTED 10 20 40 39 28 67 68 15 14 17 18 13 12 22 25 37 30 29 24 23 BPARB U1 1 8 9 7 2 5 4 REQ0 CTRL3 RSVD8 RSVD7 RSVD3 PCICLK RESET ARB_ENABLE LOCK_ENABLE FRAME IRDY LOCK REQ4 REQ3 REQ2 REQ1 CTRL4 CTRL2 CTRL0 OE2 RSVD0 RSVD6 RSVD5 RSVD4 RSVD2 RSVD1 CTRL1 2 1 2 C31 1 2 1 2 1 leaMXk(PR)decoupling (BPARB) MAX7k Altera 0.1UF C61 0.1UF BPARB 2 1 2 1 2 1 2 C16 1 0.1UF C77 0.1UF PCIARB0 PCIARB1 PCIARB2 RSVD24 RSVD22 RSVD20 RSVD18 RSVD16 RSVD14 RSVD12 RSVD10 RSVD23 RSVD21 RSVD19 RSVD17 RSVD15 RSVD13 RSVD11 RSVD9 TEST GNT4 GNT2 GNT1 GNT0 GNT3 2 1 2 1 2 C72 1 2 1 27 32 33 19 46 51 54 60 41 0.1UF 0.1UF C37 36 65 62 59 56 52 49 45 42 64 61 57 55 50 47 44 2 1 2 1 2 1 2 C17 1 0.1UF C62 0.1UF 2 C52 1 2 1 2 1 2 1 0.1UF 0.1UF C24 GNT4 GNT3 GNT2 GNT1 GNT0 2 1 2 1 0.1UF C38 ARB_SM0 ARB_SM1 ARB_SM2 3 2 1 J2 2 C23 1 2 1 0.1UF 2 1 2 1 0.1UF C32
PCI Development Backplane User’s Guide B-9 Layout and Circuit Diagrams
Figure B-9. Circuit Details: Power Connectors VIO
zz008 +12V +3.3V VDD 2 2 2 2 2 2 W4 W3 W2 W1 2.67K R20 1 1 1 1 12 1 12 1 WIRELINK WIRELINK WIRELINK WIRELINK 12 2 R14 100 2.67K R23 12 1 ***WARNING*** VIO = 5V WHENFIT FITTED 5V *OR* 3V3 LINKS VIO = 3V3 WHEN FITTED VIO voltage selection NC_PWRGD VID3 VID1 OUTEN NC_PRORES1 VDD +3.3V B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 J3 A1 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 UP VID2 VID0 2 +12V J17 100 R26 1 6 5 4 3 2 1 9 8 7 12 11 10 NC_PRORES2 2 Voltage Reference Module for 3.3V 2.67K 100 R29 R17 12 1 2 2 1 VDD +3.3V 2 2 1 47U C39 47U C41 3.3V Power Connector P9 P8 J16 6 5 4 3 2 1 9 8 7 12 11 10 C C C 2 D1 A A A A 21 21 21 C D2 D3 D4 1 0.1UF C81 WARNING - NC PIN HAS -5V FROM PSU 0.1UF 2 1 2 1 2 2 2 2 1 2 1 C73 WARNING - NC PIN HAS DC_OK FROM PSU R72 R73 2.67K 2.67K 1K 620 R74 R75 C76 12 1 1 1 22U 2 2 1 1 2 2 22U C75 VDD 0.1UF C71 Standard Power Connector 2 1 2 1 VDD +3.3V 2 2 1 0.1UF C70 Backplane voltage LED's 2 1 2 1 22U C68 -12V +12V C74 22U 1 2 2 -12V +12V
B-10 PCI Development Backplane User’s Guide Bill of Materials C
A combined bill of materials (Figure C-1) for the EBSA–BPL–5V and EBSA–BPL–3V3 Development Backplanes is given on the next page.
PCI Development Backplane User’s Guide C-1 Bill of Materials
Figure C-1. Bill of Materials A6061-01
C-2 PCI Development Backplane User’s Guide
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