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The Benefits of Compactpci Backplane

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The Benefits of Compactpci Backplane CompactPCI Specifications Corner By Wayne Fischer The benefits of CompactPCI What is user defined? What about backplane backplane I/O The definition of the I/O through the I/O sub-buses? CompactPCI opens the door to a much connectors is generally considered user Besides routing I/O through the back- broader range of I/O when compared to defined. The user can be any one com- plane, I/O can also be a sub-bus. In this earlier industrial computer platforms such pany that supplies boards to the open case, the backplane routes a set of signals as VMEbus or Multibus I and II. In fact, market, but it can also refer to any com- between other backplane I/O connectors, CompactPCI technology accommodates pany who designs and builds boards for which enables the boards to communicate the greatest I/O flexibility and the most its own internal use. These companies are among themselves using a particular pro- I/O options ever available through a the users of the I/O pins. As such, they tocol and data content. This situation dif- backplane. have the liberty to define these I/O pins fers from the main PCI bus on J1/P1 and any way they desire; or more specifically, J2/P2 (if 64-bit PCI extension is used). The front panel of CompactPCI, VMEbus, any way that best fits their individual and Multibus II are somewhat equivalent application needs. The sub-bus (also called a secondary bus) in the accommodations for I/O. They can is generally defined by a group of com- use any combination of connectors fitting What about PICMG I/O pin panies for a specific application type. a 15 mm wide by 225 mm area. The assignments? This protocol allows a variety of boards shrinking of connector size and increas- In some applications, the definition of to communicate with each other much ing of connector pin density allows more backplane I/O can be common to several more quickly and efficiently than would I/O to be routed through the front panel. companies. This commonality makes be possible over the main PCI bus. However, it is within the back-panel I/O sense in cases where a specific applica- options that CompactPCI outshines its tion definition requires a broad number of What is commonly predecessors. boards to be supplied to the market. The defined at this point? user base likes the idea of being able to The best way to answer this question is to VMEbus and VME64 have 64 user-defin- purchase boards from many different sup- list the different PICMG specifications able I/O lines through the backplane. pliers, without having to redesign the that are either fully approved or in the Multibus II has 96 pins on the P2/J2 backplane or rework the I/O interconnect subcommittee development stage. The connector. The VME64x specification scheme. chart in Figure 2 offers this information expanded the rear I/O to 205 pins. at a glance. Multibus I only offers the edge of a PCB for mounting of connectors, which limits VME64x on CompactPCI J5 the flexibility for I/O. 110 pins Both CompactPCI and VME64x mechan- ics are the same, which makes it easy to CompactPCI backplane I/O place both a CompactPCI and a VME64x The core CompactPCI Specification PICMG Defined I/O backplane in the same subrack. The board or User Defined I/O (PICMG 2.0) defines five backplane con- size, card guide rails, front panels, and so J4 nectors: Key Area forth are exactly the same. In some appli- 110 pins cations, a monolithic CompactPCI and ■ J1/P1 VME64x backplane have been built, ■ J2/P2 where VME64x’s Slot 1 originates on the ■ J3/P3 J3 2 mm connectors. Slot 2 through N are 95 pins ■ J4/P4 PICMG Defined I/O normal VME64x slots. ■ J5/P5 or User Defined I/O PICMG 2.2 defines a single-slot bridge Figure 1 offers an illustration of these five J2 between CompactPCI and VME64x. The connectors. J1/P1 is always defined as the 110 pins 64-bit PCI Local Bus VME64x signals are placed on the J5 32-bit PCI bus interface. All 3U and 6U and System Slot Cntr. connector and the upper half of the J4 or PICMG Defined I/O boards use this connector and functional- connector, while normal CompactPCI re- or User Defined I/O ity. For both 3U and 6U boards, the J2/P2 sides on the J1 and J2 connectors. J1 connector can be used for 64-bit PCI 110 pins expansion or for I/O. Key Area PMC on CompactPCI 32-bit PMC (PCI Mezzanine Cards, IEEE Connectors J3/P3 through J5/P5 are PCI Local Bus P1386.1) can have up to 64 I/O signals defined for I/O. Connectors J3/P3 through routed from its J4 connector. These I/O J5/P5 provide 315 user-defined I/O pins. signals, in turn, can be routed through a When the J2/P2 connector is included, the CompactPCI’s backplane. The PICMG total is 425 I/O signal pins. Figure 1 2.3 draft specification defines several Reprinted from CompactPCI Systems / Fall 1998 / 1 Copyright 1998 ~ All rights reserved Figure 2 Presently Defined CompactPCI Backplane I/O and Sub-Buses PICMG No. Title Status Description 2.2 VME64x on CompactPCI In Ballot A single slot CompactPCI to VME64x Bridge 2.3 PMC on CompactPCI In Ballot PMC I/O pin assignment to rear I/O connectors 2.4 IP on CompactPCI In Ballot Industrial Pack I/O pin assignment to rear I/O connectors 2.5 Computer Telephony Fully Approved TDM sub-bus & special telecom power on J4, plus telecom I/O on J5 2.6 PCI to PCI Bridge In Sub-committee Single slot PCI to PCI bridge, with J4 & J5 as slot 1 of the next CompactPCI bus segment 2.7 Dual CompactPCI In Sub-committee Will define a dual CompactPCI bus architecture Backplanes 2.8 PCI Extension for In Sub-committee Defines the power, clocks and other special Instrumentation signals for instrumentation based boards 2.9 System Management Bus In Sub-committee A two wire serial bus for management of external peripherals ways to route PMC I/O through connec- the J4 and J5 connectors are used as Slot placing instrumentation boards in a tors J2, J3, J4 and J5. For telecom appli- 1 of the next CompactPCI bus segment. CompactPCI-based system. The core cations, PMC’s I/O is routed through the If only a 32-bit PCI bridge is needed, then definition of this PXI specification (PCI J5 connector. the J2 connector can be used as Slot 1 for eXtensions for Instrumentation) is being the next CompactPCI bus segment. In handled by the newly formed PXI Con- IP on CompactPCI either case, note that slots 2 through N sortium. Once the consortium is fully IP or IndustryPack boards (VITA 4-1996) of the next CompactPCI bus segment operational, PICMG 2.8 will be moved can have up to 50 I/O signals coming are normal CompactPCI slots. Special forward into the PICMG executive ballot- from the mezzanine card. PICMG 2.4 CompactPCI backplanes are needed to ing phase. defines a common way of routing IP I/O accommodate this feature. through J2 for 3U boards, and through J4 System Management Bus and J5 connectors for 6U boards. Dual CompactPCI bus segments This activity is just getting started. The Activity is underway to define a Compact- intent is to use the Smbus (which is Computer Telephony PCI architecture that will allow a single- being defined by Intel for the Pentium- A great deal has been written in this slot width CompactPCI systems’ board to based computers) to manage the I/O magazine about the Computer Telephony drive two CompactPCI bus segments. peripherals for power control, fault and Specification (PICMG 2.5), along with One bus segment is defined on the normal diagnostics control, and other functions detailed descriptions of the TDM sub-bus, J1 and J2 connectors, and the second through a simple two-wire interface. This the CT backplane power rails, and so CompactPCI bus segment is defined on function will require the allocation of two forth, that are bused on the J4 connector. the upper two connectors, J4 and J5. signal pins, and full definition is still Also defined are several ways of routing slated for the future. analog and digital telephony signals One CompactPCI bus segment is routed through the J5 connector. PICMG 2.5 was to the right, and one to the left. It doesn’t I/O pin registration recently approved and released by the matter which of the bottom two connec- On several occasions within the PICMG PICMG Executive Committee, and is tors drives left or right. The same is true Executive and Technical committees, a now in print. (Refer to accompanying for the top two connectors. In fact, this type of pin registration has been dis- sidebar entitled New Computer Telephony approach only has one limitation: the bus cussed. This registration would provide Specification.) segment being driven from the J4 and J5 the basis for any one company to register connectors will be limited to six expan- its specific I/O with a registry. No due PCI-to-PCI Bridge sions slots. This occurs because of the diligence would be given to the pin I/O This draft specification is still under de- additional bus length required when the assignments, except for the company that velopment. The general intent of PICMG signals are routed from the upper two registered the pins.
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