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Emulating a Honeywell 6180 Computer System

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Emulating a Honeywell 6180 Computer System AU-787 218 EMULATING A HONEYWELL 6180 COMPUTER SYSTEM Edmund L. Burke, et al Mitre Corporation Prepared f or: Rome Air Development Center June 1974 DISTRIBUTED BY: National Technical Information Service U. S. DEPARTMENT OF COMMERCE EMULATING A HONEYWELL 6180 COMPUTER SYSTEM Edmund L. Burke Morrie Gasser W. Lee Schiller MITRE Corporation Approved for public release. Distribution unlimited. II- FOREWORD This intcT-lm technical report describes research accomplished hetween 30 September ^.id 31 December 1973, by MITRE Corporation, Bedford, Massachusetts, under Contract F1962P-73-C-0001, Job Order 55500802. Rome Air Development Center, Grlfflss Air Force Base, New York, was the con- trollliiB povernment apencv; Malor William W. Patterson (ISCA) the RADC Proiect Engineer. This reoort has been reviewed by the RADC Information Office (01) and Is releasable to the National Technical Information Service (NTIS). This technical report has been reviewed and Is anproved. APPROVED . Vv^-r VjQ^Ö^j^ WILLIAM W. PATTERSON, Mai, "SAP Proiect Engineer APPROVED: £/(. ( OA^ $ 'V 5 O^vu-^t *-,^ v_ ALAN R. BARNUM Asst Ch, Information Sciences Division FOR THE COMMANDER CARLO P. CROCETTI Chief, Plans Office 11 UNCLASSIFIED SECURITY CLASSIFICATION OF THIS PAGE c»7i»n D«I» Emermd) READ INSTRUCTIONS REPORT DOCUMENTATION PAGE BEFORE COMPLETING FORM I REPORT NUMBER U GOVT ACCESSION NO. 3 RECIPIENT'S CATALOG NUMBER RADC-TR-74-137 ZiA V TlTLF (mnd Subtitle) 5, TYPE OF REPORT & PERIOD COVERED Technical Report EMl'LATTNG A HONEYWELI, 6180 COMPl'TRR SYSTEM Interim 30 Sep - 31 Dec 73 S PERFORMING ORG. REPORT NUMBER MTR-2742 7 AUTHOR'S) 8 CONTRACT OR GRANT NUMBERS» Edmund L. Burke F19628-73-C-0001 Morrle Casser W. Lee Schiller 9 PERFORMING ORGANIZATION NAME AND ADDRESS 10 PROGRAM ELEMENT PROJECT, TASK MITRE Corporation AREA a WORK UNIT NUMBERS Dent D72 jn 55500R02 Bedford, MA 01730 II, CONTROLLING OFFICE NAME AND ADDRESS 12 REPORT DATE Rome Air Development Center (TPCA) June 197A Orlfflss Air Force Base, New York 134A1 '3 NUMBER OF PAGES U MONITORING AGENCY NAME » ADDRESS'!» ililltrtnl Irotr Controlling Ollice) 15 SECURITY CLASS,A«, r'of thti reporll Unclassified Sane '5» DECLASSlFlCATION DO*NGRADING v / k SCHEDULE 16 DISTRIBUTION STATEMENT tol tht» Report, Approved for nubile release. Distribution unlimited. 17 DISTRIBUTION STATEMENT 'ol tht mhstract entered in Block JO, 11 dilterent Irom Report) Same 18 SuPPLcM >|T*RY NOTES None 19 KEY *0RDS 'Confinu« on revene aide it necea**ry mnd Identlly bv block nutnberj MlcroprofratmrlnE Nanodata OM-1 Emulation BurrouRhs B1700 Honeywell 6180 Computers Burroughs D-Machlne 20 ABSTRACT ^Continue on reveree tide It neceeemry mnd Identity by block number) The Honeywell 6180 Is a new, larpe-scale computer for the Multlc8 tlne- sharlne svstem. This report describes the 6180, and examines the feasibility of emulatlnc It with each of three mlcroprocrammable processors: the Burroughs D-Machlne, the Nanodata OM-1, and the Burroughs B170n. Benchmark emulations are presented for each of these machines. M DD I J»N 73 1473 EDITION OF 1 NOV »5 IS OBSOLETE UNCLASSIFIED SECURITY CLASSIFICATION OF THIS PAGE (When Dmlm Entered) I ABSTRACT The Honeywell 6180 is a new lar^e-scale computer for the Multlcs timesharing system. This report describes the 6180, and examines the feasibility of emulating it with each of three microprogrammable pro- cessors: the Burroughs D-Machine, the Nanodata QM-1, and the Burroughs B1700. Benchmark emulations are presented for each of these machines. iii TABLE OF CONTENTS Page LIST OF ILLUSTRATIONS vi LIST OF TABLES vil SECTION I INTRODUCTION 1 SECTION II THE ARCHITECTURE OF THE HONEYWELL 6180 SYSTEM 2 INTRODUCTION 2 SYSTEM DESCRIPTION 3 SYSTEM PERFORMANCE 4 PROCESSOR CONFIGURATION 5 Controls Unit Registers 7 Operations Unit Registers 9 Appending Unit Registers 10 PROCESSOR OPERATION U Address Preparation — General 12 Instruction Cycle and Interrupts — General 14 Address Preparation — Detail 16 Address Modification 19 DAT Details 2A Address Preparation Flowchart 31 Instruction Cycle and Interrupts — Detail 36 Instruction Cycle 36 Interrupts and Faults 39 SECTION III EMULATION METHODOLOGY 40 INTRODUCTION 40 GENERAL CONFIGURATION 40 MICROPROGRAM ORGANIZATION 43 SECTION IV BENCHMARK EMULATIONS 46 INTRODUCTION 46 THE BURROUGHS D-MACHINE 49 Description of the D-Machine 49 Honeywell 6180 Emulation 49 THE NANODATA QM-1 55 Description of the QM-1 55 Honeywell 6180 Emulation 57 THE BURROUGHS B1700 65 Description of the B1700 65 Honeywell 6180 Emulation 66 TABLE OF CONTENTS (Concluded) Pap.e SECTION V SUMMARY 70 REFERENCES 72 DISTRIBUTION LIST 75 vl LIST OF ILLUSTRATIONS Figure Number Page 1 A Typical Configuration of the Multics System 3 2 Block Diagram of the Processor Module 5 3 Controls Unit Registers 7 4 Operations Unit Registers 9 5 Appending Unit Registers 10 6 Typical Machine Cycle 14 7 6180 Instruction Cycle 15 8 General Instruction Format 17 9 Tag Field 18 10 Indirect Word 18 11 Indirect Vord: ID, DI 20 12 Indirect Tally Word: IDC, DIC 21 13 Indirect Tally Word: AD, SD 21 14 Indirect Tallv Word: SC, SCR, CI 22 15 ITS Word Pair 23 16 ITP Vord Pair 23 17 PR Modification (bit 29=1) 24 18 DAT Algorithm 26 19 DAT Flowchart 29-30 20 Address Preparation 33-34 21 Instruction Cycle 37 22 Emulator Configuration 42 23 Typical Machine Cycle 44 24 Instruction Fetch and Execute Example (Store A) 47 25 D-Machine Block Diagram 50 26 Function Elements Added to D-Machine 51 27 D-Machine Emulation Flowchart 53-54 28 Register Layout for OM-1 Emulator 58 29 QM-1 Emulation Flowchart 63-64 30 B1700 Emulation 67-68 vli LIST OF TABLES Table Number Page I Instruction Execution Times 4 II Data Bases for Instruction Fetch and Execute 48 vili SECTION I INTRODUCTION This report presents results of a study of the feasibility of emulating a very sophisticated large scale computer system, the Honeywell 6180, on three mlcroprogrammable processors: the Burroughs D-machine, the Burroughs 1700 and the Nanodata OM-1. The 6180 is a third generation computer that supports the current ver- sion of the Multics system. Multics is a large timesharing system that embodies such state-of-the-art concepts as virtual memory, dynamic (execution time) linking, and advanced access controls and presents one of the most challenging architectures to an emulator of any existing system. The mlcroprogrammable machines picked for the study were chosen after a cursory evaluation of available hard- ware indicated that these were the only machines with the potential for the emulation. As new mlcroprogrammable processors become available, the emulation methodology developed in this report should make the evaluation of these new processors straightforward. This report assumes the reader is familiar with some of the basic features of Multics. Chapter I of The Multics System by Organick [14] should be considered a prerequisite for readers of this report. In addition, "The Multics Virtual Memory" by Bensoussan et al [lO] will be very helpful. Although both these publications discuss the implementation of Multics on the GE645 (a precursor of the 6180), most of the details have not been changed. Four sections follow this introduction. Section II presents the 6180 architecture in some detail. Owing to the paucity of documentation for the 6180 at the time of this writing, this infor- mation was gleaned from a wide variety of sourfes. Section III develops a methodology for the emulation of the 6180. The signif- icantly greater complexity of the Multics hardware as compared to other third generation machines requires that new ideas be de- veloped for implementing the 6180 operations in microprograms. Section IV then takes a typical 6180 operation and examines the emulation of that operation on the three microprogrammed processors. This examination is in sufficient detail to allow a benchmark to be established for each emulation. Finally, Section V suiranarlzes the major findings and conclusions of the report. SECTION II THR ARCHITECTURE OF THE HONEWELL 6180 SYSTEM INTRODUCTION This section describes the architecture of the 6180 or Multics computer system. The descriptive material is directed toward the intricacies of the instruction execution cvcle and dynamic address translation (DAT) algorithm and is complete enough to allow the development of an emulation raethodolop,' .md benchmark. The Honeywell 6180 computer svstem supports the current ver- sion of the Mjltics operating system and is synonymous with Multics. The 6180 has evolved from the current generation of Honeywell hardware, the 6000 series. The 6180 is essentially the Honeywell 6080 modified with DAT hardware for the Multics virtual memory. In fact, a switch on the 6180 allows it to run as a 6080. The 6080 is, in turn, the largest and most sophisticated processor in the 6000 series, embodying an extended instruction set, EIS, (for character string and decimal arithmetic processing) and the fastest circuitry and memory of the series. The 6180 Multics system was first offered as a product in second quarter 1973 and only one 6180 Multics is presently (September 1973) available to the general user. This available Multics is at MIT. Because the system is so recent, standard documentation does not exist. Thus the following description comes from a wide variety of sources that commonly provide preliminary documentation for evolutionary systems. These sources include Honeywell 645 processor (the original Multics machine), 6000 series and EIS manuals, MIT Informations Processing Center Memos, and articles in the Communications of the ACM. Because of the diverse origin of the descriptive materials the presentation of the 6180 architecture should not be construed as final. SYSTEM DESCRIPTION The Multics system is composed of processor» memory and input/ output modules as well as a front-end processor as shown in Figure 1. While the 6180 processor is the active element in the system, and as such deserves pre-tminent treatment in a discussion of the Multics architecture, it is necessary to have sufficient under- standing of all system modules, their interconnections and their functional characteristics to appreciate processor operations.
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