A Hybrid Vlsi Architecture of Manchester Encoder for Rfid Applications

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A Hybrid Vlsi Architecture of Manchester Encoder for Rfid Applications International Journal of Mechanical Engineering and Technology (IJMET) Volume 9, Issue 10, October 2018, pp. 1208–1213, Article ID: IJMET_09_10_123 Available online at http://iaeme.com/Home/issue/IJMET?Volume=9&Issue=10 ISSN Print: 0976-6340 and ISSN Online: 0976-6359 © IAEME Publication Scopus Indexed A HYBRID VLSI ARCHITECTURE OF MANCHESTER ENCODER FOR RFID APPLICATIONS M.Janaki Dept. of ECE(VLSI&ESD),GMR Institute of technology, Rajam,India Dr.M.V.Nageswara Rao Dept. of ECE, Head, GMR Institute of technology, Rajam,India ABSTRACT Radio Frequency identification is an emerging technique for the short range communication. RFID technology make a heed way from obscurity into modern applications like libraries, security, medical care, vehicular communication, many more consumer applications, object recognition food and medicine monitoring. To reduce the error data rate due to environmental noise and electromagnetic interference, before modulation and transmission the data must be encoded. This paper addresses the implementation of different Manchester encoding circuits, the power consumption, time delay and the number of transistors used are compared. This architecture is implemented using 90nm CMOS technology. Keywords: RFID, Manchester circuit, Non-Return-to-Zero. Cite this Article M.Janaki and Dr.M.V.Nageswara Rao,A Hybrid Vlsi Architecture Of Manchester Encoder for Rfid Applications, International Journal of Mechanical Engineering and Technology, 9(10), 2018, pp. (1208)-(1213). http://www.iaeme.com/IJMET/issues.asp?JTypeIJMETT&VType=9&IType=10 1. INTRODUCTION The radio frequency identification (RFID) have many uses in now-a-days. Depends on the present technology radio frequency identification has been utilized in number of applications like electronic toll collection (ETC), libraries transportation & logistics and object recognition etc.. Wireless data capture and transaction process proximity and vicinity are two main applications of RFID technique. The range of radio frequency is up to 3 KHz-300GHz. RFID hardware have two important parts ‘reader’ and ‘tag’. In sometimes, the reader is also termed as interceptor. The interceptor is utilizing to read the information gathered from the tag and to write the information into the tag. The tag’s special identification code is passed through multiplexer block initially merged with clock redundancy checker code to explain mistakes about the CRC function. This procedure information is modulated by Manchester encoder. The Manchester encoder is to perform the operations of Manchester code. The outcome of cyclic redundancy checker is modulated by amplitude or frequency modulation. The remaining blocks http://www.iaeme.com/IJMETT/index.asp 1208 [email protected] M.Janaki and Dr.M.V.Nageswara Rao are necessary to fulfill the performance of that system. Various Manchester coding techniques [1-8] reported in the literature are studied and few techniques are implemented in this work. Figure 1 shows a NRZ code against a Manchester code. The advantages this code are: • The DC mean value of the signal is constant and equal • No DC component has to be transmitted • The signal power is independent from the data pattern • Signal absence can he easily detected as a ‘0’ followed • Signal conflicts can easily be detected as a ‘1’ followed to 0.5 by a ‘0’ by a ‘1’ Figure 1 Code data of Manchester 2. CODING TECHNIQUES The logical values ‘1’ and ‘0’ in a binary system can be coded in various forms. The RFID system generally used the given encoding methods: Non-Return to-Zero code (NRZ), Manchester code. The two encoding techniques are illustrated in Figure 2 [1] and Table 1. 2.1. Non-Return-to Zero (NRZ) Code In non-return-to-zero code the signal have high voltage it is denoted by’1’ and the remaining is low voltage is represents with’0’. The binary values are frequently used in digital circuits. This coding methods are referred in information gathering and it has no-timing statistics. This signal represents low value with negative voltage, high value with positive voltage. Figure 2 Manchester coding sample waveform [1] Table 1 Coding relation http://iaeme.com/Home/journal/IJMET 1209 [email protected] A Hybrid Vlsi Architecture Of Manchester Encoder for Rfid Applications DATA 1 0 1 1 0 0 1 0 Non–return-to-zero 1 0 1 1 0 0 1 0 Manchester code 01 10 01 01 10 10 01 10 2.2. Manchester Code The Manchester coding technique is also called as phase encoding. This code is most preferred in high speed frequency ranges. The operation of Manchester code is depends on exclusive or gate (XOR) with related to the clock signal and data are the basic inputs have to be considered. The Manchester code is obtained from X ⊕ CLK. If two inputs are same the relevant outcome is low. If the inputs are not same it is high. In some different circuit designs we have to use three input XOR gate operations. If all inputs are low then it is low same as all three are high then high. In anyone of input is high then it represents high or vice versa. Figure 3 Prototype Manchester encoder circuit [1]. 3. RELATED WORK The prototype of the Manchester encoder circuit shown in Figure 3 can be adopted in IC design and implementation. The Figure 3 is comprises of two logic gates i.e., XOR and inverter and one D flip flop. The XOR gate have two inputs for example data and clock the corresponding output is given to input of DFF. In parallel to exclusive or the inverter is placed that outcome is act as clock signal of flip flop. The output value of DFF is our Manchester value. Here, clock2 represents doubles the frequency. To enhance the performance of the encoder, the circuit is constructed with demultiplexer and multiplexer in parallel to Manchester code. Data is the input of demultiplexer and it divides into two outputs those are given to Manchester encoder that is passes through multiplexer. The arranging of parallel encoder increases throughput and reduces the area and power consumption. http://iaeme.com/Home/journal/IJMET 1210 [email protected] M.Janaki and Dr.M.V.Nageswara Rao 3.1. Multimode encoder architecture Manchester M1=1 M2=1 Differential Manchester M1=1 M2=0 Figure 4 Multimode encoder architecture [2]. The Multimode encoder [2] architecture is shown in Figure 4. This encoder has two modes: M1 and M2. Different types of encoders are known as multimode. This circuit consists of two D flip flops. Based on mode signals its behavior changed. If both M1 and M2 are high it is Manchester circuit. If mode1 is high and mode2 is low the operation is differential Manchester. The mode signals are opposite to above case it act as FM0 encoder. D flip flop A reserves the value of A and DFF B also. Multiplexer1 may be feed the outcome of DFF A Figure 5 High speed Manchester circuit [1] High speed Manchester circuit [1] is shown in Figure 5. This is an existing technique for the design of high speed Manchester they are used both D flip flop and T flip flop. http://iaeme.com/Home/journal/IJMET 1211 [email protected] A Hybrid Vlsi Architecture Of Manchester Encoder for Rfid Applications Demultiplexer outcomes are kept in series arrangement of D flip flops respectively. The relevant output is passed through the flip flops. These values are given to up and down paths as shown in the circuit. In certain individual cases inverter out is a clock signal of DFF. 4. PROPOSED CIRCUIT Figure 6 Proposed Manchester circuit. The Proposed Manchester circuit is shown in Figure 6. Here, A and X are taken as the inputs of the xor gate. Then the output is given to inverter both the outcomes of xor and inverter feed through 2x1 multiplexer and other input is the clock signal. the resultant output is given to D flip-flop. The flip-flop requires two inputs one is the outcome of the multiplexer another one is clock2 signal. Clock2 indicates double the clock. Frequency. The outcome of D flip-flop is feedback to input of A. The proposed circuit requires less number of transistors compared to existing circuits. As well as power consumption and delay is low. Simulation results of the proposed Manchester circuit is shown in Figure 7. Figure 7 Simulation results of the proposed Manchester circuit. http://iaeme.com/Home/journal/IJMET 1212 [email protected] M.Janaki and Dr.M.V.Nageswara Rao 5. RESULT ANALYSIS Implemented Manchester circuit, Manchester/differential Manchester circuit, Multimode encoder architecture, High speed Manchester circuit and proposed Manchester circuit and the results are compared considering Power consumption, time delay and the number of transistors used. The results are depicted in the Table.2 Table 2 Comparison of various Manchester circuits Architecture Power Delay No. of S.No (µw) (ns) transistors 1 Manchester circuit 77.4 30.2 20 2 Manchester/differential Manchester circuit 89.6 40.3 42 3 Multimode encoder architecture 131.9 39.6 64 4 High speed Manchester circuit 189.4 97.1 94 5 Proposed Manchester circuit 73.8 19.9 28 6. CONCLUSION Successfully implemented Manchester circuit, Manchester/differential Manchester circuit, Multimode encoder architecture and High speed Manchester circuit and the Proposed Manchester circuit and the results are compared considering Power consumption, time delay and the number of transistors used. It is observed that, out of all the techniques, Proposed Manchester circuit consumes less power with high speed. REFRENCES [1] Yu-Cherng Hung, “Time-interleaved CMOS chip design of Manchester and Miller encoder for RFID application”, Analog Integrated Circuits and Signal Processing, vol. 71, pp. 549- 560, 2012. [2] P. Ishwerya, V. N. Kumar and G. Lakshminarayanan, "An efficient digital baseband encoder for short range wireless communication applications," 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, 2016, pp.
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