Conference of Microelectronic Research 1989 Louis Anastos Rochester Institute of Technology

Rochester Institute of Technology RIT Scholar Works Annual Microelectronic Engineering Conference Conferences (AMEC) Archive

5-1989 Conference of Microelectronic Research 1989 Louis Anastos Rochester Institute of Technology

John Bettencourt Rochester Institute of Technology

Ed Black Rochester Institute of Technology

Maia Bodnarczuk Rochester Institute of Technology

Scott rB uck Rochester Institute of Technology

See next page for additional authors

Follow this and additional works at: http://scholarworks.rit.edu/meec_archive

Recommended Citation Anastos, Louis; Bettencourt, John; Black, Ed; Bodnarczuk, Maia; Bruck, Scott; Bush, John; Campbell, Brad; Carr, Cynthia; Cheskis, David; Clemens, Stephen; Curcio, John; Fetzer, Brian; Gardner, James; Gratzer, Kevin; Koszelak, Donald; Lam, David; La Pietra, Andrew; Leach, Richard; Leathersich, Cathy; Leilich, Fr.ank; Lewis, David; Lindstedt, Robert; Linton, Ray; Luciani, Antonio; Mason, Randall; Meister, Randall; Obuszewski, Kenneth; Patterson, Ross; Phan, Tu; Picario, Paul; Raghavan, V; Rivero, Marco; Shire, Daniel; Strong, Matthew; Walters, Joseph; Wickharn, Matthew; and Wilkinson, William, "Conference of Microelectronic Research 1989" (1989). Annual Microelectronic Engineering Conference (AMEC) Archive. Book 3. http://scholarworks.rit.edu/meec_archive/3

This Full-Length Book is brought to you for free and open access by the Conferences at RIT Scholar Works. It has been accepted for inclusion in Annual Microelectronic Engineering Conference (AMEC) Archive by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. Authors Louis Anastos, John Bettencourt, Ed Black, Maia Bodnarczuk, Scott rB uck, John Bush, Brad Campbell, Cynthia Carr, David Cheskis, Stephen Clemens, John Curcio, Brian Fetzer, James Gardner, Kevin Gratzer, Donald Koszelak, David Lam, Andrew La Pietra, Richard Leach, Cathy Leathersich, Fr.ank Leilich, David Lewis, Robert Lindstedt, Ray Linton, Antonio Luciani, Randall Mason, Randall Meister, Kenneth Obuszewski, Ross Patterson, Tu Phan, Paul Picario, V Raghavan, Marco Rivero, Daniel Shire, Matthew Strong, Joseph Walters, Matthew Wickharn, and William Wilkinson

This full-length book is available at RIT Scholar Works: http://scholarworks.rit.edu/meec_archive/3 Microelectronic Engineering at RIT Mindpot~r far Tomorrow’s Technology

ROCHESTER INSTITUTE OF TECHNOLOGY

JOURNAL OF MICROELECTRONIC RESEARCH

VOLUME IV

MAY 1989

Editor: Michael A. Jackson Technical Editors: Dr. Lynn F. Fuller, Dr. I. Renan Turkman, Dr. Richard L. Lane, Dr. Santosh Kurinec, Robert E. Pearson, Katherine H. Hesler, and Bruce N. Smith

Rochester Institute of Technology Microelectronic Engineering One Lomb Memorial Drive Rochester, New York 14623 (716)475-6065 ____ I

II — II III II I I I_Ill ROCHESTER INSTITUTE OF TECHNOLOGY

II ____ MICROELECTRONIC ENGINEERING

FORWARD

The papers which follow summarize the research performed by the graduating seniors from the Microelectronic Engineering Program at the Rochester Institute of Technology (RIT). Prior to their final quarter of study, the students submit a proposal for a research topic including the relevance of the project to the Microelectronics field and the Engineering program at RIT, methodology, tentative timetable and budget. After a faculty critique, the pro5ect is either accepted as proposed or revised. Thereafter, the student performs the research independently with weekly meetings with the course coordinator to monitor progress, obtain supplies, and revise the experiment as results develop. Their results are presented orally at the Ar~ne.~al Microelectronic Engineering Conference and in written form in this journal. The student is free (and encouraged) to seek the guidance of other faculty members, both in and outside the Microelectronic Engineering Faculty, researchers at other institutes, or industrial colleagues.

The course is designed to model the type of activities involved in graduate study programs. It also provides the student with the opportunity to exercise the skills obtained over the last five years and/or to develop new skills. The main area of concern for the course coordinator is guidance in the areas of technical writing and oral presentation. A series of seminars, on areas of Microelectronics, that are not adequately covered in the course work, complement the experimental work. This provides the undergraduate students with an opportunity to prepare for their presentations by listening to the work of others. Overall, the Senior Seminar and Research Course offers the RIT student an ‘unique experience to obtain competence in both technical performance and in the presentation of their work in written and oral media. These are critical areas in Engineering that are often neglected in a conventional curriculum.

We hope the reader will find this journal informative and ask your indulgence concerning any technical errors which may appear herein. While a strong effort is made to eliminate any mistakes in theory or practice, some escape our detection due to the nature of the course. We invite your comments and questions regarding any of the papers. Further details of the experiments are available upon request from the Microelectronic Engineering Office at RIT. We encourage input from others not directly involved with the Microelectronic Engineering Program at RIT so we may see ourselves through the “eyes” of others. It is this feedback which helps keep us current in our goal to provide quality engineers to the Microelectronic industry. Michael A. Jackson ~QO~ Course Coordinato ACKNOWL EDGMENTS

A special note of appreciation is due to the people that assist the students in their work. While many of the students have individually cited those people directly involved with their project, the editors wish to acknowledge several individuals, who have directly or indirectly influenced these proz~ects. These people are the RIT technicians and maintenance staff, without whom, the facility would not function. A special note of thanks is due Scott Blondell and Gary Runkle, our Facilities Manager and Head Technician, respectively. Invariably, demands are placed on their time as students learn, modify, and or build equipment. Human nature being what it is, these demands rise “exponentially” as the student conference nears. Scott and Gary do all they can for the students, and it shows in the wide variety of projects that are reported herein. Thanks guys’ Without you, this course would not be the success it is today. TABLE OF CONTENTS

SECOND LEVEL ALIGNMENT OF THE PE MODEL 140 1 Louis 6. Anastos

ADVANCES IN PROCESS MODELING AT RIT: SUPREM III AND MINIMOS ... 6 JohnBettencourt

CHARACTERIZATION OF WELLS FOR THE CMOS PROCESS 12 Ed Black

ANALYSIS OF KTI—820 POSITIVE RESIST USING THE PERKIN—ELMER ... 18 DEVELOPMENT RATE MONITOR Maia Bodnarczuk

USING THE GCA 4800 DSW WAFER STEPPER AS A PHOTOREPEATER FOR .. 23 THE FABRICATIDN OF CHROME AND ALUMINUM MASKS Scott M. Bruck

ECL CIRCUITS 29 John J. Bush

STUDY OF THE CHARACTERISTICS OF DYED PHOTORESIST 37 BradCampbell

CHARACTERIZATION OF ARC 42 Cynthia A. Carr

IMPURITY CONCENTRATION PROFILE DETERMINATION BY 47 CAPACITANCE-VOLTAGE MEASUREMENTS David J. Cheskis

COMPUTER AIDED RETICLE MAKING FOR A MICROMOTOR 53 Stephen B. Clemens

TRENCH ISOLATION STUDIES 61 John P. Curcio

CHARACTERIZATION OF A NEW E-BEAM RESIST 67 Brian Fetzer

CHARACTERIZATION OF A SILICON NITRIDE PLASMA ETCH 73 SELECTIVITIES AND UNIFORMITY James A. Gardner’

DETERMINATION OF CARRIER LIFETIME FROM MOS CAPACITORS 80 Kevin R. Gratzer

SILYLATION OF POSITIVE RESIST 85 DonaldR. Koszelak

ELECTRDMIGRATION TESTING OF ALUMINUM INTERCONNECTS 90 David Lam

MULTI-POINTCLEANROOMMONITORIN6 97 Andrew La Pietra

FERROELECTRIC THIN FILMS: PREPARATION OF A COMPLEX ALKOXIDE.,. 103 PbZr.5Ti.5O3 Richard A. Leach

iii GROWTH AND CHARACTERIZATION OF ANODIC ALUMINUM OXIDE . 109 Cathy Leathersich

F OUR BIT CMOS ALU 114 Fr.ank Leilich

THE CHARACTERIZATION OF AN ALL ENHANCEMENT PMOS OP-AMP 123 David L. Lewis

IMAGE REVERSAL OPTIMIZATION AND A POSITIVE TONE LIFT-OFF .... 130 PROCESS WITH AZ5214-E PHOTORESIST....Robert C. Lindstedt

GREEDY CHANNEL ROUTER IMPLEMENTATION IN FORTRAN 137 Ray S. Linton

FABRICATION OF AIR-BRIDGES FOR MILLIMETER WAVE INTEGRATED ... 143 CIRCUITS AntonioL. Luciani

CONSTRUCTION OF A QUASI-STATIC C-V TEST STATION 149 Randall 3. Mason

PLASMA ETCH OPTIMIZATION OF SILICON DIOXIDE WITH A RESIST ... 154 MASk E r i c P . M e is t e r

DESIGN OF A EEPROM CELL AND THIN OXIDE EVALUATION 159 Kenneth Obuszewski

PROCESS DEVELOPMENT OF MULTILEVEL METALLIZATION UTILIZING ... 165 NATIONAL SEMICONDUCTOR POLYIMIDE EL-5510 R oss P a tt e r s on

CHARACTERIZATION OF INTEGRATED INJECTION LOGIC 170 Tu T. Phan

FABRICATION OF A SINGLE LEVEL METAL CCD SHIFT REGISTER 174 Paul F. Picario

PLANAR OPTICAL WAVEGUIDES USING A SILVER-SODIUM ION 181 EXCHANGE V. P. Raghavan

nMOSSTANDARDCELLLIBRARY 187 Marco Rivero

CONTAMINATION IN RIT PROCESSING 192 Daniel C. Shire

PLASMA DAMAGE TO NMOS CAPACITORS 198 Matthew 3. Strong

INVESTIGATION OF LOCOS PROCESS USING NITROGEN IMPLANTATION .. 204 .Joseph W. Walters

ION IMPLANTATION TO ADJUST NMOS THRESHOLD VOLTAGES 210 Matthew A. Wickharn

INTEGRATEDHALLEFFECTSENSOR 215 WilliamH. Wilkinson

V Second Level Alignment of the PE MODEL 140

Louis 6. Anastos 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

The Perkin Elmer Model 140 was investigated for second level alignment. Using a photolithographic evaluation mask, inspection of six wafers yielded overlay errors. The average x-translational error was -1.95 urn, the average y-translational error was -.4um, and the average rotational error was -.0005 uradians.

INTRODUCTION

In the photolithographic process of the microelectronic industry there are three major tools of optically transferring a pattern on a mask to a photoresist coated wafer. These methods are contact printing, proximity printing, and projection printing.

Contact printing was the earliest method used to produce patterns on silicon wafers. The mask is first aligned to the wafer. It is then clamped to the resist coated wafer (while maintaining alignment), and exposed with ultraviolet light. This form of printing yields the most faithful image transfer and best resolution, but there are a couple of major disadvantages. Defects in the mask are generated from the constant mask-to-wafer contacting process. These defects are then printed on all subsequent wafers. If these defects cannot be removed by cleaning, the mask must be replaced, involving added cost. Another problem is particles that get between the mask and the wafer preventing intimate contact which reducing resolution El].

In proximity printing the mask and wafer are placed close to one another during exposure, but do not make contact. By introducing this gap, the defect problem of contact printing should be avoided, but as the gap size is increased, the resolution rapidly degrades. The equation for minimum resolution in proximity printing is given by [2]:

bmin z 1.5 * (s)%)**1/2 (1) where bmin is the minimum resolution, s is the size of the gap,

and ~. is the exposure wavelength.

In projection printing, lens elements or mirrors are used to focus the mask image on the wafer surface, which is separated from the mask by large distances. Several types of projection printing techniques have been developed, including: a) reduction step and repeat aligners; b) non-reduction step and repeat

1 aligners; and c) 1:1 projection scanners. The reduction steppers use refractive optics to project the mask image onto the wafer. Since the image projected is stepped and repeated across the entire wafer, the wafer size is no longer a problem. The ultimate advantage of stepper technology over scanner-type aligners is higher image resolution and the possibility of greater overlay accuracy [3]. The major disadvantage of steppers compared to scanners is a lower throughput. Scanners can have a throughput of 100 wafers/hr, where steppers can only output about 10—15 wafers/hr.

Projection printing is used almost exclusively for VLSI fabrication [4]. In the 1:1 projection scanner, the wafer and mask are scanned through a narrow arc of UV radiation by means of a continuous scanning mechanism. The minimum resolution of this type of system is given by:

w k *,~/NA (2)

where w is the minimum feature size, k is a constant that depends on photoresist parameters, ,~ is the exposure wavelength, and NA is the numerical aperture of the optical system [5].

This experiment consists of performing a second level alignment on a Perkin Elmer Model 140 Micralign series projection scanner. The 1:1 wafer scan system uses a reflective spherical mirror to project the image onto the wafer surface [6]. Chrome plates will be used to make the masks involved in this process. Chrome plates are used because they have better resolution capabilities than emulsion masks. The standard ETM mask will be used for the alignment targets. This mask has a number of optical verniers, resolution targets, and alignment targets. A figure of this mask can be seen in Appendix 1. Comparisons of alignment overlay between aligners can then be performed at different linespace dimensions.

The first step in this project was to select which type of alignment targets to use, from cross hairs, verniers or any others and select a minimum resolution. When this was decided, the entire alignment site and the mask can be designed. The Kodak Exposure Test Mask (ETM) was used. The four inch wafers were first put through a full RCA clean. The exposure doses were then optimized. The lamp was characterized by taking irradiance readings at different scan speeds. The following equation was then used to determine exposure dose:

E I *(100)/Sensitivity Factor (3)

where I is the irradiance reading in mw/cm2 and the sensitivity factor is .00175. The wafers were coated on the GCA wafertrac. Line program number 9, which uses a spin speed of 5000 rpm, was used. KTIB2O positive resist and KT1934 developer (1:1) were ~ Th~ ~ do~a u~c~ was s7 mj/cm2. The development

2 time associated with this exposure was 10 sec. The first ~irtq level was then imaged onto the wafers. They were then etched in a buffered HF dip for 7 mm. The etch rate determined for the buffered HF bath was 750A per mm. The remaining photoresist was then ashed off. The wafers were then put into a RCA clean. Photoresist was then recoated onto the wafers. The second masking level was aligned and exposed. The same processing parameters were used for the second level that were used for the first level. The wafers were then developed and finally inspected. The process used for aligning a second level on the scanner was then documented for further use by the RIT facility. This documentation can be found in Appendix II.

Using the GCA wafertrac a resist coating of 1.26 urn resulted with a uniformity of 99~. This value was fo~ind by taking five thickness readings across the wafer and dividing the range by the mean. The optimum exposure dose was determined to be 36mj/cm2 with a development time of 20 sec. The developer was diluted 1:1 (dev:H2D). This may still be too strong. Diluting the developer 2:3 (dev:H20) would give a better process. This would result in a longer development time which in turn would result in a more uniform development. The exposure dose was found by using the plot of Log Exposure vs. Log Scan Speed obtained by taking irradiance readings over a wide range of scan speeds and using Equation 3. This plot can be seen in Figure 1.

Inspection of the second level alignment included determining the translational and rotational alignment errors. For four oxide wafers the data obtained is in Table 1. The x and y translational errors are read directly off of the optical verniers on the ETM mask. The numbers in Table 1 are actually an average of five sites around the wafer. The rotational errors are found by averaging the top and bottom y errors and dividing by the diameter of the wafer. What this actually obtains is the tangent of the angle, but since the angle is so small they are

approximately the same. -

I Wafer* Ave x (urn) I Ave V (urn) I Ave Rotational (urad)I

I 1 I —1.2 I 1.0 I —.019 I I 2 I -1.6 I -1.8 I .011 I I 3 I -2.2 I -0.8 I .009 I I 4 I -2.8 I 0.0 I -.003 I I Ave I -1.95 I -0.4 I -.000.5 I

~j Overlay Resulta

3 LOQ Scar’ Speed vs. LOQ Exposure Dose PerkLr~ ELmer Model 110

— — — — — — — —

~ — — - — — — — —, — — - — — -:• —

%% U) ~; U) 0 C U) P... U) 0 0~ x j--” U ~ %~%%% 0 -J g — — - - — — sI~ — — — - — ~ — —- - — — -

~ — —- - — — — —

~ — ——- — — —

— - — — — — — ~I0 1000 Log Scor’ Speed

fJ~L a k~ I~ 1~iia vs. k~ CONCLUSION Scan speed was correlated to exposure dose for the Perkin Elmer 140. Process parameters were determined for exposure and development of KTIS2O positive photoresist and KT1934 developer. First and second levels were aligned and exposed on the scanner for the first time at RIT. The scanner is now ready to be used for four inch wafer fabrication. Hopefully this -will make the conversion of the RIT factory from a three inch line to a four inch line easier.

*CKNOWL IDGEMENIS I would like to thank Scott Slondell for bringing up the scanner and for his help on the wafertrac when it was having coating problems. I would also like to thank Dr. Lynn Fuller for his encouragement. I also want to thank Mike Jackson for his help in organizing all the paper-work. ~E F E RE N~ El

[1) S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Vol I, C Lattice Press, Sunset Beach, California, 1986.) p.471.

£2] L. F. Thompson, C. G. Willson and M. 3. Bowden, Introduction to Microlithography, (American Chemical Society, 1983.) p.19

£3] Ibid., Ref 1., p.472.

£4] Ibid., Ref 1, p. 468

£5] Ibid., Ref 3., p. 20

[6] Ibid., Ref 1, p. 468

WPINDZX 1.

~DAX il~L Till ~BK 5 ADVANCES IN PROCESS MODELING AT RIT SUPREM III and MINIMOS

John Bettencourt 5th Year Microelectronic Engineering Student Rochester Institute of Technology ABSTRACT Process technology for integrated circuit fabrication continues to change and an efficent simulation of process capability must be assured, to avoid time-consuming and costly empirical approaches. Suprem III and MINIMOS are process/device modeling programs that will permit the process/device engineer to accurately simulate complete silicon fabrication technologies. An initial report on these two software packages is given here.

INTRODUCTION

Suprem III is the third generation of the process simulator Suprem. Written at Stanford University, version III attempts to substantially update previous simulator capabilities. Enhancements include five material layers that can be incorporated into the simulated structure and one hopes more accurate models for oxidation,diffusion and ion implantation.

Suprem III has recently been installed at RIT on the UNIX system. It is a computer aided program that allows the user to simulate the various processing steps used in the manufacture of silicon integrated circuits or discrete devices. The processing steps being dopant deposition and drive-in, oxidation of silicon and silicon nitride, ion implantation, chemical vapor deposition, epi growth and also etching of subsequent materials. The results of interest formulated by the model are the thickness of the layers that make up a device structure and the distribution of dopant within these layers. Suprem III can also calculate other material properties such as polysilicon grain size and sheet resistivity

MINIMDS, a software package from the Technical Institute of Vienna, is set up for two-dimensional MOSFET simulations. MINIMDS has the ability to generate two-dimensional doping profiles or to utilize two ,more accurate, one-dimensional simulations for gate and source/drain regions from Suprem and incorporate them into two-dimesional profiles of a paticular device.

This report will describe some capabilites of Suprem III, and 3ustify a change-over from previous versions;also included will be a description of MINIMOS 4.0 and it’s capabilities. S

These two software packages will be both educational as well as extremely helpful in creating new process and device technologies here, at RIT. BUPR~M 1~U.

As stated earlier, the specific goal of characterizing Suprem III was to 3ustify an update from the older version of Suprem II. One advantage is that five layers can be incorporated into the simluated structure as seen in Figure 1.

SUPRE$II 5UP~EM1I!

~//II1ih1llh//IllllhI/IJ4 ..., p I,

I I

Zliyers Slayers 1 hiterface 4 interfaces 2.terlals A~’ t.rlals

Figure 1: Material Layer Comparison

With polysilicon incorporated into the program the user may simulate such poly structures as high-value resistors, polysilicon gates or highly dopped emitters. With the use of a silicon nitride oxidation layer the user will be .ble to look into LOCOS applications. Each of these were not possible with the older version. Suprem III also had the capability of the user modifying the various parameters and coefficients associated with the prediction for each material layer. This will help the user taylor Suprem III to a desired process. Presently it is not possible to characterize the ability of Suprem III in modeling polysilicon and nitride layers due to the small database of nitride runs available and the UNIX program presently has a glitch when predicting polysilicon resistivities ( predicts poly resistivities at about 10e24 ohms/cm, unacceptable).

When making a direct comparison between Suprem III and Suprem II in modeling oxidation, ambient drive-in, and ion-implantation, for current processes used at RIT, the two have been found to give similar results. A comparison was made using the RIT Factory NMDS process as a model. This NMOS process consists of starting out with the standard 8-20 ohm/cm P <100> wafers, performing several oxidations, various implants for threshold adjust, a polysilicon gate deposition and solid source diffusion for source and drain regions. The initial oxidation for 1000 angstroms of oxide is performed in a dry oxygen ambient at 1100 degrees for 50 minutes. The field oxides and gate oxides

7 grown in the same environment as the initial 1000 angstroms of oxide except growth time of the field oxide is 130 minutes and 30 for the gate oxide. The enhancement device receives a threshold adjust implant of boron at a dosage of 7.Oell at an energy of 30 Key. The depletion device receives the same implant as the enhancement plus an added implant of phorphorous at a dosage of 3.0e12 at an energy of 65 Key. After threshold adjust, 9000 angstroms of polysilicon is deposited and is then concurrently doped with the source and drain regions by a solid phosphrous at 900 degress C for five minutes followed by a wet oxidation/drive-in for ten minutes at the same 900 degrees. Table 1 is a comparison of these results.

I I Suprern II I Suprern III I

I Initial (1000 A) I 968 A I 967 A I oxide I I I

I Field oxide 9959 A I 9687 A I

I Gate oxide I 712 A I 706 A I

Source/drain I 50.7 ohm/sq I 60.4 ohm/sq I I resistivity I I

I Source/drain 0.507 urn I 0.553 urn I junction depth I I

I Enancement I 1.35 volts I 1.344 volts I Device Vt .1

I Depletion -3.73 vol’s I -4.44 volts I Device Vt I I I

Table 1: SUPREM Comparison

From the results listed it can be noted that there is no difference between the two models when predicting oxide thickness. In the case of the phosphrous source/drain solid source diffusion, it is seen that Suprem III has slightly higher resistivties and greater junction depths. In the case of threshold voltages, both simulators give good results, but Suprem III has a greater negative voltage for the depletion device. This is due to the fact that Suprem III is taking into account a doped poly gate simulation, which has a higher work function than the default values set for the polysilicon region when used in calcualting threshold voltages in Suprem II. At present there is not data base at all for the NMDS process to determine which of the simulators is giving better actual results but it should be noted that Suprem III does make an attempt at having better predictive models than older versions and it should be accepted as better until there is a better data base of the on going proceeses at RIT.

8 MINIMOS

In additon to Suprem III, MINIMOS 4.0 will be added to the list of process simlators. Written at the Technical University of Vienna, MINIMOS 4.0 is a two-dimensional MOS transistor simulator. The software has the ability of calculating various 2-D profiles from parameters set by the user. By taking into account gate size, channel implants, source/drain doping and device biasing, MINIMOS creates a 2-dimensional models of the internal behavior of the device. Plots such as electron concentration, hole concentration, current density and doping can be generated.

MINIMOS offers several possibilities for the definition of the doping profile. First MINIMOS can calculated its own profiles or SUPREM can be used to calculate doping profiles much more accurately. From these profiles P1INIMOS solve Poisson’s equation for two dimensions and predicts the desired profiles.

The best way to further explain MINIMOS would be to give an example of a particular input file and show some examples of the results. Figure 3 is an input file where MINIMOS would determine the doping files internally.

The TITLE line is used to identify the file. In the DEVICE line the device is characterized as being an N-channel with a gate length of 2.Oum, channel width of 10.0 urn and having a gate oxide of 400 angstrorns. The BIAS statement specifies an operating point may wish to look at; here the drain to source voltage is 5.0 volts, gate voltage is 2.5 volts, and the voltge of the substrate is 0.0 volts. The PROFILE statement is used to define background concentration (2.0e15 atm/cm2) and source/drain doping (40 Key implant of phosphorous at a dosage of 1.5e15 atrns/cm2 through 500 A of oxide, then drivien in for 15 minutes at 900 degrees). The IMPLANT statement is for modeling various implants in the channel region; here will be a channel implant of boron at 20 key for a dosage of 7.lell atms/cm2 and driven in for 15 minutes at 900 degrees centigrade.

I TITLE RIT TRANSISTOR I I DEVICE CHANNEL~N TOX~0.400E-05 L~2.0E-04 WtlO.OE-04 I I BIAS UD~5.0 UG~2.5 UB~0.0 I I PROFILE NBz2.0e15 ELEM~PH DOSE~1.5e15 AKEV~40 Tox~500.E-8 I + TEMP~900 TIME:15 I I IMPLANT ELEM~B DOSEz7.E11 AKEVz2O TEMP~900 TIME:15 I END I

Figure 2 MINIMOS INPUT FILE

If the user wishes to use Suprern III to calculate the doping profiles, Suprem simulations must be performed for the source/drain and gate regions. A PRINT LAYER CONCNETR NET FILENAME~file.out statement must be used at the end of each SUPREM III input file to generate files that contain impurity distributions that can be run by MINIMOS.

The following is a description of the plots shown in figure 3, generated from MINIMOS. These were created by John Faricelli of Digital Equipment Corporation, Hudson Massachussetts with the help of Surprem III and MINIMOS software. They represent a 2X10 um NMQS enhancement device using the RIT NMDS factory process.

S 1~

2. 3-

(a) (b)

~ø(_

Figure 3: MINIMDS Examples

Figure 3(a) is a ~3D’ plot of doping concentraton. The channel implant can be seen as the small “hump~ in the doping between the source and drain regions. This type of plot would be helpful in prediciting the effects of lateral diffusion on channel lenghths and find where the current density will be the greatest under the oxide ; MINIMOS can calculate current density also. Figure 3(b) is a “3D” plot of potential in the device for a bias of Vds:5V and Vgs:2.5 volts. From the very step gradient in potential from drain to source region, voltage drops to nearly O volts at about I urn into the channel, is an indication that this device may have a high field within it. This may lead to oxide breakdown near the drain junction and other problems. Figure 3(c) is a “3D” plot of the electron concentration. The “pinch-off” point can be seen as the drop in concentration near the drain junction. Figure 3(d) is a “20” contour plot of the electron concentration near the drain region in pinch-off. The “pinch-off” region, on the 2-0 plot is the electron concentration at 10e16 electrons/cm2 that goes from 0.0 to 0.015 microns deep. From this we can see that the device is not truly pinched off.

CONCLUS! ONS

SUPREM III and MINIMDS are process/device modeling tools which are intended to be design aids in developing new devices and accompanying processes. With the update to SUPREM III and obtaining the VMS version, the process engineer will have a more usuer friendly package than previous version and have graphics capabilities not available now with SUPREM II. MINIMOS will not only allow a device engineer to quickly see the effects of doping, channel length and bias effects on a device but will also serve as an educational tool in showing the student the various internal characteristics of MOS transistors.

Also RIT will (hopefully> be obtaining a VMS version of SUPREM III from Digital Equipment Corporation. Not only will the VMS version be more user-friendly than the UNIX version, and possibly be “bug-free” upon installation, it will have the ability of producing graphics plots of the diffusion profiles on the HP7550 and DECLVP16 plotters, and on the VT340, VT240 and Workstation terminals. This is not possible now with the current VMS version of Suprem II.

ACKNOWLEDGMENTS

Special thanks are extended to John Faricelli of Digital Equipment corportation in Hudson Massachussetts for supplying the MINIMOS plots and for sending through a software requsiton for RIT to obtain SUPREM III and MINIMOS in VMS “turn-key made tapes” from DEC. Also, I would thank Rob Pearson for helping in supplying and filling out various documents for obtaining these software packages.

REFERENCES

U) Ho, Charles P. and Hansen, Stephen E. “Suprem III - A Program for Integrated Circuit Process Modeling and Simulation”. Stanford Electronics Laboratories. July 1983.

£2) Selberherr, Schultz and Potzl. “MINIMOS -- A Two-Dimensional MOB Transistor Analyzer”. IEEE Transactions on Electron Devices. Vol. Ed-27, No. 8, August 1980, pp.1540-1549

11 CHARACTERIZATION OF WELLS FOR THE CMOS PROCESS

ED BLACK 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

SUPREM simulations were run to determine a junction depth of 3um and a sheet resistance of approximately 5kohms/square to be used in wells for CMOS fabrication. From these results an experiment involving an implant energy of SO KeV, doses of 4E12/cm2, and 8E12/cm2, drive-in temperatures of 1100C and 1150C, and drive-in times between 2 and B hours was performed. Sheet resistances, measured using a four point probe, and junction depth, measured using a groove and stain tool, correlated well to SUPREM simulations.

I NTRODUCT ION

The first step in a CMOS process is the well level. There are two major methods with which to create a well: diffusion and ion implantation. Both diffusion and ion implantation are used to introduce impurity atoms in silicon. While diffusion is a thermal process, ion implantation is a kinetic process. High temperatures are necessary to diffuse impurities in silicon, while implantation dopes by providing the ionized atoms with enough energy to penetrate the surface of the material. Ion implantation allows us to obtain more accurate doping concentration profiles at the expense of crystal damage.

During an implant, ions are created in a source such as an RF gas discharge or a Penning source. Ions are extracted from this source, accelerated (10 - 5000 KeY), and focused to a beam. Undesired ions are removed by means of a mass separation magnet so that a beam of very pure dopants is made available. When the accelerated ions strike the silicon they penetrate it to a depth determined by their energy (KeY) [1].

Bombardment of a silicon crystal by a beam of ions, whose energies are about ten times greater than the energy holding the the silicon atoms in their lattice, results in displacement of the silicon atoms by both direct and secondary impact. The damage and disorder due to any implant has to be removed by annealing so that the only electrical properties of the silicon altered by the implant are those dependant on carrier concentration. Mobilities and lifetimes are both greatly reduced by disorder in the lattice and must be preserved for devices to reach their design specifications. Annealing is also required to allow the implanted dopant atoms to reach proper substitutional lattice positions and to ionize (activate). f~t annealing temperatures above 950C full activation occurs; 100~ bulk mobility, and lifetime completely recovered. It should also be mentioned that the silicon consumed during oxidation accompanying drive-in of an implant is the damaged layer of the surface [2].

There are four important practical features of ion implantation. Dose can be accurately controlled for 10E16 ions/cm2 equal to the heaviest diffused predeposition down to less than 1OE11 ions/cm2 (several orders of magnitude down on what can be achieved by diffusion) and ion implantation is always more accurate. Implantation can take place through a thin oxide. The implant may also be buried without disturbing surface concentration. Masking material dose not need to survive high temperatures, so metals or even photoresist can be used. Large impurity doses do not require long times: more impurity can be put in at room temperature than could be done with long diffusions at 110CC [3].

The p-well process had been the commonly used technology for earlier CMOS circuits before the technique of ion implantation was widely used for threshold control. Since the gates of the n and p-channel transistors are tied together and the applied gate voltage keeps one device on and the other one off, the threshold voltages of the two devices should be closely matched. In most recent designs, the control of the threshold is accomplished by ion implantation. Traditional p- and n-well structures make use of a deep impurity diffusion to form the well. Since impurity atoms diffuse vertically and laterally, a lot of the lateral area is used up, resulting in a lower packing density. With ion implantation, since the annealing temperature doesn’t need to be as high as a diffusion temperature, the implanted profiles show minimal lateral spread. The resulting profile yields many improvements such as high conductivity and a low ohmic drop, improved punch-through voltage, reduced junction capacitance and body effect, and better latch-up immunity [4].

EXPERIMENT

Different processes were researched [5-8] and numerous SUPREM simulations were run from which it was determined that a junction depth of 3 microns and a sheet resistance of around 5Kohms/square was desired. From this, an experiment involving doses of 4E12/cm2 and 8E12/cm2, energies of 150 KeV for the phosphorous implant and 100 KeV for the boron implant, drive-in temperatures of 110CC and 115CC, and drive-in times between 2 and 8 hours was planned. Upon processing, however, it was found that the implanter can only maintain focus of ion beams up to 80 KeY, so that is what was used. A summary of experimental conditions is given in Table 1.

A mask set was designed using the wells shaped as resistors. The resistors were of different lengths and widths three of which are 16 squares and three of which are 11 squares in size. four P-type and four N-type <100> wafers were cleaned and

13 TABLE 1 EXPERIMENTAL CONDITIONS I

PHOSPHOROUS ENERGY ~G0 KEV I WELL: I I DOSE~4E12 and 8E12 atoms/cm2 I

DRIVE-IN TIME~2,4,6 and B hours

DRIVE-IN TEMPS~1100C and 1150C I

I BORON WELL: ENERGYzB0 KeV

DOSE~4E12 and 8E12 atoms/cm2

I DRIVE-IN TIMEz2,4,6 and B hours

DRIVE-IN TEMPS~1100C and 1150C I approximately 7000A of oxide was grown in wet 02. This oxide was the mask during implantation. KTIB2O resist was applied and the wafers were photolithographicly patterned. This left bare silicon where the implant was desired. The wafers were cleaned, implanted, and driven in. The wafers were broken into four pieces to accommodate all the drive-in times and temperatures. The drive-in was done in wet 02 for 10 mm. Then the remaining time in N2. The thin oxide deposited during this step was to keep damaging nitrogen atoms away from the bare silicon surface. It was originally planned to process the contact cut and metal layers and probe for the sheet resistance at the probe stations, but due to time restrictions this was not done. Instead, after drive-in the sheet resistance of the implant was measured using a four point probe in large implanted regions outside of the resistor patterning and junction depth was measured using a groove and stain tool.

RESULTS/DISCUSSION

Figure 1 shows the junction depth vs. drive-in time for both boron and phosphorous implanted wells. One can see that the SUPREM simulations gave smooth curves for the junction depth vs. drive-in time graphs for both the boron and the phosphorous wells. These curves increase with increasing drive-in time as was expected. The experimental results showed actual junction depths that were a little shallower for the same energy, dose, and drive-in time and temperatures. However, they were not far off from the simulated results.

Figure 2 shows the sheet resistance vs. drive-in ti~me for both boron and phosphorous implanted wells. For the boron well the sheet resistance quickly increased then very slowly decreased with increasing drive-in time where the phosphorous implant sheet resistances quickly decreased then very slowly decreased with BORON WELL BORON WELL JUNCTION DEPTH VS. DRIVE-IN TIME JUNCTION DEPTH VS. DRIVE-IN TIME SUPREM SIMULATION EXPERIMENTAL J .1 U U N 5-~ N 5 CM CM ii~• •.••00000 TI4. • I.’ a 0R3 OR3 • a NO2.. ~ ND2 N — i DSjJ S DS1 a

El E • I I ~ P. I I I I I I I I I PO• 900900 1 9 190 200 390 490 500 600 700 800 900 T 0 H H TIME (MIN) TIME CHIN)

ENERGY - DOSE - DRIVE-IN TEMP ENERGY - DOSE - DRIVE-IN TEMP • SDKeV-4E12-IIUDEG.C • BOK.V-4E12-1100C • SUKeV-E12-IIIGDEG.C I SflK.V-8E12-11111C o OK.V-4E12-II5SOEG.C a e.K.V-4E12-ll5rC • SOK.V-8E12-II500EG.C • 1K.V-5E12-1150C

PHOSPHOROUS WELL PHOSPHOROUS WELL JUNCTION DEPTH VS. DRIVE-IN TIME JUNCTION DEPTH VS. DRIVE-IN TIME EXPERIMENTAL SUPREM SIMULATION 3 3 U U N 5’ • a CM CM i I 4’ • TI 4 •A0• IC IC OR 0 R t ~ • •~ ~ ~ I ii~I I I I I NO ND : N t N ~ •~ DSj. I I : p ~ P 9- V iée 200 360 460 50 600 760 960 900 100 2~0 300 400 660 700 960 I TO s6e e6o H H TIME CHIN) TIME CHIN)

ENERGY - DOSE - DRIVE-IN TEMP ENERGY - DOSE - DRIVE-IN TEMP • .K.V-4E12-IIUDEG.C • SOK•V-4E12-IIIIDEG.C • NIc.V-eEl2-IIUDEG.C • IDK.V-BE12-IIIODEG.C a SIK.V-4E12-II5IDEG.C a BIIK.V-4E12-II5DDEG.C • g.K.V-eEl2-IISaDEG.C • BSK.V-1E12-II510EG.C

Figure 1: junction depth vs. drive-in time ~i ~OR ~LL S~EEi ~SIST~CE VS. DRIVE-IN TItE StEEl ~SIST~CE VS. DRIVE-IN THE S SIFREM SINJ_ATION S H H D~tRItENTAL ED ED E H tWOS E H IWOO TM TM o o o • • • • ••.•V••••••.• ES SO ~uee ‘U ‘U BA 440 BA 440ê a a a a TR TR AE SWI AE 2Wê N iSO 2W 3W 4W 50 SW 7W 950 900 N S C E THE (KIN) E THE (KIN)

B~RGY - DOSE - DI~YE-IN TEMP 8~GY - DOSE - D~VE-1M TEMP • 1K.V-4E15-IISIDEG.C • ~K.V-4E1t-1IIIDEG.C • NK.V-SEIt-IIIIDEG.C I •Ik.V-IEI2-IIISD€Q.C A IIK~Y-4E12-I15SDEG.C A ~K.V-4ElS-I15IOEG.C • IeK.V-IEII-11SID€G.C • IIK.V-IEI2-IISIDEG.C

PHOSPOROUS ~LL PHOSPHOROUS hELL StEEl ~SIST~4CE VS. DRIVE-IN THE StEEl ~SISTANCE VS. DRIVE-IN THE S SLFREN SIPU..ATIDN H ~ERItENTAJ. ED ED E H 4500 E H 4400 TM TM S S RI 3046 S • P / 3045 A S ES ES SO ~W otttttt*,..... I U 2504 S BA ~ BA b S~ •~ ~ •i •• •‘ •• •• I YR tWo N I SW 2W 3W 4W 550 604 704 904 900 N • 1O2O30445 7.9049W C. E THE (MIN) E THE (KIN)

BlE~OY- DOSE - DR~ YE-IN TEMP EMERGY - DOSE - O~VE-IN TEMP • UK.Y-4E12-IIIIDEG.C • IIk.Y-4Elt-IIIIDEG.C I IIK.V-SE12-IIUDEG.C a IIK.V-IEI2-I1IIDEG.C A IIK.V-4E12-IISSDEG.C A IIK.V-4E12-II5IDEG.C • ItK.V-IElt-IIMDEG.C • IIk.V-IEIt-IIMDLG.C Figure 2: sheet resistance vs. drive-in time

increasing drive-in time. The time period of this quick increase or decrease corresponds to the time of oxidation at the beginning of drive-in. The reason for this sharp increase in sheet resistance for the boron implant is the loss of dopant to the oxide making it more resistive. The reason for this sharp decrease in sheet resistance for the phosphorous implant is what is called the ‘snow plow effect’ where dopant is piled up at the surface giving a decrease in resistance. It is my 3udgement that SUPREM dose not model resistivity due to damage anneal. If it did, the graphs would have shown a steeper decrease in resistance over time, unless it occurred during oxidation. The experimental results were higher than the simulated and showed almost straight curves after two hours in each case. Thus, the dopant atoms are fully activated at this time; they have reached proper substitutional lattice positions and the damage is annealed. The well level of a CMOS process characterized by SUPREM simulations as well as experimental data. Junction depth and sheet resistance was analyzed as a function of implant energy and and dose as well as drive-in time and temperature. Experimental data for the 3unction depth agreed well with simulated data. The experimental data for the sheet resistance also agreed fairly well, but it is my opinion that the SUPREM data dose not correctly simulate the annealing process in the case of resistivity. This information will hopefully prove to be useful in the upcoming CMOS processing here at RIT.

ACKNOWL ED3PIENTS

Rob Pearson for pointing me in the right direction at the beginning, and Mike Jackson for his help in obtaining supplies and giving helpful insights.

REFERENCES

[1] P.A.H. Hart, “HANDBOOK ON SEMICONDUCTORS VOL.4”, (North Holland Publishers, New York, 1982), pp.71-76

[2] H. Kessel, J.P. Biersack, “PROCESS AND DEVICE MODELING (ion implantation models for process simulation)” (North Holland Publishers, New York, 1986), pp.31-70

[3] S.M. Sze, “PHYSICS OF SEMICONDUCTOR DEVICES,2nd ed.”, (Wiley-Interscience Publishes, New York, 1981),pp.70-73

[4] A.D Milne, “MOS DEVICES (design and manufacture)” (Wiley-Intersciences Publishers, New York, 1983),pp.63-69

[5] M.D. HARTRANFT, H. VYAS, T.E. HENDRICKSON ~ S.J. LEE, “A HIGH PERFORMANCE ANALOG AND DIGITAL COMPATIBLE N-WELL CMOS PROCESS”, lEE CICC Proc. p 117-112, Rochester, NY, May 11-13 1981 [6] Vladimir Rumennik ~ David L. Heald, “INTEGRATED HIGH AND LOW VOLTAGE CMOS TECHNOLOGY” lEE Trans. Electron Devices 1982

[7] K.W. Terrill, P.F. Byrne, H.P. Zappe, N.W. Cheung & C. Hu, “A NEW METHOD FOR PREVENTING CMOS LATCH-UP” lEE Trans. Electron Devices 1983

[8] D. Takacs, J. Har’ter, E.P. Jacobs, C. Werner, U. Schwabe “COMPARISON OF LATCH-UP IN P- AND N-WELL CMOS CIRCUITS” lEE Trans. Electron Devices 1983

17 ANALV8IS OF KTI-920 POSITIVE RESIST USING THE PERKIN ELMER DEVELOPMENT RATE MONITOR

Maia Bodnarczuk Fifth Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

Experimental analysis via the Perkin Elmer Development Rate Monitor (DRM) has determined that KTI-820 resist, when exposed at 48 mJ/cm2 and developed for 30 sec in KTI-934 developer, gives optimum results. That is, 2 micron line-space pairs have been succesfully reproduced with minimal sidewall sloping.

I NT~ODUCT I ON

Computer simulation is a tool used extensively in the semiconductor industry. The analysis of photolithographic systems by such simulations has been established. The Perkin Elmer Development Rate Monitor (DRM) is a computer aided system which monitors the real-time development action of photoresist. The data obtained during the experiment is stored in a computer for later analysis. The stored data is combined with the cha acterization of the exposure tool to make predictions which would result under certain process conditions.

Since a thin film of resist is applied to a highly reflective surface, the wafer, it stands to reason that the total reflectivity of the system will vary with the resist thickness. According to Dill [1], reflectivity is a maximum for each even quarter wavelength multiple of resist thickness. Similarly, odd quarter wavelength multiple correspond to minimum reflectivity. This fact is the precursor to the fundamental principle behind the DRM, namely interferometry.

Interferometry is a term used to describe analysis based on data collected as a function of interference patterns. When monochromatic light is reflected from two parallel surfaces, the resulting beams will interfere and form a pattern. The interference pattern may be detected in the form of signal intensity versus time. In a resist system, the variation in the detected signal is a function of reflectivity due to the change in resist thickness. Figure 1 is a pictorial representation of this concept and depicts the sinusoidal nature of the signal. Figure 2 is a more specific representation of the DRM. As shown, several points along the wafer are monitored simultaneously. There are 256 points for which development action must be monitored. The information which is collected is passed through a photodiode array and is stored in a computer data base for retrieval and subsequent analysis.

~ j~WkkF I.*WT ?.~ ______::: ~LTWTQ~

a~s;sT ..&,.cI~

F,G-I FIQ27_

DREAMS software is used to address the analysis of the development process. The development of positive photoresist has been modeled as a surface-rate limited etch reaction [1]. The concentration of the inhibitor in the resist exposed to the developer is the ma3or factor in determining etch rate. Resist and developer chemistries are also significant variables but remain constant for most analysis. Inhibitor concentration is maximum in exposed areas, corresponding the a lowest etch rate. DREAMS uses these principles to analyze development data.

DREAMS will present to the user intensity versus time data for the 256 pixels monitored. The user examines this and manually divides the information into zones which correspond to the exposures used prior to development. The computer averages the information within each zone and reduces the 256 pixels to a particular number of zones. Each zone is examined; maximum, minimum, and steady state intensity values are indicated. This information is used to generate thickness versus time plots. Such a plot gives the time to clear, Tc, for each exposure value. In addition, DREAMS creates the characteristic curve for several development times. The sensitivity,Eo, and contrast for the resist can be extracted for such a plot.

At this point, PROSIM software is used. The first step is to characterize the exposure tool with respect to light source, mask type, lens system, etc. The end result is an aerial image af the system. This is the intensity distribution of the light that actually hits the wafer surface. Such information is then combined with rate information obtained in DREAMS to make perdictions on resist performance under specified conditions

This experiment utilized DREAMS and PROSIM software to characterize the performance of KTI-820 positive resist.

19 L~PI~ I!1~Nt Several 3 inch wafers were coated with KTI-820 positive photoresist. The wafers were exposed using the Kasper contact printer at an exposure value of 80 mJ/cm2. This was done through a multiple transmission mask as shown in Figure 3. The 15 percent transmissions for this mask range from 1-60~ thus providing values from 4 to 48 mJ/cm2. The wafers were then placed in the development tank shown in Figure 4 which was filled with KTI-934 developer. The DRM monitored the development and stored intensity versus time information for each of the 256 pixe~1s.

FIG3 FJ~-4-

The raw data was examined and the 256 pixels were reduced to 15 zones. Signal versus time data for the pixels within a zone were averaged to create one plot for each exposure value. Figure 5 is the intensity versus time plot for zone 7 which was exposed to 14.4 mJ/cm2.

V 2.5 Zon. Si~n.~ v~ Ti.. 10.44 Zone 7 Li Ta 14.40 SL.2

F1G5

Analysis of the development data as well as the characterization of the exposure tool then took place using DREAMS and PROSIM. Finally, all of the information was combined to to generate resist profiles for varying exposures and development times.

20 ~ESULii/DISCUS51ON

Thickness versus time data can be found in Figure 6. Time to clear, Tc, is shown as well as original thickness for each zone. Characteristic curves were generated in Figure 7. This is a relationship of thickness with respect to log exposure for several development times. The sensitivity for each development time is tabulated.

0-.... 2(12—220 20—Apr—12 ~. 212-100 ‘7”r. - V 2.5 ThIQ2~I ~ Ti.. 22.02 v z.s Tht~eee ‘.. L$ E.p..~. 11,45 A..r.g. 2nitL~1 Thid~~. 2~ 1.040 — Ii 7. A.w~Og. lni22.1 ThIcb~.. te 1.~ .. 1. TI.. .10 244.2 1. 41.42 12.2 4.00 122.0 41.24 212 1.00 121.2 14.21 10.2 2.10 202.4 11.11 14.4 u.~ m.e 21.4) 43.0 13.10 710 22.51 10.0 ~ 24.40 10.2 24.10 11.2 21.00 14.1 14.10 14.1 1 27.10 21.2 15.70 10.2 ~ 10.00 10.0 21.21 71.0 - 24.00 43.0 .1 1.11 25.0 ~ 21.00 $4.4 10.11 300.4 10.00 12.2 — 121.1 40.00 51.2 42.00 III

50 100

FIG- Lo FL&]

The Kasper’ contact printer was characterized for 2 micron line space pairs sighting G,H, and I lines. An intensity distribution was obtained for an 8 micron window. This can be examined in Figure 8. Once this distribution delivered through the mask was determined, it was applied to the rate information obtained earlier and several profiles were generated.

C00TACT $2221122 27—Apr—19 21 2.2 1..~. Profil. 12.02

21. I

0 0l44~2o. Al..g ~i22 04r21 0.0 0.~k un. le 2.0~ AM Cl.~ Lan. I. 2.~ AM ~.A. ln.t. of T.d..

Figure 9 shows profiles for varying exposures at a development time of 30 seconds. The best reproduction of 2 urn lines and spaces occurs for an exposure of 48 mJ/cm2. However, there is a little thickness loss and some edge rounding. In addition, the sidewalls slope at approximately 84 degrees. Figure 10 corresponds to a development time of 90 seconds. In this case, 14 mJ/cm2 provides the optimum profile. Here rounding 21 and thickness loss is more pronounced and sidewalls are sloping at approximately 76 degrees.

XTI-820 28—Ap-88 R..I.~ PI~.FI1. 10~ 58 V 1.2 R..I.~ P~~Il. 12.12 V 1.2 0e~.1op.nt Tt.e 80.000 :4 0...Iap.e~ TI.. 80.000 8.q. 48.00 48.00 40.00 40.00 U. 00 82.00 28.00 ~. 00 24.00 24.00 20.00 3 17.00 14. 00 12.00 10.00 8.00 I 4.00

- ——r—— ~~1 2 1 4 S 0 8 5 0t.ta~. Al...8 W.Fw (.~) DI.t~,n. Along W.f~ C.~.) FI~r9 Initlol ThInk.,... 1.358 FIQ~ tO CONCLUI ~ ONI

Experimental analysis demonstrated the optimum process conditions for KTI-820 resist. That data shows that an exposure value of 48 mJ/cm2 with a development time of 30 seconds will form the best series of 2 micron lines and spaces. Although less exposure with longer development time also produced the correct line and space width on the base of the image, such images have pronounced thickness loss and more sidewall sloping. Simmulations predict that For “best results” one should invoke a higher exposure value and develop for a shorter time.

~CkNOWL.ED~MENrS

I would like to thank Mrs. Kathy Hesler and Mr. Bruce Smith for their help.

[1] Frederick Dill,”Optical Lithography”,IEEE Trans. Elect. Dev. vol.22, no.7, July 1976.

[2] S.P. Grindle and E.K. Pavelchek,”Photoresist Characterization Using Interferometry During Development”, Test Meas. L4orld Expo Proc. vol.2, May 1985.

[3] Frederick Dill and L4illiam Hornberger,”Characterizatjon of Positive Photoresist”, IEEE Trans. Elect. Dev. vol.22 no.7, July 1976.

[4] M.P.C. Watts,”Positive Resist Development Model for Linewidth Control”, Semiconductor International, April 1984.

22 USING THE GCA 4800 DSW WAFER STEPPER AS A PHOTOREPEATER FOR THE FABRICATION OF CHROME AND ALUMINUM MASKS

Scott M. Bruck 5th Year Microelectronic Engineering Student Rochester Institute Of Technology

ABSTRACT

Utilization of the GcA DSW 4800 as a PHOTOREPEATER enables the production of masks with flexibility, resolution, speed, and precision. A new chuck directly interchangeable with a standard GCA 100 Millimeter wafer chuck was machined for simple conversion from STEPPER to PHOTOREPEATER. Commercial Chrome plates and Quartz plates with thermally evaporated Aluminum films were coated with KTI-820, exposed, and etched. Chrome film resolved to 1 micron and the Etched Aluminum resolved to 3 microns. INTRODUCTION Since the formation of the Rochester Institute Of Technology (RIT) Undergraduate Microelectronic Engineering program, the majority of the masks used by the Students and Faculty have been fabricated on a Mann Type 1795 PHOTOREPEATER. Reliance on this technology has created severe limitations on geometries available lithographically to the Institute. Using the current procedures, lithography is limited to fabricate emulsion masks with a ten micron rule. The Mann Type 1795 PHOTOREPEATER uses a lox Ultra-Micro Nikkor (Nikon) Lens with a Numerical Aperture of 0.28 and F=28 mm corrected for H-line exposu_e at 5458 Angstroms. The Lens can image over a 6.3 mm square area and is limited to one focus setting at any given exposure run [2]. The GCA DSW 4800 Stepper has a lOX G-Line lens with a numerical aperture (NA) of 0.28 corrected for 4360 Nanometers wavelength. The Ziess lens can image a 10 mm square area. The 4800 DSW is equipped with high precision stages that are monitored by a laser position transducer to meter X/Y coordinate stage positions. The system is equipped with automatic compensation for atmospheric pressure and work piece temperature is employed to insure stage accuracy. The 4800 DSW contains an automatic lens focus system which compensates for standard wafer thickness tolerances and surface irregularities. This is accomplished through the use of a photoelectric detection circuit which utilizes the wafer surface as a reference plane. The circuit controls a Z-axis drive which determines the elevation of the microreduction printer tube [1].

23 Utilizing the precision optical and mechanical capabilities of the GCR 4800 DSW stepper, a new process was implemented that could optically resolve geometries to 1.25 microns. The excellent flexibility of the GC~ 4800 DSW software allows for the inclusion of more than one die type on a mask and variability in its location. The primary concern of this project was to utilize the above system to develop a vertically integrated system for the production of masks, including a procedure for coating Glass or Quartz plates. An Aluminum evaporation procedure was investigated for its attractive cost and application method. Major considerations for the conversion is the relative thickness difference between the two substrates and the conversion process between modes must occur easily. The solution was to bring the mask into the focus plane of the wafer. For the Autofocus system to accept the substrate, the system must determine the distance between the optical column and the substrate on the chuck. The optics are optimized to focus on a surface of 15 mils through 20 mils above the chuck; mask plates are 90 mils thick. The increased thickness is outside the focus tolerances of the optical column, 2.5 microns per 25 ~, and the stepper will reject the substrate. EXPERIMENT A chuck was machined, illustrated in Figure 1, to be interchangeable with the 100 nun chuck on the GCA 4800 DSW that would accomplish this task. Focus adjustments were eliminated since the surface of the mask would be in the same position as a wafer under the optical column and autofocus system. The assemblies for the wafer chuck, mask chuck, and the two superimposed are illustrated in Figures 2,3, and 4.

Cb~c~ F~ tOO .... 12$ mm Pt.t.s

U . — - - _____ IOOmmIbskt~ftx

— - V.cw.m ~r..,.s . L

Figure 1 Figure 2 24 Ultra flat 125 mm Glass plates for Pattern Generator use, Quartz plates, and Commercial Chrome plates were obtained. The Glass plates were cleaned in a Bleach solution with a 1:1 ratio with water, cleaned in a soap solution, rinsed in DI water, and Nitrogen air dried.

Uas~ Focus P~n• R.pr.s.l~sliofl

>— c;e~

— .W..W/j ~ —p~ - ~ ,Z ~ - p~ c~ ~

I I

Figure 3 Figure 4

The Glass and Quartz plates were placed in a CVC Evaporator for both an Argon Glow Discharge clean and Aluminum evaporation. The chamber was pumped to a pressure of 2.OE-4 Torr and a variac was used to create a 45 Volt difference between the chamber and the plate holder. An Argon plasma was sustained at 8.OE-4 Torr for a 10 minute clean cycle. Two 0.6 Gram pellets of Aluminum were evaporated at a pressure of 1.OE-5 Torr. Measurements were taken using a Profilometer, thickness for one pellet was 3800 Angstroms and two pellets (after etch) produced a thickness of 4450 Angstroms. Plates were coated with an Integrated Technology coater. A dynamic dispense of KTI 820 was executed at 50 RPM, the resist was accelerated to 4000 RPM for a 30 second spin, and resist thickness was measured utilizing a profilometer over developed resist image. The resist was pre-baked at 85 Degrees Celsius for 30 Minutes in a convection oven. To obtain relative uniformity measurements, the Nanospec program “Positive Resist on Silicon,” one hundred measurements were collected at 12.5 millimeter intervals in both the X and Y directions. The numbers were normalized to the edges and a three dimensional plot was made using the PLT3D software on a VAX computer system.

25 A program was written in the $! I $DX1 directory of the GCA 4800 DSW STEPPER entitled ETM MASK. This program is a two pass job that allows an array of device chips to be exposed with a 10 Millimeter stepping displacement, followed by an array of test chips. This job can be altered to change stepping, allowing for multiple passes, and multiple chips to be exposed on the same substrate. The job is written for a 110 Millimeter wafer to fill the entire desired 100 Millimeter area. A second job labeled MASK1 was written for 4000 Micron square chips. This is a two pass job similar to ETh MASK. Using the EXPO(sure) feature on the GCA 4800 DSW STEPPER, a focus exposure matrix was created to determine the optimum values of Focus and Exposure for both Chrome and Aluminum plates using the KODAK/RIT ETM MASK. Optimum focus and exposure was obtained and plates were exposed at these values. The ETM MASK was utilized for its wealth of resolution targets and line width structures for characterizations. The exposed resist was developed in KTI-934 developer mixed at a 1:1 rtio with DI Water for 30-35 seconds and postbaked for 30 Minutes at 140 Degrees Celsius in a convection oven. Aluminum plates were etched in a solution of hot phosphoric acid/Aluminum etchant at 40 Degrees Celsius until clear. Aluminum thickness measurements were accomplished with a profilometer. The Chrome masks were etched in CY.ANTEK CR-4 Chromium Photomask Etchant until clear. The masks were placed in a cascade DI water rinse until resistivity was above 7 MegaOhms. The plates were examined to determine best resolution using 45 Degree Resolution Targets, Equal Line/Space pairs, and KODAK/MANN 3600 Targets. Resist was stripped in a TEGAL Plasmaline and with Acetone. The plates were rinsed in a DI water bath, sprayed with DI water, and blown dry with a Nitrogen gun. RESULTS/ANALYSIS Resist was coated and the average thickness measured. by the profilometer was 6250 Angstroms after development. A three-dimensional plot of the normalized resist uniformity is pictured below in Figure 5. The contour plot shows a uniform and stable area within a four inch diameter in the center of the plate where the mask die would be exposed.

PATTEPN GENERATOR grade Glass plates were initially used for the substrate material, however, it was. determined that the plates were not flat enough for STEPPER use. When the plates were exposed, each plate yielded a different optimum exposure and focus. More disturbing, the focus window was extremely narrow and was inconsistent from plate to plate. Quartz/Commercial Chrome plates were substituted for the Glass plates and exposure/focus performance resembled standard wafer values. Optimum exposure and focus values were as follows: For Chrome

26 plates with 12% anti-reflective coating, the best exposure was 61 mi/cm-cm with a center of focus at 250 GCA units. Aluminum exposure was calculated at 48 mj/cm-cm with a center of focus at 250 GCA units.

1CT1420 Resist Uniloimity Plot

*~t

Normalized to edges

Figure Figure 6 Completed Mask

Chrome plates were etched, clearing time was 2 to 2.5 minutes at 20-25 Degree Celsius. Aluminum Clear times were 2 to 3 Minutes at 40 Degree Celsius in Aluminum etchant The Chrome etching process was well behaved, while the Aluminum etching process produced limited lifting. From examinations under the microscope, the Aluminum lifting can be attributed to undercutting of the smaller structures. For 45 Degree Resolution Targets, the Chrome resolved 1.0 Microns and Aluminum resolved 3.0 microns. Examining Equal Line/Space pairs, Chrome resolved 1.2 Microns and Aluminum resolved 3.0 Microns. The KODAK/MANN 3600 Targets yielded 1.0 Microns in a Chrome film and 2.5 Microns in an Aluminum film. The differences between the two processes can be attributed to the developed Chrome etch. When plates were post-baked, Acetone would not remove the resist. A Chrome mask was placed in the TEGAL PLASMALINE asher in an 02 Plasma; the resist was removed and the anti-reflective Chrome-Oxide layer was destroyed. A procedure without a post-bake was examined and the resist was polymerized enough to withstand the wet •tch. A completed mask is illustrated in Figure 6.

27 CONCLUS IONS Utilizing the GCA 4800 DSW as a Photorepeater extends the optical range available, flexibility, and control for mask making. The new mask chuck provides a simple solution for converting from STEPPER to PHOTOREPEATER without requiring any adjustments to the optical column or focus system. Aluminum can be used as a masking material and with a developed etch process produce high resolution masks. For the continuation and optimization of this investigation, the following is suggested. Develop a method for depositing Chrome material on Glass or Quartz plates. Investigate methods to produce superior uniformity in resist coatings using the 125 Millimeter coater. Develop a AZ135OJ resist procedure as an alternate resist and compare the resolution of the two processes. Examine both the Chrome and Aluminum etch processes to obtain superior line width control and better uniformity. This process enables a completely vertically integrated inexpensive method for producing high resolut~.on masks ACKNOWLEDGMENTS I would like thank Dr. Lynn Fuller for all his input, Argon Glow Discharge cleaning process, and support of this project. I would like to thank Bruce Smith for his assistance with the mask making process, machining of the Mask Chuck, and rapid repairing of the Mask Chuck when a problem arose. I would also like to thank Gary Runkle for allowing use of the Lab to finish my Aluminum process development and Mike Jackson for his input on the final paper. REFERENCES [1] GCA Corporation/Burlington Division, GCA 4800 DSW manual, (1978/1979) GCA Corporation [2] David Mann Company, MANN 1795 PHOTOREPEATER manual, (1969) David Mann Company [3] David J. Elliot, Integrated Circuit Mask Technology, (1985) McGraw-Hill Inc.

28 ECL CIRCUITS

John 3. Bush 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABS TRACT Emitter Coupled Logic (ECL) gates were fabricated on a n-epi layer. SUPREM was used to simulate the fabrication including junction depth and sheet resistance. The Integrated Circuit Editor was used to layout the design based on SUPREM parameters. SPICE was also used to confirm the proper operation of the devices. Testing was limited due to a lack of a probe card for the logic analyzer. But, an npn transistor was tested with a gain of one indicating a working device was present. A subcollector implant was not performed due to the time constrains placed on the project. INTRODUCTION Emitter Coupled Logic operates all transistors in their forward active region or in their cutoff region, avoiding saturation and the accompanying stored charge [1]. Thus, ECL gates are faster than those in any other logic family. ECL gates operate with a supply voltage of -5.2 volts. The logic levels are therefore negative, being approximately -.75 (high) and -1.6 volts (low). Complementary outputs are also available which avoids the necessity of adding gates simply as inverters. A fanout as large as 25 is allowed, but with noise margins on the order of .2 volts t2]. Other disadvantages associated with ECL gates include a small difference between the two logic levels (approximately .8 volts), larger chip area occupied due to the transistor isolation regions, and a high power dissipation relative to other logic families. A typical ECL transistor is shown in Figure 1. The isolation regions are necessary to obtain devices which are electrically separate. The p-type substrate must always be held at a negative potential with respect to the isolation islands in order that the pn junctions be reverse biased.

Figure 1: Cr088 section of a typical npn transistor

29 Figure 2: (a> Inverter (b) OR/NOR gate

i.O~

ovT A vi ~it

-5.zv

This project involved the simulation, design, fabrication, and testing of ECL devices. The devices designed and built include an inverter, OR/NOR gate, ring oscillator, transistor, and base and emitter resistors. The ECL iriverter design shown in Figure 2(a) is called a difference amplifier because of the output is proportional to the difference between the two input voltages Vl and V2, which is fixed at -1.2 volts. When Vi increases above -1.1 volts, the transistor Qi turns ON and Q2 is off which causes the output to go LOW. Also, if Vl decreases to -1.3 volts, Qi is off and Q2 is ON which causes the output to go HIGH. Except for a very narrow range of input voltages Vi, the output takes on only one of two possible values and, hence, behaves as a digital circuit [3). The )R/NOR gate designed is shown in Figure 2(b). The OR/NOR gate consists of three transistors plus another two transistors to correct for DC level shift. Note if Figure 2 (b) that either the OR or NOR function can be utilized depending on where the output is taken from.

Figure 3: Ring Oscillator The ring oscillator designed is shown in Figure 3. The ring oscillator is simply an odd number of inverters arranged with the input of one going into the output of another. The purpose of including a ring oscillator in the design was to determine the speed at which the ECL circuit operates.

EXPERIMENT The wafers used for processing were p-type wafers with a Sum, 10 ohm/square epi layer. The Integrated Circuit Editor (ICE), an in house CAD tool, was used to design the layout of the devices. The layout of the design is shown in Figure 4. Reticles were made using the MANN Pattern Generator. Masks were generated on the MANN photorepeater. The process consisted of five masking levels. The levels were for isolation diffusion, base diffusion, emitter diffusion, contact cuts, and metalization. Spin on dopants were used for all diffusion steps. The Kasper contact mask aligner was used with Kodak 820 as the photoresist.

The layout was designed based on a SUPREM simulation. In addition to information about junction depth and sheet resistance, SUPREM provided a base from which the fabrication process was developed. The wafers had 5300 angstroms of oxide grown on before isolation to mask the long boron diffusion step necessary for the complete isolation of the 5 micron epi layer. After the isolation regions were defined, the base regions were diffused using boron dopant as modeled by SUPREM. The emitter regions were then diffused using phosphorous dopant. The contact cuts were then made followed by aluminum evaporation and patterning. A final sinter step was performed for 30 minutes at 450 degrees celsius in a nitrogen environment to provide ohmic contacts. SPICE was used to model the logic devices designed. Because logic circuits were used, SPICE was used only to confirm the correct logic levels of the gates. The devices were tested on the HP 4145 semiconduc~ ~r parameter analyzer. RESULTS/DISCUSSION

The critical parameters obtained from SUPREM included junction depth and sheet resistance. The junction depth and sheet resistance after each hot process.step are summarized in Table 1. The simulated junction depth was an important parameter to have when designing the circuit on ICE. The spacing between lines had to be large enough to compensate for lateral diffusion. Since the isolation diffusion went down 6 microns, it can be concluded that it will probably diffuse 3 microns laterally on each side of the lines. The HP 4145 semiconductor parameter analyzer was used to test the devices with limited success. The large and small base resistors were determined to have resistances of 220 ohms (Figure 5) and 415 ohms (Figure 6) respectively. The emitter resistors were not isolated from the n-type epi layer so the values 3.)

0 4zu >1 fri C) H

4) 14 r4 ____ _GRAO V2 1/GRAD .3000/div~XintarcQptj( V)Y1ntQrc~p~ ______

Figure 6: Small Base Resistor Figure 5: Large Base Resistor

****** GRAPHICS PLOT ~ P ****** GRAPHIcS UT ******

12 CURSOR ( 2. 6000V • 8. 8O4mA • ) 12 ?IARI

1•OOo~ •1 idly 1/ 7

.OOOfl~ 0000 3. 000

V2 .4000/div ( V) ____ [~~E1 4. 55E—03 220E+OO 665E—03 —3. 03E—03 LZr_6RA0LiL~~~0 xi ntQrcapt~ Y I nt~p~ ~J~4E2 I~~i 2.41E—031 415E+00 —iI.OE—03 28.5E—O6J Table 1: SUPREN values for junction depth and sheet resistance

I Hot Process Step I Isolation Xj I Base Xj I Emitter Xj I I Xj/PHO I Xj/PHO I Xj/PHO

I Isolation Diffusion I 5.25 I - I I 1.31 I ———— I ————

I Base Oxide I 5.52 I ---- I ---- I I 1.50 I ———— I

I Base Diffusion I 5.52 I 1.02 I ---- I I 1.60 I 16.7 I ————

I Emitter Oxide I 5.79 I 1.94 I ---- I 1.77 I 28.0 I ———— I Emitter Diffusion 5.77 I 2.98 I 0.95 I I 1.86 I 154.2 I 17.6 I Contact Cut Oxide I 6.02 I 3.73 I 2.23 I 2.02 I 2081 I 11.32

obtained did not correspond to those for which they were designed. A large npn transistor was tested and determined to have a gain of one. The characteristic for the npn is shown in Figure 7. The low gain from the transistor may indicate a problem with the quality of the diffusion steps. Spin on dopants were used in the fabrication process because of the time factor involved in using solid sources. The use of solid sources is recommended in the future to obtain more pure and uniform diffusions. Another reason for the low gain is that a subcollector implant was not performed. A subcollector implant would have lowered the collector resistance and thus increased the gain. The testing of the ECL gates was attempted but with no success. However, it was not concluded that gates lacked the potential to work. Because a probe card was not available, the logic analyzer could not be used. The use of the logic analyzer is almost a necessity when testing ECL gates because of the power supplies needed. Perhaps further testing on the logic analyzer would produce working gates. The quality of the diffusions was again in doubt when testing the ECL gates. Future ECL work should include designs with more test devices so that it could be determined if the circuits would work without actually testing them. The area needed for the additional test structures could be obtained by increasing the size of the chip used. CONCLUS IONS The project produced working resistors and a working bipolar npn transistor with a gain of one. The low gain was concluded to be the result of a problem with the quality of the diffusions.

34 Figure 7: Transistor Characteristic

GRAPHICS PLOT ****** LARCE TRANSISTOR IC Varlobi.1 (uA) VCE —Ch3 Ltnor w.gp Stort .0000v Stop 10.000v 50. 00 — V V_Vs Stop . boDy

Varlat,1.2a ia —th2 Stort .000 A Stop 40. OOuA Stop 10. OOuA ~VVVj 5. 000 Con.tantit /d iv ——--4— —-.~ i V YE —~h~ .0000V

V I

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I I ~_~;__~ ~ V - J J

• 0009 _i i~ _~i I .0000 10.00 VCE 1.000/div ( V)

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35 Also, it was noted that a subcollector implant was not performed. A subcollector implant would have lowered the collector resistance and thus increase the gain of the transistor. The ECL gates were unable to be properly tested due to a lack of a probe card for the logic analyzer. Suggestions for future work include using a pad configuration which corresponds to an existing probe card and performing a subcollector implant.

ACKNOWLEDGMENTS

Mike Jackson for his ideas on the project and for his help in presenting the work, and Scott Blondell for his efforts keeping the eqi.iipment operating. REFERENCE S [1) Arpad Barna and Dan I. Porat, Integrated Circuits in Digital Electronics, (John Wiley and Sons, New York, 1973), pp.127—129. [2) Herbert Taub, Digital Circuits and Microprocessors, (McGraw-Hill Book Company, New York, 1982), p.90. [3] Jacob Millman, Microelectronics; Digital and Analog Circuits and Systems, (McGraw-Hill Book Company, 1979), p.155-163. [4) Richard S. Muller and Theodore I. Kamins, Device Electronics for Integrated Circuits, 2nd ed., (John Wiley and Sons, New York, 1986), pp.155-163.

36 STUDY OF THE CHARACTERISTICS OF DYED PHOTORESIST

Brad Campbell 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

Undyed, AZ 1512,and dyed, AZ 1512-SFD, photoresist was coated on aluminum covered oxide topography. The exposure was varied from 7OmJ/cm2 to 130m3/cm2 and the 3.Oum line/space pairs were measured to calculate the exposure latitude. The resist lines were examined over topography for signs of reflective notching. Results showed an increase of the exposure latitude from 9.1% to 9.9% for the dyed resist. The data was inconclusive in determining any improved control of reflective notching with the use of dyed photoresist.

INTRODUCTION

The microelectronic industry is continually striving for smaller geometries. In order to extend the practical lifetime of costly lithographic equipment, alternate methods of imaging photoresist are being examined. Antireflection coatings, multilayer resist systems, and dyed photoresist have all been used successfully to enable existing equipment to meet the required smaller dimensions. The strength of dyed photoresist is that it can be directly incorporated with little variation of an existing p ocess. -

A dyed photoresist helps control notching from stray light while at the same time increasing the exposure latitude [1],[2]. Notching is a variation in the photoresist linewidth which occurs as it passes over reflective topography. The scattered light exposes the resist as it reflected through the layer. The unwanted exposure of the photoresist results in line width variations in the region of the topography after development. The addition of the dye to the photoresist will absorb stray light[3], resulting in a reduction in reflective notching. Figure 1 shows the effects of stray light in an undyed photoresist. Dyed photoresist exhibits a greater exposure

wA~ 37 latitude over the undyed material. The dye absorbs excess light which falls on the resist that would normally cause overexposure. Thus, the dye renders the resist more tolerant to small variations in exposure.

Dyed resist is not without drawbacks. Since exposure due to reflected light is removed by the dye, the dose required to expose a wafer is increased. The throughput of wafers coated with dyed resist is less than that of conventional wafers coated with undyed resist because of the increased exposure time. The other major drawback of dyed resist is am decrease in the slope of the resist sidewalls. It has been found that an increase in absorptivity of a photoresist results in a smaller side wall angle[4].

The American Hoechst corporation produces the undyed photoresist AZ 1512—SFD. The resist is a diazoquinone-novalac based system [4] with the addition of an absorbing dye. The nom-bleachable dye is most sensitive to light with a wavelength of 436mm, the g-line of a mercury vapor lamp [4].

The objective of this experiment was to compare the exposure latitude of a dyed and undyed photoresist. Also examined was the ability of the dyed photoresist in controlling reflective notching.

EXPER!MEN’l~L

An oxide layer of 5000A was grown on 16 wafer using a wet oxygen environment. KTIS2O positive photoresist was the resist layer used in patterning the Kodak Exposure Test Mask (ETM). Figure 2 shows the layout of the ETM mask which is used in evaluating photoresist imagt~s. A wet etch was used to

Fig 2

transfer the ETM pattern into the oxide. An aluminum layer, 2500A, was thermally evaporated on the wafers.

38 Five wafers were hand coated with AZ 1512 at a spin speed of 4000RPM. The wafers were prebaked on a hot plate for 45sec at 100C. A 1.lum thick layer was measured using the Nanospec. The exposure was varied from 7OmJ/cm2 to 130m3/cm2 in increments of 15m3/cm2. The ETM mask was shifted so that the arrow on the mask aligned to the marks of the center cell in the middle row. A hand development took place for 1mm in AZ312 MIF (1:1.2) developer. The 3.Oum line/space pairs were measured with a stage micrometer. Linewidth verses exposure was plotted. It was determined that a variation of 0.lum from the actual value of 3.Oum was acceptable. The maximum and minimum exposure which yielded acceptable linewidths was recorded. The exposure latitude was calculated using the equation:

Exposure Latitude EXPmax-EXPmin (1) EXPopt

The process was then repeated for the dyed photoresist, AZ 1512-SFD.

The region where resist lines crossed over 5000A of Aluminum coated oxide topography was used to examine notching. The 3.Oum photoresist linewidth was examined visually to see if variation occurred while passing over topography. This was done for both the dyed and undyed photoresist. Photographs were taken at each exposure.

RESULTS/ANALYSI8

The results for the calculation of exposure latitude are summarized in Table 1. Figure 3 shows the plot of linewidth verses exposure for the undyed photoresist, and the plot of the dyed resist is seen in Figure 4.

The optimum exposure for the 3.Oum line increased in going from the undyed to dyed photoresist. The dye in the resist absorbs the secondary light. This is light which would normally reflect off of the surface of the substrate and aid in the exposure of the resist. The exposure of the dyed resist was increased to compensate for the removal of the secondary exposure.

EXPOSURE LATITUDE EXPRESSED AS A PERCENTAGE OF THE TOTAL RANGE AZ 1512 AZ 1512-SFD

EXP~4.n~ 61.25 76.25 EXPoi~r 64.20 80.00 EXP1~2&~ 67.10 84.20 LAT 9.1% 9.9%

Table 1

39 A slight increase of the exposure latitude (EL) occurred for the dyed photoresist. As calculated above, the EL is expressed as a function of the total range. The amount of variation of the exposure from the mean exposure which gives acceptable results is plus/minus half of the EL, as calculated with Equation 1. A minimal increase in the exposure latitude occurred in going from the undyed(9.1~) to dyed(9.9~) resists.

;tn.tfl~ .. Ia....

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I.I~.Ia. a Is..... taI.a. 3.b~ Lis. •1 IW—WI ~I~flifl

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The photoresist lines which crossed over the topography were examined for notching. The inspection was done visually. All the wafers showed similar results with virtually no notching occurring at any exposure dose. Figures 5 and 6 shows the resist, which runs horizontally across the picture, at the maximum exposure of l3OmJ/cm2. No difference could be seen between the dyed and undyed resist jn the control of reflective notching. ______

undyed dyed Fig 5 Fig 6

40 CONCLUS I ONS

The exposure that was required to produce similar line/space pairs increased going from the undyed to dyed photoresist. This results because the dye absorbs light reflected from the substrate which normally aids exposure. The exposure latitude showed an increase with the addition of the dye. The change in exposure latitude was not as large as expected. Finally, the results from the reflective notching experiment were inconclusive. No variation was seen between the dyed and undyed resist.

ACKNOWLEDGMENTS

I would like to thank Bruce Smith for the help that he gave me on this project.

RJF ERJN~i9.

[1] Chris A. Mack, “Dispelling the Myths About Dyed Photoresist,”Solid State Technology,pp. 125-130, January 1988

[2] M. Bolsen, “TD Dye or Not To Dye - Some Aspects of Today’s Resist Technology,”MicrOelec. Eng., vol3,pp. 321-328 [3] M.Watts, D. DeBruin, W. Arnold,”Experimental and Modelling Study of Reflective Notching Control Using Dyed Resist,” SPE 7thPhotopolymer Conf., Ellenville 1985 [4] M. Bolsen, et al.,”Dne Micron Lithography Using Dyed Resist on Highly Reflective Topography,”SOlid State Tech., vol.. 29,no. 2,pp. 83-8B(Feb. 1986)

41 CHARACTERIZATION OP ARC

Cynthia A. Carr 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

Two Anti-reflective coatings (ARC), ARC-XL end ARC-PN2, were studied for process latitude. Temperature bake and exposure dose were varied and their effect on 5.Oum line/space pairs was evaluated. Using the software package RS1 a full factorial experiment with centerpoints was designed. The two ARCs used, did reduce notching and the manufacturer’s processing ranges were verified. However, to establish the process latitude a wider range of exposure doses needs to be evaluated.

INTRODUCTION Anti-reflective coatings (ARC) improve the performance of single layer resists with respect to resolution, tolerance, and linewidth control over topography. Also, as geometries become smaller and smaller it becomes important to avoid notching. Notching is usually a result of reflections from topographical features, especially from inside corners as shown in Figure la [1]. The interference between incident and reflected exposure light and light scattering from neighboring patterns can lead to differential light absorption across pattern steps [2).

FIGURE 1: (a) without ARC (b) with ARC

42 ARC has many features that make it part of a viable bilayer process. ARC products have greater adhesion to aluminum substrates than positive photoresists due to their resin structure. ARC is compatible with most major positive photoresists and PMI4A planarization layers and is developed in positive resist developer simultaneously with exposed resist. The only additional processing steps are the ARC spin coat and bake. ARC also has advantages over dyed photoresists. Under certain conditions, dyed resist may be plagued by scumming due to standing waves, whereas ARC eliminates all standing waves [3). ARC gives a better contrast and does not require a change in the development process. It is also easier to implement and does not require a post-exposure bake. Experiments were designed to study the ARC under varying bake temperatures and exposure doses. The experiments were designed for both Brewer Science Incorporated’s ARC-XL and ARC-PN2. Both ARC-XL and ARC-PN2 were formulated to do the same thing. However, ARC-PN2 has a larger process latitude in the bake temperature and to give better development properties in deep channels. ARC-XL is the latest formulation from Brewer Science, Inc. ARC-XL has an increased absorbance and a greater shelf life than previous ARCs. This increased absorbance allows for processing in the mid-UV to deep-UV exposure regions and thus allows for better resolution.

EXPERINENTAL DESIGN An experiment was designed on RS1 using a full-factorial design that includes centerpoints. The full factorial design with center points requires relatively few runs per factor studied and it is easy to analyze. The design is based on an interaction model, which includes the effects of the variables independently, and together. The design allows for two runs to be replicated, to determine the variability of the experiment and its validity. When using ARC it is the bake temperature and the exposure dose that are most critical to the process [2). The bake temperature and exposure dose for the ARC were varied within the manufacturer’s ranges in order to study process latitudes. Some secondary factors, such as, humidity and temperature of cleanroom were not directly incorporated into the design, but were monitored during processing. Development time and temperature were kept constant. The 5.Oum line/space pairs were used for evaluation on wafers with and without ARC, since 5.Oum geometries for IC fabrication is being developed at RIT. The response, latitude, will be in terms of a number; 1, 2, or 3 for undercutting, “normal”, and scumming results. The two experiments are given in Tables 1 and 2.

43 ______II ______II ______II

TABLE 1: EXPERIMENT FOR ARC-PN2

I WAFER ID I BAKE TEMPERATURE (C) I EXPOSURE DOSE (mJ/cm2) I

I ______I ______I ______I I ARC1 I 168.0 85 I I ARC2 I 174.0 I 95 I I ARC3 I 162.0 I 75 I I ARC4 I 168.0 I 85 I ARCS I 162.0 I 95 I I ARC6 I 168.0 I 85 I ARC7 174.0 I 75 I

TABLE 2: EXPERIMENT FOR ARC-XL

I WAFER ID I BAKE TEMPERATURE (C) I EXPOSURE DOSE (mJ/cm2) I

I ______I ______I ______I I ARC8 I 170.0 I 85 I I ARC9 I 145.0 I 85 I I ARC1O I 170.0 I 65 I ARC11 158.0 I 75 1 I ARC12 I 145.0 I 65 I ARC13 I 158.0 I 75 ARC14 I 158.0 I 75 I

In a process with KTI 820 positive resist applied with a spin speed of 5000 rpm the base dose is usually 55 mJ/cm2. Without the ARC, the reflected light from the substrate is partially responsible for the exposure. With ARC there is a greater absorbance of the energy and this needs to be compensated for by increasing the base dose.

For the exposure process, the RIT ETM mask was used. The ETh mask is a mask used by RIT in lithography courses, and contains a series of line/space pairs, and test targets which can be used for evaluating focus and resolution.

The wafers were cleaned and oxide was grown to obtain a thickness of 5000 A. To pattern the SiO2, the wafers were coated with HMDS and KTI 820 positive photoresist using the hand-spinners. The wafers were baked, exposed, and developed. The wafers were etched in buffered, ashed in the Plasmaline and cleaned. Aluminum was evaporated onto the wafers using the CVC evaporator.

The control wafers, those without the treatment of ARC, were coated on the Wafertrac, using an inhibited scrub and no HMDS. The wafers were exposed and aligned on the Kasper Aligner. The wafers were developed on the Wafertrac using KTI 934 developer in a 1:1 dilution and were then etched in aluminum etch heated to 40C. The wafers were then ashed in the Plasmaline.

44 Wafers ARC1 through ARC14 were processed according to the experiment designed by RS1. The ARC was coated on the hand-spinners for 60 seconds at 5000 rpm. The wafers were then individually baked on the CEE electric hotplate for one minute at the temperature specified. The wafers were coated with photoresist on the Wafertrac, without a scrub nor HMDS prime. All the wafers were exposed on the Kasper aligner at the dose specified by RS1 and then developed. The wafers were etched in aluminum etch heated to 40C. Finally, the photoresist was stripped using the Plasmaline. The Sum line/space pair was examined and measured using the stage micrometer.

RSUL?SIDISCUSSION

In examining the results it is apparent that many of the line/space pairs do not total bOurn, since the user’s judgment is required when reading the stage micrometer. The results for ARC-PN2 are shown in Table 3. It appears that the best equal line/space pairs were obtained at a bake temperature of 162C and an exposure dose of 75 mJ/cm2.

TABLE 3: EXPERIMENT FOR ARC-PN2

IWAFER IDIBAKE TEMP(C)IDOSE(mJ/cm2)ILINE/SPACE(urn)I STAND DEV (urn) I

I ______I ______I ______I ______I ______I ARC1 I 168.0 85 1 3.96/7.62 I 0.386/0.373 I I ARC2 I 174.0 I 95 I 3.05/5.08 I 0.254/0.285 I I ARC3 I 162.0 75 I 4.22/5.58 I 0.340/0.332 I I ARC4 I 168.0 I 85 I 3.66/7.11 I 0.495/0.505 I I ARCS I 162.0 I 95 I 3.56/5.46 I 0.439/0.427 I I ARC6 I 168.0 I 85 I 3.20/6.09 0.340/0.382 I I ARC7 I 174.0 I 75 I 3.10/5.84 I 0.417/0.400 I

I ______I ______I ______I ______The ARC-XL results are given in Table 4. ARC-XL gave the best equal line/space pair at a bake temperature and exposure dose of 145C and 85 mJ/cm2, respectively.

TABLE 4: EXPERIMENT FOR ARC-XL

IWAFER IDIBAKE TEI4P(C)IDOSE(mJ/crn2)ILINE/SPACE(Um)I STAND DEV(urn) —I I ______I ______I ______I I ARC8 I 170.0 I 85 I 3.30/5.58 I 0.597/0.623 I ARC9 I 145.0 I 85 I 3.64/5.08 I 0.227/0.223 I ARC1O I 170.0 I 65 I 3.05/4.57 0.358/0.364 I ARC11 I 158.0 75 I 3.35/6.35 I 0.455/0.501 I ARC12 I 145.0 65 I 3.20/4.06 I 0.663/0.636 I ARC13 I 158.0 I 75 I 3.05/7.37 I 0.312/0.348 I ARC14 I 158.0 I 75 I 3.10/7.37 I 0.300/0.336 — I I ______I ______I ______I From examining the replicated runs, the experiment for ARC-XL had better reproducibility than the experiment for ARC-PN2. In measuring the line/space pair of 5.Oum it was

45 apparent that the spaces, for both ARCs, were bigger than the lines. There did not appear to be any scumming nor undercutting. This did verify the manufacturer’s ranges, however, there were no results to enter into RS1. The procedure that should have been undertaken was to start at extreme exposures and work inwards towards the manufacturer’s guidelines. This would have produced ~ latitude ~hartn and allowed RS1 to predict what would happen at bake temperatures and exposure doses not tested. At the larger linewidths in the wafers without ARC, the lines did not appear to have an scumming nor undercutting. However, at the smaller linewidths, there was not enough exposure in the valleys and too much exposure in the peaks. This is the result of notching.

CONCLU8ZON~ Anti-reflective coatings, ARC-XL and ARC-PN2, were studied and compared as a means of controlling reflection and standing wave effects within a positive photoresist. ARC helped to improve the performance of KTI 820 by preventing notching in the metal lines over the topography. The manufacturer’s ranges for bake temperature and exposure dose were verified.

ACKNOWLEDGMENTS Brad Campbell for being there in the beginning for someone to bounce ideas off of during processing, Kathy Hesler and Bruce Smith for their suggestions and help, and Mike Jackson for his continued support throughout the research project.

REFEREW~ES

[1) W. Arden, H. Klose, and A. Krause, “Contrast Improvement by Antireflection Coatings for Mask and Wafer in 10:1 Projection Optics”, Kodak Microelectronics Seminar Interface’ 83.

[2] P. Burggraaf, “Positive Photoresist Enhancement Options”, Semiconductor International, April 1987, pp. 84-91.

[3] Brewer Science Product Literature. [4] R.D. Coyne and T. Brewer, “Resist Processes on Highly Reflective Surfaces Using Antireflection Coatings”, Kodak Microelectronics Seminar Interface ‘82.

[5] K. Hesler,”Anti-Reflective Coating Experiment”, EMCR 575 Lab, 2/9/88.

46 IMPURITY CONCENTRATION PROFILE DETERMINATION BY CAPACITANCE-VOLTAGE MEASUREMENTS

David J. Cheskis 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

A FORTRAN program has been written to manipulate the data obtained from 1 MHZ C—V measurements. This program utilizes the data to compute information on the impurity profile of capacitors. Capacitors were fabricated with varying doping profiles and tested. The doping proifles obtained using this program were consistent with SUPREM models.

INTRODUCTI ON Capacitance—voltage (C—V) measurements have many applications in the characterization of semiconductors, among the most popular are techniques used to study the Metal—Oxide—Semiconductor (MOS) system. Using the basic high frequency (1 MHz) C—V test, information can be gathered about the quality of the oxide with respect to both the electrical performance and the processing involved in fabrication of the MOS device. With further manipulation of the C—V data, more information can be gathered,such as the doping profile of the semiconducting E bstrate.

The typical n—type C—V curve shown in Figure 1 depicts the regions of operation of the MOS capacitor. With a large voltage applied opposite of the polarity of the- substrate (positive voltage), the majority carriers build up at the Si—Si02 interface due to the applied voltage. When the voltage is decreased toward zero volts, the majority carriers relax and the donors at the surface start to become depleted of their carriers. This results in the ionization of the donors to maintain charge neutrality in the semiconductor. Finally, as the voltage in increased with the same polarity of the bulk (negative), the depletion region width reaches a maximum value and majority carriers are then attracted to the surface to compensate for the excess charge applied to the gate. In both the accumulation and inversion regions of the typical C—V plot the ionized impurity density is only weakly proportional to the applied voltage since the free carriers in the bulk comprise the majority of the charge accumulation under these biasing conditions.

47 Vt, ~vol1s)

Figure 1: N—type capacitor C—V plot.

Therefore, using the abrupt space—charge approximation for the capacitor in the depletion region, and assuming that ‘interface traps have negligible influence, the amount of charge depleted in the semiconductor is proportional to the charge on the metal by a factor of q, the charge of an electron. The depletion region width then varies as a function of applied voltage, Va, by

W = ~(2 s/qN(x))[Vbi — VaH**l/2 (1)

where s is the permittivity of Silicon, N(x) is the impurity concentration, and Vbi is the built—in potential of p—n junction. The total charge per area in the depleted region is then given by Equation 2.

0 = qN(x)W (2)

Since the capacitance is the differential of the charge with respect to the voltage, the capacitanc~e at any given applied voltage is determined by

C = dQ/dV = A~(q sN(x)/2[Vbi — Va))’I**1/2 (3)

which can then be used to fit data from C—V analysis by rearranging Equation 3 to be C=As/W. (4)

To determine the doping profile at a given depth into the substrate, the amount of the change in the depletion region width due to additional applied voltage is necessary. The Mott—Schottky [1] relation allows the doping density to be determined by the slope of the inverse square data of the C—V plot. A plot of l/C**2 as a function of the applied voltage yields a constant slope for a uniformly doped substrate. A typical l/C**2 curve is shown in Figure 2 for an undoped substrate in the depletion region of the C—V curve.

48 1/C~2 vs. A~LLed ‘~‘cLtD~

No ImpLot, Fireo — 1.6e3 cn~2

.2 1.E~ 2 ~ ~‘~~togcr (vO~.~

Figure 2: A typical l/C**2 vs voltage curve.

If the substrate is non—uniformly doped (i.e. ion implanted, diffused concentration gradient), the Mott—SChOttky plot will, in turn, be nonlinear. The slope of the MOtt—SChOttkY plot is given in Equation 5.

in = slope = (l/C**2)/ V = 2/(Aq sN(x)) (5)

Rearranging Equation 5 provides the impurity concentration as below

Nd = 2/(Aq sin), (6) which then is plotted as a function of position into the substrate, by determining the position, W, from the capacitance using Equation (4). In addition, the maximum dept.. to which the doping profile can be determined is limited by the onset of the inversion region in the C—V curve [2]. The profiles vary, therefore depending upon the C—V charactersiticS of the particular device. A FORTRAN program was developed and implemented to determine the slope of the Mott—SchottkY curve. From the C—V data gathered with a 1 MHz test set—up, the Mott—SchOttky curve and the doping profile of the sample were generated with the program. MOS capacitors have been fabricated and tested which have varying doping profiles as a result of ion implantation.

EXPERIMENT

A FORTRAN program was developed and implemented to determine the slope of the Mott—Schottky curve. Data acquisition was performed using the method developed by Dale Webb using the HP4145 as an analog to digital converter [3]. The data is then passed to the IBM PC and uploaded to the VAX mainframe using KERMIT protocol.

49 The FORTRAN program CVND.FOR uses the central difference method to calculate the slope of the Mott—SChOttkY curve. The space charge width is on~the order of a Debye length [2] when the capacitor is biased in the accumulation mode, thus the doping profile cannot be determined accurately until near the depletion mode of operation. Since the data in the accumulation region is not as important as that in the depletion region, more attention was paid to the detail of the curve there when digitizing the data.

With the slope of the Mott—Schottky curve, the ionized impurity concentration is calculated using Equation (6) above. The depth into the substrate at which this impurity concentration occurs is then calculated by rearranging Equation (4) and solving for W.

MOS Capacitors were fabricated and obtained from Matt Wickham. In addition, Schottky diodes were fabricated to test and compare with the MOS capacitors to determine the effects of the 1 hour 1100 C capacitor oxide growth process on the impurity profile. Three p—type wafers were implanted with Boron at 80 key with a dose of 8e12 cm—2 ions. These three wafers and two bare wafers received a 900 C anneal for 30 minutes in N2 at 6 slpm to remove the damage of the implant and activate the impurities. Aluminum was then deposited onto the backside of all of the wafers and sintered at 450 C for 15 minutes to achieve an ohmic contact to the backside. Three wafers were then patterned with capacitors on the front side, two of which were implanted with one was non—implanted wafer. The fabricated deviecs were then tested and along with the wafers fabricated by Matt Wickham, wer~ analyzed using the CVND.FOR program to determine their impurity profiles. SUPREM was used to model the implant and oxidation steps performed in the fabrication.

RESULTS/DISCUSS ION

After the fabrication of the Schottky diodes, electrical testing indicated that each capacitor was shorted, most probably due to the ohmic contact on the backside. In addition, the Aluminum deposited on the front side could have been annealed to some extent during the ashing of the photoresist used to pattern the contacts, creating an ohmic contact as well. Therefore, the results described were only gathered on the capacitors fabricated by Matt Wickham, which received doses of 1, 2, 4 and 8el2 cm—2 ions of Boron at 80 key. At 80 key, the projected range of the implant is approximately 2500 A and produces a profile of about 2el7 atoms/cm3 according to the Pearson IV distribution utilized in SUPREM II.

50 Various capacitors were tested, and using the digitized data, the number crunching was performed on the VAX/VMS system. The program CVND.FOR also allows for the data to be analyzed on the VAX as the program not only outputs the doping profile as a function of position in a file called NDDATA.DAT, but also the C—V data (in a file called CVOUT.DAT) and the Mott—Schottky plot of l/C**2 vs applied voltage (in a file called MOTT.DAT). The impurity profiles correlated well with the results of simple SURPEM models. Shown in Figure 3a is a comparison of two different implant dose profiles and a non—implanted profile, while in Figure 3b, the SUPREM model of the highest implant dose is depicted.

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with thermal oxidation. -

As mentioned above, the impurity profile is calculated for a much larger portion of the bulk in the undoped capacitor as compared to the implanted capacitors. In addtion, it can be noticed that the impurity profile extends upward in the region closest to the surface of the substrate. This is due to the interface proximity limitation [2] in which the profile begins to increase exponentially as the interface is approached. This affect of the impurity profile is caused by the Si—Si02 interface within a few Debye lengths of the interface.

Additionally, the profile in the very closest region to the interface is unable to be determined as the carriers in this region are also depleted either by interface traps or other charge in the oxide.

51 SUMMARY

A program has been developed which will allow for simple determination of impurity profiles of capacitors fabricated at RIT. The program CVND.FOR (attached in the Appendix) is used to calculate these profiles and output C—V and l/C**2 curves. A capacitor was profiled and had a maximum impurity concentration of about 2e17 /cm3 approximately 2100 A into the substrate, which correlates well with a SUPREM simulation.

REFERENCES

[1) R.K. Ahrenkiel, Microelectronic Manufacturing and Testing 11

(13), 13—14 (1988). —

[2] E.H. Nicollian and J.R. Brews,MOS Physics and Technology, pp. 380—408. [3) Webb, Dale, RIT Senior Project, Automated Capacitance—voltage Measurements , 1987.

52 COMPUTER AIDED RETICLE MAKING FOR A MICROMOTOR

Stephen B. Clemens 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

The creation of MANN files, generated by computer programs, to produce other than rectangular features for the design of reticles required for the manufacturing of a micromotor has been investigated. The reticles have been designed to compensate for the lateral loss of polysilicon and silicon dioxide during the etching process and for the loss of silicon during oxidation. Three computer programs were designed to generate MANN files that would control the SCA Pattern Generator and expose emulsion coated glass plates yielding images of circles, washers, and the placement of rectangles at any orientation with respect to the center of the reticle. The reticles were developed using standard and reversal processing. The GCA MANN 4BOOSW Stepper will utilize these reticles to image wafers for the manufacture of micromotors.

I NTRODUCT I ON

The technology and processes used to produce integrated circuits has been applied to the construction of micromachines such as motors, cantilevers, sensors, gears, relays, and actuators. These micromachines provide an interface between the electrical and the physical world. Integrated circuit processing technology has provided the means to develop micromachines that can rotate, slide, and store mechanical energy in a ready made form. These structures can be formed of numerous movable parts without the problems of assembling each individual component.

This project involved the design of a micromotor, similar to that developed by Fan, Tai, and Muller[1]. Differences between the two designs lie in the formation of the fixed axle pin joint. An additional polysilicon deposition is used in this design to decrease the surface area of the rotor that is in contact with the silicon substrate thereby decreasing the frictional forces thus requiring a lower operating potential. Other variations between the two designs is the dry etching of polysilicon and silicon dioxide used by Fan, Tai, and Muller and the wet etching process used at RIT.

53 Micromotors are driven by electrostatic forces induced between the stator and rotor poles.. When a positive potential is applied to one pole of the stator and an equal but opposite charge is applied to a stator pole 160 degrees with respect to the first stator pole, the respective applied potentials will induce an opposite charge on the rotor poles. The remaining stators are grounded. The applied potentials are then switched to the poles that were originally at ground potential and the initially charged stators are grounded. The electric field on the now charged stators will attract the opposite charge on the rotor poles causing the rotor to rotate towards the opposing charge.

The reticle design project of a micromotor that consists of a rotor and six stators, required five reticles patterned with circles. The rotor reticle was designed using a washer then projecting eight rectangles at 45 degrees around the outer edge of the washer to create the rotor poles. The stators and contact pads were imaged in the same manor as the rotor poles.

The integrated circuit layout software program (ICE) used at RIT, is incapable of generating circles of sufficient resolution for implementation in the micromotor’ project. ICE also is incapable of orientating rectangles at any other angle than 90 degrees. This lead to the necessity of developing computer programs that would generate M~~NN files that would overcome some of the limitations of ICE.

THEORY

Design of the reticles must be realizable with RIT’s processing capabilities. The Fan-Tai-Muller motor [2], was produced utilizing the processing techniques of phosphosilicate glass (PSG) deposition and anisotropic dry etching of polysilicon and PBS. Since neither technique is currently available at RIT, substitute processes and their effects on the reticle designs, had to be considered, i.e. thermal oxidation and wet isotropic etching of polysilicon and silicon dioxide.

The etch rates of silicon dioxide and doped and undoped polysilicon along with the amount of silicon and polysilicon lost due to oxidation, must be considered in the reticle design. These etch rates must be measured and the reticle designed to compensate for the lateral losses of material due to the isotropic etching. The calculation of these losses will be extremely critical when attempting to resolve the 1.5 micron gap between the rotor and stator poles. This resolution will require strict control and uniformity of the thicknesses of the deposited polysilicon and thermally grown silicon dioxide films..

Cross sections of the micromotor along with diagrams of the reticles are shown in the appendix. As can be seen from these figures, the need for circular and rectangular features at arbitrary orientations on the mask, are essential for fabrication of the micromotor. Therefore special MANN files are required.

54 A MANN file contains instructions for the MANN Pattern Generator. These instructions control the carriage position of the pattern generator and the angle of the exposing tool. The exposing tool is capable of exposing a emulsion coated glass plate (reticle) with a series of rectangles. The pattern generator is capable of rotating its exposing tool between the angles of 0 and 89.9 degrees. This rotating capability of the pattern generator allows features other than rectangles to be manufactured.

The first computer program required for the design of a micromotor, needs to give instructions to the pattern generator to rotate a rectangle around its center to produce a circle. The width of the rectangle must be equal to the diameter of the circle. The height of the rectangle depends on the desired resolution of the reticle; the larger the height of the rectangle, the poorer the resolution of the circle edge. Once the height of the rectangle has been determined, the angle of rotation must be calculated. The angle of rotation (theta) is determined by the equation:

theta atan(2H/W) where H and W are the height and width of the rectangle respectively. The program must rotate the rectangle from 0 to 89.9 degrees. This will generate the first and third quadrants of the circle. The program must then exchange the H and W values and again rotate the rectangle from 0 to 69.9 degrees. This will generate the second and fourth quadrants of the circle. The output of the program must be written using the MANN file format. This can be accomplished by a series of format instructions.

The rotor of the micromotor requires two programs. The first program will generate a washer and the second produces the rotor poles, stators and contact pads. The washer is generated similar to the circle with the exception that the rectangle is rotated about the center of the reticle. A rectangle is chosen with the width equal to the diameter of the base of the washer. The height of the rectangle is again chosen for best resolution. The angle of rotation is different for the washer generation. This angle is determined by the equation:

theta atan(H/2W)

This program then rotates the rectangle in the same manner as the first program. The last program uses the inputed values of the rectangle height and width and will place the rectangles at any orientation and distance from the center of the reticle. Output from both files is in the MANN file format.

The computer programs were written and the MANN files generated. A problem that could not be resolved was the leaving of spaces in the MANN file when a value was less than the allowed

55 space. This was overcome by editing the MANN file and deleting the spaces.

Tapes containing the instructions for the pattern generator were made. These tapes were then run through the pattern generator in the edit mode to check for errors (this is why the rectangles are rotated to a maximum angle of 89.9 instead of 90 degrees). Once the errors were eliminated, the reticles were produced. Examination of the reticles revealed no apparent f laws.

A process for production of the micromotor was designed to use along with the reticles. The reticles were designed specifically for this process sheet. A change in the process will require a change in the reticles. With the micromotor computer programs a design change is not difficult.

SUMM~RV

Three computer programs were written with output in the MANN file format. These programs generate circles and washers and will place rectangles at any distance and orientation form the center of the reticle. Six reticles containing the micromotor subassemblies were produced.

A process for the building of the micromotor with the use of these masks has been completed. Etch rates for silicon dioxide and doped and undoped polysilicon have been determined and compensation for the loss of material has been accounted for in the reticle designs.

ACKNOWLEDGEMENTS

I would like to thank the following people for their assistance on the micromotor pro3ect: Dr.Lynn Fuller, Mike Jackson, Robert Pearson, and Kathy Hesler.

REFERENCES

[1] “Integrated Movable Micromechanical Structures for Sensors and Actuators”, Long—Sheng Fan, Yu-Chong Tai, and Richard S. Muller. IEEE Transactions on Electron Devices, Vol. 35, No. 6, June 88, page 724 [2] “MICROMACHINE”, R. Gannon, Popular Science, March 89, pg.88

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John P. Curcio 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

The Tegal 700 plasma etcher was used to etch trenches into four micron deep p-type diffused resistors to evaluate the quality of the electrical isolation. Etch times of nine and twelve minutes were used to etch trenches approximately 7.B and 11.5 microns respectively. Current flow was detected in all resistors, despite the fact that the trench should have resulted in open circuits. Theref ore, at this time, results are inconc lus ive.

INTRODUCTION

Silicon trench isolation has become the most favorable method of device isolation in the fabrication of YLSI devices. Prior to the use of trench isolation, devices were separated from one another by diffusing a junction between the devices and reverse-biasing the junction. This technique required large amounts of chip area due to the isotropy of the diffusion and the associated depletion regions [7].

Trench isolation provides a relatively simple method of device isolation which requires minimal “real estate”. ~ deep well, or trench, is etched through the epitaxial layer and into the substrate. If performed by a dry-etching technique, the minimum width of the trench is dictated by the lithographic process used. The trench is then filled with a CVD oxide in order to fill the trench and planarize the wafer surface [1].

One particular gaseous species used to produce a silicon plasma which etch is sulfur hexafluoride (SF6). The SF6 will form fluorine radicals upon the creation of a plasma, which will in turn react with silicon atoms at the surface of the wafer. The atoms will react to form SiF4, a volatile, non-reactive endproduct which is removed from the etching system. In addition, oxygen is added to the SF6 in order to tie up the sulfur in the system and form the product S02. Insufficient oxygen addition to the system will cause the formation of S(x)F(2x) complexes, which can deposit on the wafer surface, retarding the etch and destroying the wafer.

This experiment was performed to investigate the feasibility of isolating devices by creating trenches using the Tega]. 700 plasma etcher. t~ mask set and process was developed in order to electrically test the quality of the isolation. 61 EXPERIMENT

The etch rate of silicon masked with KTI-B20 photor’esist using a 3:1 SF~/02 plasma in the Tegal 700 single wafer plasma etcher was investigated. Flows of 10.0 and 3.3 sccm of sulfur hexafluoride and oxygen, respectively, were used. The etcher was tuned to minimize the reflected power, while yielding approximately 125 Watts of forward power. Etch times ranging from one to six minutes were investigated; however, it was found that the etch rate of the resist mask was very high. The experiment was then repeated on wafers on which 5000 angstroms of thermal oxide was grown to act as an etch stop. Etch times of six, nine, and twelve minutes were used in order to find an average silicon etch rate.

A process was developed with which to evaluate the effectiveness of the trench isolation. First, a test chip was designed on ICE (an internally-developed and maintained CAD tool) with which to perform the photolithographic steps. This mask contains three layers: diffusion, trench, contact cut, and metal. The trenches, ranging from zero to ten microns in length, were designed to completely separate the two ends of the diffusion. Testing would then reveal if the trench in fact did separate the two ends of the diffusion. The cross-sectional view of this structure is shown in Figure 1.

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Figure 1. Cross-section of trench etch test structure

Six n-type wafers were obtained and cleaned using a standard RCA clean. Next, an oxide was grown in order to mask the diffusion at 1100 degrees celsius for 45 minutes in a wet oxygen ambient. The first mask was used to image the wafer and etch the oxide in regions which were to be diffused. B150 spin-on dopant was then spun on the wafers, which were then placed in an 1100 degree furnace for 130 minutes in a nitrogen ambient, followed by 20 minutes in a dry oxygen atmosphere to assist in removal of the spin-on dopant layer. The oxide was then stripped.

A drive-in was performed for 120 minutes, also at 1100 degrees. A dry oxygen flow was used for the first 75 minutes, followed by 45 minutes in a wet oxygen ambient. The resulting was used as the etch stop for making the trenches. Windows were transferred into the oxide photolithographically using the second masking level (trench level).

62 The Tegal plasma etcher was then used to etch the trenches. ~ 10.0/3.3 sccm SF6/02 mixture was used, with a forward power of 125 Watts. The chamber pressure was 0.550 torr. Etch times of six, nine, and twelve minutes were used. The oxide mask was then removed, and the step heights measured on the ~lpha-Step. Finally, following visual inspection with an optical microscope, a HP4145 Semiconductor Parameter ~nalyzer was used to find the resistance of the test structures.

RE8ULTS/D~SCU9SION

The Pdpha-step profilometer was used to measure the depth of the trenches. Results of the initial studies shown in Figure 2 reveal a silicon etch rate of approximately 1.0 micron per minute while using the oxide mask. The oxide mask showed minimal damage from the SF~/D2 plasma, but the etch was not very anisotropic- the sidewalls appeared large and dark under dark field illumination. The groove and stain apparatus revealed that the junction depth of the diffusion was 4.04 microns. From this data, etch times of six, nine, and twelve minutes were selected for the experiment.

I I ETCH ETCH ETCH I I DEPTH TIME RP~TE I ID I (microns) I (minutes) I (u/mm) I

I TEST2 I 5.00 e.0 I 0.9333 I I D3 I 6.00 I 6.0 I 1.0000 I TEST1 7.40 I 9.0 I 0.8222 I I D6 I 8.00 9.0 I 0.8888 I D4 I 10.50 12.0 I 0.8750 I

Figure 2. Silicon etch rates using Si02 mask

The inspection of three of the six wafers revealed that the silicon in the etched areas was extremely discolored and grainy in appearance. The etch rates obtained agreed with those results from the previous study; however, it is apparent that there is a problem with the process. This discoloration appears to be the from the deposition of an S(x)F(2x) complex, caused by an insufficient amount of oxygen in the system. It should be noted that only the first three wafers exhibited this problem; this reveals the need to run many “dummy” wafers through the system before performing the etch on product wafers.

The resistors with zero, five, and ten micron trenches were compared using the HP4145 parameter analyzer. From the graphs in Figure 3, it can be seen that the etches did not open-circuit the devices, as significant current flow was measured. It is easily seen, however, that there is an increase in resistance as the 63 + ****** GRAPHICS PLOT ****** ****** GRAPHICS PLOT ****** TRENCH WIDTH 0.0 TRENCH WIDTH 0.0 12 12 (mA) (mA)

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(a) (b) Figure 3. Resistance of trenches versus trench length (a) Wafer D6 (9 minute etch); (b) Wafer D4 (12 minute etch)

64 trench width increases. The trench depth has been measured to be more than twice as deep as the diffusion, meaning that there must be some mechanism which allows for current flow through or around the channel. The high-energy ions created in the etch plasma may cause lattice dislocations at the bottom of the trench, which could allow current to flow around the trench. It would be worthwhile to investigate this possibility; one method of repairing such damage would be a high-temperature anneal following etching of the trench.

Wafer 06, which was etched for nine minutes, shows the same trends as wafer 04, which received a twelve minute etch. This leads to the conclusion that the time of the etch is not much of a factor in the isolation; in other words, for trenches less than ten microns in length, the etch will be limited by the width of the trench. In addition, through a conventional microscope, the etch appeared to be almost totally isotropic.

CONCLUSIONS

There are many areas in which this experiment may be improved. The absolute thicknesses measured on the ~lpha-Step profilometer have been shown to be inaccurate in previous work, but no other device is available to measure the trench depths. It would also be possible to perform scanning electron microscopy to evaluate the trench depth, as well as the degree of isotropy, but the SEM in the lab was not in functional order.

Furthermore, a true trench etching process involves the backfilling of the trench with a CYD oxide. When CYD capabilities are implemented at RIT further processing, using the same mask set, can be performed, including the use of metal contacts. It should be noted that the mask set designed on ICE can be used to implement this.

One further enhancement would be the use of a different style plasma etcher. The Tegal 700 is a single wafer, relatively low power etcher, while the use of a triode etcher or high-powered etcher is recommended [1,2].

ACKNOWL EDGMENTS

I wish to express my gratitude to Mr. Bruce Smith and Dr. Richard Lane for their assistance and expertise in the plasma etching area, Mr. Michael Jackson for his continued support, and Scott Blondell for his assistance with the “temperamental” Tegal 700 plasma etcher.

65 [1] M. ~meen, M. Monfils, and 2. Hasan, ‘Silicon Trench Etching Made Easy’, Semiconductor International, September 1968, pp. 122-128

[2] R. Carlile, V. Liang, and M. Smadi, “High Quality Trench Etches in Silicon”, Solid State Technology, ~pril 1989, pp.1 19-123

[3] ~. Esquivel, A. Mitchell, 3. Paterson, M. Douglas, M. Gill, H. Tigelaar, B. Riemenschneider, T. Coffman, R. Lahiry, D. McElroy, and P. Shah, “A Novel Trench Isolated Buried N+ FAMOS Transistor Suitable for High Density EPROM’s”, IEEE Electron Device Letters, Vol. EDL-8, No. 4, April 1987, pp. 146,147.

[4] R. Lane, Personal conference, 9 May 1989.

[5] 3. Mucha, “The Gases of Plasma Etching: Silicon-Based Technology”, Solid State Technology, March 1985, pp. 123-127.

[6] M. Pons, P. Delpech, A. Schlitz, and A. Inard, “Mini- Trench Isolation: Trench Etching, Oxidation, and Refilling Planarization”, Microelectronic Engineering, May 1986, pp. 403,404.

[7] H. Pogge, “The Spaces Between the Functions on a Chip”, Chemtech, March 1986, pp. 168-173.

66 Characterization of a New E-Bearn Resist Brian Fetzer 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

Waycoat HEBR-214 Positive E-bearn resist was characterized for coating properties, thickness vs. dose, and thickness vs. development time. For a thickness of .5 urn, resist sensitivity was 65 uC/crn2 for a 2 minute develop, and 20 uC/cm2 for a 4 minute develop. Contrast was 6.28, which promises good resolution. Dry etch selectivity of the resist over oxide and over poly-silicon was attempted, but poor results were obtained.

INTRODUCT ION

As lithography tolerances, linewidth and registration, continue to decrease, electron beam (E—beam) exposure systems will become increasingly popular in direct write applications while maintaining it’s dominance in maskmaking. E-beam systems exhibit better registration, due to the maskless nature of exposure, and they have better resolution than UV systems since E-beams aren’t diffraction limited. There are, however, problems that exist in current E-beam technology which limit their practicality in a manufacturing environment. Included among these are the high cost of the system itself, lower throughput than UV systems, and image transfer limitations. The image transfer limitations occur because smaller critical dimensions require an anisotropic (RIE) etch, and traditional E-beam resists have demonstrated little dry etch resistance. The low throughput in E-beam systems is a result of the slow, direct write mechanism employed for exposure, but can be improved by using a more sensitive resist. A MEBES system has recently been donated to RIT, so the need exists to characterize the resist(s) that will be used in the system.

Currently, some negative e-beam resists exhibit dry etch resistance, but negative resists suffer from other problems, mainly that of image swelling and the need for organic solvents. In most negative resists, exposure yields an insoluble cross-linked polymer. The swelling occurs in the process of dissolving the unexposed polymer, as the solvent penetrates the exposed area and is unable to escape, resulting in swelling. The main problem with organic solvents are that they are a safety hazard and require special disposal procedures. An aqueous base developer would solve many of these problems.

67 Olin-Hunt has manufactured Waycoat HEBR-214. Information about the chemical structure of the photoactive component in this resist has not yet been released because it remains proprietary information. It is known that it is a novolak based resist that is developable in an aqueous base. This is very similar to the NQD-novolak resist formulation that is common in industry. Because of these similarities, the chemistry involved in the exposure of NQD will be discussed with the assumption that it is similar to this E-beam resist. The NQD-novolak mixture begins as a dissolution inhibitor in aqueous base. Upon exposure to a wavelength of light the resist is sensitive to, nitrogen gas(N2) is evolved from the photoactive component(N~D). For NQD-novolak systems, Wolff rearrangement occurs, which gives a ketene. The ketene reacts with water to give an indene carboxylic acid, which is a dissolution accelerator in an aqueous base.

Characterizing a resist includes finding the relationships between resist thickness vs. exposure as well as resist thickness vs. development time for a given coating thickness. The best way to find these relationships is to develop thickness versus develop time curves for each exposure dose. Once these curves are done, a dose versus development curve may be created, as well as characteristic curves. From a characteristic curves, resist sensitivity as well as contrast may be found.

A final important parameter that needs to be found is that of dry etch selectivity to both oxide and poly-silicon. This is important because resolution of the etched image is not only a function of resolution of the resist, but also of the image transfer capabilities. Therefore, to obtain vertical sidewalls and maximum image transfer, dry etching must be used. Therefore, the resist must not only have good resolution capabilities, it must also offer good dry etch resistance so t”at the developed image doesn’t wash out while undergoing dry etch.

E ~ ME N~T Before characterization can be done, the wafers must be prepared, which, for this experiment included scrubbing and cleaning the wafers in APM and HPM. About 5000 A of oxide was then grown, which completes the preparation.

To obtain coating characteristics, HMDS was spun on all wafers at 5000 RPM for 30 seconds, followed by the desired spin speed for 30 seconds. The spin speeds tested were 3000,4000,4300,4600,4900,5000,6000 RPM. The spinner was calibrated at each point using the strobe light. After each spin, a softbake was done at 100 C for 30 minutes, then resist thickness was measured on the Nanospec using program 11 (positive resist on Si02).

A wafer was coated with HMDS and then resist at 4500 RPM, then softbaked for 20 minutes. The wafer was then cleaved into squares, which were mounted onto SEM sample holders, and baked

68 another 10 minutes at 100 C. Beam current was measured using a Faraday cup , and the area scanned was measured using the stage micrometer, and from these scan time was calculated for each dose. Samples were placed in the Cambridge SEM and scanned for the appropriate time, with 3 identical doses per sample being exposed. Exposure was done on the SEM at a potential of 25 KeV, a magnification of 200, and the third largest spot size. Doses exposed were 10,20,30,40,50,60,80 uC/cm2. The samples were each developed in Waycoat LSI developer until an image appeared, at which time the sample was rinsed, dried and measured. Then another development step was done for 30 seconds (followed by a rinse,dry, measurement), and these steps were continued until the resist cleared.

The samples were then hard-baked for 20 minutes at 110 C, then mounted to a wafer with silver paint, then baked for 10 more minutes at 110 C. Resist , oxide, and polysilicon thicknesses were measured on the Nanospec using existing programs. The samples were then etched in the Tegal 700 for 1 minute in CHF3, followed by thickness measurements, and another etch. This continued until 10 minutes of etch time had been completed.

RESULTS/DISCUSSION

Figure 1 shows the thickness vs. spin speed data, and from the graph, it appears that a spin speed of about 4500 RPM will yield a .5um thick resist, which was the desired thickness.

Beam current in the Cambridge SEM was measured to be I:1.BnA/cm2 for a potential of 25 KeV,the third largest spot size, and a magnification of 200. The area scanned was measured to be .00452 cm2. From these numbers, and the desired dose, scan time was calculated, as shown beLow: Exposure Dose(uC/cm2) Scan Time(seconds) Time to Clear(sec)

10 25.1 20 50.2 228 30 75.3 204 40 100.0 188 50 125.5 165 60 150.6 135 80 200.8 113

Time to clear ranged from 228 seconds for a dose of 10 uC/cm2 down to 113 seconds for a dose of BO uC/cm2. No time to clear was found for the 10 uC/cm2 dose as, after 9 minutes of develop, no image had yet formed, so it is possible that this dose is not high enough to generate the photochemical reaction which acidifies the resist. Figure 2 is a plot of resist thickness vs. development time for each dose. This plot shows a few stray points, but the general trends do emerge. A plot of times to clear as a function of exposure dose can be seen in Figure 3, which shows an almost linear plot, as expected. By finding the thickness of each dose at a specific development

69 FLaure 1: SoLn Speed Curve ~ fl~ - E~5eam ResLst Woycoct HE3R214

0) C 0 L. C) E

0) 0) C)

0 £

5000 SpLn Speed (RPM)

Exposure Dose2O,3O,4O,SO,6O,80 uC/cm2 C C C CD

C —.0 C

0)~,. 0’)c

r)C 0) 0) C)0C.

0 -c

0 0.5 1 1.5 2 2.5 3 3.5 4 DeveLopment TUne (mLnutes) F~gure- -r -. ~r ~ 3:-rrrttat~trDose.~.rL~_rr~~flvs. TLmer,t~ ,, :rPtorr_~-~_CLear.- — EBeam ResLst Woycoat HEBR—214

DeveLopment TLme to CLear (seconds)

E~&~ ~ Ghcr,.c J~~ DeveLopment TLme2.O mLnutes

a) ci) a, C -~ 0(0 cc t-l -Da, N

C E C 0

23 100 Lo9 Exposure Dose (uC/cm2)

71 time, a characteristic curve (Figure 4) can be made, which shows a sensitivity of 65 uC/cm2 for a 2 minutes develop, and contrast calculated from this curve was 6.28.

The dry etch selectivity portion was unsuccessful, as the resist etched away within 2 minutes in CHF3, and neither the oxide or polysilicon had begun to etch after 10 minutes of etch time, so there was definitely a problem with the Tegal or my operation of the etcher. A possible cause to these problems would be if oxygen was in the etch chamber, or it could be polymer build up causing the oxide and poly to resist the etch.

CONCLLJS~ONS

From this project, many favorable resist parameters were found. First, the resist showed excellent coating characteristics, as no problems with adhesion or nonuniformity were found. The resist showed a sensitivity of 65 uC/cm2 for a 2 minute develop, and a sensitivity of 20 uC/cm2 for a 4 minute develop. A contrast of 6.28 was found for a minute develop, which should lead to high resolution capabilities. The resist showed poor selectivity to both oxide and polysilicon, but this must have been a problem with the etch process, and not the resist itself.

ACKNOWLEDGEMENTS

I would like to thank Bruce Smith for his help in obtaining the resist materials and for his recommendations. I would also like to thank Scott Blondell for his work on the SEM, and finally I would like to thank Mike Jackson for his help and advice in the presentation of the project and paper.

RE!~ENCES

[1] Bowden,Thompson,FahrenhOltZ, and Doerries,”A Sensitive Novolac-Based Positive Electron Resist”. Journal of the Electrochemical Society, Vol.128, no.6 June 1981 pp 1304-13

[2] Chang,Kyser and Ting.”Resolution and Linewidth Tolerances in Electron Beam and Optical Projection Lithography”. IEEE Trans. on Electron Devices, voi..ED-28,no.11 November 1981. pp 1295-9.

[3] Thompson,Wilson and Bowden.’IntroductiOn to Microlithography’. American Chemical Society, Washington, D.C. 1983.

[4] Olin-Hunt Data Release on Waycoat HEBR-214 positive electron beam resists.

72 CHARACTERIZATION OF A SILICON NITRIDE PLASNA ETCH: SELECTIVITIES AND UNIFORNITY

James H. Gardner 5th year Nicroelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

A silicon nitride plasma etch process with good nitride-to-oxide selectivity has been developed at RIT. Two fluorine etchant gases, CF4 and SF6, were characterized for etch rate and selectivities, and the effects of oxygen and hydrogen loading determined. It was found that the $~b stoh provided a selectivity of 6:1 (with a nitride etch rate of about 700 A/minute) when no loading was applied. The 3:1 CF4:02 etch demonstrated a comparable nitride etch rate, but with a poorer selectivity (about 5:2). The uniformity of the Tegal 700 plasma etching system was deterined to be the limiting factor during the etch.

INTRODUCTION Silicon nitride (Si3N4) is a CVD film commonly used in the VLSI industry as a masking material for the localized oxidation of silicon (LOCOS). The nitride prevents the diffusion of oxygen to the silicon surface and any subsequent oxide growth. LOCOS has become the most common isolation technique because it reduces surface topography considerably with a minimum amount of process difficulty. A simplified LOCOS isolation process is shown in Figure 1. To protect the underlying silicon substrate from the nitride etch, a thin pad oxide (A) is grown before the nitride deposition to serve as an etch-stop. If the silicon substrate is exposed to the etch, surface defects and poor thermal oxides may result. To decrease the effect of the bird’s beak encroachment (B) and allow for a higher packing density of devices, it has become necessary to use thinner pad oxides under the nitride [1). This dictates the need for a high nitride-to-oxide selectivity to protect the underlying silicon.

The chemistry involved with the plasma etching of nitrides and oxides is now discussed. Freon 14 (CF4) will be used as an example, but the etching mechanisms of SF6 plasmas are analogous. The dissociation of the fluorocarbon CF4 can be summarized by the following equation, e+CF4--->CF3+F+e (1)

73 Figure ii Schematic representation of a simplified LOCOS process and the resulting TMBird’s BeakN encroachment.

where e represents an electron and F is the free fluorine radical. At the electron energies encountered in typical glow discharges, the above reaction does not proceed directly but by the following 2-step mechanism (2].

e + CF4 ---> CF3 + F- :dissociative attachment

e •e F- ---) F + 2e :(rapid) detachment

It has been shown that the F radical is the primary etchant of silicon, while the CP3 radical is most responsible for the etching of Si02 and Si3N4 [3]. The basic chemistries involved in the etching of oxide and nitride can be described by the following unbalanced equations. These are the chemical reactions which occur when oxide and nitride are exposed to a CF4 plasma.

CF3 + Si02 ---> SiF4 + CO,C02 (2)

CF3 + Si3N4 ---> SiF4 + CFN (3)

All the products are volatile allowing both reactions to proceed readily. The problem of acquiring a high nitride-to-oxide selectivity results from the similarity of the two etch chemistries.

74 The etch rates of silicon based materials have been found to depend on the carbon-to-fluorine (C/F) ratio of a fluorocarbon plasma [4]. To adjust the C/F ratio of a plasma, fluorine promoters or scavengers are added to the process chemistry to increase or decrease the fluorine radical concentration. Efficient scavengers of F atoms in a plasma include H2, CH4, and C2H4. The addition of the hydrogen ties up some of the available F producing HF and decreasing the F concentration. CHF3 has also been used to decrease the F concentration in an etch. Oxygen is the most common F promoter, reacting with the carbon to produce CO or C02 and increasing the F concentration. The C/F ratio is often used to describe the composition of a fluorocarbon plasma. The addition of a scavenger to a CF4 plasma increases the C/F ratio, while oxygen loading results in a decrease in the C/F ratio. Since a fluorine-deficient plasma provides a high oxide-to-silicon selectivity, a high C/F ratio plasma is often used to etch oxides and nitrides in case the substrate happens to be exposed during the etch. However, if too much fluorine is removed, carbon deposits or polymers may form on the wafer surface preventing further etching [2]. For this reason, most oxide and nitride etches operate close to the etching/polymerization borderline, creating difficult process control. The new NMOS and CMOS technologies presently being introduced into the RIT microelectronics facility will utilize a LOCOS process for the initial field oxidation. Therefore, the optimization of a nitride etch process with high nitride-to-oxide selectivity has become a necessity.

A Tegal 700 series plasma etcher (a single wafer etcher with a shower-head gas delivery system) was utilized for this experiment. Gas flows were controlled using two NKS mass flow controllers and an I4KS 247B Digital Readout. From previous experiments, the acceptable total gas flow for the Tegal 700 was found to be about 15 sccm [5]. This flow was used for each of the gases and gas mixtures to determine the etch uniformity and select ivities. Several wafers were prepared with alternating lines of nitride and oxide, cross-hatched with lines of KTI-820 positive photoresist as shown in Figure 2. This allowed for the etch rates of all three materials to be determined simultaneously. The initial thicknesses were determined by standard Nanospec measurement programs and found to be approximately 1000A, 900A, and 1.2um for the nitride, oxide and resist, respectively. Table 1 gives the etch parameters used throughout the experiment.

75 ~m z~x~

Figure 2s Wafer layout used for the experiment.

I Table 1: Etch parameters I I I Total Gas Flow 15 sccm I I Chamber Pressure 650 liT I I RF Power 125W I I EtchTime 30 sec I

The uniformity of the etch was determined by Nanospec measurement of each material at each point on the wafer before and after a CF4 etch. To measure the nitride—to-oxide selectivity of various gas combinations, five points were measured on each wafer before and after etch and an average etch rate calculated. The gases and gas mixtures used were CF4, CF4/02 (2:1,3:1), CF4/CHF3 (2:1,3:1), SF6, SF6/02 (2:1,3:1), and SF6/CHF3 (3:1).

RESULTS/DISCUSSI ON Figure 3 shows a wafer map of etch rates across a wafer and the calculated uniformity [8]. The poor uniformity (52% variation across the wafer) is most likely due to chamber leaks or an uneven gas delivery. The lack of uniformity necessitates the need for a nitride etch with good nitride-to-oxide selectivity and should be improved to ensure process stability.

76 - z 100% - 32%

Figure 3: Wafer map of etch rates measured across a wafer. Average etch rates for straight CF4 and SF6 plasmas were determined as given in Table 2. From these rates, the nitride-to-oxide selectivities were calculated by the following equation. Nitride/Oxide Nitride Etch Rate Selectivity = (4) • Oxide Etch Rate

It was determined that the SF6 etch provided better selectivity than the CP4 etch with comparable etch rates. The selectivity of the SF6 plasma was almost 3 times better than the CF4. The following table provides the etch rates and selectivities obtained.

table 2: Etch Rates and Selectivities for CP4 and SF6

I Parameter I CF4 I SF6 I I I I Nitride I I Etch Rate I 645 I 730 I I (A/mm) I I I I Oxide I I I Etch Rate I 313 I 125 I (A/mm) I I I I I Nitride/Oxide I I I I Selectivity I 2.1 I 5.9 I

77 ...... ~.

The average etch rates and selectivities for each combination of gases were also determined. Figures 4 and S summarize the resulting etch rates and selectivities.

FiO~a. 4: ~ Etch J~t.. va LadinG

— I I I I I I

Inc Cl)’ ratio —> I..

a S A A 1. I .0 CA a H/ C N — .1 T RI I AN .0 I I A

C— inc 02 inc D~3 —~

I I I I (2: 12:2) 02 ~4 02 LOADING

FiG.r. 2: •FG Etch ~t.. ~I LaNding

CA H/ N NI AN 1~ A

LOADING —a— NITRIDE ETCH RATE OXIDE ETCH RATE NO LOADING —a---- NITRIDE/OXIDE ~LECTIYITY

Increasing the C/F ratio decreased both the nitride and oxide etch rates for the CF4 etch chemistry as expected. This is probably due to polymer formation on the wafer’s surface. The nitride-to-oxide selectivity was observed to increase slightly with the addition of CHF3 to the process, but the best selectivity (about 5:2) occurred with a [3:1] CF4/02 mixture.

An interesting result was observed when CHF3 was added to the SF6 etch in a 3:1 mixture. Although the total concentration of available fluorine in the plasma should have decreased, both nitride and oxide etch rates were found to have increased substantially. This result is difficult to explain without an extensive amount of additional materials and research, but clearly warrants further investigation. The use of spectral monitoring of the plasma or a residual gas analyzer would be beneficial in further understanding the mechanisms involved.

78 CONCLUSIONS

This experiment provided valuable ipformation on the limitations of the Tegal 700 plasma etcher presently being used at RIT. A uniformity variation of 52% across the wafer is extremely high and dictates the need for etch chemistries with high selectivities to the underlying substrates. The SF6 etch was found to provide a better nitride-to-oxide selectivity (6:1) than the CF4 etch (5:2). straight SF6 was found to provide the best selectivity of all the gases and gas combinations analyEed. This result has been substantiated by previous experiments where superior nitride-to-oxide selectivity has been observed with SF6 chemistries [1,7].

[1] N. Hayasaka, H. Okano, Y. Horiike, “Highly Selective Etching of Si3N4 Over 5i02 Employing a Downstream Type Reactor,” Solid State Technology, p127-130, April 1988

[2] S.P.Venkatesafl, I.Trachtenberg, T.F.Edgar, “Effect of Flow Direction on Etch Uniformity in Parallel-Plate (Radial Flow) Isothermal Plasma Reactors,” J.Electrochem. Soc., p3194, December 1987

[3] J.A. Mucha, “The Gases of Plasma Etching: Silicon-Based Technology,” Solid State Technology, p123-7, March 1985

[4] P.H.Sheir, “Dry Etching of Si02 and Si3N4,” Semiconductor International, p98-103, Nay 1986

[5] Previous work performed by Dr. R. Lane, RIT Microelectronic Engineering Faculty, Rochester Institute of Technology, One Lomb Memorial Drive, Rochester, NY 14623

[6] Aaron D. Weiss, “Plasma Etching of Oxides and Nitrides,” Semiconductor International, p56-62, February 1983

[7] W. Beinvogl, H.R. Deppe, R. Stokan, B. Hasler, “Plasma Etching of Polysilicon and Si3N4 in SF6 with Some Impact on MOS Device Characteristics,” IEEE Transactions on Electron Devices, Vol. ED-28 No.11, p1332-7, November 1981

[8] CJ.Nullins, “Plasma Etchers: Design and Performance,” Microelectronic Manufacturing and Testing, p1,13-16, Vol.9 No.7, June 1986

79 DETERMINATION OF CARRIER LIFETIME FROM MOS CAPACITORS

Kevin R. Gratzer 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

MOS Capacitors were used to determine minority carrier lifetimes by obtaining capacitance vs time data (C-U. A test system, utilizing an IBM PC as the driver for a Princeton Applied Research model 410 C-v plotter, Kiethley programmable power supply, and HP4145 parameter analyzer, was built to obtain the C-t data. The data can then be down-loaded to the VAX mainframe computer and analyzed by various FORTRAN programs, using analytical techniques developed by people such as, Zerbst, Schroder and Guldberg, Heiman, and others.

INTRODUCTION

The determination of carrier lifetime in the bulk of a semiconductor is often desirable to determine electrical properties in a transistor, and may be influenced by fabrication conditions. Many methods have been investigated to determine recombination/generation lifetimes in semiconductor materials. Several of these techniques include, Photoconductive Decay, Spectral Response, Microwave Reflection, Optical modulation, Electron Beam Induced Current, Open circuit voltage decay, pulsed MOB capacitor, and reversed biased diode [1].

Each technique exhibits advantages and disadvantages relative to the others. Some techniques may require separate test wafers due to their complicated aspects of analysis or destructive nature. These methods however, may yield semiconductor parameters globally, meaning in the interior of the wafer. The more complex techniques often require special sophisticated (and often expensive) equipment. Since we are normally concerned with the properties of the active area of the device, we therefore concern ourself with generation properties in the volume under exterior control (gate control, Depletion width*gate area).

Although other techniques may prove to be more sensitive and non-destructive, pulsed MOB capacitor (MOB-C) methods still dominate generation lifetime measurement techniques in industry. One of several reasons for this popularity is the availability of commercial test equipment and software packages. Another reason is the relatively simple processing required for fabrication of a MOB-C, which often times can be easily integrated within device fabrication processes. Often times the MDS-C is used as a test structure or “Drop-infl structure in modern I.C fabrication industry.

Lifetimes are determined by pulsing the MOB-C into deep-depletion and monitoring the capacitance as it relaxes back to equilibrium. Initially the capacitor may be biased in accumulation, depletion, or inversion, as long as it is in equilibrium before being pulsed into deep-depletion. Figures 1 and 2 show typical high frequency C-V and C-t plots for a MDS-C.

A A Co —

B :; ~

FIGURE 1: C-v Curve FIGURE 2: C-t Curve

When pulsed from accumulation to deep-depletion the capacitance is driven from point A to B as shown in both Figures 1 and 2. Thermal generation will return the MOB-C back to equilibrium shown in the figures by paths B to C. The recovery time , sometimes referred to as storage time, is determined by the electron/hole pair generation properties of the semiconductor bulk, and by the gate oxide/semiconductor interface.

The minority carriers needed to create the charge in the inversion layer in a P1DB-C cannot be provided instantly. The carriers are provided by diffusion through the depletion layer from the quasi-neutral bulk or are generated in the depletion layer. If the gate voltage is sweep at a slow rate, relative to this generation or diffusion time, then the MOB-C will remain in equilibrium (at C(inv)) throughout this change. However if the MOS-C is pulsed into deep-depletion (i.e by a step voltage), minority carriers can not be generated quickly enough to satisfy the demand for inversion layer charge. In this case, the depletion layer width will increase to maintain overall charge neutrality, compensating the gate charge with ionized dopant ions until such time as sufficient minority carriers can be supplied to the area. When carriers are being supplied, the depletion layer width begins to return to it’s equilibrium value (C(inv)) t2]. The return back to equilibrium was shown by the paths B to C in Figures 1 and 2.

81 Zerbst related the change in depletion layer width, as the MOS-C returns back to equilibrium, to a change in inversion layer carrier density, which in turn is related to the carrier lifetimes. An approximation to Zerbst analysis was proposed and studied by Schroder and Guldberg in which they determined generation lifetime by the following equation £3].

Upon obtaining the transient response of the MDS-C (C-t), arid transferring the data to the VAX mainframe, the two analysis techniques will be investigated.

Figure 3 shows the set-up for obtaining C-t data:

FIGURE 3: SET-UP for obtaining C-k data.

The Princeton Applied Research model 410 c-v plotter was used in conjunction with a HP4145 parameter analyzer, Keithley model 230 Programmable power supply, and an IBM PC to obtain C-t curves for MDS-C’s. Modifications were. made the model 410 to allow for external synchronous control of the step voltage applied to the capacitor gate. This is achieved by turning the ‘LIFETIME’ switch to ‘ON’ position and selecting the gate ‘Start’ and ‘Stop’ limits on the 410. When a step voltage (via the Keithley 230) is applied to the 410 via the rear-panel ‘SWEEP INPUT’ connector, the MDS-C is pulsed from ‘Start’ to ‘Stop’ voltage instantaneously. The sweep input circuitry can be altered to allow control voltages between +1.0 and +1000.0 peak volts. This is achieved by changing an internal resistor according to manufactures specifications (refer to Appendix I). Thus the capacitance transient is monitored, in synchronicity

82 with the step input, via the HP4145, by connecting the V-axis output of the model 410 to an input channel on the HP4145.

The IBM PC is used as the remote controller of the HP4145 and the model 230 power supply via the IEEE4BB interface bus (Refer to appendix IV). A Microsoft BASIC software routine was written and automatically initializes, and programs these devices to obtain C-t data. The software is written in a menu format in which variables may be altered by the user by choosing the appropriate menu selection. Once a satisfactory C-t curve is obtained on the HP4145’s graphics display screen, the software menus allow data to be stored on disk. In this manner the HP4145 is used as an AID converter. The data file may then be transferred to the VAX mainframe (into users account) by using a software routine called KERMIT (Refer to Appendix II for transfer procedure).

This data transfer will allow the use of the VAX mainframe as the analysis tool. Carrier lifetime can be determined and compared with theoretical results, using Zerbst analysis, Schroder and Guldberg analysis, or any other technique. This system is a very powerful tool for parameter extraction and could be modified to do semi-automatic testing via IEEE48S interfacing.

RESULTS/P I SCUSS ION

Capacitance .vs. time plots were obtained using the set-up described in the previous section. Figures 4 and 5 show typical C-t plots obtained, and the Zerbst, and Schroder ~ Guldberg analysis on this data.

The C-t data was transferred to the VAX and analyzed using a FORTRAN program (CAP.FOR, Refer to Appendix III), which analyzed the data and reported the minority carrier lifetimes. The data was also analyzed using Mike Jackson’s Zerbst FORTRAN program, and the two techniques were compared.

TLrne (sec)

FIGURE 4i Capacitance .vs Tim. Data

83 ~erbst ~ia3ysia

0 ic d/dt(CowfCCt))a.2 a 0 a C a a a Co

—J.~ I I I 0.0 0.5 1.0 1.5 3.0 3.5

C1.nv!C(t) — I mnority Carrier U1etlae a 3.51 usec

FIGURE 5: Zerbst Analysis

Schroder ~c Guldberg Analysis: Minority Carrier Lifetime 3.17 usec

These two techniques yield very similar lifetimes as shown above (3.51 and 3.17 usec). Further investigation into minority carrier lifetimes using these techniques should be done to determine which is appropriate.

CONCLUSIDN

In this investigation, a method for determining minority carrier lifetimes was presented using software-driven equipment. This allowed data to be transferred to the VAX for analysis via two techniques. Both techniques proved to be effective and the calculated minority carrier lifetimes were very similar. The capability for determining minority carrier lifetimes now exists at RIT, and this technique can now be implemente.d in characterizing various future processes, such as CMOS.

ACKNOWL EDGEMENTS

I would like to thank John Connor for his assistance with programming using the IEEE4BB interface, and Mike Jackson for his suggestions with this investigation.

[1] D.K Schroder , Semiconductor Material and Device characterization. Arizona State University 1984/85

[2] Nicollian E.H., Brews J..R., MOS Physics and Technology John Wiley and Sons, Inc.,(19B2).

[3] D.K Schroder and J.Guldberg, Solid State Electronics, Vol 14, 1285 (1971)

84 SILYLATION OF POSITIVE PHOTORESIST

Donald R. Koszelak 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

The silylation of KTI Positive Resist 809 with hexamethyldisilazane(HMDS) was performed by liquid phase and vapor phase techniques. A vacuum chamber was designed and constructed for the vapor phase silylation. Process evaluation was performed by oxygen plasma etch rates of silylated exposed and unexposed resist which showed that the vapor phase technique did change etch rates while liquid phase did not.

INTRDDUCTION

The decreasing size of geometries in the fabrication of integrated circuits is stretching the limits of optical lithography and wet development of photoresist. In the past, multilayered resists extended optical lithography into the submicron range by decreasing such problems as standing waves and topography considerations. These multilayered systems are limited by the complexity of their processing. In order to obtain the desired resolution, each step of the multilayered process must stay under strict control. One way of obtaining a high resolution while minimizing the complexity of processing is to use a single or bilayer scheme in which the positive photoresist is silylated [1,2].

Silylation is the incorporation of silicon into the photoresist where the silicon reacts with the resin of novolac-based resists [3]. Conventional novolac based positive photoresist’s with low glass transition temperatures, Tg, are ideal for silylation. KTI Positive Resist 809 is excellent example of such a resist, whose low Tg aids in the diffusion of silicon. HexamethlydisilaZane (HMDS) is a good silylation source for this process.

Selective incorporation of silicon into the exposed regions of the resist layer is the basis of image formation in the silylation process. The silicon containing material diffuses much easier in the exposed resist than the unexposed, since exposure changes the resist’s chemical compound into a photoproduced acid [4]. This exposed area increase the incorporation of silicon, thus allowing selective diffusion to take place. Increasing temperature reduces the matrix of the exposed resist even more, again aiding the diffusion of silicon. However, the temperature must stay below Tg to prevent the resist from flowing.

85 The silicon that is in the top layer of the exposed resist reacts with oxygen to create a thin silicon dioxide layer during plasma ashing. It is this thin layer that acts as an etch mask when exposed to an oxygen plasma. This exposed resist etches slower than the unexposed, giving an image after dry development.

Positive or negative tone patterns can be obtained using a single or bilayered resist, respectively. For negative tone, a single layer resist is used. This occurs by exposing the resist, silylating, then dry etching. Figure 1 shows cross sections of this process. Positive tone can be obtained by using a bilayered system. This is done by first putting down a planarization layer that will not silylate, such as a hard baked positive photoresist with a high Tg. Next, a thin layer of the soft resist is exposed and wet developed to produce a positive image. This pattern is then flood exposed, silylated, and put in an oxygen plasma. This process is known as the SABRE process £2], which can be seen in Figure 2.

~TI bO~ bESIST (TI II~ ~SI$T $102 lISTS STI $25

Fl..r. II 11gw. 2.

FL~E~PIStI — • $102 I ______

SILTLRTED flgur. 2b riwos~o flper. lb RESIST ~

/ Ilgur. Zr flp.r. IC 2 Pt~lI

HZ PLISMA W~F W ~.W.’ ZfZ fiW ~‘W ‘,‘~/~ ETCH

flg.r. Ii Hl~ur. I FI3ura 2 1*.gl. ,.g.r ..pn. .n~i.t.a r.sist pre.ss •..bI. l.g.r a.g.tb. .~g$.t.d wsi;t pr.c..s

This project involved the design of a system to provide conditions so that vapor phase silylation could occur. The main concern of the vacuum chamber was to remove all oxygen out of the heated chamber before HMtJS was introduced. This is a concern because HMDS may combust in an oxygen ambient at elevated temperatures.

IXPi~ZMtN!

Figure 3 shows the basic vacuum chamber that was built for the vapor phase silylation. The main components needed were a roughing pump, used to evacuate the oxygen from the chamber before the HMDS was introduced, a hotplate, used to heat the surface of the wafer to the desired temperature, and an Omega ~Type—J” thermocouple, used to measure the temperature.

‘94€S i~( - ~ we

/ t_~.J*

Figure 3 VACUUM CHAMBER ASSEMBLY

The construction of the system was very important for this project. The chamber was made of 4” PVC tubing with two screw in endcaps so that it could be sealed. One endcap was cemented while the other had an 0—ring to help seal the chamber. A nitrogen purge line and HMDS line were attached to the chamber along with the vacuum hose. Nitrogen was bubbled through the .HMDS to allow HMDS vapors to enter the chamber. The tubbing going from the chamber to the roughing pump was immersed in liquid nitrogen to act as a cold trap for the unused HMDS.

KTI Positive Resist 809 was the resist used for both liquid and vapor phase techniques. The resist was coated with the 809 resist on about 5000 angstroms of oxide for a thickness of about 1.0 microns. Table 1 shows the process conditions for the wafers used.

Table 1 : Processing Steps

I Spin coat HMDS (33~ in Freon) 5000 rpm 20 sec I I Spin coat 809 (35~ solids) 6000 rpm 30 sec I I Hot plate bake 90 C 60 sec I I Expose half the wafer lOOmJ/cm2 I Silyiate liquid or vapor phase Etch in oxygen plasma

The liquid phase silylation was done by the steps followed in Table 2, With HMDS diluted in freon to give concentrations of HMDS of 33~ and 3.3~.

87 Table 2 : Liquid Phase Silylation Process

I Expose half the wafer 100m3/cm2 I I Heat wafer 70 C I Heat HMDS 70 C I I Expose liquid HMDS to wafers 3 mm I I Rinse in DI water I

The vapor phase was done for substrate temperatures of 75, 90, and 105 C. These process steps can be found in Table 3.

Table 3 : Vapor Phase Silylation Process

I Expose half the wafer lOOmJ/cm2 I I Heat wafer to temperature I Pump down to below 1000 microns I I N2 purge I I Pump down to below 1000 microns I N2 purge I Pump down to below 1000 microns I I Fill chamber with HMDS vapor 5 mm I pump down to below 1000 microns I I N2 purge I

The etch rates were studied for both the liquid and vapor phase techniques. This was done by measuring the exposed and unexposed regions prior to the etch. The etch was then done in the Tegal Plasmaline for 5 minutes. Again the exposed and unexposed regions were measured after the etch and etch rates for each were found.

RESULTS/DISCUSSION

The number of results obtained in this experiment are limited because a large amount of time was spent in the design and construction of the vacuum chamber for the vapor phase silylation. Only the single layer reverse image was looked at through while the double layer positive image was ignored. The number of experiments done on the single layer for both techniques are small do to the lack of time.

The results obtained in the liquid phase silylation were not noticeable. For both the 33~ and 3.3~ HMDS in freon, no difference in etch rates in the oxygen plasma were found. The only evidence of silylation was a slight image seen on the wafer after silylation took place.

In using the vapor phase silylation method, results were obtained for three wafers which had different temperatures. After the silylation took place, a visible image was noted on the wafer. The wafers were then etched and the results from this part can be found in Table 4. These were all done for silylation times of 5 minutes.

88 Table 4 Vapor Phase Silylation Etch Rate Results

I TEMPERATURE ETCH RATE ETCH RATE SELECTIVITY I I DEGREES C UNEXPOSED EXPOSED UNEXP/EXP I I ANGS/MIN ANGS/MIN I I 75 C 664 556 1.19 I I 90 C 583 424 1.38 I 105 C 596 521 1.15 I

The results obtained in this experiment are not great, but they are a start for dry development at RIT. A few reasons that might explain the bad results obtained are given. First of all, the measurements taken of the resist after silylation may not be correct. This is because the small silicon dioxide layer on top of the resist changes the index of refraction and thus the true thickness. Another problem is that there may be a lack of HMDS vapors entering the chamber. Perhaps the design of a better bubbling system would help this problem.

SUMMARY

The effects of post exposure silylation on KTI Positive Photoresist 809 were studied for liquid and vapor phase techniques. It was found that the vapor phase does decrease the etch rate in an oxygen plasma of the exposed slightly, while the liquid phase had no apparent effect. For better results, adjusting the silylation time and temperature could be tried for a future project, since the vacuum chamber is already built. Also in the future, imaging of lines and spaces may be attempted and look how well the resist mask holds up under actual etch processes.

ACKNOWLEDGEMENTS

I would like to thank Scott Blondell, Mike Jackson, Dr. Daly and especially Gary Runkle, in assisting me in designing and building the vacuum chamber.

REFERENCES

(1) Coopmans, Roland, and Lombaerts. “Effects of Silylation Parameters on the Lithographic Performance of the DESIRE System”. Microelectronic Engineering 5. (1986) 291-297.

(2) McColgin, Daly, Jech, and Burst. “Silicon-added bilayer resist (SABRE) system”. SPIE Proceedings, 820, 1988.

(3) Visser, Schellekens, Reuman-Huisken and van Ijzendoorn. “Mechanism and Kinetics of Silylation of Resist Layers from the Gas Phase”. Proceedings of SPIE 1987.

(4) Bailey, Daly, Brust, and Pearson. “Silicon Containing Polymers and Organo-Silicon Chemistries for Microelectronics”. Polymers for Advanced Technologies,1987.

89 E1.ECTROMIGRATION TESTIN3 OF ALUMINUM INTERCONNECTS

David Lam 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

Pure evaporated aluminum interconnects on a flat surface and over topography were sub3ected to high current densities of 8e5 A/cm2 and measured for Electromigration induced failure times. An electromigration test station was built and used for obtaining Mean Time to Failure, MTTF, data. A rapid statistical approach, where multiple interconnects under the identical conditions could be tested, was utilized to determine that the MTTF was lower for interconnects over topography versus flat surfaces.

I NTRDDUCT ION

The never ending push towards ultra large scale integration has placed a critical concern on the increasing number of metallization failures caused by Electromigration induced voids and subsequent open circuits. It is obvious that the smaller the geometry the smaller the voids necessary to cause electrical failure. Increased current densities, which tend to-decrease reliability, will ultimately set a limit on current carrying capabilities of interconnections.

Electromigration is the transport of mass in metal interconnects stressed by high current densities which results in pile up in some regions and void formation in others. The migration of metal ion is likely to occur at grain boundaries, where the interconnect structure is weak due impurity and dislocation defects El]. Figure 1 depicts metal ion imposed by two forces during current flow. The first is the field force, Fl, directed towards the negative terminal. The second force, F2, is the result of the exchange of momentum from the electrons, due to the applied electric field, to the metal ions. The result of F2 is known as the electron wind effect [2]. The region where the metal ions leave acts as the site of void nucleatiom which can consequently become large enough to sever an interconnect. —v

• • -~ ______F • c~~- _____. • .

. tiectron C~uctor C

Figure 1: Forces on Metal Ion

Since void accumulation during electromigration typically occurs at grain boundaries, induced failures will preferentially occur at steps over topography or into contacts due to increased number of grain boundaries created by the steps [3]. The average grain size is smaller in and around the vicinity of steps. This may be due to the nature of thin film formation. A metal ion will travel until it is stopped by a corner or a wall. Consequently, corners have high binding energy and thus tend to be the preferred site of nucleation. As the thin film grows on either side of the corner, different orientation usually are produced and grain boundaries are formed. As a result the periphery of the contact will be the region of many boundaries, in other words small grain sizes. The net result is a shorter lifetime for metal interconnects over topography [4].

A typical method of increasing the life time of metal interconnects, used in the industry, is the use of aluminum/copper materials. The amount of .1~ copper is sufficient enough to act as a trap for excess vacancies. The bonded copper and vacancy remain fixed at an arbitrary site thereby decreasing the rate of void formation[4]. Deposition conditions also play a role in reducing electromigration. Metals deposited by a high rate magnetron sputtering cathode exhibited a more narrow distribution of grain sizes [5]. Annealing metals can increase lifetimes by causing the agglomeration of grains, which decreases the total number of grain boundaries. The net result is a decrease in resistance and regions of possible void nucleation. Final passivation has also been observed to reduce electromigration induced failures by confining the mobility of vacancy diffusion.

The test station used for the acquisition of electr’omigration data utilized the hardware interface board developed by Helen Marz [6]. The interface board allows a simple custom test program to execute the necessary functions. The electromigration test station was designed to hold a fixed potential across the probes and extract current versus time data at specified intervals. The test structure used was developed by C.V.Thompson and J.Cho [7]. The technique allows high volume testing of interconnect failure with deviation in time in a single test.

91 Figure 2 depicts a condensed version of th test structure used. The structure used consists of two contact pads on either side which are connected by 50 parallel, periodically spaced and l000um long lines. The structure used for this experiment dealt only with lum lines. The lines were originally patterned for 2um, but the A]. wet etch accounted for the lum undercutting.

Figure 2: Condensed Test Structure

The design of the structure allows the simultaneous testing of identical lines at the same conditions. By placing a constant voltage across the probes each line should experience the exact same flow of current. A current density of 8-10 e5 A/cm2 per line is necessary for electromigration effects to occur[5J. Since the total voltage is constant, the total resistance increases as the lines begin to fail. The total current increment caused by each line failure can be determined by dividing the number of lines into the initial total current monitored. The times at which the failures occur are recorded and used to determine the MTTF and deviation.

The purpose of this investigation was to determine the change of Mean Time to Failure due to Electromigration-ir~duced failures over topography compared to a flat surface. Secondly, the functionality of the data acquisition station will be tested in order to evaluate its reliability.

[!PE~R I ~

Four 3” p-type wafers were processed for this experiment. A thermal oxide was grown in dry ambient at 1050C, for 25mm, with a resultant thickness off 721.5A. Two of the four wafers were patterned into an array of 10 um wide lines and spaces, to create topography. The photolithography was performed by using the standard Wafertrac KTI 820 coating and developing and exposed on the GCA 4800 stepper. Finally, all four wafers were brought together, sent through the RCA cleaned, coated with 2400A of pure evaporated aluminum and patterned to form the desired test structures.

92 Fig~re 3t: Test Circuit

HP tnterface Cable

~Bii PC/XT

Figure 3b: Test System

Testing was done on the test station shown in Figure 3. The heated stage was manually controlled by the Model 410 high frequency C-V equipment. The functions of the Keithley.. voltage sources, digital rnultimeter, and matrix box were controlled by a simple custom program given in Appendix A, that was written for the IBM PC. Communication between the equipment utilized the Hewlett Packard Interface Bus, HPIB. Testing was performed on the heated chuck at 200C, with the voltage held fixed and the current density of 8e5 A/cm2 through the lum test structures. Current density was determined by dividing number of interconnects into the initial total current along with the individual area, thickness times width.

Current versus time data was acquired and transferred into the Vax system using Kermit where data files and plots were generated. The statistical package RS1 on the Vax, was used to calculate the mean and median times to failure along with the associated deviation. Plots were generated using RS1 and OISB.

93 RISULii/DSCUESZDN

Figure 4 and 5 are current versus time graphs plotted from data obtained through the electromigratioT~ test station. The testing over topography yielded an expected shorter lifetime for 100X failure. 1~ histogram for the time to failure for the two cases, shown in Figures 6 and 7, presents the frequency of failures per interval of time.

EL.ctr~LrotLon ~, a fLat. Surf~oc. 2 ft1 no .wl.&., no ~ Jl.~ 41a. 2 I~ b..

• IL_ (~.) TLno (b.)

Figure 4 Figure 5

Histogram of TIt4E_TOJAILURE Histogram of TIMEJOJAILURE F F r to S ~~1 a q ci F U F’ U a a I.’ r1 I n ‘ ‘ i C r1 C I 4 a 0 1 • S 7 a y

Figure 6: Topography Figure 7: Flat Surface ?i~ (vs) ~zieb1e net Top. ~iI1.

8.$1 S. 19 2.12 8.Ie 3.14 2.24

STDET 1.11 1.21 0.10

1~b1. i~ Ti-s To Ti1~2T.

Means, medians, and standard deviations, STDEV, were determined by using the RS1 statistics software. Table 1 is a summary of these values. The Median time to failure, MTF, is the time at which 5O~ of the testing sites will have failed. The summary shows that the testing done over topography has a MTTF of 3.19 hrs with a STDEV of 1.21 as opposed to the MTTF of 5.31 hrs and STDEV of 1.11 over a flat surface. The MTF over topography was 3.14 hrs compared to the MTF of 5.38 hrs over a flat surface. Under similar testing conditions, the difference of the MTTF and MTF for both cases were 2.12 hrs and 2.24 hrs.

z ~ T..t TL~.

Figure 8: ~ Failure vs. Test Time

Figure 8 is a plot of cumulative percent failures versus test time for both cases. Failure times for electromigration induced failures for testing on a flat surface and over topography where compared. 4O~ decrease in MTTF was determined for interconnects over topography

Contact resistance and probe slipping were some major difficulties encountered. One method to insure reproducible results is to eliminate contact difficulties through wire bonding techniques. Contacts can be directly bonded to substrates, that

95 can be plugged into test sites. Also, for testing large linewidth test structures should be modified by reducing the number of lines tested. The decrease in interconnects will allow testing to be done at a lower voltage setting. Experiments testing the effects of the addition of copper, linewidth variations, testing temperatures, annealing temperature, passivation, and deposition conditions can be easily performed by using the test station developed in this experiment.

CONCI..U8ZQN

The experiment has presented data that demonstrates the decrease in MTTF due to electromigration testing over topography versus flat surfaces. A decrease of 2.12 hrs or 40 percent has been determined from the data acquired. The Test station used for acquiring Current vs. Time values has yielded valid data. Future experiments can be performed on the effects of other factors for electromigration lifetimes. Improvements can be made by decreasing contact difficulties through wire bonding techniques.

REFERENCE

[1] Ghandhi, “ VLSI Fabrication Principles,” Wiley-Interscience 1983

[2] Sze, “ VLSI Technology,” 2nd Ed. McGraw Hill 1988

£3] Strausser, Euzent, Smith, Tracy, Wu, “ The Effect of Metal Film Topography and Lithography on Grain Size Distribution and on Electromigration Performance,” IEEE/IRPS 1987

[4] Wolf, Tauber, “ Silicon Processing,” Lattice Press, Sunset Beach, Ca. 1985

[5] Park, Roessle, Majewski, Smith, “Electromigration in Aluminum Films Prepared with a High Rate Magnetron Sputtering Cathode,” 3.Vac.Sci. Vol.3, No.6, Nov/Dec 1965

[6] Honan, “Automated Testing of Electrical Linewidth Structures,” Masters Thesis, RIT, 1985

[7] Cho, Thompson, “ A New Electromigration Testing Technique for Rapid Evaluation of Interconnect Technology,” IEEE/EDL Dec 1986

96 MULTI-POINT CLEANROOM MONITORING

Andrew La Pietra 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

The feasibility of installing a multi-point particle monitoring system in the Rochester Institute of Technology Class 1000 Cleanroom at work level was examined. This consisted of monitoring 10 separate locations in the cleanroom at work level, including flow hoods, processing equipment and room air. An RS1 procedure was written to generate control charts and count information. The results showed that during low and high activity at a station the particle counts were in and out of process limits, respectively. Recommendations were made concerning installation of a complete system.

I NTRODLJCT I ON

Failure analysis of Integrated Circuits has shown that in Semiconductor Processing, particles one-tenth the smallest geometry can be hazardous to successful IC operation [1]. At RIT the minimum geometries in a standard process are 5 microns, and decreasing. Therefore, particles sizes of .5 microns arrd smaller must be controlled.

Cleanroom cleanliness is broken into several catagori~, according to Federal Standard 209D on clean rooms £2]. The general misconception is that only the number of .5 micron particles per cubic foot of air determines the room rating. In fact, several particle sizes should be used, especially in rooms with gross particle generators such as paper. The Class 1000 specification may be met at the .5 micron size (1000 particles percubic foot), but it may not be met at the 5 micron size (7 particles per cubic foot). It is for this reason that several particle size ranges should be monitored.

The Hiac/Royco 4150 A particle counters CX) are capable of monitoring airborne particles as small as 0.5 microns, and two units have the potential to measure 0.3 micron size particles. These counters can also be used to monitor particles in process gases and liquids. The 0.5 micron counters use standard optical particle counting methods to detect particles. As particles pass through the focal plane of the optical system, a white light beam is focused on the particles which causes light scattering according to particle size. The scattered light is collected by another optical system and a corresponding voltage level is triggered by a Photo Multiplier Tube. This is known as a white

97 light, or incoherent light optical particle counter. Counters with laser sources are known as laser counters or coherent light optical particle counters.

The optics system has a limit to the number of particles that can be measured without error. If too many particles are sampled by the counter the optics will count several small particles as one large particle. This is known as coincidence error, or coincidence loss. For the Hiac/Royco counters the threshold value for coincidence loss is approximately 300,000 particles per cubic foot [4].

Another area of concern is the flow rate of the counters.

The factory setting is 1 cubic foot per minute (+ or - .5 CFM) [4]. This amount of error can cause serious descrepancy in the number of counts recorded because different flow rate counters do not produce identical counts for the same cleanliness levels. To minimize this error, long count times should be used (1 minute samples). In a one minute sample, ideally one cubic foot of air would be sampled. If 6 second samples were taken and multiplied by 10, the error in flow rate, and correspondingly the number of counts, would be also multiplied by 10.

One must also examine the sampling tube length. If the tube length is greater than 50 feet, severe particle dropoff will occurr in the tube due to gravitational effects. This results in less than actual particle counts at a given location. The larger the particle size, the more severe the dropoff effects. For the purposes of this project the maximum length will be approximately 25 feet. Even at this length, large particles will be captured in the sampling hose, but the critical .5 micron size particles should still reach the counter.

Proper particle monitoring is done at the work level to determine the cleanliness of a given process. If equipment restraints do not allow for at level monitoring, then the equipment should be monitored as close to the center of operations as possible. Also, monitoring should be done well above the floor since most clean rooms have an 18 inch gross particle zone at floor level. The Laminar flow of a well designed cleanroom should prevent these particles from contaminating a process. The RIT cleanroom has sidewall returns, but with enough Laminar flow to sweep particles away from workstations.

X-Donation by Fairchild Semiconductor Corporation

Ten hoses were installed to obtain preliminary particle count data. The hoses were extended from the counter set-up in a service chase. The monitored locations included several flow hoods, wafer cleaning equipment, a computer terminal, chemical cabinets and room air. Many of the specific locations, such as the computer terminal, were chosen because the jump from low to

98 high particle counts occurs rapidly. Most of the hoses were been run under the service chase floor so as to be unobtrusive. There is still a concern as to how the long hose lengths will affect the particle counts. The longest hose is approximately 22 feet long, and the shortest is approximately 15 feet long. Prior to this specific project a FORTRAN communications program was written that allows for remote operation of the counters. The program controls the operating parameters of the counters, such as sampling time, and also collects and stores the particle count data. Data is stored for particles >0.5 urn, >1.5 urn and >5.0 urn for each of the 10 locations, with 30 samples per location. For this project an RS1 procedure was written that generates control charts and other particle count information. This procedure retrieves the particle count data from the VMS files, prompts the user for which station is to be examined, generates and stores the mean and standard deviation of the location, and creates a report that provides information on the number of points inbounds, the specific particle count for a given sample time, the mean and the standard deviation. The program then uses the data to create a control chart of particle counts vs. sample number (with 4 minutes between samples). An example of the control charts is shown in figure 1. .5 MICRON DATA

L4o~ a a

~00 a ~S00

D COUNTS uj -. UPPER PROCESS LIMIT

‘-I

a a a

-e a a a a a a a a ao ODDa hO

~ I I i I I I I I I I I~I 1 4 0 S *0 *0 *4 11 1* 00 04 10 SAMPLE lRJMSER

Figure 1: Contral Chart ~ampie

99 RESUL1S/AN~LYS! S

From the data that has been obtained, it appears that the contamination levels for the RIT cleanroom during )ow activity are well below the process limits, as shown in figure 2. Howeve~, as shown in figure 3 , while the low activity counts are well under control the high activity counts are out of control. If we also examine the mean chart, in figure 4, the contamination again appears to be in control overall. However, please notice the one outlying point on the mean graph. This point is the mean of particle counts taken during high activity at that location. This indicates that while the background, or low activity, contamination is in control, the actual processes are quite dirty. This general trend appears for >1.5 urn and >5.0 urn particle ranges as well.

.. — a~y*

Figure 2: a

O eaaTI Control Chart during low activity — ~ ii’ C — C~ C a ~ 000

d 3d dNè.. oa..aa..

.a —~ I~T*

C — C C Figure 3: C Co a C a Control Chart during high activity 0 — - — a C C C a B C

B C

ii 4 é ö -a a a a a a a a a a .

.1 — I*T* -

—

Figure 4: o .itTS —~ — ~ Control Chart of the Means — a — C a a a a 0 0 — ~ — I 3 -a a a a a

100 A small report on each sample set was also generated by the RS1 procedure. As seen in figure 5 this report provides information on the Mean value, the number of points out of bounds, and the individual particle counts for each sample. )11218P4 Lisit~ ta~l. for );1190M control chart: CO4ART );ll34M0 SU3~OUP 1 1UZ~OUP 2 Ronconforniti.; 3 USE. 4 TAR 5 LII. 6~t )~1l06M ID IUNBJ~ )~1078M — )ilO5OH 1 1 1280 500 0 0 08—MAY—89 )~1022)4 2 2 1324 500 0 0 08—MAY-89 .~;994I4 3 3 644 500 0 0 08—MAY-89 )~966H 4 4 1044 500 0 0 08—MAY—89 •)j93814 5 5 580 500 0 0 08-MAY-89 3~9l0M 6 6 472 500 0 0 08-MAY-89 i$982H 7 7 324 500 0 0 08-MAY—89 0gB54H B B 272 500 0 0 08-MAY-89

D~826M 9 9 312 500 0 0 08—MAY—89 Dg798M10 10 192 500 0 0 08-MAY—89 0;7701411 11 224 500 0 0 08—MAY—89 O~742M12 12 116 500 0 0 08—MAY—89

037141413 13 212 500 0 0 08—MAY-89 D$6861414 14 164 500 0 0 08—MAY—89 036581415 15 276 500 0 0 01—MAY—89 0~630)4l6 16 436 500 0 0 08—MAY-89 036021417 17 164 500 0 0 08-MAY-89

035741418 18 216 500 0 0 08-MAY-89 0g546Kl9 19 140 500 0 0 0l*IAY89 035181420 20 136 500 0 0 01-MAY-89 0~49OH2l 21 248 500 0 0 08—MAY—89

034621422 22 224 500 0 0 08-MAY-89

034341423 23 244 500 0 0 08-MAY-89 034061424 34 216 500 0 0 08—MAY-89

379321$ OH 0~l2741~.port for chart: CCHART 0g1218I~ype of control chart: .5 MICRON DATA Osltê2ll4ethod of dterininq control unit.: Ui1O7~Joer-zpecif1M Wlues for TAP, U~L~ and LII. 0 310221~ER84ARYs OgS6iWron X • 1 to X a 30: 0393814 Det•: 01-MAY-89 0391014 USL • 500 03*8214 TAR a 0 03854$ LII a 0 0 179114fot&1 of 30 qroi~., 5 groi~e out of bawd. 0g77014 (5 ) USE.; 0 ( LII) 037423417% out of bounds 0;71414 (17% > USE.; 0% C LII.)

Figure 5: Report on data Based on the collected data several recommendations are made. First, sample times of 15 seconds should be sufficient to sample. This allows enough time for the counters to minimize flow rate concerns previously mentioned and reduces the sample time between counts to four minutes. Also, each location should be ñ~onitored every day, but charts need only be generated once per week. This will require changes in the FORTRAN communications program output files in order to store one full day of data. As far as sampling locations, a list of locations is in the appendix. Also, the hoses should not be bend at more than a 90 degree angle; this minimizes particle drop-off in the tube. The tubes should be changed when visibly dirty. At each chosen location the hose should be as close to process level as possible, without interfering in processing. If this is not possible, the hose should try to be placed in the particle path of the area of interest (this is usually directly below a certain station). Also, the counters need to be calibrated and correlated to one another to ensure consistent particle counts.

CONCLUSIONS

Ten sampling hoses were installed at 10 locations and monitored for airborne particle counts. Results show that during low activity at a location the particle counts were within acceptable limits. However, during high activity, the particle counts were outside the acceptable limits. Recommendations were made for the completed system, and this will require changes in the FORTRAN program that remotely operates the counting systems.

ACKNOWLEDGEMENTS

Brad Moore wrote the communications program connecting the VAX and the particle counters, Steve Wilkins helped with RPL procedures, John Carlberg of Eastman Kodak assisted with proper particle monitoring techniques, and Bruce Smith of RIT lent his QCA manual.

~ ~

[1] 6.3. Sem, “A case for Continuous Multipoint Particle Monitoring in Semiconductor Clean Rooms”, j~. Proceedinos, 1986.

[2] “Federal Standards for’ Clean Room and Work Station Requirements, Controlled Environments”, Journal ~j Environmental Sciences, 9/SB.

[3] .W. P. Acito and L. Fuller, “University Clean Room Management Program”, Proceedinas: Seventh Bienniel University/Government/Industry Microelectronics Svmoosium, Rochester, NY 6/87.

[4] “Operations and Service Manual”, Hiac/Royco 4150 Systems manuals.

102 FERROELECTRIC THIN FILMS: PREPARATION OF A COMPLEX ALKOXIDE PbZr~Ti~,O1 THIN FILM

Richard A. Leach 5th Year Microelectronic Engineering Student Rochester Institute of Technology ABSTRACT

Ferroelectric thin films were prepared by sd—gel processing. The complex alkoxide was prepared by reacting a Lead (II) salt with Titanium and Zirconium alkoxides in a Methoxyetharkol solvent. The gel was produced using a dilute acid catalysis to hydrolyse the bonds of the complex. The metal alkoxides were Ti/Zr isopropoxides, and Lead salt was a Lead Acetate. Working devices were not fabricated due problems in adhesion, cracking and problems with the viscosity of the gel.

INTRODUCTION

FerroeleCtrOfliC devices provide a promising new technology for memory design. This new surge in memory technology uses the ferroelectric effect of a Lead Zirconate Titanate thin film. The resultant Ferroelectric Random Access Memory (or FRAM, as trademarked by Ramtron Corp.) has the advantages of all present memory components. It has device densities greater than or equal to DRAMs; nonvolatility greater than EEPROMs; and the speed, life cycle endurance, and symmetrical read/write capabilities of SRA!ls. It is as easy to use as SRAMs, arid also has excellent radiation hardness [1,2].

The Lead Zirconate Titanate (PZT) thin film is used as the dielectric material for a memory capacitor. The PZT capacitor can be used in the same fashion as DRAM storage capacitors without the associated leakage. The PZT capacitor can also be used as a storage capacitor for SRAMs giving them memory retention. The difference between standard oxide capacitors and the PZT capacitor is that the PZT capacitor has two stable polarization states. This gives it the ability to be polarized in one direction and remain polarized in that direction until repolarized. The change of polarization state is accomplished by applying an electric field across the PZT thin film. Once the polarization state is set, the memory capacitor will hold that state until reset with a memory retention of greater than 10 years. The endurance of the device is greater than 1OE1O R/W cycles [1,2). This project is centered on the area of preparing the complex alkoxide PZT film. The complex gel was made by first dehydrating the Lead(II) Acetate trihydrate as in equation 1.

103 (1) Pb(~H ~ 211,0 —~ Pb(CH ~C0,), ~ A- ~ A

Equation 1

Next a Lead salt (Lead acetate) was reacted with Titanium and Zirconium alkoxide (Ti/Zr isopropoxide) as in equation 2.

~2s Pb(cH ,cO~,), ~H,), cH-O-)~ • 1~(GH ,), cH.0-), 11d(U) A.~sIi ~_U... bb...pm.14. Th..~. ka~r.I~zI~

-~ cZr,T1(OC ~I ,~ ,0),Pb • 2~I,CO0C, 117 aa(i~ Ii_a~t~

Equat ion 2

The reactions were done using a solvent of 2—Methoxyethanol to dilute the complex and drive off impurities. A gel was then produced by diluting the bis(alkoxy Zirconato, Titanato) Lead(II) complex in 2—methoxyethanol and using water to hydrolyze the bonds of the complex as in equation 3.

~2) ~ZY,fl(OC,Hp,0),Pb • 111,0 IC,H,0H. ~1T~ L(I~

~r,Tl(0H) 0) Pb -J.~,.L_, ~.TT) II~

Equat ion 3

The resultant gel is then coated on a wafer and the solvents are driven off on a hot plate. The perovskite phases crystallize from the bulk gels at temperatures between 450 to 600 degree Celsius [3). The desired film is a 0.1 to 1.0 um Lead Zirconate Titanate compound (1:1 Zr to Ti ratio in the PZT). This should produce a ferroelectric thin film with a dielectric constant of approx. 750, remanent polarization of 20 uC/cm**2 and a coercive field of 20 ky/cm [4]. Most of the present research is done using the PZT thin film as a capacitor dielectric, this project was to evaluate the PZT thin film for use as a gate material for a Metal Ferroelectric Semiconductor device.

104 £XPERI!’IENTATION

The method of gel preparation is a combination of the methods used by Budd, Dey and Payne [3,4) and Gurkovich and Blum [5]. 600m1 of 2—tlethoxyethanol was transferred into a single neck round bottom flask and mixed with 5 grams of Calcium Hydride in a Nitrogen ambient. The solvent was refluxed for 72 hrs as seen in figure 1. The refluxed methoxyethanol was distilled off and collected in a 2SOml flask. The Methoxyethanol that was refluxed and distilled is used to distill and redilute the Lead Acetate, and is used to dilute the bis(alkoxy Zirconato, Titanato) Lead(II) complex. Anhydrous tlethoxyethanol was distilled off as needed. 17.08g (0.045 moles) of Lead Acetate trihydrate was added to 15m1 of anhydrous Methoxyethanol and a stirbar in a two neck 500m1 round bottom flask in Nitrogen. One neck held a thermometer in contact with the solution, the other neck had a distillation head with a septum mounted vertical. Figure 2 shows the apparatus set up.

Figure 1: Figure 2: Reflux Apparatus Dist illat ion/React ion Apparatus

The solution was heated, at 118C the associated water was distilled off. Afterwards the temperature reached 124C, the boiling point of I~1ethoxyethanol. Three successive distillation and redilutions were preformed to remove the water from the salt. Titanium isopropoxide and Zirconium isopropoxide were transferred into syringes in a Nitrogen ambient. The distillation was stopped by cooling the solution when there was lSrnl of Hethoxyethanol in solution. The solution was cooled to 75C at which time 7.02m1 (0.0225 moles) of Titanium isopropoxide and 6.20m1 (0.0225 moles) of Zirconium isopropoxide were injected into the solution and mixed. The color of the solution changed from a golden to a light brown color. The temperature of the solution increased to 90C at which time the isopropylacetate was 105 driven off (B.P. 85 C) in the reaction. The temperature was increased to 150C to assure the reaction went to completion, then cooled to approximately 80C. Care must be taken when heating the solution because if overheated the complex will decompose. The solution was cooled to 65C and diluted with 60m1 of anhydrous Methoxyethanol. 6.5rnl of a 0.1 molar concentration of Nitric acid was added to the complex as the water of hydrolysis. The solution gelled rapidly and became too viscous to pour out of the reaction vessel. The gel was spooned out of the reaction flask and diluted in lOOml of anhydrous tlethoxyethariol to reduce the viscosity however the gel never went back into solution. Wafers were then evaporated with Al and sintered at 450C for 20 minutes. Attempts to spin coat the PZT complex on the wafers was unsuccessful due to the high viscosity. Ceramic thick films were evaporated with Chromium and the PZT gel was applied by means of screen printing and brushing it on. Due to the high viscosity and the poor adhesion to Chromium both methods were unsuccessful.

RESULTS & DISCUSSION

The results of this project is that the complex produced was simular to that obtained by Gurkovich and Blum [5]. This was demonstrated first, when the Lead Acetate trihydrate was dehydrated the associated water was driven off at 118C. Second, when the Ti and Zr isopropoxides were added to the Lead Acetate, the temperature rose as the reaction occurred, and the isopropylacetate was boiled off. Third, when the water of hydrolysis was added the solution gelled rapidly.

Ideas for future experimentation are that the complex should be diluted with more methoxyethanol than the 6Oml used, I would try 120m1. Another idea is to use copper as the metal because it is necessary to be able to etch the thin film without etching the metal. An idea for an etchant would be a HF, HCJ. mixture.

Figure 3 shows the structure formed. This structure is a face—centered cubic with a Ti/Zr atom lying on a vertical axis.

IVZr 0 .,o

Figure 3: PZT Unit Cell 106 ______1~

Titanium’s electron configuration is simular to an Ar core with 2 electrons in the 3d and 2 electrons in the 4s levels. Zirconium’s electron configuration is simular to an Kr core with 2 electrons in the 4d and 2 electronS in the 5s levels. The structure in figure 3 is formed when both Ti and Zr give up their electrons resulting in a positive four electron charge. The position of the Ti/Zr atoms is dependant upon the direction of the last field applied across the thin film. The thin film was proposed to be used in the following manners. First, the PZT thin film was to be used as a memory capacitor as shown in figure 4. Second, the PZT thin film was to be used as a gate material in different layer schemes as shown in figures 5,6,7. The Integrated Circuit design layout is located in the Appendix.

Figure 4 : PZT Capacitor

Figure 5 : Metal Ferroelectric Semiconductor Device

oi~__~ ~

Figure 6 : Metal FerroelectriC Oxide Semiconductor Device

b— __ )z~ ~

Figure 7 : Metal Ferroelectric Metal Oxide Semiconductor Device

The crux of this lab was to prepare a FZT thin film capacitor using sd—gel processing to produce a liquid that could be spin coated on a Si wafer. The gel produced was too viscous to spin coat, the method of coating was to brush coat the PZT complex on the substrate. The resultant film had many cracks and could not be used as a dielectric. One possible reason for the cracks could be that when the complex was rediluted after the water of hydrolysis was added, the gel never went back into solution. Another reason could be that there was not enough MethoxyethanOl used to dilute the bis(alkoxy Titariato/ZirCOnatO) 107 Lead(II) complex.

~CKNOWLXDGEMtNTS

I would like to thank Dr. Marvin Illingsworth for his help in unraveling the chemistry, Scott Blondell and Michael ~Jackson for helping obtain the chemicals required.

R~REN CES

[1] Richard Horton, Raridel Castelberry, “Nonvolatile FRAMs fit standard memory applications” in Electronic Products, pp.41—45, June 1, 1988

[2] Technical Report on Nonvolatile Ferroelectronic Technology and Products, Ramtron Corporation, Date and Author of publication unknown.

[3] K.D. Budd, S.K. Dey and D.A Payne,”Thin-Film Ferroelectrics of PZT by Sol-Gel Processing” in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 35, No. 1, pp. 80—81, Jan 1988 [4] lCD. Budd, 5.1<. Dey and D.A Payne, “The effect of hydrolysis conditions on the characteristics of PbTiO3 gels arid thin films” in Better Ceramics Through Chemistry II, Vol. 73, Pittsburg: Materials Research Society, pp. 711—716, 1986.

[5] S.R. Gurkovich, 3.R. Blum, “Preparation of Monolithic Lead—Titanate by a Sol—Gel Process” in Ultrastructure processing of ceramics, glasses, arid composites, New York: John Wiley & Sons, 152—160, 1984.

108 GROWTH AND CHARACTERIZATION OF ANODIC ALUMINUM OXIDE

Cathy Leathersich 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

The growth of anodic aluminum films on silicon was investigated. The films were formed using an electrolytic cell with sulfuric acid and a lead cathode. The effects of electric potential, electrolyte concentration and anneal time were investigated with respect to film thickness, index of refraction and oxide quality with a three level-three factor Box-Behnken designed experiment. The results of the statistical analysis indicated poor repeatability in film qualities as evidenced in ellipsometric and C-V measurements.

INTRODUCTION

The development of alternate methods of oxidation has been driven by interests in oxidizing Ill/V compounds such as In/P [1], multilevel metallization schemes where oxides cannot be thermally grown [2], and the need for low temperature oxidations due to the trend towards shallower junction depths. c~nodic oxid ation of aluminum is one method that has been investigated.[3].

~nodic growth refers to the formation of an oxide by electrochemical reactions. It can be carried out in a simple inexpensive electrolytic cell with great accuracy and without costly and complicated equipment, such as chemical vapor deposition and sputtering systems used to deposit dielectrics [2][4]. The anodization apparatus consists simply of a voltage source, a multimeter for monitoring purposes, a lead cathode, a well for the electrolytic solution and a holder for the wafer which will also provide electrical contact to the backside of the wafer [5].

For the aluminum anodization process, the electrolytic solution used is sulfuric acid and the cathode is lead [6]. The reaction mechanisms are as shown below:

~l --> M3+ + 3e-

4 Al3+ + 3 (604)2- --> 2 ~l203 + 3 S02

where e- represents an electron. The aluminum is converted to

109 its oxidized state at the anode and the reaction is completed by the sulfate ion provide from the electrolyte to form the aluminum oxide [7]. The sulfuric solution was chosen due to immediate availability of materials.

Several parameters affect the formation and quality of anodic films. The parameters of concern in this experiment were the applied electric potential, the electrolytic concentration of the solution, and the annealing time in a 450C nitrogen/hydrogen ambient. A Box-Behnken, three level-three factor, style experiment was designed around these parameters. The electric potential was varied from 5 to 15 volts as selected from literature values. The concentration ranged from 2.5 to 15X by volume, again, selected from literature values. Annealing times of 0 to 30 minutes at 450C in a nitrogen/hydrogen ambient were chosen from standard RIT processes. The responses of interest were the film thickness, index of refraction and quality of the oxide as evaluated from C-V curves. Increasing solution strength tends to produce films that are more porous [6]. The porosity would degrade the oxide quality and be reflected in deviations in the index of refraction from the accepted value of 1.76 and in the electrical characteristics. The electric potential and electrolyte concentration both effect the growth rate in that as they increase so does the reaction rate [6][7]. If the rate is too high the reaction may not follow the one cited above and take the following [7]:

Al --> Al2+ + 2e-

2 A12+ + (S04)2- --> 2 AlD + 602

The resulting films would deviate in their indices of refraction and film thicknesses from run to run depending upon the stoichiometry and differences in the material properties between the two aluminum oxides. Annealing was seen to reduce the hysteresis of C-V voltage curves with increasing temperatures in an argon ambient by Matsui, et. al. [B]. It was desired to repeat this effect employing the standard RIT anneal process with varying times.

EXPERIMENTAL

The anodization cell consisted of the apparatus described above and was arranged as shown in the schematic in Figure 1. The aluminum anode had an area of 5.5 cm2 exposed to the electrolyte. The cathode had an area of 5.0 cm2 of lead foil. The rubber 0-ring formed a seal between the teflon plate and the wafer to contain the electrolyte. Figure 1: Anodization Apparatus

P-type <100> wafers were obtained with an average background doping of 2.2 x 10E15 boron atoms/cm3 as determined by four point probe measurements. They were scribed and cleaned via a standard RCA clean process. The back sides of the wafers were coated with aluminum using an evaporator with a tungsten filament. The film was annealed for 15 minutes at 450C in a nitrogen/hydrogen ambient. This was to provide ohmic electrical contact to the back side of the wafer as required for the anodization process. The front sides were next coated with 2000A of aluminum. The aluminum films were anodized in ten milliliters of solution according to the concentration and voltage listed in the Box-Behnken experimental worksheet created in RS1 as shown in the Table 1.

E~ri.ent ~rksheet 0 1 tX 2 ~OT~ 3 ~W~L 4 HYSTE~SIS S D~ & THID(1(SS 7 iM)~ ( by vol) (v) (MIN) (V) (*/csZ) (~igstroms) 1 6.3 15 0 2.5 6.?e+Z3 1890 1.55 2 10.8 18 8 6.0 8.Se+Z3 2029 1.52 3 6.3 5 8 1.8 5,9~~23 1829 1,44 4 2.5 18 8 1.2 1.1e+23 1185 1.51 5 6.3 18 15 1.8 2.Se+Z1 1939 1.69 6 2.5 5 15 1.3 1.?e+21 1~3 1.48 7 2.5 15 15 0.9 3e+Z1 1221 1.56 8 10.0 15 15 1.6 Z.&+24 2038 1.~ 9 18.8 5 15 2.8 2.3e+24 288? 1.45 18 6.3 18 15 8.9 2.3e+24 1139 1.48 11 ... 6.3 18 15 1.0 3.4e+24 1411 1.54 12 6.3 15 38 8.1 3.le+24 . 1622 1.54 13 10.0 10 38 1.2 Z.3e+23 1631 1.~ 14 6.3 5 38 4.8 1.?e+24 1189 1.51 iS 2.5. 18 38 8.2 3.3e+24 1314 1.55 Table 1: RS1 Experiment Worksheet

The anodization end point was noted by stabilization of the current as monitored with the ammeter. Agitation was provided by a pipet. The film thickness and index of refraction were determined using the AME-500 ellipsometer at a wavelength of 6328A. The C-V plots were obtained after evaporating aluminum

111 through a shadow mask with 9.6 x 1OE-3 cm2 and 31 x 1OE-3 cm2 holes and the appropriate anneals in a 450C nitrogen/hydrogen ambient as prescribed by the experimental worksheet.

RESULTS/DISCUSSION

The films produced ranged in thickness from 1221 to 2087A with an average thickness of 1646 +1- 296A. These are relative values due to possible misalignment of the system. True nulls were not obtained when determining the polarizer and analyzer angles. The confidence limits also varied for the thicknesses. Also imaginary portions of the indices were ignored. The colors varied from green to purple from wafer to wafer and some wafers were hazed. The haze is indicative or porosity caused by higher concentrations of electrolyte which is what the films were processed in. The uniformity across a wafer was noted by color gradients across the wafer as the ellipsometer had a large spot size and did not allow for exact values to be obtained. The color was very uniform across eight of the fifteen wafers. The other seven showed slight gradients across the wafer, slight meaning that it varied from a light blue to a dark blue from one side to the other. This nonuniformity can be accounted for by a nonuniform initial aluminum deposition. The variations among the wafers were far to great to be accounted for by differences in stoichiometry as suggested in the introduction. The statistical analysis with RS1 supported this view. The F—ratios indicated that the coefficients could all be zero with only an 80~ confidence in the values it did calculate though there was no evidence of lack of fit for these coefficients.

The indices of refraction obtained varied from 1.44 to 1.54 with an average value of 1.54 +/- 0.07, again, the inaccuracies in the ellipsometry measurements apply to these values. These were all lower than the value of 1.76 as listed in the QE~ Handbook gj Physics ~ Chemistry suggesting that the stoichiometry was not A1203 and that the films were not of perfect quality as noted by haze on four of the wafers. Again no definite correlation was shown to the parameters investigated by the statistical analysis. The F-ratios indicated that all the coefficients could be zero with 60X confidence in the values it did calculate and with no evidence of lack of fit. This suggests that the range of concentration was too narrow to show a noticeable effect.

The C-V measurements obtained were evaluated for charge nonidealities such as mobile ionic, fixed, and trapped charge in the oxide as determined from shifts of the threshold voltage from the corrected ideal threshold (corrected in that the metal/semiconductor work function was included in the threshold determination). The amount of charge ranged from 0.1 x 10E24 to 3.4 x 10E24 ions with an average value of 1.9 x 10E24 ions. The RS1 analysis could not be completed due to a divide by zero error that was encountered while analyzing it. The amount of charge was high. The amount of mobile ionic charge was expected to be very high due to the use of sodium in the formation of the tungsten filaments used for the evaporations. The amount of interface traps was also very high as noted by the spreading of the C-V curves.

The hysteresis was measured by plotting the C-V curves with the capacitor biased at +10 volts for one minute and then replottirig the curve after it had been biased at -10 volts for the same time and taking the voltage difference between the curves. The differences ranged from 0.1 to 6.0 volts. The average of the zero minute anneals was 2.8 volts, the 15 minute anneals was 1.4 volts and the 30 minute anneals was 1.6 volts. This demonstrated that annealing reduced the hysteresis with the 15 minute anneal showing the greatest reduction.

SUMMARY

The anodic aluminum films were grown. The effects of electric potential, electrolyte concentration and anneal time were investigated with respect to film thickness, index of refraction and oxide quality with a three level-three factor Box-Behnken designed experiment. The results of the statistical analysis were inconclusive. It is suggested that a screening experiment be done to determine the factors that are of significant influence in the anodization process as performed at RIT. The films produced varied in thickness from 1221 to 20B7P~ with an average value of 1646 +/- 296~ and in the index of refraction from 1.44 to 1.54 with an average value ofl.54 +/- 0.07. The amount of mobile ionic and fixed charge in the films ranged from 0.1 10E24 to 3.4 x 10E24. The hysteresis was decreased by annealing with the smallest average shift of 1.4 volts for an anneal time of 15 minutes in a 45CC nitrogen/hydrogen ambient.

ACKNOWLEDGEMENTS

Scott Blondell and Gary Runkel for their assistance with equipment and obtaining material. ~ssistant Professor Michael Jackson for his guidance throughout the project.

~IE~E RE N~E ~

[1] Hirayama, Park, Kishiga and Sugano, 3. of Electronic Materials, jj, 1011 (1982). [2] Schwartz and Platter, 3. of Electrochemical Society, ~2Z, 1508 (1975). [3] Grimsley, RIT Senior Research Project, 1986. [4] Barber, Lo and Jones, 3. of the Electrochemical Society, 123, 1404 (1976). [5] Parmelee, RIT Senior Research Project, 1988. [6] Henley, ~nodic Oxidation ~.j Aluminum ~ i±~ Alloys, (Pergamon Press, 1983), pp. 57-61. V [7] March and Windwer, General Chemistry, (Macmillan Publishing Company, 1979), Pp. 501-526. [8] Matsui, Hirayama, Arai and Sugano; IEEE Electron Device Letters, EDL-4, 308(1983).

113 FOUR ~IT CMD8 ALU

Frank Leilich 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

A four bit CMOS arithmetic logic unit was designed. The design was layed out in ICE (integrated circuit editor).

Z NTRODUCT I ON

The f~LU or arithmetric logic unit is the heart of the microprocessor. It performs all the arithmetic and logic operations that give the computer its power. Its design would be one of the first steps in creating a microprocessor. The current technology being used most in industry is CMOS. It has the advantages requiring only one power supply, operating in a wide voltage range with good noise immunity, and dissipating very little power when in a high or low state.

The most basic operations an arithmetric logic unit should perform are the add, subtract, and, or, not, exclusive or, and decrement. The seven functions necessitate the use of three

select lines - one select option will not be used. The start of an ~LU can be reduced to the design of the operation for one bit. The design of the one bit is then replicated and interconnected to get a full bit ~LU.

The first step in the design was to draw up the possible truth tables for the one bit. The truth table that produced the shortest expression for the bit was used for the design. This ensured that the design would be as small as possible by using the fewest gates in the design.

The easiest gates to implement in CMOS are the NAND and the NOR. The layout of the project began with the design of standard NAND, NOR and inverter cells. The cells were then used to make the design of the bit. The bit was then copied four times into a chip. The individual bits were oriented and interconnected from the center of the chip. The output pads were added and the connections completed.

The process choosen for the CMOS uses a 2 micrometer deep P-well in a n-type wafer. The transistors are made using the self-aligned gate process. The steps were simulated using SUPREM. Times and temperatures for the growing of the oxides were computed and the doses and acceleration voltages for the ion implants were estimated. ~I1L~ Figure 1 is the truth table for the shortest expression of a bit. A Karnaugh map was made for each possible order the functions could be placed in and the table resulting in the shortest expression was used for the design. The total number of possible orders is eight factorial, which is 40,320. For finding the shortest expression a computer program was written in BASIC and run. The design of a bit for the ALU is shown in Figure 2.

One Bit Truth Table Ax Bx S2 Si SOIDx Ax Bx S2 Si SOIDx Ax Bx S2 Si SOIDx 0000 OIX 1101 010 1010 lii 0100 OIX 0001 110 1110 lii 1000 0Ix 0101 lii 0011 011 1100 OIX 1001 lii 0111 011 0000 110 1101 110 i0~11 010 0100 lii 0010 010 1111 010 1000 lii 0110 010 0011 110 1100 110 1010 010 0111 111 0001 oIl 1110 011 1011 lii 0101 011 0010 110 1111 iii 1001 010 01 10 lii

Select Function State S2 Si SO Function State S2 Si SO Function 0 0 0 0 not used 4 1 0 0 AND 1 o 0 1 SUBTRACT 5 1 0 1 ADD 2 0 1 0 DECREMENT 6 1 1 0 NOT 3 0 1 1 XDR 7 1 1 1 OR

Figure 1

Figure 2

The three most used technologies for making CMOS in silicon are the P-well process, the N-well process, and the twin tub processC2]. The twin tub design was not used because of the extra processing steps that would be required. The reason the P-well process was choosen over the N-well is that most of the processing done at RIT is done on n-type wafers and the. P-well process is the more common of the two. The design rule is 10 microns with 10 micron gates.

115 The process involves seven levels of masks. The steps involve taking a clean n-type wafer and growing a thick field oxide. The first mask then defines the p-well for the n-channel transistors and is shown in Figure 3a. The thick oxide is etched and the p-type diffusion is done. The second mask is the thin oxide mask, it defines where the transistors are going to be on the wafer, and is shown in Figure 3b. Photoresist is patterned on the wafer and the thick oxide is etched. The thin oxide is then grown around 500 ~ngstroms thick and now covers where the gates, sources, and drains of the transistors will be. The gates are polysilicon and the poly is deposited on the wafer at this time. The third mask defines the gates and is used now to etch the pattern into the polysilicon. This mask in shown in Figure 3c. In the process the “self-aligned” gate technique is used. The forth mask is the “p-select” and is shown in Figure 3d. The mask defines where the p-type implants go for the p-transistors. The fifth mask is the negative of the “p-select” mask and serves to define where the n-type implant goes for the n-type transistors. The mask is shown in Figure 3d. The wafer is covered with a deposited glass for protection. The six mask level defines the contact cuts and is shown in Figure 3f. Lastly the aluminum is deposited on the wafer and patterned with the metal pattern mask. The metal mask is shown in Figure 3e[2J. The final cross-section of a CMOS gate is shown in Figure 4.

The gate designs were made to allow the use of one supply rail to power gates above and below it. This eliminated the need to have two metal lines carring different voltages running next to each other. The standard cell layouts are shown in Figure 5. The construction of one bit layout was done by connecting the gates and making changes as needed. The final one bit layout occupies an area of 1170 microns from top to bottom and BlO microns from input to output and is shown in Figure 6. The final design of the ~LU with all the inputs and outputs labeled is shown in Figure 7.

The processing was simulated using SUPREM. The six different regions in the cross section of the CMOS were simulated and can be identified in Figure 4. Region ~ is the P-well and gate of the NMOS transistor. The minimum desired depth of the P-well is 3 micrometers. The Boron was implanted into the wafer so that there would not be a high surface concentration which would lead to a high threshold voltage. The drive in was then done for 9 hours at 1100 degrees Celsius and the gate oxide was grown in dry oxygen for 35 minutes at 1000 degrees Celsius. The final estimated junction depth was 3.015 microns and the gate oxide thickness was 475.2 Angstroms. The ion implant was dome with an acceleration voltage of 1BO Kiloelectron volts and a dose of 3.65 E12 atoms per centimeter. The final estimated surface concentration was 4.8 E14 atoms per centimeter and a threshold voltage of 0.97 volts. Region B is the diffusion of the n-type drain and source in the P- well. The goal was to get •a sheet resistance of around 60 ohms per square. This was done with a diffusion of Phosphorus for 15 minutes at 890 degrees Celsius. The final estimated sheet resistance was 62.75 ohms per square CROSS SECTION OF PHYSICAL STRUCTURE MASK (TOP VIEW) (SIDE VIEW) . PTUBMASK

FIELD OXIDE (FOX) 4-5 ~.m DEEP

1I1I1lII11IlIIiiIi~ui~IIIlIIIIIHII ~

. p.WELL n.SUBSTRATE

(I)

THINOXIDE (—500 A)

~~IiIIllItIIL

- ~ Jj n-SUBSTRATE

(b)

METAL METAL — — — MASK POLYSfl.~0N

p p n~ ~ p-WELL n-SUBSTRATE n-SUBSTRATE (MetaIonè) (9) (c) (Poly)

p.TRANSISTOR Figure 3~ CMOS process steps with masks~

S:TRA:L—~j~

(d) and a junction depth of 0.438 microns. Region C is the gate oxide over the n-type wafer for the PMDS transistor. The oxide is grown with the gate on the NMDS and was simulated with the same time and temperature. The final estimated thickness was 475.2 microns and the threshold voltage was -1.25 volts. Region 0 is the diffusion of the p-type drain and source for the PMOS transistor. The goal was to get a sheet resistance of 10 to 100 ohms per square. This was done by diffusion of Boron for 15 minutes at 890 degrees Celsius. The final estimated resistance was 35.74 ohms per square and a junction depth of 0.292 microns. Region E is the field oxide over the P-well. To provide protection from the 180 Kilo- electronic Volt implant the oxide had to be at least 8000 Arigstroms thick. It was grown with steam for 1 hour and 40 minutes at 1100 degrees Celsius. The gate oxide is grown on the field oxide in this region and was simulated also. The final estimated thickness was 8121 Angstroms. Region F is the field oxide over the rest of the wafer. This is simulated the same as region E except with out the ion implant. The final thickness was also 8121 Angstroms.

Figure 4

CONCLUSIDN~

The ALU or arithmetric logic unit is the heart of the microprocessor. It performs all the arithmetic and logic operations that give the computer its power. A four bit ALU designed as part of the first step in creating a microprocessor. The current technology now available at RIT is CMOS. The CMOS technology has the advantages of requiring only one power supply, operating in a wide voltage range with good noise immunity, and dissipating very little power when in a high or low state.

~CKNOWLEDBMENT8

I would like to thank Rob Pearson for his help in designing the standard CMOS cells and the simulation in SUPREM. NAND NOR :LNVERTER

GND J {~~:::~f: Ax r~ ID Ax +~x Ax

+5 4~~z ~

NOR INVERTER +5 ~]j Ax

Ax ~x Ax +E~x E~x

GND

ue — Aluminum

Red — Polysilicon

8lack — Contact Cut Fiqure 5: Layouts for ALU Gates

Green — Active (thin oxide)

Orange — Pwell

Purple — Pselect (ion implant) +5

52 Dx Ax

33 GND

Ex Ax 33

Si c~~ ~‘ Dx Dx GND

Si 53 Ax

8x Ax Si

GND

Fiqure 6; Layout for one Dit a-f ALU __ I LI______I __: ______~!c.:__ —______—

~1 ~2 A3 A4 —

811 1 • r ~ ___ 1=

~ jj~.~1• i ~i ~ BIT

1D2J ______~NDI

= z -- ______

E41T2 = ____

-~ ~ ____ - I t LZ~ - L ~ I L{IT 4

: ~ ______

- Figure 7: Four Bit CMOS ~LU REFERENCES

[1] McGlynn, Daniel, Microprocessors Technology, ~rchiture, ~ ~polications , Wiley Iriterscience Publication, New York, 1976

[2] Weste, Neil, Eshraghian, Karman, Princi~le~ ~j CIIflS VLSI EJesiQn & ~vstems Perspective, ~ddison-Wesley Publishing Company, Reading Mass., 1985

[3] Klingman, Edwin E., Microprocessor Systems DesiQn, Prentice-Hall Inc., New Jersey, 1977

[4] Moll, John L., Computer 1~ided Desi~n ~ VLSI Development, Kluwer ~cademic Publishers, Boston, 1966

122 THE CHARACTERIZATION OF AN ALL ENHANCEMENT PMOS OPmAMP

By David L. Lewis 5th Year Microelectronics Student Rochester Institute of Technology

ABSTRACT In present day electronic systems a basic building block is the operational amplifier. Therefore, a better understanding of characteristics of Op-Amps and their importance to overall circuit operation is essential. In the electronics industry manufacturers supply data sheets for the IC’s they produce. These data sheets provide a wealth of information: absolute maximum ratings, intended applications, electrical characteristics, performance limitations, equivalent circuits of devices, and more. These defined parameters make the design of more complex systems a much easier task. As do manufacturers in the industry so too must RIT characterize their devices. This project will characterize the important parameters of an All Enhancement Pmos Op-Amp designed and fabricated using R1T’s standard 10 micron design rules and pmos metal gate process. More specifically, the parameters characterized will be the input offset voltage, output offset voltage, input voltage range, output voltage swing, supply voltage rejection ratio, large signal voltage gain, common mode gain, common mode rejection ratio, power consumption, and slew rate. These parameters will be defined, measured, and compared to a SPICE simulation for the given Op-Amp.

INTRODUCTION It is known that the Op-Amp can be used as an inverting, non-inverting, or differential amplifier, and that the negative feedback can be used to stabilize the voltage gain and increase the bandwidth of the Op-Amp circuit. It is also known that when treated as an ideal device it provides characteristics such as high input impedance, low output impedance, high voltage gain, and broader bandwidth, if the appropriate external components are used. These ideal characteristics, a1though~ very desirable, are not fully present in practical Op-Amp circuits. The nonidealities that are present are due to the limitations and imperfections involved in fabricating these devices. These imperfections, of course must be characterized along with the various parameters of an Op-Amp.

THEORY Even though all the components are integrated on the same chip, it is not possible to have two transistors in the input differential amplifier stage with exactly the same characteristics. This mismatching between the two input terminals causes an output offset voltage. The output offset voltage Voo is a d.c. voltage, and it may be positive or negative in polarity depending on whether the potential difference between two input terminals is positive or negative. This voltage is measured at the output when no external inputs are applied. The input offset voltage Yb is the differential input voltage that exists between input terminals of an Op-Amp without external inputs applied. In other words, it is the amount of the input voltage that should be applied between two input terminals in order to force the output voltage to zero. The polarity of Vio depends on the mismatching at the inputs. A typical value of Vio for the 741C Op-Amp is 6mv d.c.. The smaller the value of Vio, the better the input terminals ale matched.

123 When the same voltage is applied to both input terminals, the voltage is called a common-mode voltage Vcm and the Op-Amp is said to be operating in the common-mode configuration. For the 741C the range of the input common mode voltage is +1- 13v maximum. This means that the common-mode voltage applied to both input terminals can be as high as +13v or as low as -13v without disturbing proper functioning of the Op-Amp. In other words, the input voltage range is the range of common-mode voltages over which the offset specifications apply. As shown in figure 3 the common mode configuration is generally used only for test purposes to determine the degree of matching between the inverting and non-inverting input terminals. Because ideally an Op-Amp amplifies only differential input voltages, no common mode output voltage Vocm should appear at the output. However, due to imperfections within an actual Op-Amp, some common-mode voltage Vocm will appear at the output. The amplitude of this Vocm is vexy small and often insignificant compared to Vein. Therefore, in practice the ratio of the output common-mode voltage Vocm to the input common-mode voltage Vcm, which is called the common-mode voltage gain Acm, is generally much smaller than 1. In equation form, Acm=Vocm/Vcm

Ideally, the common-mode voltage gain Acm is zero.

Acm can be calculated for a given Op-Amp by applying a known value of common-mode input voltage Vcm and measuring the resultant output common-mode voltage Voem. Op-Amp manufacturers usually list a common-mode rejection ratio CMRR. Generally, it can be defined as the ratio of the differential gain Ad to the common-mode gain Acm, CMRR=Ad/Acm

The CMRR can also be expressed as the ratio of the change in input offset voltage to the total change in common-mode voltage. CMRR=Vio/Vcm

Generally, the CMRR value is very large and is therefore usually specified in decibels (dB), where CMRR (dB) =20 log (Ad I Acm) or, CMRR (dB) =20 log (Vio I Vcm)

CMRR is a measure of the degree of matching between two input terminals; that is , the larger the value of CMRR (dB), the better is the matching between the two input terminals and the smaller is the the output common-mode voltage Vocm. On the other hand, a large voltage Vocm for a given common-mode input voltage Vcm is and indication of a large degree of imbalance between the two input terminals of poor common-mode rejection.

As supply voltages change because of poor regulation and filtering, for a given Op-Amp any change in the values of the supply voltages results in a change in the input offset voltage, which in turn causes a change in the output offset voltage. The change in Op-Amps input offset voltage caused by variations in the supply voltage is generally specified by a variety of terms: the input offset voltage sensitivity, the power supply rejection ratio, the power supply sensitivity, and the supply voltage rejection ratio are some of them. All of these terms are equivalent since they convey the same infomiation. These terms are expressed either in inicrovolts per volt or in decibels. SVRR=iWio/AV

SVRR =20 log (AV / AVio)

Note that the higher the value of SVRR in decibels, the lower is the change in input offset voltage due to the change in supply voltages or, in others words, the lower the value of SVRR in uV/V, the

124 better for Op-Amp performance. In fact, ideally the value of SVRR in uV/V should be zero. Slew rate (SR’ is defined as the maximum rate of change of output voltage per unit of time and is expressed in volts per microseconds. In equation form, SR=dVo/dtlmax V/us Slew rate indicates how rapidly the output of an Op-Amp can change in response to changes in the input frequency. Ideally, we would like an infinity slew rate so that the Op-Amps output voltage would change simultaneously with the input. Practical Op-Amps are available with slew rates from 0.1 V/us to well above 1000 V/us. Generally, the slew rate is specified for unity gain and is measured by applying a step input (d.c.) voltage. Slew rate is sometimes given indirectly as output voltage swing as a function of frequency or as voltage follower large signal pulse response. The slew rate of an Op-Amp is fixed therefore, if the slope requirements of the output signal are greater than the slew rate, the distortion occurs. Thus slew rate is one of the important factors in selecting the Op-Amp for a.c. applications, particularly high frequencies.

Power consumption Pc is the amount of quiescent power (Vin = Ov) that must be consumed by the Op-Amp in order to operate properly. The amount of power consumed by the 741C is 85mW.

EXPERIMENT

To test the Op-Amp parameters the circuit shown in figures 1 through 6 were set up and the appropriate voltages were measured. Prior to that a SPICE analysis was performed for each of the aforementioned circuits. The SPICE output files for each analysis is shown in the appendix.

FIGURES

OOTPL)T ô~se-r g4~ Vot.TA”E VOLTAC’e V~o V00

VIAIi +qy

-iv t€P.MI~ - VOLTA G~AI~J eoP3F ,c,UgATiON V ~W2~ VOQr V~Ni 10K-n. VCfr~

tsiE(~,ATi~JI~ VOL TA ~ FEE~SACK POLL o~ER. C,aCLIrr c~&c vii-

VIWI

125 RESULTS

Shown below are the tabulated parameters generated by the SPICE analysis compared to the measured parameters, complete with test conditions and percent difference where applicable.

CONI) SPICE MEASURED % DIFF

input offset voltage Rs=50≤2 15.3uV Vcm=0 output offset voltage -38.2mV -1.56V >100% input voltage range -2.5 to 1.4 output voltage swing Rl=0~2 -4.2 to 5.4 -5.2 to 1.0 supply voltage rejection ratio Rs=50≤2 58.41 dB large signal voltage gain Rl=10K≤~ 1.5K 27 98% common mode gain Vcm=1.0 3.0 0.32 89% Rl= 10K≤~ common mode rejection ratio Rs=50≤2 54dB 38bB 30% power consumption Vin=0 13.2mW slew rate Rl=0~2 0.58V/usec 0.14V/usec 76% Av=1.0

DISCUSSION OF RESULTS

The SPICE analysis served to fully characterized the All Enhancement Pmos Op-Amp. Given ideal process conditions this design will produce and operational amplifier capable of a 15.3uV input offset voltage, -38.2mV output offset voltage, -2.5V to 1.4V input voltage range, -4.2V to 5.4V output voltage swing, 58.4dB SVRR, 1.5K large signal voltage gain, 3.0 common mode gain, 54dB CMRR, 13.2mW power consumption, and a 0.58V/usec slew rate.

Note that the input bias current and offset current were not characterized due to their insignificance when using Pmos Op-Amps. The inputs terminals are actual Pmos gates in which very negligible current flows by definition. In comparison to typical Op-Amp parameters the input offset voltage obtained was very low. This implies a good match at the input terminals, which is quite believable considering that the transistors used were Pmos and not Bipolar. Pmos transistors provided a higher input resistance and a negligible offset current at the input terminals. The range of input voltage that can be applied common mode without disturbing the proper functioning of the Op-Amp generated by SPICE was -2.5V to 1 .4V. This input range is non-symmetric about zero volts and might suggest that a few transistor channel ratio changes are in order. These changes might also help the output voltage swing of -4.2V to 5.4V. This voltage range means that the output voltage is directly proportional to the input difference & gain only until it reaches the saturation voltages and thereafter output voltage remains constant. When calculating the large signal and common mode gain of 1.5k and 3.0 respectively, the inputs had to be within the appropriate ranges to avoid the clipping of the output. This clipping effect will cause invalid voltage gains to be measured. The large signal voltage gain obtained by SPICE, however, was very low. This produced a common mode rejection ratio that 126 was also low. Since the CMRR is a measure of the degree of matching between the two input terminals, a high ratio would be expected to correspond to the low input offset voltage obtained. This, however, was not the case. Typical Op-Amp power consumption ranges from 75mW to 165mW. The SPICE analysis determined the device dissipates a low 13.2mW, which is a very favorable consumption. The slew rate obtained was 0.58V/usec. This value is usually merited depending on it’s intended a.c. application. As predicted, the ideal characteristics provided by SPICE for the given design were not fully present in the fabricated circuit. The realized Op-Amp produced a - l.56V input offset voltage, -5.2V to 1.OV output voltage swing, 27 unit large signal voltage gain, and 0.32 unit common mode gain. Due to the small voltages envolved, in addition to the apparent poor fabrication of the device, these were the only measurable parameters. Appendix E shows the output voltage obtained by the Op-Amp in the Voltage Follower configuration for the specified input. Theoretically the output should follow the input over the operating input voltage range. However, the output remains constant at 0.82V for negative input voltages up to 1.5V, at which point it then begins to follow the input. This effect might be explained by any number of process considerations. The output transfer function for the Op-Amp connected in the negative feedback configuration is also shown in appendix E. The transfer characteristic is accurate for negative feedback, however the output voltage swing is offset for both positive and negative voltages.

CONCLUSION

The designed All Enhancement Pmos Operational Amplifier has shown favorable device characteristics for applications desiring low power consumption, low voltage gain, low input offset voltage, and high input resistance. When the actual Op-Amp circuit was realized, the ideal parameters where not fully present, due primarily to the fabrication imperfections. Furthermore, an optimization of the circuit design, which can be realized by reassigning transistor channel ratios, may prove to enhance the existing input voltage range, and output voltage swing.

REFERENCES 1. Jacob Miliman: “Microelectronics”, Chapter 15, McGraw-Hill Book Company, New York, 1979. 2. Ramakant A. Gayakwad: “Op-Amps and Linear Integrated Circuits, Prentice Hall, New Jersey, 1988

3. K.R. Roberge: “Operational Amplifiers: Theory and Practice”, John Wiley and Sons, Inc., New York, 1975.

ACKNOWLEDGMENTS

R. Pearson: for providing insight on the methodology of my testing and analysis. L. Fuller for providing the Op-Amp design to fabricate and characterize.

127 ______1M~ APPENDIX

APPENDIX A Circuit Schematic of the All Enhancement P-type Op-Amp.

r,c, t.

APPENDIX B Layout Design for the Op-Amp.

?~ib5 O~/1MP

APPENDIX C Alternate Layout Design for the Op-Amp with test structures.

I’D ~ EU~W D mm ~E~t~ti —

H ~rn~mH m~E m 128 APPENDIX D SPICE Simulations for the Op-Amp Voltage Follower and Negative Feedback Circuit.

2.1*_It 4l444~ fl 40.1 4144*0412 4412.14*41.4..4

401*9114207 - 40.704* blCW *9*2 Ii 410 - 44*5 40201

.4—4 4*0144*1 14241111 *040*0 - 12.424 0*

4*44*1 4424*122 04 *020*0? — 21 444 . 44.24. 1047 *011* 97404 *0*4.4*11 494*4*200191= * — 2=49 (4*424

—. *0.2 22241*0 *0401.2*0 . 12.ll• 00 — 2*1* 1.244*0 4*4004.1 - 2~~2 0 SLEW RATE 1 0.55 %9.

TX 90442

Ill) 24 4*4 9,4.1 2-42111.4,4 23.200 44.11490.1141fl.41 *1 II II 222 444 1*41 2.4401.1(21 44.1*4* *8.122*9I.14*2 91.4424

,.e 2 4 2 14. 9,aa 2—Ill 44424* 44.11419 43.194*4 (4.1*4* fl.114*S

- 9.120-04 I.I2=.•I . I: 4079 flTI~ 44*1 1*17* 49 Ml 144211 *090? 1., 49 ? 124 92021 2.111 4.4*4* 44.412* 41.2144* 91.144099.4142 I ~ l.1240-•l - 1.1*01* 1.1714-41 - 1.24044 2.1.40.4* - ~ 012 III III 22 142 94021 2.440 ...4044•444*4*44141440.I84*p*-4442 ~ ~ =

011 422 1*2 *4 422 9,444 2.1* 41*144-124* 48.44*499.4440 9:1*1*4 2.4240.40 2.2*20-41 - .4*4* 9*~14* 9*9 4444.4*24 9.144041 4.2*0-2* *141 4 I 290 94*40*4 1 1*1*1 4 4 1*440 124* 49420—a 4.122 - :101014*29294*3 .:...... 1.4,40—42 .400 4*444 — tflfl.1 0-lfl1 l.74*—4l 191.11=44.I1444.74 1.9.129.44.1.1=294.4.15* 2.174041 4.220-21 -

1.1400.24 4.1*40-lI - 14400.2414 0W Yav.a Fou.o..cg 0.9210-41

.*92Wl .44.2 4*1 2.7240.41 1.2714-41 - —- *249912*9*4* 4* 1.40*4-21

4.9444.24 2.400-41 - 4.1*0.41 2.47041 . —

4924040.1 4400*22 14111 404.4-44 0.1.0.40 1.4740.44 - _I_ 94*4* -49*1.2249494*42004~49~ ~W,bl, — 720.24 9940440 494*40.1 *11* 412,4•,2*44

— 1001 - 002242 49 01 M8( Wile - 9.04444*72

4244 4* ~ 2*10 4441.92*0 - 27.112 *0 Vo4.~o1c 1.2,4000

:: ~‘ 114407/O**’tP9T ~ 4r~oi.w (40...~/041Po7) .4* 99122 Feots*c,c ,4.4______4.l*44 —2*4044° •.4l*~44 2.4404* 4.1*041* ..:..S..4 .2.1(24~44 . 4 - . . — ~ 1:~~: ..~.-5_il~i~74: APPENDIX F

~ ~C~n

Table 154 Typical parameters of monolithic 4.144044, .1.140-fl - - I operational amplifier at 25°C 1.111041 22141.44 - . - X . - 9.4440.44 1.1*44-41 . , . . I . - Input o(100t voltage V_ 5 mV Input offset current 144 20 nA i.s.o.— ldIl*.28 . . - .4* — Input bun current!, lOOnA 2.40-l4 4.444*244 . . . 4° 1.4440142 2.4121.44 . - . . 4 100dB L~.42 4.4449.42 . . . . * Cousmon-mode rejection ratio p 4A4022 2.41.044 . - . . 4 PSRR 20j4V/V I,, dot 01 siA/C I’49 dolt 5i0v/.c Slew tate I V/jos Unity pin frequency J MHZ Full-power bandwidth 50kHZ Open-loop difference gain A~ I00,000 Open-loop output resistance R 1000 Open-loop input resistance R~ I MO R~fora3FETinput stage 10110 APPENDIX £ Measured Output Characteristics for the Voltage Follower and Negative Feedback Circuit.

****** GRAPHICS P1.OT *~- .***** GRAPHICS PLOT *~**** NEGATiVE FEEDBACK ~.‘DLTACE FDLL0W0~ V2_4l~I2I. YXI V2_Il*121. VMI VS .C15 C V) 0* CII C V) 4.111*0 .7*21* tIo..r 01497 MARI4ILR 1 2. 0000V —5. 013.9k ~ —*0. SOC. . - I4ARKER( I. 6000V 9132V ) 512_I .-S.OIOVV SIp IC. CCC’ 5. 040 1 — I II 29*4 •.0000V 2.450.~~iET-1.. .~‘E[Z’Ei 19*p ~ Sl..p .~0V I I

C1172901101 VI -CII ~CV dzE:1i~ r:r:i~~ VS -CbS .25001 VI ~O*) .000C* Vi .013 .00004 04 —094 .00001 04 —024 .~00 05* 941 —I. 00001 VII -.9.1 —1. 00001 y~ -Vol 5.00001 ~--i_ ~‘--~--AHi VIZ -0.5 1.50001 L~tEf~

.8203~ -i--I~-- --1— -~ ~ .‘div~---1- ~ .._-

0~E~itrE ~1:±1’ .._LJ_ .1. —10.00 0 10.00 5.040 V2 2.000/div C V) VI .6300/div ( V) 129 IMAGE REVERSAL OPTIMIZATION AND A POSITIVE TONE LIFT-OFF PROCESS WITH AZ5214-E PHOTORESIST

Robert C. Lindstedt 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

An optimum reversal process utilizing AZ5214-E photoresist has been defined with respect to profile angle along with statistical modeling of critical variables on the resulting resist profile. A novel positive tone lift-off process was also attempted with AZ5214-E with limited sUccess.

INTRODUCTION

As semiconductor geometries approach the submicron regime, there exists the need for an imaging technique which is capable of printing submicron features with a wide process latitude and better film properties [1]. Methods that are capable of printing in the submicron range include X-ray and direct write E-beam exposure tools, high numerical aperture and shorter wavelength steppers, and image reversal techniques of positive working photoresists. With the exception of image reversal techniques, all the methods mentioned involve using an exposure tool that is not commonly found in high volume semiconductor manufacturing. Image reversal techniques have the advantage over conventional positive resist schemes in that they exhibit greater resolution, a wider process latitude, higher thermal stability, and higher contrasts [1],[2],[3J. These benefits are however at the expense of increased processing time due to the steps necessary to obtain a reversed image.

Early image reversal techniques were not manufacturable due to the increased number of processing steps significantly impacting device throughput. The reversal method fitting this category involves treating a positive working photoresist with heat and an alkali amine after the normal exposure step. The exposed regions form indene carboxylic acid and when treated with the amine in the presence of heat form indene, which is insoluble in aqueous base and photofunctionally inactive. The unexposed regions are not affected by the amine, and a subsequent blanket exposure converts the photoactive compound to the aqueous base soluble indene-carboxylic acid. Development in an aqueous base solution removes the indene carboxylic acid, leaving the initially exposed region in place [2]. The disadvantages of this approach include the increased processing steps involved with the amine treatment and flood exposure.

130 ______A C A

AZ5214 photoresist can produce a positive or negative image depending upon the processing conditions [l],[2],[3],[4]. Under normal processing conditions, the AZ5214 functions as a high resolution positive working photoresist sensitive in the near

(365 - 405nm) and mid-ultraviolet (310 - 365nm) spectrums. It is also sensitive at the commonly used G-line (436nm), but a penalty in terms of photospeed must be paid [2]. In order to obtain a negative tone image it is not necessary to treat the exposed resist to an alkali amine. Two documented methods to obtain a reversed image with AZ5214 are to treat the exposed resist to a post-exposure bake (PEB) prior to development and to treat the exposed resist with a PEB and flood exposure prior to development. [1],[3]. Thus, the complexity and the time penalty of the amine step is removed from processing.

Using the above technique, the most important variables in obtaining a reversed image are the temperature of the PEB, PEB time, developer concentration and type, and development time [1). Manipulation of these variables allows for the optimization of the reversal process. Upon exposure of the AZ5214 the photoactive compound generates a very strong acid, much stronger than conventional positive resists. The PEB causes the acid to diffuse through the resin system and causes acid catalyzed crosslinking. Submicron geometries can be obtained by controlling the amount of acid generated via exposure, and controlling the temperature and duration of the PEB [4]. A negative image is obtainable with this method, or a flood exposure before development can be added to increase the solubility of the unexposed regions. This image reversal process may be used to obtain profiles that are sufficient for metal lift-off processes. Proper selection of the variables mentioned makes it possible to obtain an image wider at the top than at the base, ideal for a lift-off technique. Figure 1 illustrates the processing steps to obtain a reversed image. a1 C..t Omet cr4 like

INAGE REVERSAj PROCESSING STEPS — — I

at 1 ______t..qeliui E.#..ire FIH Eep.i.re

I I I keel.tAfl27ltF P~1t E~iii~t lake Figure 1: Image Reversal Processing Steps

AZ5214 can also be processed in the positive tone to obtain metal lift-off profiles, without any chemical treatments to modify the resists surface [4]. The use of the resist in this mode involves a novel processing approach. The steps necessary to obtain the positive tone lift-off profile are illustrated in Figure 2. POSITIVE TONG PROCESSING STEPS Solubility 6radaent After 1 Image—Wise Exposure let Resect ar4 lake

Il~ B B B FIc,4 E.pere CI II I~ ~ ______rest E.~.we like kestH Rfl~7 lit

B > C >) 8 > A Figure 2: Figure 3: Positive Tone Lift—off Process Solubility Gradient The initial flood exposure must be low enough to induce acid generation only in the upper surface of the film. A PEB then induces cross-linking at the surface, reducing the photsensitivity of the upper resist regions. A high energy image-wise exposure consequently changes the resists solubility gradient. Figure 3 illustrates the resulting solubility gradient, with the order of maximum to minimum solubility regions given by D, C, A, and B. Thus when developed, an undercut profile can be achieved.

The main objectives of this experiment were to obtain and characterize a workable image reversal process with a wide process latitude using AZS214-E photoresist and to investigate the feasibility of using AZ5214 for metal lift-off applications.

EXPERIMENTAL Since AZ5214 is designed for use in the wavelength range from 310 nm to 405 nm, it was necessary to expose wafers on both a GCA stepper (wavelength = 436nm) and Kaspar aligners

(wavelengths 365 - 436nm) to determine the potential of using either tool. Six wafers were processed for an initial investigation. The starting wafers’ substrates were silicon with 4600 angstroms of Si02. The wafers were prebaked and HUDS was handspun on the wafers. AZ5214-E was handcoated at 4000 RPM for 45 seconds (1.25 micron thickness) and softbaked for 60 seconds at 100 degrees Celsius on a hotplate. An exposure test mask/reticle was used in both cases. This test mask consisted of various size line and space arrays along with test structures, such as focus stars and Murray daggers, that allow for the evaluation of imaging conditions. Three wafers were exposed on a Kaspar aligner at exposure energies of 30,45, and 60 mJ/cm2, while three wafers were exposed with the GCA 4800 stepper. The stepper exposure energies ranged from 20 to 220 mJ/cm2 utilizing an exposure matrix job program. All wafers received a Post-Exposure Bake on a hotplate at 125 degrees Celsius for 30 seconds. A 175 mJ/cm2 flood exposure was performed on the Kaspar aligners, and the wafers were developed in prediluted AZ327 MIF developer until visually clear. The PEB temperature and time were selected from literature [2). Found in this initial investigation was that both exposure tools yielded a reversed image in the range of conditions selected. An interesting detail that was observed with the wafers exposed with the stepper was that for exposure energies below 80 mJ/cm2, no image remained after development. Since the stepper proved adequate in obtaining a reversed image, all further image-wise exposures were performed on it, while the flood exposure step was performed on the Kasper aligners because of its ease of use. The purpose of using the stepper as the exposure tool was due to its ability to yield data quicker than the aligners, and steppers of the wavelength 436 nm are commonly found in production environments.

132 The software package RSDiscover (RS/1) was then used to generate an Inscribed Central Composite (CCI) Experimental Design of the factors exposure energy, PEB temperature and time, and development time, with responses of resolution and resist profile angle. This design type was selected as it allows for five levels of each factor to be investigated while determining response surfaces which best model the obtained results. From this model, predictions can be made as of the effect of the variables on the selected response and also give insight on different variable combinations. The RSDiscover generated design was then ran (experimental trial runs can be found in Figure A in the appendix). Summarised in Table 1 is the range of levels for each factor

used in the design. _____ FACTOR RARE RANGE I~4TTS

Exposur. 250 to JIc..~ En.rgy 190 P28 220 to D.gre.s T..p.ratur. 1’.0 Cr1siu~ PEE Ti.. 20 to S.conds (HOTPLATE) 60

Develop Ti.. 45 to Eeoo,.de (AZ 327 MIF) 105

Table 1 Variables and Ranges Investigated

Cross-sectional analysis of the resist sidewall profiles was then performed with an International Scientific Instruments scanning electron microscope. The responses of resolution and profile angle were then modeled with RSDiscover. For comparison purposes AZ5214 was processed in the positive mode and compared to the optimum condition of the reversed mode. Positive tone processing consisted of identical coating and softbaking steps as the reversal mode, with the exception of no flood exposure or PEB. For the positive mode, a focus-exposure matrix was performed on a GCA 4800 stepper, development was with I4icroposit 351 in a (3.5:1) solution for 35 minutes, and microscopic inspection yielded the maximum resolution. A Nanometrics Nanospec yielded thickness information necessary for determination of the characteristic curves for both modes.

Five wafers were processed in the positive tone lift-off mode. Table 2 illustrates the variables investigated and the levels of each.

Table 2: Positive Tone Lift-Off Variables

133 Specific processing steps included a 40 second spin coating at 4000 RPM (1.25 micron thickness), a softbake at 95 degrees celsius for 90 seconds, a reversal bake at 115 degrees celsius for 90 seconds, and development with Microposit 351 in a dilution of (5:1). The samples were examined with the SEM to determine the processes success.

RESULTS/DISCUSSION

All combinations performed in the CCI design resulted in reversed images. Some combinations however exhibited slight under development. The reversal process was determined to resolve equal line-space pairs of approximately 2.0 microns. Resolution test structures (Murray Daggers) resolved features down to 0.7 microns, indicating submicron capability with AZ5214. Cross-sectional analysis revealed sidewall profiles exceeding 80 degrees could be obtained at the 2.0 micron level. However, no combination yielded a negatively sloped profile as as desired. Figure 4 illustrates a 2.0 micron line-space pair cross-section with a sidewall profile of approximately 82 degrees.

Figure 4: 2.0 micron Line/space 82 Degree Profile

The RSDiscover modeling yielded mixed results. The surface fitted to the response of sidewall profile fit extremely well with an R-squared value of 0.97. This value indicated that 97 percent of the variation exhibited in the experiment was explained by the model. The optimization function was performed for the sidewall profile angle. The greatest angle the model predicted that could be obtained was 86 degrees, which would

134 occur at an exposure of 168 mJ/cm2, a PEB of 126 degrees for 33 seconds, and development time of 71 seconds. Contour plots of PEB time versus temperature at the optimum exposure energy and develop time revealed that the PEB temperature could vary from 120 to 131 degrees, and the PEB time could vary from 25 to 45 seconds and still maintain profiles of 80 degrees or better. Thus there is a wide process latitude for the PEB temperature and time variables at the optimum exposure and develop time. Inconclusive results were obtained for the response of resolution. R-squared values below 0.90 were obtained when the regression model was initially fit. Because of this, several trials were removed from the experiment to obtain a model with an acceptable R-squared value greater than 0.90. The optimi2ation function was ran and a negative resolution value was given, which led to the conclusion that something was seriously wrong and the resolution response could not be accurately modeled from the data obtained in the experiment. Figure S illustrates the contour plot for the response of profile angle at the optimum exposure and development time. A three dimensional plot of the response surface may be found in Figure B of the appendix. pr.fll._1t41.. !XC1U.~fl - £II.~I. OSv.1C.2I.. - 7L.4O~

p I

I I

— ~fl1M~Z — ,mLmX~4 Figure 5: Contour Plot of Profile Angle Response

Table 3 illustrates the results of the comparison between the positive and reversed (negative tone) modes, with the reversal mode demonstrating superior resolution, contrast, and photospeed. The characteristic curves for both modes may be found in Figure C of the appendix. COMPARISON OF POSITIVE AND NEGATIVE TONE (Reversal) PROCESSES USING AZ 5214—E PHOTORESIST

Table 3: Positive/Reversal Comparison

135 The positive tone lift-off process was of little success. The combinations ran resulted in near vertical sidewall profiles. This leads to the conclusion that the variable combinations were not correct, or the developer type, concentration or time should have been different. However, the near vertical profiles warrants a future investigation with a stronger developer, such as AZ400K, or a stronger dilution of Microposit 351 to H20.

CO$CLUSIONS A range of process conditions and a optimum condition for vertical profiles have been defined which result in image reversal of AZ5214-E photoresist. Resolution of 2.0 micron equal line-space pairs was obtained with resolution test structures indicating submicron capability. Resist profiles exceeding 80 degrees can also be obtained without sacrificing resolution. Variable effects were successfully modeled on the response of resist profile angle with the software package RSDiscover. The reversed mode demonstrated superior resolution, contrast, and photospeed compared to the positive tone process. The positive tone lift-off experimentation exhibited vertical profiles, which are not adequate for a repeatable lift-off process. In summary, a successful image reversal process has been defined while the use of AZS214-E for lift-off profiles needs further experimentation.

ACKNOWLEDGMENTS I would like to acknowlege the great amount of inputs and assistance that I received on the project from Katherine Hesler and Bruce Smith of the Microelectronic Engineering faculty and Dr. Thomas Frederick for his assistance with the SEM.

REFERENCES [1] Marriott, V, C.M. Garza, and N. Spak, “Image Reversal: A Practical Approach to Submicron Lithography”, SPIE Advances in Resist Processing and Technology, 1987.

[2] Balch, E.W., S.E. Weaver, R.J. Saia, “CharacteriEation of a Submicron Image Reversal Process”, SPIE, 1988. [3] Spak, 14., D. Mammato, S. Jam, and D., Durham, “Mechanism and Lithographic Evaluation of Image Reversal in AZ 5214 Photoresist”, VII mt. Tec. Photo Polymer Con., 1985.

[4] Dunbobbin, D.R., and 3. Fagnet, “Single-Step, Positive-Tone, Lift-Off Process Using AZ 52l4-E Resist”, 1988.

136 GREEDY CHANNEL ROUTER IMPLEMENTATION IN FORTRAN Ray S. Linton 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

During this project, the Greedy Channel Router was implemented in FORTRAN. This will allow students to break their general routing problems into channel routing problems to be done by the program. Since many students know FORTRAN, it will also be possible to build on the program and develop a more general router in the future [1]..

I NTRODUCT ION The main goal of any routing scheme is to join all pins having the same electrical node number. It is generally desirable to route the wiring paths efficiently. This is especially true in the design of an integrated circuit since a smaller chip is less costly and operates at a faster speed. Thus, a second goal of a router should be to minimize the use of chip real estate. The router should be implemented on a computer in such a way as to make it reliable and repeatable, since a third goal is to achieve design automation. Specifically, a channel router wires between two parallel pin sets within a rectangular bounding box. These pins may belong to IC functional cells or gate arrays. Joining all pins with the same node will effectively join the cells. To accomplish this wiring, two levels of conduction paths are needed. One level is used for vertical wires while the second is used for horizontal wires. The horizontal and vertical wires do not short when they cross over each other due to an insulating layer between them. A via may be made in the insulating layer when it is desired to have a horizontal/vertical connection. The upper conduction path is usually a metal, such as aluminum. The lover conduction path may consist of a diffusion, doped polysilicon, or a metal. The insulating layer usually is silicon dioxide. The vertical wiring is done in a column, and the horizontal wiring is done in tracks. The number of tracks defines the channel width. A channel router may be part of a more general area routing scheme. The area router first breaks a general problem into pieces or component channels. The channel router then performs each partial routing. The area router joins all the solutions together to form the final routing solution [2]. In this case, the area routing package is only as effective as the channel router.

137 During this project, the Greedy Channel Router was implemented in VAX FORTRAN. The Greedy Router has several advantages over other channel routers. The algorithm uses a left to right, column by column approach. This avoids vertical wiring problems and makes the computer code easier to understand and modify. Other routers, such as Deutsch’s Dogleg, have difficulty when there are vertical cycles in the pin net numbers. For instance, a cycle would be a pin set (topbottom) of 1,2 followed by a pin set 2,1 in a future column. The node 1 has to cross the channel as well as the node 2. The Greedy Algorithm can deal with this situation, if necessary, by extending the right end of the channel and joining the nodes in a spill over region [2]. The algorithm is also unique in that it allows a node to occupy more than one track at a time. This allows conflicts to be resolved in a later column. If the channel proves to be too narrow to bring in a new node number from a pin, other channel routers do not complete. The Greedy Router can automatically widen the channel when it runs out of room. In fact, the authors claim that a proper implementation of the algorithm will yield a program that always completes a routing. Routers such as Deutsch’s Dogleg, the Revised Dogleg, and the Least Cost Path algorithm do not have these automatic adaptability features. Other channel routers are also significantly more difficult to implement [3).

The input to the Greedy Router is a list of net numbers belonging to pins along the channel. A top and bottom pin in the channel defines a column. The router performs a series of six steps for each column. These steps are done in order of priority. Once the router completes a column, it never returns. Figure 1 illustrates these steps with before and after diagrams. Step one performs minimal pin connections by bringing the pins in the current column into the channel. If a track with a pin’s net number exists, the pin may be connected to it. However, if an empty track is closer, a new track with the pin’s net number will be started. Future steps may alter this connection if required. Step two attempts to join all tracks having a given net number together. This is called collapsing split nets.’ The collapses which free the largest number of tracks are given priority. Step three attempts to jog all split nets, that could not be collapsed in step two, closer together. Step four jogs tracks towards their target edges. The target edge for a track is either the top or bottom channel edge, based upon where the next pin with the same net number as the track is located. Step five automatically widens the channel if there was no room in step one to bring in new pins. Step six extends all tracks which continue to the right into the next column. It is also necessary to do a wrap up step to determine if the routing is complete. If there are more pin sets, or there are un-collapsed split nets, the six steps must be performed again [4).

138 Figure 1: Greedy Router Steps

0 o1 -~-~ -.~ ale— STEP 1: BASIC PIN CONNECTIONS Connect new pins to an existing track or begin a new track. Use a minimum ~ of vertical wire in alt cases.

STEP 2: COLLAPSE SPLIT NETS —.- —.-- Reduce the number of tracks needed Li.__. by connecting ones having the same electrical net. Optimize by doing ~- ~- net collapses which free the largest number of tracks.

STEP 3: JOG SPLIT NETS 3.—.— 3—, There will be split nets that step two could not collapse together. Lj.._, Lf_..,,, Jog the these tracks closer to each other if possible. 3 STEP 4: JOG TOWARDS TARGET EDGE Move tracks closer to their target 3 :5 edges. A target edge is where the —.-.—.. - next pin with that track’s net number exists. 3— 3-i

STEP 5: ADD NEW TRACKS IF NEEDED If step one failed to wire the new 3 3 pins (due to lack of channel space), ~ 3—_L---->(3) add a new track to the channel and ~ wire the pins now. I — 4 I’ STEP 6: EXTEND TRACKS Terminate all tracks whose net number .___._ —.____.__ does not continue. Extend all active 1 —4-->g’,) 1__!__ tracks to the next column. 1—-->(2) 1 •-->(3)I. -I..— 3 WRAP UP: ARE WE DONE ? If there are more pin sets to do we continue. If we are done, but there are still split nets, continue. Otherwise, we are finished.

139 RESULTS The Greedy Channel Routing Algorithm was implemented in FORTRAN at Rochester Inátitute of Technology using a Digital Equipment Corporation VAX/VMS system. The software consists of a main program called ROUTER and six subroutines. The function of each is described in Figure 2.

FIGURE 2: Parts of the Router Implementation I I I I I I ROUTER Main program, performs six steps I plus wrap up. Calls subroutines. I I I HELPROUT Help facility, displays help files on screen. I I I CHECKRT Checks for pins of a given net number to I I the right of the current column. I I I I EXTEND Extends active tracks into the next column. I I I I TRACKADD Part of step five, widens the channel. I I I I OUTSUB Sends output matrix to a file when called [5]. I I I I OUTSCR Sends output matrix to screen when called. I I Attempts to overlay steps on screen to I permit viewing of the routing in progress. I

There are four help screens a user may view when the program is started. These describe the program, the input variables, the output format, and the references used. Next, the user is prompted for various output options. The user then enters routing parameters and the pin set net numbers along the channel. The program performs the routing and displays the results as desired. Only text characters are used in the output to avoid problems with terminal compatibility. The characters representing vertical lines, horizontal lines, and vias may be easily changed in the main ROUTER program if desired. The router has been successfully implemented. Figure 3 shows a simple channel routing problem, the input pin sets, and the text based output. A visualization of the two conductor levels is also shown. Note that all pins with the same net number have been joined. Different net numbers do not short at any location. The program is capable of adding tracks if needed. The program will also expand the channel to the right by adding null pin sets if there are tracks that could not be joined in the user defined columns. Figur~e 3: A SiMple Routing ProbleM

CeliA Ce11B Ii 4521 2 61036 . .•.—J . •.••• Channel

34 ~Dj F

COLUMN NUMBER 1 2 3 4 S 6 7 6 9 10

TOPPINS 1 4 5 2 2 6 1 0 3 6

BOTTOMPINS 4 5 0 1 4 3 4 0 3 4

TOP PINS 1452261036

TRACK 1 *—--* *——: ————: ——*

TRACK 2 ———*

TRACK 3 I *—:—* I

TRACK 4 ~-: *—41:

TRACK S ~ :—:——* I

TRACK 6 —*—— I —*

BOTTOM PINS 4501434034

TOP PINS 1452261036 R~BB6R RB. TRACK I B ~ll B TRACK 2

TRACK 3 B XJX ~ S B B IF TRACK 4 B ______B TRACK 5 ~ X1F-X ~

TRACK 6 x~~—x £x BR BOTTOM PINS 4501434034 The output of the program may be altered by changing input parameters such as the initial channel width, the minimum jog length, and the steady net constant. In this way, users will be able to optimize the routing done to conform to their applications [6]. The program code includes many comments so that a future programmer may make modifications. A user’s guide and a programmer’s guide are included in the appendix. This, along with the on-line help screens, make the package fairly easy to use.

SUNNARY

The Greedy Channel Router was successfully implemented in FORTRAN. Students will now be able to break their general routing problems into channel routing problems and use the program. This will save effort and serve as a valuable educational tool concerning routers. If the user chooses to display every step on the screen, he/she may watch the program making the wiring decisions. It is easier to understand an algorithm if one can make up an example and watch it run. Since many students learn FORTRAN, it will be possible for users to make modifications and extensions to the program in the future.

REFERENCES

[1] Amar Mukherjee, Introduction to nMos and CMOS VLSI Systems Design, (Prentice-Hall Publishers, New Jersey, 1986), p. 314-324. [2] Amar Mukherjee, Introduction to aMos and CMOS VLSI Systems Design, (Prentice-Hall Publishers, New Jersey, 1986), p. 323-324. [3] Rivest, R. L., and C. N. Fiduccia, “A Greedy Channel Router,” 19th Design Automation Conference, June 1982 (Las Vegas), pp. 418-424. [4] Amar Mukherjee, Introduction to nNos and CMOS VLSI Systems Design, (Prentice-Hall Publishers, New Jersey, 1986), p. 326-333. [5] R. Pearson, Initial OUTSUB Output Subroutine, Rochester Institute of Technology, 1983. [6] Rivest, R. L., and C. N. Fiduccia, “A Greedy Channel Router,” 19th Design Automation Conference, June 1982 (Las Vegas), pp. 418-424.

142 FABRICATION OF AIR-BRIDGES FOR MILLIMETER WAVE INTEGRATED CIRCUITS

Antonio L. Luciami 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

High frequencies and sub-micron geometries inherent in today’s millimeter wave integrated circuits mandate utilization of low capacitance cross-over structures such as the air-bridge. A silicon based aluminum air-bridge fabrication process is described. The structure and capacitances associated with these aluminum air-bridges was evaluated for potential use in the fabrication of integrated circuit acoustical disturbance sensors.

INTRODUCTION

In the last few years much interest has arisen for the research and development of technology for the fabrication of millimeter wave integrated circuits. Possible applications include utilization in the areas of radar,communication, and wideband electronic warfare [1]. Conventionally, substrates such as GaAs and InP have been implemented in the fabrication of millimeter wave integrated circuits [2], but silicon based technology for millimeter wave applications has also been recently researched [3]. As technology pushes the operatinal range of integrated circuits to yet higher frequencies and into the realm of sub-micron dimensions, the need for low capacitance cross-over structures in the various metallization schemes has arisen. One such cross-over is the air-bridge. The air-bridge consists of a higher level metal line traversing a lower level metal line. The air gap is due to the absence of an interlevel dielectric support where the lines actually cross. In short, the higher level metal line forms a bridge over the underlying line by coming off of the substrate. The use of air as the interlevel medium, as opposed to a dielectric such as polymide, reduces the capacitance inherently associated with two conducting “plates”. The reduction in capacitance results from the relative permittivity of air, 1.0, being less than that of an interlevel dielectric, usually in the 2.0 to 3.0 range. The capacitance between two plates is given by the following equation [4].

C (e A)/D

143 ______A\Y______Silicon1stAirMetal ______—1 ______

The area of the capacitor plates (cross-over area) is denoted by A, e is the permittivity of the interlevel medium (resist or air>, and D is the distance between the first and second metal lines forming the air-bridge structure. The area which yields the capacitance due to the bridge is shown in Figure 1.

Side View Top View

—2nd Metal

\\\\\\\\\\\\V v//I! \\\\\\\\\ Oxide -

FIGURE 1: Capacitance Inducing Structure.

The characteristic of the air-bridge which makes it a rather unique candidate for an integrated cir’uit acoustical disturbance sensor is the fact that as the span dimensions, length and width, of the bridge increases with respect to the thickness, flexing of the span can be promoted when subject to an acoustical disturbance such as compression or decompression. This resulting vibration varies the distance between the two metal lines which, in turn, inversely affects the resulting capacitance. Typically, air-bridge structures are composed of a gold film utilizing a titanium-tungsten barrier layer to prevent the diffusion of gold into the GaAs substrate [5]. The process developed here utilizes an all aluminum bridge structure in order to keep processing to a minimum.

E XpE~Lt~j~T A test chip, shown in Figure 2, was designed using the CAD program ICE, the Integrated Circuit Editor developed at RIT. The chip consisted of four quadrants each serving a specific function. Quadrant 1 (upper left) consisted of an assortment of air-bridges of varying dimensions, from 10 to 50 microns wide spanning 50 to 70 micron distances. Quadrant 2 (upper right) contained structures to check the ability of turning in mid-air. Quadrant 3 (lower left) was composed of Mesa to Mesa and serpentine air-bridge structures. Quadrant 4 consisted of 30 and 60 micron wide bridges spanning 50 to 170 micron distances. These were used to measure any possible size to capacitance relationships. The test structures in Quadrant 1 served only to see if a large number of air-bridges could be fabricated successfully. Capacitance values of this large array were not calculated as the only result desired was having no shorts or opens. Quadrant 2 yielded information as to the performance and ability of turning air-bridges. Quadrant 3 was constructed without any “capacitor” structures while Quadrant 4 was created to check capacitances and span capabilities.

144 ___ — I

FIGURE 2: ICE Design Test Chip.

The air-bridge test structures were fabricated on oxide over silicon to insulate the bridges. The first metal layer was thermally evaporated to a thickness of 4300 angstroms. Patterning was accomplished using KTI-B20 positive photoresist with a Kasper aligner as the exposure tool. The dielectric structures consisted of KTI-820 resist at a thickness of 1.1 urn. Patterning was similar to that for the metal layer with the same exposure due to the support structures being predominantly over the first metal lines. Hard-baking of the support structure pattern was identical to that used for the first metal litho graphy to observe if standard processing of the resist would create supports capable of withstanding the evaporation process. The second metal was processed similar to the first. After the second metal was patterned initial capacitance measurements were made, with the support resist intact,using a Princeton Applied Research Model 410 high frequency capacitance-voltage plotter with the d.c. value set to zero. The wafers were then plasma ashed for a total of 15 minutes to insure complete removal of the resist support structures. After plasma ashing a few bridge structures were randomly torn away, using a probe, while being observed under a microscope to validate that all the supporting resist was indeed removed. Figure 3 shows the process steps for creating standard air-bridges and Mesa to Mesa air-bridges.

145 ______Slhco~______4-SWccii04thOxidelit Metal ______&licon______Silicon

Standard Air-Bridge Mesa to Mesa

e-S~lkoc

lit Metal litMetal t?717A O~de V777A o~de

~— Ru~ litMetal ~ litMetal

~d Metal ~d Metal

:~:

Metal ~d Metal ~ \\\\\\\\\\\\V V77771 ‘~~\\\\\\\\\\\‘ oxite ~ FIGURE 3: Process Diagrams of Air-Bridges.

RESULTS/DISCUSSION

Table 1 show the calculated capacitance values of the air-bridge structures, if applicable, as well as the average measured values and range. Permittivity of the resist was approximated at 2.72.

IT~BLE 1 I - Theoretical Measured I I I Area -Capacitance (pf) Capailtance (pf) I IQuad. I * I (lOe-6cm2) I(with resistlw/o) I(with resistlw/o) I

I 1 I 1 I N/A N/A I 11.9 3.56 1 I 1 I 2 N/A I N/A I 7.82 9.81 I

I 2 I 1 I 213 I .467 .171 I 1.96 2.85 I I 2 I 2 I 152.5 I .334 .123 1.17 2.03 I

I 4 I 1 I 9 .019 .007 I .67 .97 I I 4 I 2 18 I .038 .014 I .72 .94 I 4 I 3 18 I .038 .014 I .73 .99 I I 4 I 4 I 36 I .079 .029 .70 .99 I I 4 I 5 I 27 I .060 .022 I .63 .93 I I 4 I 6 I 54 I .117 .043 I .69 1.10 I I 4 I 7 I 90 I .196 .072 I .98 1.34 I I 4 I 8 I 45 I .098 .036 I .89 1.02 I I 4 I 9 72 I .158 .058 I .77 2.07 I I 4 110 I 36 I .079 .029 I .73 1.44 I I 4 Iii I 54 I .117 .043 I .78 1.47 I I 4 112 I 27 .060 .022 I .69 1.55 I

146 CapacLtance vs. Area FiLumLnum 9Lr—6ri~d~es at I~IT

0: ~ ..34i~k Q: ~.i.4,L .qj4~ ~ ~: ~ ,~1ii~ •ts~J~~ Lfl 4 ~~~

+ CN a)

0o 0~ + C C) In

C 25 50 75 iCC 125 150 175 2CC Firec (lOe—6 cm2)

FIGURE 4: Capacitance vs. Size of Air-Bridge.

A plot of the data gathered regarding the capacitance versus size relationship is shown in Figure 4. The plot shows the theoretical as well a ~mea~. ired relationships. The theoretical values show a linear dependence due to the variation of the area of the bridge only. The difference of the slopes for the curve of theoretical with resist and without resist is due to the relative permittivity factor being 1 for no resist present and approximately 2.72 with resist. The curves of the actual values indicate the effects of possible stray capacitances incurred in the probe leads. Another factor that may contribute to the discrepancies observed could be variations in the distance between the first and second metal lines, D. This variation could arise from the sagging of the second metal line due to its length to thickness ratio. This assumption of sagging appears to be relatively well supported by the upward curve of the measured value plots. This upward curve is indicative of a faster increase in the slope which infers a more rapid increase in related capacitance as the size of the bridge “capacitor” increases. Also the presence of undulations in the spans after removal of the support resist is a contributing factor. Functioning as an acoustical disturbance sensor, of possibly a miniature microphone., it was found that the capacitance did vary when the air-bridges were subject to an acoustic disturbance such as a loud voice or gust of air. Changes in capacitance have been measured ranging from 3.7~ of the original value to a 471~ increase with the average being 44~. 147 CONCLUSI ON

The process developed for creating aluminum air-bridges has shown that air- bridge structures can be fabricated at RIT using established process steps. The air-bridges fabricated cam span distances up to 170 microns (the upper limit of this study) and can turn in mid-air. The capacitances obtained after the removal of the resist support structures suggests that a host of other factors influence the values obtained for the finished structures. Further research in this area is required to achieve production worthy air-bridge structures. Possible avenues for study include thickness of the actual spans and bimetal construction.

ACKNOWLEDGMENTS

Mike Jackson for ideas and supplies, Dr. Fuller for his valuable input and subliminal prodding, Rob Pearson for his insight during initial testing phases, Karen Muniak for her “old stuff”, and Brad Campbell for reading the fine print.

REFERENCES

[1] Binari, Neidert, Keiner, and Boos, 3.8. “Millimeter-Wave Passive Circuit Components”. RCA Review. Vol. 45, December 1984. pp. 579-586. [2) Niedert, R.E. and Binari, S.C. “mm-Wave Passive Componenets for Monolithic Circuits”. Microwave Journal. April 1984 pp. 103-120.

[3] Stabile, P.3. and Rosen, A. “A Silicon Technology for Millimeter W~ie Monolithic Circuits”. RCA Review. Vol. 45, December 1984. pp.587-605.

[4) Pierret, R.F. Modular Series On Solid State Devices, Volume 4: Field Effect Devices. Addison-Wesley Publishing Company. Reading, Mass. 1983. pp.43-47.

[5] Andrade, T. “Manufacturing Technology for GaAs Mololithic Microwave Integrated Circuits”. Solid State Technology. February 1985. pp. 199-205.

148 CONSTRUCTION OF A QUASI—STATIC C—V TEST STATION

Randall 3. Mason 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

The construction of a Quasi—Static C—V measurement tool and proper operation are presented. Gate oxides were analyzed for ion implanted regions. Guidelines for obtaining higher quality Quasi—Static C—V measurements will be presented.

INTRODUCT ION The physical and electrical properties of the metal—oxide—semiconductor (MOS) capacitor are the cornerstone to building, developing, and monitoring a MOS process. New processes such as plasma etching, rapid thermal processing (RTP), and e—beam lithography are placing increased concerns on the quality of gate oxides. The MOS capacitor is widely used to evaluate gate oxides because it has a simple structure and can be easily fabricated. Quasi—Static C—V curves of the MOS capacitor can be used to determine such properties as:

1. Oxide Thickness 2. Charges in the Oxide 3. Work Function Differences 4. Interface Trap Densities 5. Properties of Electron and Hole traps Of these parameters the Quasi—Static C—V curves are used primarily for measuring interface trap densities and the distribution of these traps across the bandgap. Quasi—Static (Q—S) C—V curves can be obtained by several methods. One common method is to use an extremely low frequency signal and monitor the change in current as a function of voltage variations. Typical frequencies range on the order of 10hz and below, due to the long minority carrier lifetimes in device quality silicon. An alternative method involves ramping an applied voltage slowly and monitoring the displacement current in the MOS capacitor. This technique (developed by M. Kuhn [11) enables MOS capacitors with long minority carrier lifetimes to be evaluated.

A low frequency curve is similar to a high frequency (1Mhz) C—V curve until the onset of inversion in the MOS capacitor. Figure 1 shows the difference between a high frequency and low frequency curve. In a high frequency C-V curve the minority

149 carriers are unable to respond to the changes in the AC signal thus the depletion region edge expands and contracts. In a 0—S C—V curve the minority carriers are able to respond to the variations in the applied voltage. Therefore the capacitance rises back up to the oxide capacitance after strong inversion of the surface of the semiconductor has taken place. If the applied voltage is varied to quickly a C—V curve which lies between the true low frequency and high frequency curves will be the result, because not all of the minority carriers are in equilibrium.

VG.(VDh$)

Figure 1: Ideal High Frequency and Low Frequency Curves

Concentrating on the displacement current technique, the measured current (I) in the MOS capacitor is proportional to the voltage ramp rate (dV/dt).

I = Capacitance/(dV/dt)

An electrometer must be used to measure the displacement current due to the extremely small currents associated with lower voltage ramp rates. Currents on the order of several picoamps are typical for low voltage ramp rates of 3 to 5mv/sec. A properly designed and shielded probe station is essential to generating accurate high frequency C—V curves but is necessitated for a Quasi—Static test station. A Faraday cage is required to shield the device under test (OUT) from external fields. The Faraday cage must enclose the DUT entirely, shield the MOS capacitor from light, and must be electrically conductive. Light must be shielded from the device to prevent the generation of minority carriers under the capacitor. Ground loops must be avoided in the design of the test station. The electrometer is accurate enough to measure currents flowing in such loops. Ground loops can be avoided by having one central test station ground and connecting all other grounds directly to the test station ground only once. The shielded cables used for all conductors in the current path were tied directly to ground also.

150 While Quasi—Static C—V measurement techniques are susceptible to parasitic resistances and capacitances shielded cables are appropriate. Care should be taken in choosing the coaxial cables. A total resistance from the core to the shield should be greater than 1e12 ohms over the entire path of the circuit. The coaxial cable should be anchored to prevent movement. When coaxial cable vibrates the shield can generate triboelectric currents this can be avoided by using cable in which the shield is lubricated with graphite [21. Cable lengths should be minimized to prevent parasitic impedances from affecting the Quasi—Static C—V measurement. Any cable only acts to degrade the signal no matter how long or short. The drawbacks to the Quasi—Static C—V technique are the non—idealities associated with the resultant curve. A higher current than theoretically expected is often observed with slower voltage ramp rates. This is due to parasitic capacitances in the measurement tool. One will also note that the curve may be slightly tilted. This is due to parasitic resistances in the measurement tool. This can be minimized by using a higher rate of change in the applied voltage. The measured curve can be the additive result of the real low frequency curve, an offset current due to parasitic capacitances, and a slight tilt due to the parasitic resistances. The following equation describes the capacitance at any point on the Q—S C—V curve.

C = [I — (Va/Rp)1/(dV/dt) — Cp

This equation takes into account the offset due to the parasitic capacitances (Cp), and the tilt due to the current drawn by parasitic resistances, Va/Rp, where Va is the applied voltage.

EXPERIMENT

The voltage ramp circuit shown below was used to generate the applied voltage. This circuit was built to provide a linear voltage ramp rate which would remain constant regardless of the magnitude or polarity of the output voltage. I~Is

Icoh

2Sk IZAgI /JIeI~~ 500

Figure 2: voltage Ramp Circuit Schematic

The circuit has several additional features to aid in the characterization of MOS capacitors or in the trouble shooting of

151 the test equipment. The voltage ramp rate can be varied by both a fine and course controls. This allows faster voltage ramp rates to be used when measuring devices with shorter minority carrier lifetimes. The voltage can be ramped in both directions between +16 volts and —16 volts. This allows one to plot the 0—S C—V curve in both the positive and negative directions which aids when adjusting the measurements for parasitic impedances. The voltage ramp can be stopped at any time. This can be a useful feature in ionic contamination studies or in oxide charging experiments. The output of this circuit was buffered to help isolate the circuit from noise which might be picked up on the output cables. The circuit is battery powered to provide a noiseless DC voltage, and eliminate any AC signals from within the box. An external DC power supply was not used because the input leads would be susceptible to noise from the environment and ripple voltage on the DC level.

RESULTS/DISCUSSION The circuit which was designed to generate the voltage ramp was found to be controllable and extremely immune to noise. The parasitic shunt resistance was determined to be on the order of 1e12 ohms. This was not significant until the voltage ramp was decreased below lOmV/sec. The voltage ramp rate was linear through zero and did not vary by more than 5 percent across the desired range. The ramp voltage hold switch did not function to the desired standards. When the hold function was initiated the voltage would decrease in magnitude at approximately lmV/sec. This is believed to be due to leakage in the integrator capacitors. Several Q—S C—V curves have been generated with different ramp rates. Shown below are two Q—S C—V curves, one ideal curve and one measured curve. Notice that the measured curve is tilted slightly in the parasitic resistance example.

PorosLt~Lc CpDocLtpnce ExomDLe ~I4~cho.L fi. JOC)%a04l a

4 U U

- 0 .+ GATE IêAS

Figure 3: Parasitic Impedance Effects on 0—S C—V Curves [3]

152 It was found that if the circuit was allowed to stabilized at the starting voltage for about one minute prior to the measurement a more accurate curve could be generated. Also notice the current offset in the measured curve from the theoretical Q—S C—V curve. This is due to parasitic capacitances in the current loop. The integrator operational amplifier was changed from a 741 op—amp to a FET input op—amp. This was found to decrease the amount of change in the applied voltage when the hold function was initiated.

CONCLUS IONS This project has shown that low frequency C—V measurements can be made using a Quasi—Static technique. The attention to detail when designing the Faraday cage was demonstrated by the test stations excellent immunity to external noise. The non—idealities associated with the Quasi—Static C—V measurement technique were not apparent until the lowest voltage ramp rates were used. The electrometer also proved to be an accurate instrument when measuring currents in the lpA to 5OpA range. In the future a short triaxial cable leading to the electrometer may even increase the immunity to external noise.

ACKNOWLE DGMENTS Special thanks are extended to Michael A. Jackson for his help in designing the voltage ramp circuit and raising various concerns which had to be addressed to guarantee a “clean” Quasi—Static C—V curve. Other individuals who contributed to the success of this project were Florence Layton for her donation of the equipment used to construct the Faraday cage and Professor A. Reithmeier for his advice on designing circuits to measure the extremely small currents involved with Quasi—Static C—V curves.

REFERENCES

[11 M. Kuhn. Solid State Electronics. Vol 13, 1970. Pp.873—885. [21 Thomas Mego. Research and Development. May 1987. Pp.86—90. [3] E.H. Nicollian, J.R. Brews. MOS Physics and Technology. [4] Herbert S Bennett, Co—authors (4). IEEE Trans. on Elec. Dev. Vol. ED—33, No. 6, June 1986. Pp. 759—765. [5] AS. Grove, B.E. Deal, E.H. Snow, C.T. SAH. Solid State Electronics. Vol 8, 1965. Pp 145—163. [6] David L. Health IEEE Trans. on Elec. Dev. October 1976. Pp. 1191—1192. [71 Gregg Meyers. Senior Research Project, 1988 [81 M.A. Jackson, W.A. Anderson. Eighth Biennial University, Government, and Industry Microelectronics Symposium. Software and Hardware Developement for C—V Analysis. [91 E.H. Nicollian, A. Goetzberger. Bell System Tech. Jou. Vol XLVI, No. 6, July—Aug. 1967. Pp 1055—1133.

153 PLASMA ETCH OPTIMIZATION OF SILICON DIOXIDE WITH A RESIST MASK

Eric P. Meister Fifth Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

A dry etch process was developed and characterized to etch silicon dioxide (Si02). Characterization included increasing the etch rate o-f Si02 while decreasing the etch rate of a KTIB2O positive photoresist mask, which is used in RIT’s fabrication processes. Successful masking and etching of silicon dioxide occurred with 15 sccm CHF3 mixed with

6 sccm 02 at a chamber pressure of 750 - 800 mtorr and a power of 100 watts.

ThEQRV

As VLSI geometries become smaller, the need arises for an etch process in which one can control the directionality of the etch. Wet etching systems are available which provide a high selectivity between the substrate and mask, However these systems usually etch isotropically. With linewidths on the order of one to two microns, isotropic etching undercuts the mask and the pattern may be lost, if not greatly altered.

An important advantage of dry etching is the ability to control the direction of etching. By lowering pressures in an rf plasma, processes can combine the chemical reactions found in wet etching with a physical bombardment of the substrate with ions. The sputtering mechanism provides the directionality.

Figure 1 represents a single wafer reactor setup. After a wafer is loaded, chamber pressure is reduced, etchant gases are introduced, and, once stabilized, an rf signal is applied. The primary frequency for this signal is 13.56 MHz. Molecular collisions between the gaseous species create electrons and radicals, and the higher mobility of the electrons with respect to the heavier radicals creates an electric field. The radicals, which are

154 electrically neutral, but in a state of incomplete chemical bonding, are highly reactive and responsible for the chemical etching which occurs.

ças I~I RF Gerierakor

Blocking capacikor

+ $:*.:*..* 4- Plasma

~ ~ ~ Vaf

Figure 1. Plasma reactor set—up Sequencing of the etch can be explained in the following manner. Molecular collisions create the reactive species. The rf induced electric field moves them towards the surface of the wafer where absorbtion can occur. Here the reaction occurs, products desorb and diffuse to the exhaust outlet.

As chamber pressure is reduced to the order of 100 millitorr, processing enters the regime of RIE , or reactive ion etching. Under these parameters, the radicals are still highly reactive. However, after absorbing and reacting, ions present in the plasma sputter off the products from the reaction sites, rather than having them desorb. It is this sputtering process which increases the control over the direction of etch. As pressure in the chamber rises above this value, the mean free path of the ion is reduced, as well as its velocity. Pressures of 400 mtorr or greater produce a completely chemical etch and results in an anisotropic profile similar to a wet chemical etch.

The primary chemistry for the etch of silicon dioxide when using CHF3 (Freon 23) as an etchant can be seen in the following equations.

CHF3 ~ e > CF2 + HF + e (1) 2CF2 + SiD2 > 2CF2D + SiF4 (2)

The CHF3 molecule collides with an electron to create the CF2 radical (eqn 1). The CF2 radical is then available to absorb and react with the Si02 to create products which can desorb and outgas. Equation 1 also demonstrates that HF is a product. The hydrogen acts as a scavenger of fluorine radicals, and it is these radicals which are important to the etch of silicon. Utilizing CHF3 rather than CF4 lowers the concentration of fluorine and lowers the etch rate of silicon. The etch rate of silicon dioxide, however, is not greatly reduced. 155 EXPERIMENT

Preparation for experimentation was essential. First the Tegal 700, the dry etch tool for all tests, was checked for leaks and these leaks were minimized with tube and clamp replacement where necessary. Secondly, mass flow controllers were connected to all gas lines in order to better regulate the flow of desired gases. Previous to this, gases were crudely mixed and flow rates were determined by the number of turns on a particular valve. The mass flow controllers provided more accurate data with respect to actual values.

With the etching tool in optimum order, experimentation began. Twenty 3 inch wafers were obtained, scribed, and subjected to a standard RC~ clean. ~pproximately 4500 angstroms of silicon dioxide, using an 1100 C wet 02 flow for 60 minutes, were grown. Following oxidation, wafers were coated with KTIB2O positive photoresist on the GC~ Wafertrac. They were then exposed using the contact aligner using a striped resist test mask. Following development, the pattern on the wafer was that of alternating stripes, approximately 1/2 inch wide, of resist and oxide. This allowed for selectivity analysis between oxide and resist, as well as uniformity analysis across the wafer.

Experimentation runs utilized these wafers to develop a process which would etch silicon dioxide. Plasmas of CHF3, CF4, and a mixture of these two were used to attempted. Pressures ranged from 460 millitorr to 1000 millitorr. Pressures below this could not be obtained because the mechanical pump with this tool was not large enough to do so. Varying the gas flow controlled this pressure with higher flows yielding higher pressures. With these runs, it was discovered that a polymer buildup was occurring across the entire surface of the wafer. To combat this problem, a plasma chemistry of CHF3 and 02 was implemented. The CHF3 acted as the etchant of Si02 while the 02 served as a polymerization inhibitor. Flows of CHF3 ranged from 10 to 20 sccm while the 02 flows ranged from 0 to 8 sccm. Optimization involved determining which flows determining which flows provided the best selectivity between the silicon dioxide and the resist mask.

RE5LJL~S/ANALYSI9

Successful etching of SiO2 was the result of the addition of oxygen to the CHF3 plasma. Without it a polymer formed across the entire wafer, and was the result of an excess of CF2 radicals. These radicals were allowed to buildup on the surface of the wafer without reacting to form the polymer. The addition of oxygen in its molecular form (equation 3) or in its radical form (equation 4) prevented polymer buildup.

C + 02 > CO2 (3) 2C + 0 > 2CO (4)

Table 1 illustrates the effect of oxygen additionto this process. Oxide thicknesses were measured before and after an etch. If a

156 polymer was formed, on the oxide, the nanospec would indicate this as an increase in the thickness of the oxide. After an oxygen ash however, the oxide thickness would return to its original value. The fact that this material could be removed in an ash was the key in determining that it was a polymer. As the 02 flow increased the polymer buildup lessened until the flow was 6 sccm. At this point, polymerization was inhibited and the oxide etch occurred. Note that this flow yielded a negative value for (delta t ox).

TABLE 1: ETCH CHARACTERISTICS

I CHF3 FLOW 02 FLOW ETCH TIME PRESSURE DELTA t OX I I (sccm) (sccm) (minutes) (mtorr) (angstroms) I

I I I I 15 0 j 3 590 +2867 I 15 2 3 I 638 I +1000 15 I 4 3 I 690 I +563 I 15 6 I 3 I 793 I -826 I I I

The following is the process which was found to demonstrate the best results for an SiO2 etch using a resist mask.

TABLE 2: RECOMMENDED CONDITIONS FOR ETCH OF SILICON DIOXIDE

I CHF3 flow I 15 sccm

02 flow I 6 sccm

I pressure I 750 - 800 mtorr I

I power I 100 watts I

There are several comments with respect to these parameters. First, selectivity, which equals the etch rate of SiO2 divided by the etch rate of resist mask, ranged from 0.16 to greater than twenty. The major cause of this inconsistency may be the result of the mass flow controllers, which are designed to regulate up to 500 sccm. With such small flows actually being used, one must question the percent error of flow. Ideally, flows controllers in the range of 25 sccm should be implemented. Secondly, the pressure varied from 750 to BOO millitorr. This is too high to create an anisotropic profile. The present pump is too small to pump down to the 100 mtorr range and a larger pump could enable a RIE process.

It is possible to achieve an oxide etch using the Tegal 700 plasma reactor. However, the present system has its limitations and a 157 more powerful pump may improve its capabilities dramatically. Maximum power for this tool is only 100 watts, which is relatively low compared to more recent models which are capable of 800 watt rf signals. Finally, obtaining more efficient mass flow controllers may improve the consistency of etching. Future investigation into these aspects is a definite possibility.

ACKNOWL ED~MENTS

I sincerely thank Dr. Richard Lane for his ideas behind the chemistry and experimentation of this research. f~s well, I would like to thank Scott Blondell and Gary Runkle for their assistance with the Tegal and its maintenance.

ER E S

[1] S. Wolf and R. N. Tauber Silicon Processing for the VLSI Era Sunset Beach, California. Lattice Press. 1986

[2] Brian Chapman, Glow Discharge Processes New York. John Wiley and Sons. 1980

158 DESIGN OF A EEPROM CELL AND THIN OXIDE EVALUATION

Kenneth Obuszewski Fifth Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

An electrically erasable programmable read only memory (EEPROM) device, utilizing a double polysilicon structure was designed. An extremely thin gate oxide (100 ) was required to allow for Fowler-Nordheim tunneling. Thin oxide polysilicon gate capacitors were fabricated, and evidence of tunneling was existent. However, the oxide integrity was generally poor, and processing did not proceed past this point.

I NTRODUCT I ON

A EEPROM is a non-volatile memory; therefore, memory contents are retained when power to the chip is off. It possesses the capability of programming or erasing memory contents in a matter of milliseconds. Successful fabrication may allow the device to be programmed and erased up to 100,000 times. The outstanding feature of the EEPRDM is that it is erased electrically, unlike an EPROM. An EPROM must be erased with ultraviolet light for up to 30 minutes. Consequently, while an EPRDM must be removed from its setup to be erased, a EEPRDM may be programmed and erased entirely by software. The major drawback of a EEPROM is that it is very difficult to fabricate successfully.

Both an EPROM and a EEPROM require two polysilicon gates. The difference is that a EEPROM utilizes a very thin first gate oxide which allows current to flow between the gate and the drain under proper bias. This current flow is termed Fowler-Nordheim tunneling. Subsequently, this oxide is termed the tunnel oxide, and it is responsible for the ability of the EEPRDM to erase electrically.

A typical EEPROM is shown in Figure 1. The first gate, called the floating gate, can be charged and discharged depending on whether the cell is being programmed or erased. The tunnel oxide must be very thin, probably no more than 130 Angstroms. The thinner the oxide, the more current that will tunnel at a lower voltage. The second polysilicon layer is used to form the control and select gates. A normal gate oxide thickness is required, as the select gate is a standard NMOS transistor. Thus, EEPROM processing is similar to standard NMOS processing with the exception of the extra gate.

159 Control Gate Floating Gate Select Gate

~~~n+)~J t I \~nJ Source Tunnel Oxide Drain Source

Figure 1: Typical EEPRDM cross-section.

~ EEPRDM cell is programmed by grounding the control gate and applying 20 volts to the select gate. This causes electrons to tunnel from the floating gate to the drain region overlapped by the floating gate. This leaves the floating gate at a more positive charge. In order to erase the device, 20 volts is applied to both the control and select gates, while each source is grounded. Electrons from the source, drain and channel regions subsequently charge the floating gate to a more negative potential [2]. The state of the cell can read using the select gate in a current sensing mode [2]. The control gate is grounded and 5 volts placed on the select gate during this operation. Figure 2 show the operating modes of the cell.

CL SG CL CG S

ERASE 20 0 20 0

PqOGRAM 20 20 0 5

S UNSELECTED 0 X 0 0

F,OU~ 2 OPI~ATâG UODES OF MEOfiY cELl.

Figure 2: EEPRDM schematic and voltage levels [2]. Perhaps the most vital part of EEPRDM processing is the thin oxide growth. Very high integrity thin oxides are difficult to produce. The oxide cycle must be carefully developed through extensive characterizations. The tunnel oxide utilized in a EEPRDM must be of higher quality than a standard gate oxide, since it must withstand voltages near or at the breakdown voltage. Care must be taken in further processing to prevent damage to the thin oxide. This includes high temperatures and exposure to plasma.

EXPERIMENT

The basic process steps to be followed in the EEPRCM process are: 1) Threshold adjust implant 2) Grow and pattern field oxide 3) Grow tunnel oxide 4) Deposit first poly and pattern 5) Implant poly and source/drain regions 6) Grow interlevel oxide 7) Deposit second poly and pattern B) Implant second poly and source/drain regions 9) Grow contact cut oxide and pattern 10) Deposit metal, pattern, and sinter

Since SUPREM II does not model polysilicon, simulations were not very useful

Several single bit EEPRDM cells were designed on an in-house CAD tool Seven masking layers were required to achieve the desired process Gate lengths and widths were varied to achieve a range of values for the voltage dropped across the tunnel oxide. Standard NMOS transistors were also laid out, for first and second poly transistors. Gate lengths of 6, 10, ~and 50 microns were utilized. Six microns is near the minimum gate length at RIT, and 10 microns is standard. The 50 micron device will allow effective channel length to be calculated. Subsequently gate underlap of the source and drain could be determined This is a very important parameter in EEPROM fabrication The greater the underlap, the more of the gate oxide that is tunneled through This reduces the current density and charge trapping A field transistor is included to calculate the field threshold value. This is a concern since 20 volts will be passing across the field. Poly resistors and capacitors are also included to evaluate poly sheet resistance and oxide integrity Figure 3 shows the chip layout

Initially, a complete EEPROM cell was to be fabricated. However, after mask generation and initial processing, it was determined that time would not permit processing to be completed. Instead, a thin oxide capacitor was evaluated. A threshold adjust implant of boron was performed. The energy and dose were chosen because of previous results in NMDS pojects at RIT. An oxide of approximately 4000 Angstroms was grown and subsequently etched away. The temperature served to activate the implant and the oxide served as a sacrificial gate for the thin oxide growth.

161 • 7/ ~ ~ .. ~ Sttb’.’” ‘-I., • •~ ~ :~. :~ ~~ ~ .-14 ‘:~

(P4/

~, .& k~-~ /-.‘~

r;7,7; ~ 4,. .7;~~/

7’ ‘7,3

~‘ ~-f~i ~/ ~/1

7/ ~r; ~7 :;t~ 4 7~ ~, ‘~;h~ ~fLI1/7 V

~/ :/5d ‘4. 4Z~

7777-~ y.’j 7)

Figure 3: Cell layout.

162 Tests were performed to determine the proper time for an oxide thickness of close to 100 Angstroms. Ten minutes in a dry oxygen ambient at 900 C was sufficient. The wafers were pushed in at 700 C in a nitrogen atmosphere to prevent initial oxide growth. After stabilization at 900 C, oxygen and TCA were turned on for 5 minutes. The temperature was ramped to 1050 C in nitrogen and annealed for 15 minutes. This was to help remove interface trap sites. The temperature was then ramped back down to 900 C, and the oxygen and TCA turned on for another 5 minutes. The TCA helps to reduce oxide defects, fixed charge, and mobile ionic charge. One last anneal at 900 C in nitrogen and pull out at 700 C finished the cycle.

The wafers were immediately transferred to the polysilcon furnace for deposition, since exposure to the air greatly damages a thin oxide. After deposition, the poly was implanted with phosphorous. An implant was chosen rather than a diffusion since the implant depth can be controlled. Phosphorous entering the oxide would affect the integrity. An anneal at 900 C in nitrogen was utilized to activate the implant. A low temperature was used since high temperatures are detrimental to a thin oxide. The poly was wet etched and the resist stripped with acetone in order to avoid a plasma. Plasma also damages thin oxide integrity.

Ellipsometry measurements of test wafers showed a thickness of between SO and 150 Angstroms. However, the accuracy of the ellipsometer comes into question. By ramping the gate voltage and plotting versus the current between gate and substrate showed leakage in the nanoamp range until between 7 and 12 volts. At this time tunneling seemed to be apparent. This is a reasonable voltage for a 100 Angstrom oxide since oxides should breakdown at 10 Mv/cm2, which would be 10 volts for 100 Angstroms.

After further investigation the oxide appeared to be of poor quality. After being exposed to 100 microamps of current, the capacitor starts tunneling at a lower voltage. This agrees with literature; however, at times the difference in voltage was as much as 5 volts. This suggests that the oxide is becoming porous and is of poor quality. It almost behaves as a diode formed by a n-type poly layer and a p-type substrate. Figure 3 shows a typical curve generated by the 4145 Analyzer. Curve A was ramped until the current through the oxide reached. 10 microamps. Curve B was allowed to reach 100 microamps. The differe nce in tunneling voltages can be clearly seen.

Capacitance-voltage analysis was attempted. Results were very inconclusive. Most capacitors had high frequnecy C-V curves that looked as if they were low frequency curves. This might lead one to believe that excess minority carriers were present in the substrate. Perhaps this could have been prevented by guard banding, which consists of a heavy implant surrounding the capacitor. It is also possible that phosphorous channeled through grain boundaries in the poly and into the thin oxide.

163 — I -~ Sta~t —20.GODV

****** GRAPHICS PLOT ****** TUNNEL OXIDE CAP IT V~-1th1a1i (uA) VG -~ MARKER (—5. B000V . —96. 55nA , -~‘~ ‘~P ao.ooti_L_H I ~EL~

O7J ~

1O.00~ —10.00 0 10.00 VG 2.000/div ( V) Figure 4: I-V Curve of a thin oxide capacitor.

SUMMARY

Fowler-Nordheim tunneling appears to be achievable with thin oxides at RIT. Unfortunately, further testing could not be performed to confim Fowler-Nordheim tunneling. Nonetheless, oxide integrity needs to be improved. The poor quality thin oxide may be attributable to several factors. The oxide cycle may not yield a high quality oxide. Pinholes may be present in the oxide. Problems may exist with the silicon-silicon dioxide interface or the polysilicon-silicon dioxide interface. It is likely that the gate oxide and/or polysilicon furnace(s) may not be capable of producing high quality oxides. A further investigation into thin oxide growth is certainly warranted. With smaller geometries in RIT’s future, thinner gate oxides will need to follow. ~

Richard Lane for a poly run, Frank Schmitt and Scott Blondell for implants, and Alex Pepe and Mark Chonko of Motorola, Inc. in Austin, Texas for technical advice. ~E~,ERENCE~

[1] Wolters, D.R.~, and Peek, H.L. “Fowler-Nordheim Tunneling in Implanted MOS Devices.” Solid State Electronics. Vol. 30, No. 8, 1967, pp.835-839.

£2] Veargain, John R., and Kuo, Clinton. “A High Density Floating- Gate EEPRDM Cell.” IEEE. 1981, pp. 24-27.

164 PROCESS DEVELOPMENT OF MULTILEVEL METALLIZATION UTILIZING NATIONAL SEMICONDUCTOR POLYIMIDE EL-5510 Ross Patterson 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

This project is concerned with double-layer metal using National Polyimide EL-5500 as the of an aluminum /dielectric/ aluminum scheme. The polyimide was an attractive candidate for the dielectric die to its use in trilayer resist schemes. However, results obtained showed incomplete via clear-out.

~NTRDDUCTIDN

The use of multilevel metallization is common in VLSI fabrication to overcome the limitations encountered with single level metal. The need for more than a single metal layer is evident in circuit performance characteristics. A significant limitation on the switching speed comes from the propagation delay of fine-line interconnects placed on an insulating film [1-3]. The relationship between the delay time, RC, is seen to •be directly proportional to the square of the interconnect length, as shown in the following equation: 2 RC (Rs x (L ) x Eox)/Xox where, Rs and L are the sheet resistance and length of the interconnect line; Eox and Xox are the dielectric constant and the thickness of the insulating film, respectively. The length of the interconnect line must be minimized, to obtain desired device performance. Thus chip size and switching speeds are essentially limited by the interconnect network of VLSI devices.

The microelectronic engineering department at RIT has conducted several preliminary investigations of aluminum /dielectric/aluminum multilevel metallization schemes. A brief critique of procedures and results is in order, followed by a statement on this project.

The project by Chris Knaus [4] concentrated on using a DuPont photosensitive polyimide as the dielectric between the two metal layers. His study found that during the development and a subsequent 02 plasma etch of the photosensitive polyimide for the vias, that insufficient clean out and possibly Al-oxide formation caused very high contact resistance. After a dc voltage of 2-36 volts a dielectric breakdown in the via occurred and low contact resistance was observed. 02 plasma processes, overdevelopment 165 arid a buffered hf dip were tried with little success resulting in high contact resistance.

Eric Westerhoff’s project [5] extended the above work and considered BOG, photoresists Kodak 820 and Shipley 1400-27, arid thermally deposited silicon monoxide for the dielectric. Test features that he used were via chain resistance, step coverage, capacitance, and electrical interference. Upon repeating for- photosensitive polyimide, he found that development specs by Kriaus were less than adequate, mainly due to the use of the same container of polyimide as Knaus used. Increasing the dose and a longer development time also produced a poor image. ~ttributed cause was the polyimide was over 1 year old. For resist as a dielectric between the metal layers, it was found that the resist could not stand up to 2nd metal imaging in adhesion. SiC could not be evaporated with the vacuum system at RIT and thus was not tested. For the 506, he found it to be a good planarization layer but no further accomplishment with it is noted.

The project done by Robert Newcomb [6] consisted of trying to characterize 506 by breakdown voltage vs. dielectric thickness. He also obtained very high via resistance which he attributed to the fact that he did not have oxide insulation between first metal and the substrate. The breakdown voltage results properly showed increasing voltage for increasing dielectric thickness.

Manuel Carneiro’s project [7] attempted characterization of both polyimide and SOG as the dielectric. The BOG attempt failed due to severe underetching of the vias. The polyimide processing resulted in good breakdown characteristics but very high via

contact resistance. In Manny’ -~ design he experimentally tried different size vias for the via chains and also attempted results from various thicknesses of the dielectric.

This project proposed to try to resolve the high via contact resistance utilizing National Semiconductor polymide EL-5510 as a dielectric. The major cause of the high contact resistance is due to incomplete via clean-out [4-7]. Incomplete via cleanout can be due to many factors [8], such as: Polyimide reflow, insufficient etching, polyimide scum formation and aluminum oxide growth. Figure 1 shows results of an open and short circuit due to improper via etching. ~n open circuit is seen when the via is insufficiently cleared-out, whereas a short circuit is seen when the dielectric is overetched causing undesirable contact between metal layers. The dielectric used, polyimide EL-5510 series was chosen for its superior characteristics over other polyimides and the fact that it is well documented at RIT.

EXPERIMENTAL

The process sequence shall be presented in abbreviated form, where the complete process flow is given in ~ppendix ~. The same process mask set from the previous study by Manny 166 FIGURE 1: An open circuit and short circuit due to improper via etching

Carneiro were used. This mask set could only be successfully aligned for two rows of die due to intial mask generation on the GCA photo-repeater caused differing spaces between die. The mask set contained various via dimensions and capacitor areas. As such, hopes that the larger vias of 30 microns would be cleared out sufficiently to enable proper metal to metal interconnect, and analysis as to the lowest via size obtainable could be realized.

Different areas of processing touched upon included: utilizing an aluminum/silicon alloy metal for 1st and 2nd metallization, a buffered HF dip prior to 2nd metal deposition, an aluminum etchant dip to remove aluminum oxide from the via, and an argon sputter prior to 2nd metal deposition to attempt enough damage in the via to breakthrough to the 1st metal layer.

Intial processing of five wafers showed adhesion problems of the alloyed metal after two weeks from deposition. The photoresist lifted during aluminum etching and etched away desired aluminum. Upon rework only three wafers were processed to completion for parameter testing.

The processed wafers were subsequently tested using the HP-parameter analyzer for measurement of via resistance, capacitance value and dielectric breakdown.

167 RESULT S

Problems with resist adhesion to the metal layers occurred beyond a week from deposition. This strongly suggests trying to do the entire processes between 1st and 2nd metallization within the shortest time span possible. This will provide the best potential for metal to metal connection.

Etching of the vias using the plasma ash process involved a ~‘trial and error’ approach, where visual inspection with an optical microscope was not capable of detecting complete via etch. Polyimide coated silicon wafers, which were flat with no metal, were used to determine the etch rates of the polyimide in the plasma asher. ~pplication of these etch rates to processing via etch led to incomplete clean out in many cases. Complete clear out could not be detected with microscope inspection, but showed up as opens in electrical test. This would suggest creating a program on the nanospec for polyimide on metal such that it could be used to analyze via clean out.

The test structures for measuring capacitors [4-7] consisted of various dimensions of vias and capacitor sizes. Upon testing capacitance, poor data was obtained due to bad connection through the via of the 1st metal structure to the 2nd metal pad. ~lso, the test masks limited the number of die aligned properly due to mask error during manufacture on the GC~ photo-repeater.

Several recommendations to address or possibly fix these issues exist. Future test masks should include various via dimensions as in the case of Manny Carneiro’s study and also should include via clean-out detec’ ‘on structures to enable comprehensive analysis into the capacity of etching through the via. Formulation of a program on the nanospec for determining polyimide thickness on a metal layer would enable inspection for complete via clear out of device wafers. P~lso, a SEM study of via clean out utilizing dielectric on 1st metal could enable determination of an optimal etch process, including etch time, to clear out the vias. Planarization and step coverage examinations would study the capabilities of the materials to reduce hillock formation, opens and short circuits. Lastly, investigations into silicides or barrier metals including refractory metals could resolve the metal to metal contact problem.

CDNCLUSIDNS

This study showed that incomplete via clean out caused insufficient contact between the two metal layers. However, the superior characteristics and well defined process for the polyimide make it a potentially useful dielectric material for a multilevel process. Continued investigations should follow to try to resolve the via clean out with the polyimide EL-5510.

168 ~CKNOWl. ED~MENT8

I would like to thank Mike Jackson, my instructor, for his help throughout this project and to Kathy Hessler for her help and support with the polyimide EL-5510.

REFERENCES

[1] V. Pauleau, “Interconnect Materials for VLSI Circuits”, Solid State Technology, p. 61-67, 2/87.

[2] S. Wilson, R. Mattox and 3. Seeger, “Multilevel Interconnects for Integrated Circuits with Submicron Design Rules”, SPIE ~dvanced Processing of Semiconductor Devices II, p.9-I7, vol. 945, 1988.

[3] Yoshio Nishi, “Challenges in CMOS Technology”, Solid State Technology, p. 115-119, 11/88.

[4] C. Knaus, Unpublished RIT Senior Year Undergraduate Research Project, 1985.

[5] E. Westerhoff, Unpublished RIT Senior Year Undergraduate Research Project.

[6] R. Newcomb, Unpublished RIT Senior Year Undergraduate Research Project.

[7] M. Car’neiro, Unpublished RIT Senior Year Undergraduate Research Project.

[8] Vue Kuo, “Planarization of Multilevel Metallization Prc’esses: a Critical Review”, SPIE ~dvanced Processing of Semiconductor Devices, p.49-57, vol. 797, 1987.

169 CH~R~CTERIZ~TION OF INTEGRP~TED INJECTION LOGIC

Tu T. Phan 5th Year Microelectronic Engineering Student Rochester Institute of Technology

~BSTRP~CT

Integrated In3ection Logic gates (IlL) were fabricated at RIT by the use of a double diffused, four mask process. The IlL devices contained neither a buried contact nor an epitaxial layer. The propagation delay time of invertor gates was measured at different injection current levels.

INTRODUCTION

Integrated Injection Logic (IlL) was invented in 1972. It is the most recent logic system to be introduced to commercial applications, and is used in electronic watches and timers, microprocessors, and ~nalog/Digital and Digital/~nalog converters. Finally, large-scale integrated circuits using IlL can be built over the full military temperature range and exibit good radiation resistance characteristics.

IlL represents an innovation in bipolar integrated circuits that achieves superior advantage in packing density and power-delay product, as compared with the transistor-transistor logic (TTL). First,the IlL gates can be packed with a density between 120 to 200 gates per square millimeter which is almost ten times higher than of TTL gates packing density. Second,the speed-power product of IlL is in the range of 0.1 p3 to 0.7 p3, where the speed-power product of TTL is typically 100 p3. In addition, the design of IlL eliminates the current sources and the load resistors of TTL which occupy much of the real estate on the chip.

Integrated In.jection Logic (IlL) is an extension of bipolar technology into LSI by new circuit design technique. Figure 1 shows a cross-sectional profile and a schematic of an IlL cell. The basic IlL cell consists of a lateral pnp transistor (Q2) and a vertical npn transistor (Qi) with multiple collectors (Cl, C2). The emitter of Qi and the base of Q2 are grounded. The collector of Q2 is connected to the base of Qi which is the input B.

170 The basic IlL cell of Figure 1 is also an invertor gate whose input is B and outputs are Cl and C2. When the input B at logic low (0 V) the outputs Cl and C2 will be at logic high which depend on the external supplied voltage. If the input B changes from logic low to logic high (.7 V)5 the injection current will flow into the base of Qi. Thus Qi is saturated and the outputs Cl and C2 will change from logic high to low which is the Vce of Qi at saturation. Inversely, when the input B goes from high to low, the outputs Cl and C2 will change from low to high.

E Iinj BC1 C2

Imi 4:-ip HI I UL1L~J C2 B Li P n substrate

(a) (b)

Figure 1: ~ basic IlL cell: schematic (a), and cross-sectional profile (b).

Delay time is the time needed for an output to response an input signal such as from high to low or vice versa. Figure 2 describes the delay time from high to low and from low to high respectively. In an IlL circuit, the delay time is inversely proportional to the injection current, Icc, as expleined below.

(V) ‘in

0.7

Vin — 0 Vout—.—. time Figure 2: Delay time from high to low and low to high

~t low injection current level, the propagation delay time of an IlL gate is the time required to charge junction and parasitic capacitors of Qi. Since the injection current Icc will distribute the charge to these conducting capacitors, the propagation delay time is inversely proportional to the number of these capacitors.

~t medium injection current level, the propagation delay time is the time needed to establish or remove excess minority carriers in the baseof Qi. This charge is proportional to the transistor current available to remove it, and hence the delay

171 time is independent of the injection current.

Finally, at high injection current level, the propagation delay time will increase with the increase of injection current because the npn transistor is driven into saturation in which the stored base charge increases more than in proportion to transistor current. Figure 3 displays the normalized propagation delay time versus injection current [1].

1o6 Low ‘mi Normalized ~ Delay Time ,,Hih 1~r~.i

icr3 io_2 icr2 100 101 io2 io3 (mA,)

Figure 3: Normalized propagation delay time VS injection current.

~XP~~M~NT

This project was to measure the propagation delay time of IlL invertor logic gates which were designed and fabricated in the class EMCR-é50. The HP4145 was used to check the performance of all individual transistors of the circuit to be tested prior to take the measurement of the propagation delay time. The program BETA of HP4145 was used to measure the gains and obtain the plots of Ic versus Vce of npn (Qi) and pnp (Q2) transistors. In this program, the emitter of Qi and base of Q2 were conneceted to ground, and the base of Qi was the input which was connected to the collector of Q2. The input signal was a square-wave whose amplitude and period were 0.7 V and 50 nano-seconds respectively. The external connections for the input, output and injection current are shown in Figure 4. The delay time was measured on an oscilloscope.

Vout

= 330 K

~5V v. B ~iL

Figure 4: The testing set up

172 RESULTS AND ANALYSIS

The output voltage at Cl was measured to be 3.0 V when the input was high. This voltage was expected to be lower than 1.0 V. The 2.0 V higher than the expected value was caused by the large internal emitter resistant. When the input was low, the output did not go higher than 3.5 V. This is the problem of large leakage current Icec. The circuits behaved like a voltage divider between Ri and the internal emitter resistor. Individual transistors Qi and Q2 were then tested to check its performance. None of transistors worked properly. The npn transistor did not work with the collector is heavily doped. When the polarities of emitter and collector were interchanged, the Qi showed a large leakage current Iceo (see the attached plots). In addition, the Vce was always low with all level of input voltage B which means the npn transistor suffered a large leakage. current and large internal emitter resistance. The pnp lateral transistor had a long base width of 10 urn which caused all minority carriers to be recombined within the base; therefore, the current gain Beta was significantly small. The propagation delay time coud not be measured because the logic gates did not function properly.

CDNCLUS ION

The IlL logic gates of this project could not work because of the reasons described above. To improve the performance of an IlL circuits the design should include the following: First, a short base width for the lateral transistor (less than 2 um)to increase the current gain Beta. Second, the emitter contact of the npn transistor (ground) should be doped and located slose to the main devices in order to reduce the internal emitter resistance. Third, a burned contact should be included in the design to promote the current gain of npn transistor.

ACKNOWLEDQMENTS

Mr. R. Pearson for lending the wafers of EMCR-650 class. Dr. R. Turkman for the instruction of circuits testing.

REFERENCES

[1] Herbert Taub, Donald Schilling. Digital Integrated Electronics. New York: McGraw-Hill Book Company, 19B3, chapter 4.

173 FABRICATION OF A SINGLE LEVEL METAL CCD SHIFT REGISTER

Paul F. Picano 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

Using a “shadow mask” technique, a single level metal 3-phase CCD shift register was fabricated with electrode separations of 2.5 microns. Testing is pending at this time.

I NTRODIJCT ION

A Charge Coupled Device, or CCD, is essentially a linear array of closely spaced MDS capacitors. Major applications of CCD’s have been in the fields of photo-sensor arrays, signal processing components such as variable delay lines, transversal filters and also in the area of large storage memory [1].

A three phase CCD shift register can be fabricated by terminating the array of capacitors with a diode at each end (to inject minority carriers), and connecting every third gate to a common conductor. A cross section of such a three phase CCD shift register is shown in Figure 1.

*tfl - TRANSFER ELECTROOE.S SATE OUtPLFT

4.1 __ t~~ I~. p.4LICOtdS*STRATE

Figure 1: Cross section of three phase CCD shift registert2].

Consider such a device fabricated on a P-type silicon substrate. When a large positive voltage is applied to the first electrode in the array, a depletion region is formed in the underlying silicon, temporarily creating a potential well for electrons, as shown in Figure 2a. Electrons injected from the input diode accumulate in the potential well formed under the electrode. If a positive voltage is then simultaneously applied to an adjacent electrode, the potential wells will overlap and any charge stored under the first electrode will then be shared with the second electrode, as shown in figure 2b (hence the name

174 “charge coupled”). It then follows that when the bias is removed from the first electrode, the charge is transferred completely to the second, as shown in Figures 2c and 2d. A similar transfer process moves the packet of charge under the third electrode. When the electrodes are pulsed with overlapping clock pulses, as shown in Figure 2e, a moving array of potential wells is established. In this fashion, packets of electrons supplied from the input diode are shifted sequentially through the device, to be detected at the output diode. A CCD is a dynamic device, in which charge may be stored for times shorter than the thermal relaxation time of the capacitors. This time varies from one second to several minutes, depending on the processing [3].

——

\b4 T______—————— ti

~ j ~ .~ ~ ~ ____ (ii P2 ______~ ‘ —n ______

H —‘

, . (bi

, . ~ I (ci Figure 2: Dpera~ion of three-phase CCD[2].

Critical to the operation of the device is spacing the transfer electrodes close enough so that their depletion regions overlap. If they do not overlap no charge-coupling takes place and the device fails. The fraction of charge transferred from one well to the next is defined as the charge-transfer efficiency. Factors which affect the charge-transfer efficiency include incomplete charge transfer, surface states, leakage currents and charge loss. Charge transfer efficiency is the most important performance parameter because it defines how many transfers can be made before the input signal seriously distorts and/or becomes delayed [4]. For transfer efficiencies compatible with today1s technology this spacing must be less than three microns [4].. IXP~M~N1

The device fabricated was a three phase CCD, and therefore has 24 transfer electrodes, plus 4 electrodes for input/output. The transfer electrodes are 250 by 40 microns and are contacted through diffused buses. A P-type substrate was chosen for two reasons. First, in a P-type substrate the minority carriers are

175 + + II II j~~•ii ii ~ ~ ~ an

LEVEL 1: P—type channel stop LEVEL 2: Diode and clock bus N Diffusion II D •~ ~~uUnnUouUo IE1~

LEVEL 3: Contact cuts LEVEL 4: Every other electrode

Metal 1

c?ra EID ~ ED ~ IEIDIEID

LEVEL 5: Remaining device features An overlay of all levels Metal 2

Figure 3: Masking levels for a single level metal CCD.

176 _I______~______Over-etchSecond

are electrons, which have a higher mobility than holes and should therefore result in a higher charge-transfer efficiencies. Second, for a silicon dioxide insulator on a P-type substrate the fixed charge held near the surface is positive and the silicon at the interface is held in depletion even at zero volts bias, again improving the efficiency of the device. The transfer channel was surrounded by a P-type channel-stop diffusion. The resulting high majority carrier concentration prevents the formation of a depletion region of a significant width, creating a surface potential wall around the transfer channel. This serves to laterally confine the direction of charge transfer, and electrically isolate the device. The masking levels for this project are shown in Figure 3. Fabrication started with the growth of a masking oxide for the ring diffusion. This oxide is 5500 angstroms thick and was grown on P<100> 5-8 ohm-cm substrate in wet 02 for one hour. Windows were opened and a boron diffusion was done to define this channel stop. The masking oxide was then stripped and regrown to approximately 5000 angstroms, windows were opened and the input/output diodes were defined along with the clock buses for each phase. A phosphorus diffusion was used to define these regions. The masking oxide was then stripped and the gate oxide was then grown. This oxide was 800 angstroms thick and grown in dry 02 with TCA, contacts to the diffusions were cut through this oxide. The wafer will then be coated with a thick layer of aluminum, and using the shadow mask technique, the electrode structure will be fabricated.

—— (a) I

I ~I •_~I — — (b) I I

I ~ I ~ P — — — Cc) t~row ~ps

— — — — — —— ~‘ F

Figure 4: Technique for sub-micron electrode spacing[4].

Figure 4 is a illustration of the “shadow mask” technique that was employed to obtain electrode spacings necessary for the proper operation of the CCD. The process was developed by Browne and Perkins t3,4]. This technique involves defining every other electrode in the array with photoresist on a thick layer of aluminum. The metal is then etched to clear, and then carefully overetched, producing an overhung structure. A second thinner layer of metal is then deposited over the entire wafer. By

177 Figure 5a: Picture of completed device.

Figure 5b: Close up of electrodes using dark field illumination. Spacing is 2.5 microns.

178 virtue of the overhang, solvent can access the photoresist and lift off the unwanted metal over the resist in an ultrasonic acetone soak. The remaining device features are defined in a subsequent photoresist application. The result was a linear array of electrodes, with the separations between them determined by the degree of overetch. Using this technique it was possible to fabricate single level metal structures with spacings as close as one half of a micron. This lower limit is imposed to allow for possible lateral surface migration of aluminum during the second metal deposition, which could short the device.

Figure 5a shows an optical micrograph of the completed device. Figure 5b shows a close view of the electrode structure using dark field illumination. Using the “shadow mask” technique, electrode separations of two and a half microns were obtained for a one minute time to clear and two minute overetch. The yield for this step was very high. Subsequent attempt may obtain closer spacing using shorter overetch time. Future attempts at this project would require that some modifications be made to the layout. Changes include removing the input/output electrodes which allow the packets to be written into and read out of the array. These electrodes complicate testing and do not affect device performance. For easier testing of the devices the pad layout should be modified so the probe card can be used instead of attempting to place multiple probes. Figure 6 shows my suggestion for the testing circuitry. Without the input/output electrodes testing is made easier. D Flip-flops can be used in conjunction with a function generator to develop the necessary three-phase overlapping clock and one other function generator would be necessary to inject the pulse into the array. An oscilloscope can be used to montor the output as well as the clocking circuitry.

CIcc.c J1SL

O~,rP~ir ..rL—ow IIoccop€

Figure 6: Testing circuitry for three phase CCD.

CONCLUSION

An 8-bit three phase single level CCD shift register with 2.5 micron separation between electrode was successfully fabricated using the “shadow mask” technique.

179 ACKNOWLED~EM~N1~

I would like to acknowledge Scott Blondell for his assistance with equipment difficulties, Mike Jackson for obtaining supplies and Rob Pearson for his redesign which may benefit future attempts at this pro3ect.

~J!~ENCES

[1] G.S. Hobson, Charge Transfer Devices, Halsted Press, pp. 71-76, 1979.

[2] C.H. Sequin and M.F. Tompsett, Charge Transfer Devices, Academic Press, pg. 21, 1975.

[3] R. Melon and D. Buss, Charge-Coupled Devices: Technology , and Applications reprint; W.F. Kosnocky, “Charge-Coupled

[4] M.J. Howes and D.V. Morgan, Charge Coupled Devices and

Systems, Wiley - Interscience publications, pp 62-85, 1979.

[5] V.A. Browne and K.D. Perkins, Nonoverlapping Gate Charge-Coupled Technology for Serial Memory and Signal Processing Application, Journal of Solid-State Circuits, Vol. SC-il, No. 1, pp. 203-207, February 1976. PLANAR OPTICAL WAVEGUIDES USING A SILVER-SODIUM ION EXCHANGE

V .P.Raghavari 5th Year Microelectronics Engineering Student Rochester Institute of Technology

ABSTRACT

A planar optical waveguide fabrication is reported using a silver-sodium, electric field enhanced, Al thin film masked, ion exchange process. In this study, silver atoms from the thin film replace the sodium ions in soda-lime glass, resulting in a higher index of refraction. It should be noted that soda lime glass was used as a substrate even though it varies in composition, contains metallic impurities and is generally not of optical quality. Problems related with sterling silver and design width are discussed. A better understanding of requirements for coupling light into the waveguide, edge polishing, index profiling, focusing of the source etc, is needed to further analyze this wave guide.

INTRDDLJCT ION

From a historical perspective, the basic design of optical systems did not change for many years and consisted of bulky and heavy components which required careful alignment and protection against vibration, moisture and temperature drift. The concept of integration of optical components was motivated during the early 1970’s by a desire to minimize these problems and make them more compatible with modern technology. Integrated optics is basically guided wave optics, where light is constrained (within a guide) by total internal reflections to propagate in discrete guided modes. In order to transmit light from one component to another, guiding structures have replaced light transmission through space.

Most text books carry an indepth theoretical analysis of light wave propagation along waveguides [1-8]. The basics of the theory is given here in order to understand wave propagation due to total internal reflections along a waveguide. Figure 1 shows the conditions for total internal reflection. They are as follows: n(f) > n(s),n(c) Sin &c n(s)/n(f)

Condition for guiding the lowest order mode depends on wavelength Lambda, and is given by the following equation

h lambda/2*{n(f) - n(s))

181 If ‘h’ is allowed to increase, other discrete modes can propagate

‘If,,,,

r//I/ /1~ ‘ ‘ ‘ ‘ ‘ ‘t k e’s

Figure 1 - The guided mode.

Another important concept is that of the evanescent field, a field that extends outside the boundaries of the waveguide. It is this field that allows coupling between waveguides. It can also be used to determine index profiles and the number of allowable modes in a given waveguide [9,10].

Recently, considerable attention has been given to glass waveguides due to their compatibility with optical fibers, ease of fabrication and low cost [1,2,3]. The ion exchange process is a popular technique for fabricating graded index planar optical waveguides in glass. This method involves exchanging monovalent cations such as Li, Cs, Rb, Ti, Ag, or k with Na present in the glass as Na20.

The need for Na makes soda lime glass, which is rich in sodium, inexpensive and readily available as commercial microscope slides a good choice. Even though soda lime glass varies in composition, contains metallic impurities, and is generally not of optical quality, it was used as the substrate in the following waveguide feasibility study.

EXPERIMENT

This project consists of three phases. The first phase was to develop a computer program which could generate data files for the Mann 3000 pattern generator. The pattern used for the study consisted of two straight line segments connected by a S curve as shown in Figure 2.

Figure 2 - Waveguide design.

182 ______?______ma.oI(

The S curve was chosen to demonstrate total internal reflections. The channel is designed to avoid abrupt twists. A sudden change of 4 degrees will leak approximately 1 dB of the propagating optical power(guide NA 0.2) [13]. Given the length and height of the main rectangle and the width of the waveguide, the program creates a data file in the Mann 3000 format. A width of 5Oum was chosen in order to propagate rnultimodes [13]. Due to the exposure scheme of the pattern generator, the mask for the 5Oum width waveguide was made via reversal processing. The exposed areas are bleached out, and a second flood exposure is done to expose previously unexposed areas.

The second phase consisted of the ion exchange process. The ion exchange is performed through an aluminum mask on the substrate glass. A 2500A thick Al film was thermally evaporated onto the substrates at a pressure of 1.5E-5torr. Prior to deposition the slides received a clean on the MTI scrubber. The cleaned side of the slides received a spin coat of KTI-820. A specially constructed chuck was used to hold the slides without a vacuum. After a convection prebake, a 36 mJ/cm2 exposure was done on a contact printer. Shiply 351 developer was used with a 1:1 DI water. A visual check showed a good image formation. A convection postbake followed for 30mm at 150C. The waveguide was etched into the Al mask using Al etchant. In order to balance the thermally induced stress of the patterned Al film, the slides received 2500A of evaporated Al on the unpatterned side.

This study is done utilizing electric field assisted Ag-Na exchange because of several advantages offered by the process: the total amount of silver ions in glass can be controlled accurately by the Ag film thickness [4], the index profiles of the waveguides are very insensitive to temperature variations during fabrication [5], and the surface index of the waveguides can be controlled in wide ranges [4,6]. The patterned side of the slides were then coated with silver, with film thickness of 470A. This film of silver was the Ag ion source.

A hot plate capable of 400C was used as the thermal source. The diffusion was electric field aided: produced between the Al plate, (positive) and the hotplate surface (ground). The sandwich structure is shown in Figure 3.

,1 ,‘ : ‘, ~

[320 ‘c, ~ I 1 ~

Hot ~

Figure 3 - The sandwich structure.

183 Finally the remaining silver film and the Al mask were etched off. The following composition of bleaching solution was used to etch the silver film: 1 lit of H20, 9.5 gm of K2Cr2O7, 12 ml of H2S04.

RESi.JL.18/ANALVBIS

The following observations were made after stripping the silver source film and the Al masking film. The waveguide was visible to the unaided eye. Observations under the microscope showed a continuous guide formation with no breaks. Also to be noticed were a number of circular defect on the Al masked areas of the glass sub5trates.

The circular defects were not noticed on the undiffused slides. No hillocks were seen under dark field observation on the unpatterned Al mask. However, such speckles could be seen under transmitted light on the microscope, after pattern etching and subsequent stripping of the photoresist. This would indicate some problem with the photoresist step, such as small air bubbles, which escaped subsequently, leaving a void in the masking photoresist layer. The end result would be the diffusion of silver through the pinholes into the glass.

Another possibility would be the diffusion of contamination particles trapped between the glass and the Al film. This could have originated from some particles on the glass not removed by the clean, or from such contaminants on the Al pallets which were then evaporated onto the slide. A possible solution would be to subject the slides to a plasma clean before evaporation.

Sterling silver was used for an ion source. Sterling silver comprises of 92.7~ silver and about 7~ Cu. The effect of Cu on the ion exchange process is not known. Fine silver (1OO~ pure silver) could be investigated for an ion source in future studies.

As seen from the theory, the depth of the diffusion or the height ‘h’ of the waveguide controls the number of modes propagating along the guide. From this, the minimum ‘h’ required for propagation of the single mode for 632.Bnm light is calculated to be 1.S2um. Values of h greater than this would result in the propagation of additional modes. As a result, obtaining the cross sectional profile of the guide is important. This is more so because of the saddle shape of the profile. This results from an increase in the electric field at the edges of the guide [15]. Some profiles obtained under the same conditions as used here, are given in Figure 4.

184 ≥O/Aftl j ~

—~-,

— ~-

1hao (r~ro~ii~ 44k.1 ~so< ~i~o< lIIo (far ~

Figure 4 - Profiles. ?~CR7’ c.onh•Gw~.)

The narrowing of the guide at center is of interest. From these photographs, it is obvious the widening of the guide alone does not solve coupling problems as expected. The 5Ourn width was chosen in order to easily detect the propagation of multi modes. In contrary, a narrower guide in the range of lOurn is seen to have a better semicircular profile (with a greater h) which is preferred for a guide. By shining a laser perpendicular to the waveguide and measuring the diffraction pattern, the width of the guide or the saddle was calculated to be 62um or an increase of l2um from design.

While the areal profile was visible, the cross sectional profile was not visible. Some problems associated with this are due to edge polishing. Since the polishing process is tedious, and due to the lack of expertise in this field, the slides were sent out to a commercial polisher. However, microscopic examination shows flaws such as chips and trenches on the polished surface. While a low quality saddle like profile was visible, the well defined profile seen in the above photographs could not be detected, mainly due to surface flaws.

CONCLUSION

Wave guides were fabricated using the Ag-Na electric field enhanced ion exchange process. However, the following recommendations are made to the above described process. A design for the masks should have an array of guides having widths comprising of 10, 20, 50 and 100 urn. Appolo work station interfacing with the MEBES electron beam mask making and exposure system needs to be explored with regards to patterning. Problems such as polishing and propagation loss associated width soda lime glass substrates, needs to be further investigated. Fine silver (100~ silver> should replace sterling silver as an ion source layer. A capping layer such as gold should’ be used to prevent oxidation of the silver layer. SEM profiles of the silver film over the Al mask will be needed in order to analyse and control the electric field pattern. Institu polishing techniques need to be developed.

In order to analyse the waveguide, an understanding of light coupling techniques and index profiling methods need’ to be further studied and developed.

185 ACKNOWI. EDOMEN’~’S

I would like to thank - Dr Fuller, Mike Jackson and Santosh Kurinec for their guidance, Rob Pearson for providing valuable processing information, Prof. Roger Heintz and the EE department for all the support, guidance, finances and equipment backing without which this project would not have been made possible, Prof. Delorenzo for the theoretical knowledge, Scott and Garry for providing clean room support and Jeff Pelz for making optical instruments available.

Bi ~ER E ~

£1) H.Kogelini, “Limits in Integrated Optics”, Proceedings of the IEEE, Vol.69, No.2, p.232, Feb.1981.

(2) J.E.Gortych and D.G.Hall, “Fabrication of Planar Optical Waveguides by K+ Ion-Exchange in BK 7 and Pyrex Glass”, IEEE Journal of Quantum Electronics, Vo].QE-22, No.6, p.892, June 1986. £3) R.V.Ramaswamy and S.I.Na~afi, “Planar, Buried, Ion-Exchanged Glass kjaveguides: Diffusion Characteristics”, IEEE Journal of Quantum Electronics, Vol.QE-22, No.6, p.8B3, June 1986.

[4) S.Honkanen, A.Tervonen, H.Von Bagh and M.Leppihalme, Appi Phy.61, 52 (1987).

[5) A.Tervonen, S.Honkanen and M.Leppihalme, Appi Phy.62, 759, (1987).

£6) 5.I.Na3afi, P.G.Suchoski and R.VRamaswamy, IEEE 3. Quantum Electron .QE-22, 2213 (1986).

[7) M.Young, “Optics and Lasers”, Springer-Verlay, New York, p.3, 1984.

[B) J.Sen~or, “Prentice-Hall International Series in Optoelectronics,. Englewood Cliff, N.3, p.22-28, 1985.

(9) Y.Suematsu and K.Iga, “IntroductiOn to Optical Fiber Communications”, John Wiley L Sons, NY, p13-24, 1982. (10) P.K.Tien, R.Ulrich and R.J.Martin, “Modes of Propagating Light Waves in Thin Deposited Semiconductor Films”, Appl Phy, Vol.14, No.9 p 291, May 1969.

[11) K.Hotate and T.Okoshi, “Measurement of Refractive Index Profile and Transmission Characteristics of a Single Mode Optical Fiber from its Exit Radiation Pattern”, Optical Society of America, Vol.18, No.19, p.3265, Oct 1979.

(123 C.Yeh, K.Ha, S.S.Dong and W.P.Brown, “Single Mode Optical Waveguides”, Appl Optics, Vol.18, No.10, p.1490, May 1979.

(13) Juha Vil~anen, M.Maklin and M.Leppihalme, “Ion Exchanged Integrated Waveguide Structure”, IEEE, p.13, March 1985.

(14) John W.Eerthold 3 and Ben3amin winters, “Integrated and Guided Wave Optics and Device Applications”, National Security Agency Technical Journal.

(15) S.Honkanen, A.Tervonen, H.Von Bagh and M.Leppihalme, “Fabrication of Ion Exchanged Channel Waveguides Directly into Integrated Circuit Mask Plates”, Appl.Phy, 51, p 296. August 1987. 186 nMDS STANDARD CELL LIBRARY

Marco Rivero 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

A set of standard nMDS cells was designed following the MOSIS lambda-based design rules, with a lambda of 2.0 microns. The nMOS process was modeled using SUPREM II, and each of the cells was simulated in SPICE. The cells, an inverter, two, three, and four input NANDs and NORs, NAND and NOR RS flip-flops, a 2-bit Multiplexer, and a 2-bit Demultiplexer/Decoder, were designed with ICE, an in house CAD tool.

I NTRODUCT I ON

The fabrication of pM0S devices dominated the 1960’s, due to the simplicity of processing, and the fact that the P106 non-idealities did not severely impact their operation. However, pMOS has the inconvenience of negative source voltages and slow operation. In the 1970’s nMOS became the dominant process due to it’s positive source voltages and it’s ability to output voltages, with depletion loaded inverter stages, equal to the supply voltage. nMOS devices are also faster, because of the higher mobility of electrons versus holes. The drawback for nMOS devices comes in its fabrication sequence. In order to counteract the non-idealities of P106 devices, we need to use ion implantation to adjust the substrate threshold voltage. For the same purpose, polysilicon gates were used, since they have a reduced workfunction difference. Furthermore, implants are needed for an n-type channel if we are to build depletion mode devices.

The design process for any circuit will be very slow if it is started at the transistor level, as it would require optimizations in the gate sizes and transistor gains. If a set of pre-designed, optimized, and operational standard logic cells is created, the design could be done at the logic gate level, much more easily and quickly. The purpose of this project is to provide designers with such a library of working standard cells for faster design of circuits in nMOS.

The operation of nMOS devices with depletion loads is as follows. Take, for example the most basic cell, the Inverter, seen in figure 1. The Driver, or pull-down transistor, is an enhancement mode device with a threshold voltage of at least one volt. The load transistor is a Depletion mode device, and has a threshold voltage of less than zero.

187 jJ~ MOSFET N I r’ Output MDRIVE Input ______MOSFET N

Figure 1.. The Inverter.

Since the loads gate is connected to a voltage that is at least ground, it will always be turned on. When the voltage on the driver’s gate is high (positive voltage for nMOS) the driver transistor will be turned on, and the output will be driven to ground, or pulled down. Inversely, when the input voltage is low, the driver transistor will be turned off, cutting off the current through it, and causing the output voltage to be driven up to the supply voltage, since the load transistor is always on. Summarizing, the output voltage will always be driven towards the inverse of the input voltage, from this the name Inverter. If more than one driver gate was connected in series, they would all have to be turned on in order for the output voltage to be low, thus making a NAND gate. If the drivers were connected in parallel, we will have made a NOR gate. By connecting these gates together it will be possible to make more intricate gates and circuits.

This project was concerned mainly with the full characterization of the standard cell library. Each different area of the devices will be simulated, namely: the Enhancement and Depletion gate areas, the Source and Drain areas, and the field areas. The gate area simulations will yield the MOS threshold voltage for each device for a given number of surface states, and the gate oxide thickness. The Source and Drain simulations will output the sheet resistance of such areas, and their junction depth. The field areas are also important, since SUPREM will calculate their threshold voltage, to check for possible parasitic type transi3tors. This will dictate the appropriate Threshold adjustment implant at the beginning of the process. The calculation of the appropriate implant dose is described in Appendix 1.

CELL DESIGN

The cells are all to be designed following the self—aligned nMOS process, and the inverter stages must have enhancement mode drivers, and depletion mode loads. This configuration requires ion implantation over depletion mode gates, polysilicon gates, and the use of buried contacts at the source of the load devices. The necessary ion implantation, and CVD polysilicon process steps have recently been made available at RIT, making it possible to design integrated circuits using this technology. The process can be modeled using the simulation software package SUPREM II, which will yield oxide thicknesses, impurity concentration profiles, and will also compute threshold voltages for a given

188 number of surface states. Enhancement mode devices require a threshold voltage of about 1.0 volt, and depletion mode devices are preferred to have about —4.0 volts for threshold. These thresholds can be obtained from the SUPREM simulation of the gate areas of the devices. Refer to Appendix 2 for the nMOS process description in the SUPREM simulations.

The MOSIS lambda—based design rules were followed for the layout of the cells in the in house CAD tool ICE (Integrated Circuit Editor). All cells are 150 microns high, and the width is in increments of 12 microns. As an example, the Inverter cell is shown in Figure 2. Supply voltage and ground lines run at the top and bottom of each cell, and all inputs and outputs to and from the cell were placed at the top and bottom, in polysilicon.

Figure 2. The Inverter cell layout.

The design was done in a six layer process: Diffusion, Implant, Buried Contact, Poly, Contact cuts, and Metal. In order to fabricate the devices a mask set for each level can be obtained from the ICE designs.

Each cell will be electrically simulated using SPICE. SPICE has the advantage of being able to simulate devices following very specific electrical parameters. These parameters form the nMOSFET model card in SPICE, and can be calculated from the SUPREM output values for oxide thickness and sheet resistance, among others. Figure 3 illustrates the role each parameter plays in the nMOSFET electrical model.

Some model parameters can be calculated, but others will have to be given assumed values. This is necessary since they are only extractable from test results on fabricated devices, and this type of process has not been completed at RIT. In the SPICE simulation we will also have to choose the appropriate gate sizes for the desired gate gains. This gain was chosen to be 10.0 at first, but it was found from SPICE that a gain of 7.0 would give much better output characteristics. A gain of at least 5 will be satisfactory for our purposes, should the finished devices not function properly and yield a gain lower than desired. Note that

189 SATE G

Figure 3. The nMDSFET model parameters.

the gain selection was done at the layout level, since it was then when the gate sizes were decided upon. If the SPICE simulation was not satisfactory, design changes were done on the layout.

The parameters extracted directly from the SUPREM output are RSH (source and drain sheet resistance), VTO (zero bias threshold voltage), TOX (gate oxide thickness), NSUB (substrate doping), TPG (type of gate material, which is polysilicon), and XJ (junction depths). Other calculated SPICE nMDSFET model parameters are the Junction capacitance, CJ, and the Gate to Source and Drain overlap capacitances, CGSO and CGDD. Mso, the bulk capacitances of the Source and Drain, CBS and CBD, and the Source and Drain series resistance, RS and RD. Other parameters such as NSS (number of surface states), and L~MBDPi (channel length modulation) were given assumed values.

Upon completion of the fabrication and test of the devices, the assumed values entered into the SPICE nMOSFET model can be amended. From the process results we can also obtain more accurate values for the SUPREM parameters (TOX, RSH, etc). More accurate nMOSFET parameters will yield a more reliable and realistic simulation, and will help in determining if any further design adjustments should be made.

RESULTS/DI 8CUSS ION

The calculated nMOSFET model parameters that were used are shown on Table 1.

The optimum sizes were researched in order to achieve the desired gain of 10.0. Gate sizes of (1/w, in microns) 4.0/60.0 for the driver, and 28.0/4.0 for the load transistors were attempted, and the results were dissappointing. The simulated hold, propagation, and fall times were in the picosecond rage, while the rise time was of about 1.4 nanoseconds. Note that all the values obtained from fabricated devices are not likely to be as good as the simulated ones. The high gain was supposed to make up for any problems and malfunctions due to processing.

190 However, it was found that a gain of seven yielded much better results in terms of pull up times, and output voltages reached, with gate sizes 4.0/60.0 for the driver and 16.0/4.0 for the load.

Parameter Enhancement Depletion

LEVEL 1 1 VTO 1.52 v -4.19 v NSUB 5.0 E14 5.0 E14 TOX 601 Angs 601 ~ngs TP6 1.0 (n+) 1.0 (n+) XJ 2.41 microns 2.41 microns L~MBD~ 0.01 0.01 RD 100 ohms 100 ohms RS 100 ohms 100 ohms CJ 2.59 nF 2.59 nF CGSO 13.8 pF 13.8 pF CGDO 13.8 pF 13.8 pF

Table 1. nMOSFET model parameters.

The cells designed are an Inverter, two, three, and four input N~ND gates, two three, and four input NOR gates, a Multiplexer, a Demultiplexer/ Decoder, a N~ND RS flip flop, a NOR RS flip flop, and an XOR gate. Each cell, as it appears in the library, comprehends an electrical circuit layout, a plot of the ICE layout, the logical truth table, and a SPICE deck that characterizes it.

CONCl.~tJ8 IONS

There now exists at RIT the possibility to design in nMOS at the logic level, using a set of standard cells. Future designers at RIT will be able to call these cells from within ICE, and build circuits, simply by connecting the cells to one another. It is then possible to produce designs at the logic gate level, not having to worry about the gate’s electrical behavior.

~CkNOWl.. ED~EMENTS

I would like to thank Robert Pearson for his extensive help in the parameter calculation techniques, that helped develop this library. ~E~E~ENCL~.

[1] James C. Taylor, pMOS Standard Cell Library, (Provided by R. Pearson).

[2] SPICE Simulation of PMOS Digital Structures. (Provided by R. Pearson).

191 CONT.~14INATION IN RIT PROCESSING Daniel C. Shire 5th Year Microelectronic Engineering Student Rochester Institute of Technology .ABSTRACT

Contamination during processing in RIT’S cleanroom facility is a leading cause in the failure of fabricated devices and circuits. Detection of these contaminants is possible using an ESTEK WIS-600 surface inspection system. Before and after particle counts were taken using this system when processing wafers in many common RIT procedures. It was found that contamination levels were significant in most areas, and cleaning procedures were useful only to remove large particles. INTRODUCT ION particle contamination is a leading cause of yield reduction in semiconductor processing. Effects such as short or open circuits and ineffective lithography are among the problems caused by particles on a wafer’s surface, as many particles are larger than film thick nesses and minimum linewidths. This experiment will attempt to determine the extent to which wafers are being contaminated in RIT’s cleanrOom facility during processing. particles originate from cleanroOm air, chemicals, processing equipment and human sources. Some of the most common contaminants are pump oils, solvent vapors, skin oils, cosmetics, and vacuum pump exhausts. Sources of other contaminants include street clothes, human hair, smoker’s breath, and solid film lubricants. Even cleaning processes are guilty of contamination, as residual films may be left behind on a wafer’s surface. These particlr’ will adhere to a wafer until proper steps are taken for removal. Several types of adhesive forces exist which bind particles to wafer surfaces. One such type is electrostatic forces, where a particle is attracted to a wafer via being charged or being an electric dipole. Capillary condensation is another form of adhesive force. In this case a liquid bridge is formed between the surface and particle, and the bridge will not evaporate even at high temper atures. Chemical bonding is a way in which a particle will react with silicon or oxygen and adhere to the wafer. The particles often come to contact surfaces due to Van Der Waal’s forces, which draw the particles to large masses nearby. The energy of these adhesive forces must be equaled before removal is possible. The equipment used to determine the quantity of particles on a wafer surface is the ESTEK WIS-600. This machine uses a HeNe gas laser and a high speed polished rotating multifaceted mirror to generate a line of light of approximately lOOum. As the wafer passes through the line, light is scattered and deflected toward fiber optic collectors which direct the light into photomultiPlier tubes for conversion into electrical impulses. These signals are electrically analyzed arid converted into flaw counts.

192 WIS400 Laser Scanning System

Da~ Osanx*l Photomuluplict Tube Light O~annel Photornultipliet Tube

I ii Wafer Spot Scan Une Direction of Wafer Travel

The light channel assembly is controlled by two threshold values, t4 and t5, which are fixed scales of sensitivity. These thresholds are set to a level above the electrical noise level so as to measure only real defects on the wafer’s surface. The dark channel assembly is controlled by three threshold values, Tl-T3, which work similarly to the light channel. These thresholds, however, may be calibrated by usibng standard calibration wafers to detect flaws of a certain size. In this experiment the thresholds are set to detect particles of 5um respectively. See the chart below for more details on thresholds and flaw categories.

Flaw Types (Thresholds Utilized)

Fl- Raze(Tl). P2- Small pits arid particulates (0.2 to 2J.Lm) Cr2). P3- Lgr~tsafldpa~culatS(2to2~m)C~ F4- Cumulative sum of flaw types 2,3, A, and C. Totalization of particulates. F5- Scratch count. Flaw types 1,2. and 3 located in a minimum of four adjacent pixels are converted toflaw typeS. P6- Area Defects. P7 - Orange peel, slip bands, large mounds, and polished out saw marks (T4).

F8 - Distortion with abrasion such as art unpolished out saw mark (T3 and T4). P9 Distortion defects of smaller size such as dimples, grooves, mounds and slip lines (13).

PA - Large particulates (20 to 50 ~im) (T3 and T5). PB- Heavy orange peel and related defects (T4 and T5). FC- Sevreparticlesorpi5(50t0l00~)~,T4~~TS)

PD - Not used currently.

FE - Not used currently.

PP - Not used currently. PC- Number of edge types not resolved. Also very large defects above bOurn. (17).

zXpERI?~NT The experimental procedure consisted of scanning each wafer’s surface, performing a processing step or sequence of steps, and r.sca.nniflg the wafer to find particulate add-on. The treatment each wafer saw and the before and after particle counts appear in the results of this paper.

193 RESULTS The standard RCA clean used at RIT, shown below, has a backgrOulid contamination level of over 700 small (5um). The RCA clean is effective in removing large particles, but does not remove the smaller flaws.

H202:NH4OH:R20 HF:R20 RC1:H202:H20 RINSE 1:1:5 1:10 1:1:5 18 Meg. 10 mm 2 mm 10mm To Resistivity

The MTI scruber has a background level of over 100 small and mid-range particles each, while being ineffective in removing contamination. The wafertrac high pressure scrub was better able to clean than the MTI scrub, removing a large percentage of particles >lum, but has a background contamination level of over 400 small particles. Ultrasonic cleaning with Wegman’s soap was generally an ineffective process. Several contaminant sources exist which may not be obvious. The ambient air, airgUfls, and spin dryer were all found to add high numbers of small particles and a significant number of larger flaws. Also, scribing a wafer causes large numbers of particles of every size to be added, as seen on the included wafer plot. Photoresist coating removal adds very high numbers of small and mid-range particles~ with less of an effect seen when exposure and development are included. Few large particles are added in either case, however, which may indicate that a post_lithography clean is not useful with current cleaning capabilities. Aluminum evaporation and etching adds thousands of small particles and a significant number of large particles. LPCVD processing also adds small particles, but fewer large particles. Ion implantation is a clean process. The gate oxide and boron predeposition tests performed demon strate the pitfall of using a scanner on an altered surface, as the reflectance of the wafer’s surface has been changed and pours have been formed in the respective tests. CONCLUSIONS It was found that the contamination levels in most areas tested were eignificafltr and that the cleaning procedures performed poorly in removing small particles. For some of the current lOum design rules contamination issues are not vital, but as the GCR stepper and MEBES electron beam masks are used to shrink device geometries to 1-2um consideration must be given to contamination. k~OWEDG!~TS I would like to acknowledge Thomas Grims lay of the ESTEK company for his advice and use of his facilities, and Rob Pearson for his ideas and time.

194 REFERENCES “Semiconversatiofla”, Volumel, Number 2

“An Analysis of Particle Adhesion on Semiconductor Surfaces” R. Allen Bowling Solid State Science and Technology, September 1985 “Surface Cleanliness and Adhesion” K.L. Mittal Surface Contamination Genesis, Detection, and Control Volume 1, pp3-46

195 wafert treatment 5um 1 scribed~>RCA clean 765->1353 1043>486 1390->23 2 scribed-->UltraSOfliC clean 1194->1137 1228->776 295->116 3 tap water containinate&”> 2621->2130 1600->1104 142->33 ultrasonic clean 4 tap water contamiflate&> 2633->2425 1551->l265 253->37 MTI scrub 5 repeat of 4 2644->2332 1306->l200 75->57 6 tap water contaminated”> 2246->442 1856->122 277->4 RCA clean 7 virgin->afllbient test 43->105 7->84 0->21 8 virgin->airlifle dry 51->l69 2->109 0->22 9 virgin-->caacade rinse & dry 43->237 2->162 0->5 10 repeat of 9 54->315 4->208 2—>lO 11 virgin~>waferraC8c~~ deh. 46->2849 2->386 1->11 bake, HMDS, PR, prebake, plasma ash l0min250w 12 repeat 11 91->3054 10—>412 0->12 13 virgin->wafertraC5C~~~~ 22->901. 6->289 1->18 bake,BMDS,PR,Prebake, expose, develop,pOstbake, ash 10,250 14 repeat 13 20->1303 5->534 2->16 15 virgin-->AJ. evaporate in 9->4012 3->531 0->146 CVC,Al etch 45c 3mm 16 repeat 15 9->4337 2->446 0->48 17 virgmn”>stafldard lpcvd 14->229 4->105 O->8 run,no silane 18 repeat 17 13->228 O->59 0->14 19 virgin-->BOrOn predeposit 45->23 5->3 0->l 5000rpm, 40s, ilOOc, 10mm 20 repeat 19 19->20 1->5 0->4 21 virgin-->gate ox growth 13->3913 2->0 2->679 1050c,l5min,flO tca, 5.O6lpm 22 repeat 21 11—>4673 1—>515 0->57 23 virgin-->iOfl implant 15->3l 5->19 2->9 6okev, 6e12,backside 24 repeat 23 10->16 4->12 0->13 25 virgin->RCA background 15->1406 2->735 4->41 26 tap water contaminated”> 1434->796 2514->126 757->6 wafertrac scrubbed 27 virgmn-’>wafertrac scrubbed 28->515 6->84 28 repeat 27 30->408 9->116 3->18 29 virgin”>MTI background 32->240 4->218 0->20 30 repeat 29 13->132 6->135 O->19 31 virgin-->RCA background 18->925 9->195 1->5 32 repeat 31 19->746 4->132 0->8

196 _ — ~.

RCA Background Contamination Photoresist coat, exposure. ond ash

p.~d. ~X* — £ZJ bd~*

Ultrasonic clean of scribed wafer RCA Clean of Scribed Wafer V %\. Ø/~ Ii ii ~Iø %~‘ CI1_di1-5 .~

p.*k ~ —~‘

Al evaporation & etch u ~ ~ ~ FLI4 ILLOW CNT ~CtPE 660 NORMAL. 1 9999 741 LINE CNT 93 2 ~999 ~59 WAFER SIZE: 3.~Ø (75) ,~ 999 3b~ 4 9999 :56 9999 ~7 9999 71 99999 14 A 9999 B ~99 C~999 I Ii I 8G 9999 370 AccEPT

[ExxTjI~J CI

~zJ ~

197 PLASMA DAMAGE TO NMOS CAPACITORS

Matthew 3. Strong 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

High frequency C-V curves were taken of NMOS capacitors to determine the effect that a RF oxygen plasma has on the underlying thin gate oxide. This plasma was used to remove a positive photoresist. The C-V curves show a threshold voltage shift of 3.75 volts with respect to the undamaged capacitors. The C-V curves also show that the thinner were more affected than the thicker oxides.

INTRDDUCTION

In todays semiconductor industry the use of plasma etching is wide spread. Thus, it is important to understand its effects on the electrical properties on thermally grown gate oxides. The plasma etching process exposes the thin gate oxides to high stress electric fields and energetic electrons and ions. These energetic particles damage the gate oxide. This damage introduces energy levels in the forbidden band gap. These levels provide more generation and recombination sites. When these sites are exposed to a high energy stress, such as a plasma, they become charged [1-5]. It is important to understand the plasma?s affect on gate oxides, since performance of the devices are affected. In any thermally grown oxide there are electrically active traps at the Si-Si02 interface. These interface traps result from dangling bonds. These dangling bonds are caused by the abrupt ending of an silicon lattice or impurities in the oxide [4,5]. Figure 1 illustrates the physical model of a dangling bond. These traps introduce energy levels in the forbidden band gap that act as centers for generation and recombination site. When these sites are exposed to a high energy stress, such as a plasma, they become charged. This charge trapping is a major reason for degradation and instability in the operation of P105 devices [1-5]. This research project will reexamine Patrica Ostling’s senior project, done in 1988, on how plasma damage affects gate oxides [1]. The major difference will be the use of n-type wafers instead of p-type wafers. How the plasma 198 damages the oxide will be determined by examining the high frequency C-V curves of NMDS capacitors. The first step in the project is the fabrication of these NMOS capacitors. From the C-V curves, the flatband and the threshold voltages will be examined for shifts, as well as general slope vs theory curves. Figure 2 shows an ideal C-V curve vs a plasma damaged C-V curve. This experiment will attempt to match these curves.

Figure 1 Physical model for the interfacial traps caused by the abrupt termination of the Si lattice. E5] n.type(llI)Si No H2 anneal H2 anneal

Q 0.8 C

0.6

U N 0.4

I 0.2 -

—25 —20 —15 —10 —5 0 5 10 15 Gate voltage (V) Figure 2 Ideal C-V curves vs plasma damaged C-V curves. £5]

1~P~! ~MINT Eight 3 ohm-cm silicon wafers <111> orientation were used. The wafers were cleaned in NH4OH/H202/H20, HF/H20, and HCL/H202/H20, in preparation for the gate oxide growth. The wafers were divided into two lots, wafers one through four had 600A of oxide grown on then, and wafers five through eight had 45O~. Half of each of these lots of were coated with KTI-820 photoresist and ashed. The plasma ash was done for twenty minutes at a forward power of three

199 hundred watts. All of the wafers then were then cleaned using the standard RCA clean. A film of 2500 angstroms of aluminum was then evaporated on all eight wafers and then patterned into the capacitors. Since N-type wafers were used the back side of the wafer was abraded using a sand blast. This was done to get an ohmic contact on the back side of the wafer [6]. After the silicon lattice was damaged aluminum was evaporated on the back side of all eight wafers. All eight wafers were then sintered at four hundred and fifty degrees in forming gas. At this point testing was then done using the PNP model 410 high frequency C-V set up in the testing area.

~~iDIiCUWI~ ON

Figure 3 and Figure 4 are typical C-V plots. These C-V plots have both the damaged and undamaged capacitors shown. As can be seen the oxides that saw the plasma suffer degradation. The C-V plots show a shift in both the threshold and the flatband voltage as well as a change in slope. The gradual slope of the damaged oxides indicates more interfaces sites than the undamaged oxides. The thinner oxide shows the greater shift in the C-V curves. Tables 1 and 2 show the summary of the Ccx, Cmin and VFlatband values for the capacitors.

Summary of Results Oxide Thickness of 450A TABLE 1

ICapacitor sizel Cox (pf) I Cmin (pf) I Vfb(volt) I

I ______I ______I ______I ______I IPlasmalNo PlasmaiPlasmalNo PlasmaiPlasmalNo Plasma!

I ______I _____ I ______I ______I _____ I ______I I .OO6lcmA2 I 4001 390 I 40 I 140 I -2.0 I -.45 I I 101 I 100 I I —1.57 I l.0046cmA2 I 236! 240 I 30 I 90 I -1.671 -.25 I I I 02! I 060 I I -1.42 I I.0023cmA2 I 110! 148 I 25 I 60 I -1.401 -.25 I I I I 381 I 035 I I -1.44 I I.0006cmA2 I 0231 034 I 09 I 22 I -2.0 I -.30 I I I I lii I 0131 1—1.58 I

For an oxide of 450A the delta Vt shift was found to be -1.50 volts with a deviation of 1.16.

200 L ..L_.~ ..~:_____:.~..~._~_:__L ..~...t --~---~+H t~hf H~+.V~ti

4-, .-~--, - -“.- .- -- C L ~4 - — I ‘ :f~ 1_.._J 0 ,_ :_

t4 ~ - - ___- - - ~—-~--4~ - ___—i— ~- - ~ tziz~z_ 3 (4 -t ~1 ~ ___r~ z~...J ~- L ___ -~- I to ~ _ iiz ~~_—-z_ -c ..j~ ~ H~-j--~-- -~-‘Ii~---1’ 4-, -I-- - 3

:1 .4’ .1 — - -1—~:I~- ~ 1’: ,. ~ I _-~__ _ +r ( —----, :———---~—~-~\ H4 ~T ‘~--~-~ -— . ~ w ci’ tH ~t to z~z:~~- ~z; a 4-, -~

0 -4

___ ~ 41

CO 1 ____ _ ±~t~z -~. ~

~ ... to a’ ~ C.) £ P. ~____ _ L 4-, J. ~ LL~zz~~ F: L - - -~ - . ———~1— -—-—

•. 0 ~ ~ -~ -.i~~:.: ~~ .+ ~. ~ F~ —~-* H — :4 T”~* —-- LE * -~- * — —------—.—--i -~ ... ~.:j~:~~L: * -~- ~EiPtE - O’to 4::: E~:t~. L~ ~ -_l ‘-1 f.. i: 1.. u-cL :;~~~: Summary of Results Oxide Thickness of 600A TABLE 2

ICapacitor sizel Cox (p1) I Cmin (p1) I Vt(volt) I

I ______I ______I ______I ______I I IPlasmalNo PlasmalPiasmalNo PlasmalPiasmalNo Plasmal I ______I _____ I ______I _____ I ______I _____ I ______I I.0061cmA2 I 3421 340 I 160 I 113 I -1.501 -.20 I I I I 021 047 I I —1.11 I

I.0046cm~2 I 2671 250 I 60 I 75 I -1.451 -.05 I I I I 171 I 015 I I —1.06 I I.0023cm*2 I 1451 130 I 27 I 60 I -1.451 -.12 I I I I 151 I 0331 1-1.03 I

I.0006cm~2 I 0491 041 I 11 I 22 I -1.561 -.10 I I I I 081 I 011 I I —1.16 I

For an oxide of 600A the delta Vfb ~hi1t was found to be - 1.1OV with a deviation of 0.35.

From the table the thinner oxide was more noticeably affected by the plasma damage. The thinner oxides flatband voltage was shifted by -2.17V, whereas the thicker oxides flatband voltage was shifted by only -1.68V. The tables indicate that Cc and Cmin were also affected. The Cmin of the plasma damaged capacitors were less capacitive. The Cox how ever became more capacitive in the plasma damaged cases. The thinner oxide showed the greater affects of the plasma

damage. -.

CONCLUSI ONE

This experiment confirms Patrica Ostling’s experiment from last year, except with N-type wafers. It shows that plasma process’s effect P105 devices. Significant voltage shifts occurred in both of my oxides. The thinner oxide was more affected. The thinner oxide showed a shift of -1.58V were as the thicker oxide showed a shift of -1.1OV.

ACKNOWLEDGEMENTS

I would like to thank Mike Jackson for getting me started on this pro3ect. I would also like to thank Gary Runkle for helping me with the sand blasting equipment.

202 E RE ~JI

[1] Ostling, Patricia,”Evaluation Of Plasma Damage To Thin Gate Oxides”, Rochester Institute of Technology Microelectronic Conference, 1988

[2] Wolf and Tauber, “Silicon Processing”, Lattice Press, Sunset Beach,CA 1985

[3] Singer, Peter, “Evaluating Plasma Damage in Thin Gate Oxides”, Semiconductor International, ~ugust 1987

[4] Osburn, Weitzman,”Electrical Conduction and Dielectric Breakdown in Silicon Dioxide Films on Silicon”, 3. Elechem. Soc Vol.119, 603 (1967)

[5] Pierret, Robert, Modular Series on Solid State Devices, ~ddison-Wesley Publishing Company, 1983

[6] Ghandi, Sorab,”VLSI Fabrication Principles Silicon and Gallium ~rsenide”, ~ Wiley—Interscience Publication, 1983

203 __V

INVESTIGATION OF LOCOS PROCESS USING NITROGEN IMPL~NTATION Joseph W. Walters 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT A localized oxidation of silicon (LOCOS) process was investigated using nitrogen ion implantation. The doses of 2E12, 2E13, 2E14, and 1E15 atoms/cm2 were implanted through a photoresist mask using the Varian/Extrion 40-100 ion implanter. The results show the initial formation of a LOCOS oxidation. The localized image faded on extended oxidation which indicates the implanted region did not adequately inhibit the diffusion of oxygen.

INTRODUCTION Localized Oxidation of Silicon (LOCOS) processes are used throughout the VLSI industry [1). This process involves exposing silicon and silicon nitride to an oxidizing environment. As shown in Figure 1 this process produces silicon dioxide regions on the wafer through localized oxidation. SIIJCON WITRIDE

. SILlCD~ OXIDATION

FIGURE 1: The LOCOS Process Typical LOCOS processes in industry utilize a silicon nitride film that has been generated through low pressure chemical vapor deposition (LPCVD). The film is deposited uniformly on a wafer and then patterned through typical lithographic techniques. In conjunction with this nitride, the process requires a thin silicon dioxide film to underlie the LPCVD nitride. This pad oxide acts as an etch stop during the silicon nitride patterning process. A large etch selectivity is required between the silicon nitride and silicon dioxide films so the appropriate silicon nitride regions are totally consumed before the pad oxide is broken through. This ensures that the silicon wafer underlying the pad oxide is not damaged by the nitride etch.

204 The major disadvantage to this type of LOCOS process is the formation of the bird’s beak featureti]. This feature, shown in Figure 2, results from the accelerated oxidation around the pad oxide residing under the patterned nitridet2]. The increased oxidation in these regions is caused by a greater diffusivity of oxygen in the silicon dioxide film. The lateral growth can be minimized in this process by choosing the correct thicknesses for the silicon nitride and silicon dioxide films. The minimum growth obtained, however, can still represent a significant distance that the oxide extends under the silicon nitride region. The extension of the localized oxidation into these areas reduces the ultimate resolution of the process.

FIGURE 2: Bird’s Beak

A different type of LOCOS process has been developed which reduces the bird’s beak by four fold ti]. This process uses nitrogen implantation to create the silicon nitride regions in the wafer. As shown in Figure 3, the nitrogen is selectively placed in a wafer using a photoresist mask and implantation. Depending on the implant energy and the implant current the nitrogen is transformed into a silicon nitride material either immediately upon implant or during a post implant anneal step. Experiments have shown that low energy, high currer~t. implantation create the nitride layer in situ. The high energy, low current implantation require an anneal step to generate the nitride.

WIN INI~~ININ IKIN RtSIST

— OXIDE

I I RESIST SILICON

MQIEAL ~J, ETCH OXIDE

I;i~~~I SILICON

FIGURE 3 : LOCOS THROUGH IMPLANTATION

205 Once the silicon nitride is formed the process behaves like the other LOCOS process. Exposing an implanted wafer to an oxidizing environment generates silicon dioxide in localized areas. The bird’s beak is diminished because there is no pad oxide to act as a conduit for oxygen diffusion. The emphasis of this study was to determine if a LOCOS process could be developed at RIT using its Varian 400-10 ion implanter. To develop the process the following parameters had to be determined: peak dose required to from silicon nitride, implant dose which provided the peak dose, projected range of the ions given specific implant energies, and the oxide thickness required to bring out the I~OCOS effect. The literature points out that a peak concentration of approximately 5E21 atoms/cm3 is required to form a silicon nitride compound [1]. This number is slightly less than concentration required for stoichiometrically correct Si3N4 as shown by the following derivation. This equation provides the concentration of Si3N4 molecules: L8i3N4]~(D*NA) /N.W. In this equation D is the density of silicon nitride (2.8 g/cm3), NA is Avogadro’s number, and M.W. is the gram molecular weight of silicon nitride (140 g/mole). The concentration resulting from this calculation is 1.2E22 molecules/cm3. Remembering that there are four nitrogen atoms per molecule of Si3N4 results in a nitrogen concentration of 4.8E22 atoms/cm3. The nitrogen concentration of 4.8E22 atoms/cm3 represents the peak concentration of the implanted profile. The implant dose required to obtain this concentration is obtained from the formula for peak concentration [3]

[ N I C 0.4 * Di ) / St In this equation N is the peak nitrogen concentration, Di Is the implant dose, and St is the straggle associated with the implant profile. The formula was rearranged to solve for the required implant dose (Di). The value for straggle used here, 0.1 microns, accounted for the implant energies used in this experiment. This number was obtained from Reference 1. The required implant dose for stoichiometrically correct Si3N4 came out to 1. 2E1 8 atoms / cm2. The last process parameter concerning nitrogen implantation is the time required for the implantation. The implant time required to obtain the proper dose is given by the following formula: t~ (Di*A*q) /1 In this equation t is time, Di is the implant dose, A is the implant area, q is 1.6E19 Coulombs, and I is the implant current.

206 £~ER~T The substrates used were <100> p-type silicon wafers. The ion implanter used was a Varian/ExtriOn 400-10. In the first experiment the wafers were prepared for implantation through the following process. They initially received an RCA clean followed by a dry oxidation (1100 C for 11.0 minutes) which grew a surface oxide 450 Angstrom thick. The wafers were then coated with KTI-820 positive resist and prebaked resulting in a film thickness of 1.2 urn. The photoresist mask was generated by subsequent exposure via the ETH mask at 58 m~T/cm2 using the Kasper Contact Aligner. The ETM mask contains several resolution charts and line space pairs. After exposure the P.IT standard development process was performed. This process incorporated KTI-934 developer and a 140 C post bake. At this point the wafers were ready for implantation. Two wafers were implanted with 2E12 atoms/cm2 and 2E13 atoms/cxn2 using an implant energy of 30 Key. The other two wafers were implanted with 2E14 atoms/cm2 and 1E15 atoms/cm2 using an implant energy of 60 KeV. After implantation the resist was stripped using an oxygen plasma asher. The wafers were then annealed in a nitrogen ambient at 1000 C for 30 minutes After annealing the samples were oxidized at 1000 C for 1.0 hours in steam ambient. A post oxidation inspection was performed by both eye and optical microscope to determine if a localized oxidation was present. After inspection the wafers were submitted for a second oxidation using the same conditions but increasing the time to 2.0 hours. A second inspection was then performed. The second experiment processed the wafers differently in order to bring the surface of the wafer closer to the implanted region. In this experiment the surface oxide was grown through wet oxidation at 1000 C for 12 minutes to provide a thickness of approximately 1500 Angstrom. The photoresist mask was patterned in the same manner. The implant dose for the wafers was boosted to 2E15 atozns/cm2. The post implant process also varied slightly form the first experiment After the resist was stripped, the surface oxide was etched back using buffered HF to expose the silicon surface. The wafers then went through an RCA clean. The anneal step followed at 1000 C for 60 minutes in nitrogen ambient. The wafers were inspected visually and then oxidized at 1000 C for 15 minutes through wet oxidation. The samples were inspected again and then oxidized for a second time. The second oxidation was 5.0 minutes in duration. A third inspection was performed and then a third oxidation. This last oxidation time lasted 3.0 minutes. The wafers were then inspected a final time.

RgSULTS Localized oxidation was observed on the wafers that received implantation doses of 1E15 and 2E15 atoms/cm2. The LOCOS effect, however, was weak. When the two samples mentioned above were further oxidized the localized image faded. Equipment limitations prevented implantation of higher doses.

207 In the first experiment the sample that received an implant dose of 1E15 atoms/cm2 was the only wafer to show localized oxidation. The oxide pattern mimicked the pattern of the resist mask. The oxide grown on all wafers after the anneal was 0.33 microns thick. This thickness was of sufficient depth to detect the presence of the nitride material. The projected range for nitrogen at 30 and 60 Key implant energies was 0.06 microns and 0.1 microns, respectively. This wafer was oxidized a second time to bring the total oxide thickness to .66 microns. At this point the localized image was nearly faded. An etch back using buffered HF was attempted to bring the image back. This step had limited success. It was observed that after a time all materials on the wafer were removed exposing the bare silicon. This indicated that the material formed through implantation is not a pure silicon nitride since HF does not etch silicon nitride readily.. The second experiment attempted to more clearly differentiate the LOCOS effect by bringing the surface of the wafer closer to the implanted region. This entailed growing an initial oxide which was almost the depth of the implanted nitrogen. The initial oxide grown was .15 microns. After implantation this oxide was etched back exposing the silicon surface. This resulted in bringing the silicon surface nearer to the implanted region. Subsequent oxidations provided the same results as the previous experiment, however. The first oxidation provided the strongest image. Further oxidations washed the image away. This indicated that the implanted material allowed oxygen to diffuse through it given enough time. Higher implant doses were not obtainable using the Varian/Extrion 400-10 implanter due to time constraints. Initially the maximum implant current was found to be 4 microamperes. Using the implant time formula stated in the introduction yields an implant time of 2 hours for an dose of 2E15 atoms/cm2. To obtain the doses stated in the literature (5E16 atoms/cm2) an implant time of 51 hours would be required using our iutplanter. The implant current limited the dose that could be implanted. It was observed that the implant current slowly rose to higher currents during long implant times. For the dose of 2E15 atoms/cm2 the initial current was 4 microaxnperes. As the implant proceeded the current had increased to ~ microamperes after the first hour and up to 10 microamperes by the end of the implant. This resulted in an implant time of only 1.25 hours for that dose. This current creep could indicate that the machine is not as limited as previously thought.

208 coNcLusIoNs The LOCOS process using nitrogen implantation was not developed at RIT. The present implant current limitation of the Varian 400-10 restricted the implant dose by requiring implant times which were unobtainable in practice. The current creep observed during long implant times indicates that the machine may riot be as limited as previously thought. Although the LOCOS process was not developed it was observed that a silicon nitride like material starts to form at doses of 1E15 atoms/cm2. AcXNOWLgDagMENT3 I must acknowledge those people who were invaluable to the success of this project. They are Scott Blondell for his exemplary work with the ion implanter, Dr. Richard Lane for providing me with the process concept, and Frank Schmidt for training me on the ion implanter. RE1~REN~ES [1]. Kim M. J., Ghezzo M., “Characterization of Implanted Nitride for VLSI Applications”. Journal of the Electrochemical Society, 131, 1934—41, (1984) [2]. Sze S.M., VLSI Technology, Second Edition. McGraw-Hill, 1988.

[3]. Wolf S., Tauber R.N., Silicon Processing for the VLSI Era, Volume 1. Lattice Press, Sunset Beach, California,1987.

209 ION IMPLANTATION TO ADJUST NMOS THRESHOLD VOLTAGES

MATTHEW A. WICKHAM 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

NMOS processes require a variety of threshold voltages for differing applications. For this experiment, the threshold voltages of NMOS devices were altered by a using several different ion implant doses (none, 1, 2, 4, and 8e12/cm2) of boron. This shifted the threshold voltage in good agreement with literature values [1].

INTRODUCTION

One of the most important applications of ion implantation in MOS technology is the control of threshold voltages within the devices. By implanting a specific quantity of B atoms in the channels of an NMDS device will bring the threshold voltage to a more positive value. This change is in proportion to the amount of atoms implanted into the channel over the gate oxide capacitance per unit area [1].

Ion implantations are used to control the threshold voltage (Vt) of MDS devices, since they have the advantage of being able to introduce a precisely controlled amount of dopant material into the substrate. Implants can also be performed at lower temperatures, and can be masked with a wider range of materials than diffusions. Lattice damage may occur during an implant, as well as the fact that not all of the implanted atoms may be electrically active [1]. However, under the conditions where an amorphous layer is not formed, temperatures as high as 1000C are needed to anneal the crystal damage, and activate the implanted ions. Typical anneal times are on the order of thirty minutes, and result in virtually all of the species becoming electrically active [2,3].

NMOS devices have gained in popularity as their threshold voltages are typically half of that for the p—channel devices [4]. The smaller threshold voltage is benifical for several reasons; 1.) it allows for the use of smaller power-supply, and hence less power, 2. ) it becomes compatible in operation with bipolar devices, and 3.) it makes room for a higher packing density [5].

To lower the threshold voltage, several methods can be used. The use of the crystal orientation <100> will yield a lower Vt up to one third of <111> orientated silicon), but it will also cut down on the mobility of the holes. The addition of silicon

210 nitride (Si3N4) to the silicon (Si02) dielectric layer will increase the dielectric constant, thereby lowering lYti. ~ silicon gate, polysilicon doped with phosphorus to be conductive, will have a lower work function difference with the oxide, than the metal (aluminum), lowering the threshold voltage. Ion implantation can also be used to fabricate both enhancement and depletion mode devices on the same wafer [5]. For this final reason the effects of ion implantation were chosen for study.

The onset of inversion exists when enough gate voltage is applied to bend the band edge to a point where p-type (n-type) material in bulk becomes equally n-type (p-type) at the surface. The inversion layer is formed when the gate voltage exceeds the threshold voltage [2]. The gate of the capacitor being the top (aluminum), deposited atop a Si02 dielectric, with the bottom plate being the silicon substrate (doped p+).

~ MOS device is considered to be in the depletion mode if it is on with the gate voltage equal to zero, and in the enhancement mode if it is off with a gate voltage equal to zero. NMOS devices are ideally enhancement mode devices, but nonidealities tend to shift the threshold voltage toward the negative. Until about 1977, PMOS technology was dominant due to the fact that NMOS transistors were typically of the depletion mode type [6]. For this reason, an experiment was designed to involve a preliminary investigation into threshold voltage adjustments performed with an ion implanter.

EX~M~NT

Since a variety of threshold voltages may be required for various devices, a process for which differing threshold voltages could be obtained was designed. Several different implant doses (none, 1,2,4, and 8e12/cm2) were performed to examine the shift of the threshold voltage due to these doses. ~s the metal gate process is now in use at R.I.T., that is what was used for this experiment.

First a mask of several differing size capacitors was designed on ‘ICE’,an in house C~D tool, and the mask was fabricated through reversal processing of the retical. The capacitor sizes ranged from squares of 10x10 microns square, 400x400 microns square. Other shapes, both rectangles and hallow squares were designed, but overall differing shapes did not affect the threshold voltage.

Ten p-type wafers of <100> orientation were obtained, and scribed with numbers one through ten. The average resistivity of these wafers was 5.50 ohm-cm. The wafers were then cleaned with a standard RCt~ clean (fifteen minutes in NH4OH/H202/H20 (1:1:5), two minute rinse, two minute HF/H20 (10:1), two minute rinse, fifteen minutes in HC1/H202/H20 (1:1:5), and a final five minute rinse).

211 blanket boron implant was then performed at 6OKeV for the following: wafers 1,2 -- no implant

wafers 3,4 -- implant 1e12/square cm.

wafers 5,6 -- implant 2e12/square cm.

wafers 7,8 -- implant 4e12/square cm.

wafers 9,10 -- implant 8e12/square cm. ñfter this a thin gate oxide was grown at 1000C for forty minutes. This resulted in an oxide thickness of approximately 470 angstroms, and was also long enough to anneal out damage as well as to make the boron electrically active C2—3].

~luminum was then evaporated on the frontside of the wafers and patterned with KT1820 photoresist. The photoresist having been spun on with the wafertrac, exposed with a Kasper aligner, and developed with the wafertrac also. The aluminum was the patterned with aluminum etch, and rinsed. Then the photoresist was stripped of with the plasma asher in an oxygen ambient. ~luminum was then evaporated on the backside of the wafers to produce an extremely large capacitor in parallel with the much smaller frontside capacitors, to make the stray capacitance negligible. The odd numbered wafers were then sinter’ed in a forming gas ambient for twenty-five minutes at 450C. Finally, the capacitors were tested with capacitance-voltage measurements.

RESULTS/ANALYSIS

Capacitance-voltage graphs were taken of all the wafers to determine the actual threshold voltages of the implanted doses. The plots were taken from the 400x400 micron squared capacitor, as it gave the most repeatable results. Figure 1 shows a plot of a capacitor which was not adjusted by implant or sintering after metal deposition. It shows a threshold voltage (marked Vt) of magnitude 0.89V.

fOo.oOj~ . -‘--‘H

so .000 .~4/div E_

r~i~r~r~I 0 iO.0O VOLTS 2.000/div ( V)

Figure 1: Capacitance vs. Voltage (no implant or sintering)

212 The positive accumulation voltage implies an n-type substrate, which was not the actual case since p-type substrates were used. This can be explained by the fact that the ramp voltage was applied to the substrate, and not the gate, during the capacitance-voltage measurement, which will invert the voltage.

Figure 2 shows a plot of a capacitor which received a dose of 4e12/square cm., and was not sinter’ed after metal deposition. It shows that the magnitude of the threshold voltage has shifted to 1.85V, however the accumulation voltage had the same problem encountered in Figure 1.

.00 VOLTS 2.000/div C V)

Figure 2: Capacitance vs. Voltage (4e12/cm2 dose, no sinter)

It is also noticed that the values for the maximum capacitance decrease with the increasing dose, assymtotically approaches 250 pf, and the value of the minimum capacitance increases with increasing dose, approaching about 200 pf.

These changing values of capacitance are due to the higher mobility in the substrate, the fact that there are more mobile species in the substrate. ~t a high enough implant dose, the capacitor would break down completely, and be of no use, as the capacitance-voltage plot would become a straight line.

Figure 3 shows a plot of threshold voltage magnitude versus implant dose for the values used. It can be seen from this graph that sintering the wafers after metal deposition to tie up the loose bonds between the metal and the oxide had little effect on the overall adjustment. Sintered capacitors had a slightly higher threshold voltage, but not appreciable.

213 ~1

c’6

~c5.a ()~ ~

Figure 3: Threshold Voltage Magnitude vs. Implant Dose CONCLUSIONS

It is now possible to predict the threshold voltage shift for various implant doses at 6OKeV. This is of much use as threshold voltages will be important in the upcoming CMOS and NMOS projects. The oxide quality, and processing cleanliness of the NMOS/CMOS processes will also be evaluated through the comparison of past and future results.

The lowest dose implant preformed was 1e12/square cm. This was due to the fact that the implanter beam current was to high to accomplish any lower doses. It may be of use to study lower implant doses, as well as different implant energies and their effect on the threshold voltage shifting. More experimentation needs to be done to gain more insight into this process at R.I.T.

ACKNOWL EDBMENTS

Rob Pearson for his help in the formation of the pro5ect, Mike Jackson for his support and guidance throughout the process, Frank the implant guy, and Michelle Myer for her support, and a shoulder to lean on.

REFERENCES

El] S. Wolf and R.N.TauiDer, in “SILICON PROCESSING FOR THE VLSI ERA”, (Lattice Press, California, 1986), pp.225-226, 305,325

£2] W. Till and J. Luxon, in “INTEGRATED CIRCUITS: MATERIALS, DEVICES,AND FABRICATION”, (Prentice—Hall, Inc., New Jersey, 1982), Pp. 80,196

£3] J. Mayer and L. Eriksson, in “ION IMPLANTATION IN SEMICONDUCTORS SILICON AND GERMANIUM”, (Academic Press, New York, 1970), p.232 £4) A. Mukherjec, in “INTRODUCTiON TO NMOS AND CMOS VLSI SYSTEMS DESIGN”,(Prcfltice-Hahi, New Jersey, 1986), p.15

£5] J. Millman, in “MICROELECTRONICS”, (McGraw-Hill, Inc., New York, 1979), pp.113-il4, 244-252 £6] R. Pierret, in “MODULAR SERIES ON SOLID STATE DEVICES: FIELD ~~CT DEVICES; VOL. IV”, (Addison-Wesley Publishing Co., California, 1983), pp.43-SB, 95-98 214 IUTEGRATED HALL EFFECT SEIZOR

William H. Wilkinson 5th Year Microelectronic Engineering Student Rochester Institute of Technology

ABSTRACT

Experiments relevant to the development an integrated Hall effect sensor have been performed. Carrier concentrations calculated from the Hall voltage generated in samples of bulk silicon did not agree veil with values measured by tour point probe or Van der Pauw techniques. However, the relationship between Hall voltage and sagnetic field was highly linear and should produce a well behaved sensor. A sensor design has been proposed, but not fabricated.

IHTRODUCTION Hall Effect sensors are integrated circuits that produce a voltage proportional to the magnetic field through the circuit. They are used in contactiess switches and proximity detectors. The devices operate on the Hall effect, which is illustrated in Figure 1. A current I flows through a uniformly doped sample of

I / y VA + Y

Figure 1: The Hall Effect voltage ru.

thickness t, width W, and length L. The application of a uniform magnetic field, B, perpendicular to the current causes a Lorentz force to be exerted on the carriers in the y direction. This force is governed by

-.~ -~ F = qE • g(Vd X B) (1)

were Vd is the drift velocity of the carrier. Since the net force is zero in equilibrium, an electric field E must counter the magnetic force in the y direction. Setting F equal to zero in Equation 1 and using the fact that the vector quantities are mutually perpendicular leads to

215 E = (Vd)B. (2)

The small but measurable potential difference associated with this field, called the Hall voltage, Vh, is given by

Vh = EW = (Vd)BW. (3)

The drift velocity of carriers in a semiconductor is

Vd = I/nqtW (4)

were n is the carrier concentration. Substituting for Vd in Equation 3 yields

Vh = IB/nqt (5)

If I, B, and t are known, the carrier type and concentration can be determined from the Hall voltage. This information can be compared to data obtained by four point probe and Van der Pauw techniques. If I, n, and t are known, then the Hall voltage is proportional to the magnetic field. Hall sensors make use of this relationship. The general design of an integrated Hall sensor is shown in Figure 2. It consists of a uniformly doped, isolated n-region similar to that shown in Figure 1. Contacts are fabricated In an appropriate geometry on the region to allow connection of a current source and voltmeter.

current current contact Hall contact3

Figure 2: Typical Hall sensor [2].

Tony Scelsi, a former RIT student, devised a procedure to obtain Hall voltage measurements on bulk samples of p-type silicon [33. This project involved replicating Scelsi’s experiment with p-type samples, refining his technique, extending it to n-type samples, and fabricating a Hall sensor.

216 IXPERIHENT The samples were prepared by cutting a square geometry from a wafer and creating aluminum contacts in the corners as shown in Figure 3. In order to make ohmic contact to n-type silicon it was necessary to perform a phosphorous predeposit in the contact regions before depositing the aluminum,, creating a heavily doped p+/n+ junction. The square was mounted on perforated plastic board and wire leads were connected to the contacts using silver paint. k

t3 C-

Figure 3: Typical sample with aluminum contacts 13].

The experimental set-up used for making Hall measurements is shown in Figure 4. A Kiethley 220 Programmable current source with a voltage limit of 10 volts was connected across diagonal contacts on the sample. A kiethley 197 autoranging microvolt digital multimeter was connected across the remaining two contacts to measure the Hall voltage. Van der Pauw resistivity measurements were made with the magnet of f and the current source connected across adjacent contacts. The Hall voltage was measured as the current and magnetic field were varied. From this data the carrier concentration, which is expected to be cons ant, was calculated and compared to that found by four point probe and Van der Pauw measurements.

JooOcoL • C C 0 0 tO I’ C • 0 0 0 fl 0 C 0 0 000000•• C e.c’_occec ocr (Ci ~cC tel ICC o ch1 ~ c 000CCC CCC

A) Mounted Sample Figure 4 [3]

HSULTS1 DISCUSSION Scelsi reported that the carrier concentration of the p-type samples varied unexpectedly with magnetic field in a manner that was neither liner nor logarithmic [3]. This relationship was 217 observed again when the experiment was replicated. An offset voltage was observed when there was a current through the sample but no magnetic field, and is most likely an 1k voltage drop caused by the contacts not being aligned on an equipotential field line. When the offset voltage was subtracted from the measured voltage, the carrier concentration became independent of magnetic field. Figure 5 shows a comparison of the calculation results for corrected and uncorrected data.

~p~pri~LC a me dand Un comrec~.~ Data n vs B for I—1.OmA, p4pe sampLe, 4/10/89

E 0

10 B (kGauss)

Figure r

Figures 6 and 7 show typical results for carrier concentration calculated as a function of current and magnetic field, respectively, for an n-type sample. There is some scatter for small currents and magnetic fields because the Hall voltages generated were at the sensitivity limits of the milivoltmeter. Otherwise, the curves are reasonably flat. Unfortunately, as shown in Table 1, this concentration was far higher than that measured by four point probe and Van der Pauw techniques.

sample 4 pt probe Van der Pauw Hall effect

n - l.OE15 7.OE1S 2.2El6 p 2.OEl4 l.8El4 8.5El4

Table 1: Carrier concentration in cm3. L *,n511 e •~‘Z~d r~

68/s/S (WQ WL.~O 9—s) G,dwos edf~i_u UWi~IJ0T~~ EJ[ ii_H_H i~ J I2 Figure 8 shows a typical relationship between Hall voltage and magnetic field. Since this curve is almost perfectly linear, Hall sensors should be very well behaved once they are calibrated. A proposed sensor design is shown in Figure 9. It is essentially a Greek Cross Van der Pauw structure that can be used for both resistivity measurements and Hall effect measurements. It is also proposed that a structure similar to that shown in Figure 2 be designed and fabricated. CONCLUSIONS Experiments relevant to the development of a Hall sensor were performed. Work performed by Tony Scelsi. on p-type silicon was replicated and extended to n-type silicon. An explanation has been proposed for an anomalous result observed by Scelsi. The Hall effect measurement technique needs further refinement before it can be used as a characteri2ation technique, but the relationship between Hall voltage and magnetic field is linear and should produce a well behaved sensor. A design for such a sensor has been proposed but not yet fabricated. ACKNOWLEDGEMENTS Thanks to Mike Jackson for his help in obtaining supplies and his interminably good spirits, and to Dr. Peter Cardegna of the physics department for his adivce and cooperation. REFERENCES

[1] Pierret, Robert, and Gerold Neudeck, ed. Modular Series gj~. Solid State Devices,. Volume ~j. Addison-Wesley Publishing Company, Reading Massachusetts.

[2] Muller, Richard S. and Theodore I. Kamins. Device Electronics ~gL Integrated Circuits, ~ ~. 1981.

[3] Scelsi, Tony. Hall Measurements 1J~. Semiconductors. EMCR66O Senior Research Paper, RIT, 1988

220