event guide EVENT GUIDE
Alpes Congrès, Grenoble, France March 14 - 18, 2011 Design, Automation & Test in Europe
The European System Design Show From Systems-on-Chip to Embedded Computing www.date-conference.com WWW.DATE-CONFERENCE.COM
CONTENTS contents
At-a-Glance Timetable 4
Conference Highlights 5
Exhibition Theatre Programme 8
DATE 11 Commercial sponsors 12 Welcome to DATE 11 Media Partners 13 Tool Seminars 14 In this exhibition guide you will find listings of exhibitors contact details and their products being demonstrated on Venue Plan 15 the exhibition floor. The classified product finder will help you locate the right solution within the show; maps and Exhibition Floorplan 16-17 plans of Alpexpo, exhibition hall and additional exhibition space will also help you to get around. Exhibitor List 18 FREE - ENTRY to KEYNOTE SESSIONS Exhibitor Listings 19 & EXHIBITION THEATRE (see p.8) & SPECIAL EVENTS! Call for Papers 36 OPENING PLENARY KEYNOTES – 0830-1030, Tuesday 15 March, Auditorium Dauphine Exhibition Biologically-inspired massively-parallel architectures– computing beyond a million processors Opening Times: S Furber, ICL Professor of Computer Engineering,School of Computer Science, Manchester U, United Kingdom Tuesday 15 March How technology R&D leadership brings a competitive advantage in the fields of multimedia convergence and power applications 1000 - 1830* Philippe Magarshack, Group Vice-President, Technology R&D - General Manager, (*Evening Reception offered by Central CAD and Design Solutions, STMicroelectronics, France the City of Grenoble from 1830 – 1930hrs)
LUNCH AND LEARN SESSION SPONSORED BY Wednesday 16 March MENTOR GRAPHICS 1000 - 1800 1300-1400, Tuesday 15 March, Auditorium Dauphine Grenoble EDA Ecosystem - From Research to Market Thursday 17 March 1000 - 1700 SPECIAL DAY KEYNOTE - WIRELESS Entrance to the Exhibition is FREE INNOVATIONS FOR SMARTPHONES 1400-1430, Wednesday 16 March, Room Oisans DATE Event Secretariat Hannu Kauppinen, Director, Head of Radio Systems Laboratory, European Conferences Nokia Research Center, Finland 3 Coates Place Edinburgh EH3 7AA, UK
SPECIAL DAY KEYNOTE - SMART ENERGY AT ST T: +44 (0)131 225 2892 1330-1400, Thursday 17 March, Room Oisans E: [email protected] or Carmelo Papa, Executive VP Industrial and Multisegment, STMicroelectronics, Italy E: [email protected] W: www.date-conference.com DATE 11 EVENT GUIDE 3 • TUESDAY • TUESDAY • TUESDAY • TtUueEsdSayD 1A5 Ym a•rch 0730 REGISTRATION & SPEAKERS’ BREAKFAST BREAKS 1030-1130 Exhibition Break, 1300-1430 Lunch, 1600-1700 Exhibition Break (1600-1630 IP1) 0830 1.1 PLENARY: OPENING, KEYNOTE ADDRESSES AND AWARDS PRESENTATION, Auditorium Dauphine
SPECIAL TRACK EMERGING TECHNOLOGIES APPLICATIONS DESIGN TECHNOLOGY TEST EMBEDDED SOFTWARE SYSTEM DESIGN SPECIAL SESSIONS
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1130 2.1 2.2 2.3 2.4 PANEL AND EMBEDDED 2.5 2.6 2.7 2.8 EMBEDDED TUTORIAL EXECUTIVE SESSION – Ideas System-Level Techniques to Modelling and Simulation of TUTORIAL SESSION – Logic Transient Faults and Soft Networked Embedded Design of Energy-Efficient – Addressing Critical Power to on Future of EDA and IP Handle Performance, Interconnects Synthesis and Place and Route: Errors Systems and Automotive Systems Management Verification 1300 Industry Reliability and Thermal After 20 Years of Engagement, Issues in Low Power Issues Wedding in View Designs
1400 3.0 SPECIAL LUNCH-TIME SESSION 1300-1400 Grenoble EDA Ecosystem Session - From Research to Market sponsored by Mentor Graphics, Auditorium Dauphine
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1430 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 PANEL SESSION – EXECUTIVE SESSION – 22nm Power Optimisation of Core Algorithms for Formal Predicting Bugs and Timing Related Issues in Performance and Timing Implementations for Power Formats: Beyond to Challenges and Multi-Core Architectures Verification Engines Generating Tests for Test Analysis Digital Baseband UPF and CPF 1600 Wealth/Knowledge Creation Validation Processing Opportunities
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1700 4.1 4.2 4.3 4.4 4.5 4.6 4.7 SEE WEB OR EVENT GUIDE EXECUTIVE SESSION – Robust and Low Power Formal Verification System Level Simulation Advances in Analogue, Design Automation Resource Management for FOR LATEST EXHIBITION to System Level Complexity Systems Techniques and and Validation Mixed Signal and RF Testing Methodologies and QoS Guaranteed NoCs PROGRAMME 1830 and Innovation Applications Architectures for Three- Dimensional ICs
1830 Evening Reception Offered by the City of Grenoble • WEDNESDAY • WEDNESDAY • WEDweNdnEesSdDayA 16Y m • arch 0730 REGISTRATION & SPEAKERS’ BREAKFAST BREAKS 1000-1100 Exhibition Break, (1000-1030 IP2), 1230-1340 Lunch, 1600-1700 Exhibition Break (1600-1630 IP3)
SPECIAL TRACK EMERGING TECHNOLOGIES APPLICATIONS DESIGN TECHNOLOGY TEST EMBEDDED SOFTWARE SYSTEM DESIGN SPECIAL SESSIONS
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 0830 5.1 5.2 5.3 5.4 5.5 5.6 5.7 EXHIBITION SMART DEVICES EMBEDDED An Encyclopedia of Routing Temperature and Variation Advanced NoC Tooling and INDUSTRIAL 1 Analysis, Compilation and EMBEDDED TUTORIAL – to TUTORIAL –Smart Devices Aware Design in Low Power Architectures Runtime Techniques Architectures for Online OPENS AT 1000 for the Cloud Era Systems Error Detection and 1000 Recovery in Multicore Processors
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1100 6.1.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 to SMART DEVICES HOT Placement and Power Modelling, Analysis Design and Test of Fault New Techniques for Embedded Software for HOT TOPIC – Virtual PANEL SESSION – TOPIC/EMBEDDED TUTORIAL Floorplanning and Optimisation Resilient NoC Architectures Diagnosis and Debug Parallel Architectures Manycore Platforms: Embedded Software Debug 1230 – Ultra Low Power Smart Moving Towards 100+ and Test Devices Processor Cores 1340 6.1.2 SPECIAL DAY KEYNOTE AND AWARDS 1340-1400 Awards and 1400-1430 Keynote, Room – Oisans
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1430 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 to SMART DEVICES HOT TOPIC Emerging Memory Architectural Optimisation Advanced Technologies for Emerging Test Solutions for Innovative Power-Aware HOT TOPIC – Foundations of EMBEDDED TUTORIAL – – Smart Medical Implants Technologies for Low Power Systems NoC Implementation Advanced Technologies, RF Systems for a Green and Component-Based Design Predictable System 1600 and MEMS Devices Healthy Society for Embedded Systems Integration
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1700 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 to SMART DEVICES PANEL System-Level Design Power/Error Tradeoffs Memory System Testing and Designing Cryptanalysis, Attacks and HOT TOPIC – Flows, EMBEDDED TUTORIAL – SESSION – Integrating the Techniques for Automotive Architectures SRAM Memories Countermeasures Application and Future of Communication Networks 1830 Real World Interfaces Systems Component-based Design in Next Generation for Embedded Systems Automobiles • THURSDAY • THURSDAY • THURSthDursAdaYy 1•7 march 0730 REGISTRATION & SPEAKERS’ BREAKFAST BREAKS 1000-1100 Exhibition Break, (1000-1030 IP4), 1230-1330 Lunch, 1530-1600 Break (1530-1600 IP5)
SPECIAL TRACK EMERGING TECHNOLOGIES APPLICATIONS DESIGN TECHNOLOGY TEST EMBEDDED SOFTWARE SYSTEM DESIGN SPECIAL SESSIONS
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 0830 9.1 INTELLIGENT ENERGY 9.2 9.3 9.4 9.5 9.6 9.7 EXHIBITION MANAGEMENT TUTORIAL – Design Automation System Modelling Modelling and Verification INDUSTRIAL 2 Embedded System Resource EMBEDDED TUTORIAL – to Energy Transfer, Generation Methodologies for Emerging of Analogue and RF Circuits Allocation and Management Sub-Wave Length OPENS AT 1000 and Power Electronics Technologies Lithography and Variability 1000 Aware Test and Characterisation Methods
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1100 10.1.1 INTELLIGENT 10.2 10.3 10.4 10.5 10.6 10.7 10.8 to ENERGY MANAGEMENT – Advanced Algorithms and System Optimisations and Design and Simulation of Advances in Test Model Based Verification EMBEDDED TUTORIAL – Die PANEL SESSION –State of Smart Energy Generation: Applications for Adaptivity Mixed-Signal Systems Generation and Fault and Synthesis of Embedded Stacking Goes Mobile and the Art Verification 1230 Design Automation and the Reconfigurable Computing Simulation Systems Embedded Methodologies in 2015 Smart-Grid 1330 10.1.2 SPECIAL DAY KEYNOTE, 1330-1400 Keynote, Room – Oisans
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1400 11.1 INTELLIGENT ENERGY 11.2 11.3 11.4 11.5 11.6 11.7 11.8 to MANAGEMENT – Smart Architectural Innovations Asynchronous Circuits and High Level Synthesis New Directions in Testing Hardware Design for HOT TOPIC – New Frontiers HOT TOPIC – Stochastic Energy Utilisation: From for Reconfigurable Advanced Timing Issues in Multimedia Applications in Embedded Systems Circuit Reliability Analysis 1530 Circuits to Consumer Computing Logic Synthesis Design: Technology and in Nanometer CMOS Products Applications
Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre 1600 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 to INTELLIGENT ENERGY Design and Run-Time Reliability and Error Reliability and Error Error Correction and Security Modules from HOT TOPIC – Sustainability HOT TOPIC – Synthesis MANAGEMENT PANEL Support for Dynamic Tolerance in Logic Tolerance in Logic Resilience Layout to Network-on-Chip through Massively Supported Increase of 1730 SESSION – The Role of the Reconfigurability Synthesis Synthesis Integrated Computing... Efficiency in Analogue EDA Community Design
DATE 11 EVENT GUIDE 4 • MONDAY TUTORIALSm •on dMayO 14N mDarAch Y TUESDAY tuesday 15 march 0730 TUTORIAL REGISTRATION AND WELCOME REFRESHMENTS
BREAKS 1100-1130 Morning, 1300-1430 Lunch, 1600-1630 Afternoon.
A (Room - Belle-Etoile) B (Room – Chartreuse) C (Room – Les Bans) 0930 Low Power SOC Design: Best Practice Electronic System Level Design and Manufacturing, CAD and Thermal- to – and what’s next? Verification Aware Design for 3D System-on-Chip LUNCH AND LEARN 1800 Design SESSION SPONSORED BY D1 (Room – Meije 3) E1 (Room – 7 Laux 4) F1 (Room – 7 Laux 5) G1 (Room – Room Meije 2) MENTOR GRAPHICS - 0930 MPSoC Hardware/Software On-chip interconnect for new Renewable energy: solar power Power-Aware Testing and Test to Architectural and Design generation of SoC generation, conversion and delivery Strategies for Low Power Devices Grenoble EDA Ecosystem - Challenges/Solutions 1300 From Research to Market – Time: 1300 - 1400 D2 (Room – Meije 3) E2 (Room – 7 Laux 4) F2 (Room – 7 Laux 5) G2 (Room – Meije 2) Location / Auditorium Dauphine 1430 Model-based MPSoC Architecture Design and Verification Challenges Overcoming CMOS Reliability Testing TSV-Based 3D Stacked Ics to Synthesis for Highly-demanding for Automotive Electronics Challenges: From Devices to Circuits Moderator: Mark Croft, Mentor Graphics, UK Embedded Applications and Systems 1800 Three views of the value of European Research to EDA and Semiconductors: CEA-LETI, ST and Mentor Graphics speak of the value of close cooperation in 1800 Welcome Reception the EU.
plenary session 1300 FROM RESEARCH TO MARKET PLENARY SESSION Laurent Malier, CEO, CEA-LETI, FR Tuesday, March 15, 2011, 0830 – 1030 • Opening Address – Awards – Keynote Speakers With its research centers, university campus, 500 foreign companies and 40,000 scientists, engineers and technicians employed in the area, the Grenoble- KEYNOTEfir sAt kDeyDnoRteE aSddS ress Isere region, otherwise known as France's Silicon Valley, mixes world-class intellectual and scientific dynamism with exceptional quality of life. It is the ideal sprinboard for Academia-Industry collaboration. Biologically-inspired massively-parallel This presentation details collaboration schemes between Industry and research institutes and industry architectures – computing beyond a million happening in Grenoble. This often involves long-term projects based on sharing research costs and requires processors joint technical programs with a predeterminable S Furber, ICL Professor of Computer Engineering, School of Computer Science, timetable, with specific technology transfer and Manchester U, UK operating conditions. Moore's Law continues to deliver ever-more transistors on an integrated circuit, but discontinuities in the progress of technology mean that the future isn't simply an extrapolation of the past. For example, 1320 SUCCESSFUL R&D design cost and complexity constraints have recently caused the microprocessor industry to switch to multi-core architectures, even though these parallel machines present programming challenges that are far from solved. Moore's Law COLLABORATIONS AS A now translates into ever-more processors on a multi-, and soon many-core chip. The software challenge is compounded by COMPETITIVE ADVANTAGE the need for increasing fault-tolerance as near-atomic-scale variability and robustness problems bite harder. We look beyond this transitional phase to a future where the availability of processor resource is effectively unlimited and Philippe Magarshack, computations must be optimised for energy usage rather than load balancing, and we look to biology for examples of how Group Vice-President, Technology such systems might work. Conventional concerns such as synchronisation and determinism are abandoned in favour of real- time operation and adapting around component failure with minimal loss of system efficacy. R&D - General Manager, Central CAD and Design Solutions, STMicroelectronics, FR KEYNOsTecEon Ad kDeyDnoRteE aSddS ress STs Grenoble center was born as a spin-off from a Grenoble research lab several decades ago. Since then we have continued to maintain our innovation How technology R&D leadership brings a leadership with long-term Public-Private Partnerships in Grenoble, France and Europe. Starting in 1992, ST competitive advantage in the fields of has partnered with its competitors to build its 200mm and 300 mm R&D centers and fabs in Crolles, near multimedia convergence and power applications Grenoble. In 2008, ST joined ISDA alliance in Fishkill NY to collaborate to its 32/28nm and 20nm CMOS Philippe Magarshack, Group Vice-President, Technology R&D - General Manager, processes. More recently, ST has reinforced and Central CAD and Design Solutions, STMicroelectronics, France enlarged the scope of its local R&D partnership to Design and Design Automation. This complete eco- From 1985 to 1989, Magarshack designed microprocessors arithmetic blocks at AT&T Bell Labs in system is now bringing valuable innovation to our New Jersey, Pennsylvania and California. In 1989, he joined Thomson-CSF in Grenoble, France, as libraries and ASIC Manager. products and our customers. In 1994, Magarshack joined the Central R&D of SGS-THOMSON Microelectronics (now STMicroelectronics), where he held several Program Management roles in advanced CMOS Design Platforms. Since 2005, Magarshack heads ST’s Central Library, IP and CAD organisation, which defines and provides design solutions to all ST Product Groups in CMOS, embedded NVM and BCD processes, ranging from 0.35um to 1340 INVESTING IN THE TOP TALENT 20nm technologies. FOR EDA In his current role, Magarshack oversees ST’s EDA vendor strategy, setting up and managing joint R&D programs to address Eric Selosse, Vice President and ST’s future design needs. Magarshack is ST’s Enablement Executive at the IBM ISDA CMOS Bulk Alliance in 32/28nm and 22/20nm. General Manager, Emulation Philippe Magarshack was born in London, UK, and graduated with an engineering degree in Physics from Ecole Division, Mentor Graphics, FR Polytechnique in Palaiseau, France in 1983 and with an Electronics Engineering degree from Ecole Nationale Supérieure des Mentor Graphics has a long track record of investing Télécommunications in Paris, France in 1985. in Europe for R&D expertise. Over the last year, despite the economic conditions, we have continued to recruit in France, the UK and Poland. Our industry is a meritocracy which relies on the hiring, nurturing and retention of the best world-class engineers WIRELESS NETWORK for LAPTOP USERS available in electronics and associated fields. This presentation will outline why we invest in Europe, Access will be FREE throughout the exhibition area for all attendees why France is such a significant part of this and look at the particular place Grenoble has in this story.
DATE 11 EVENT GUIDE 5 • WEDNESDAY • WEDNESDAY • WEDwNedEneSsDdaAy 1Y6 m• arch
Smart Devices of the 6.1.2 LUNCH-TIME KEYNOTE AND AWARDS Room – Oisans - 1340-1400 Awards Future Special Day and 1400-1430 Keynote 1400 Organiser/Moderator: A Jerraya, CEA-LETI MINATEC, FR 1340 Awards Moderator: Z Peng, Linkoping U, SE Keynote Speaker: 5.1 EMBEDDED TUTORIAL – Smart Hannu Kauppinen, Director, Head of Radio Systems Devices for the Cloud Era Awards: Presentation of the DATE 10 Best Paper Awards: Laboratory, Nokia Research Center, FI
TRACK D - PROPERTIES OF AND IMPROVEMENTS TO TIME- WIRELESS INNOVATIONS FOR SMARTPHONES Room – Oisans 0830-1000 DOMAIN DYNAMIC THERMAL ANALYSIS ALGORITHMS Abstract: The ever increasing demand for fast mobile X Chen and R P Dick, U of Michigan, US internet connectivity continues to set challenges for Organisers/Moderators: L Shang, U of Colorado at Boulder, US A Jerraya, CEA-LETI MINATEC, FR research in radio communications. On one hand the J Goodacre, ARM, UK TRACK E - SKEWED PIPELINING FOR PARALLEL SIMULINK capacity demand can be served by offloading data traffic to local networks. On the other hand using more Cloud computing will provide unlimited computing power SIMULATIONS A Canedo, T Yoshizawa and H Komatsu, IBM Research, JP bandwidth, and possibly dynamically allocating spectrum and mobile terminals will take benefit of these new flexible in a flexible way, will improve the usage of the available computing platforms. This session presents the context of BEST IP - TOWARDS A CHIP LEVEL RELIABILITY SIMULATOR spectrum. The future of wireless access continues to be future mobile terminals, the key evolutions that will enable FOR COPPER/LOW-K BACKEND PROCESSES defined by the 3GPP and IEEE standards setting bodies. access to cloud computing and the new functions that will M Bashir and L Milor, Georgia Institute of Technology, US Radios can also provide innovative features that offer new require cloud computing. functionalities for consumers, such as ultra fast local Presentation of the EDAA Outstanding Dissertation connectivity, sensing and positioning. Awards HOT TOPIC/EMBEDDED 6.1.1 TUTORIAL – Ultra Low Power Smart Devices • THURSDAY • THUtRhuSrsDdaAy Y17 •m arch Room – Oisans 1100-1230 Organisers/Moderators: J Goodacre, ARM, UK Intelligent Energy Management - Supply and A Jerraya, CEA-LETI MINATEC, FR Low power is considered the key enabling technology for Utilisation Special Day future smart systems. For most applications stringent requirements on power consumption has to be satisfied. This session presents power issues in different application The Role of the EDA Energy Transfer, Generation domains and how specific requirements are addressed. This Community in the Future of 9.1 and Power Electronics 12.1 is illustrated with hardware/software design techniques for World Energy Supply and concrete products. Room – Oisans 0830-1000 Conservation?
Organisers: HOT TOPIC – Smart Medical Room – Oisans 1600-1730 7.1 Implants P Mitcheson, Imperial College, UK P K Wright, UC Berkeley, US Organisers/Moderators: P K Wright, UC Berkeley, US Moderator: P Mitcheson, Imperial College, UK Room – Oisans 1430-1600 P Mitcheson, Imperial College, UK Organisers: Panellists: Issues relating to energy resources are set to play an A Jerraya, CEA-LETI MINATEC, FR L Bomhold, Synopsys, US increasing role in all of our futures. This special day at J Goodacre, ARM, UK T Green, Imperial College, UK DATE is intended to further involve the EDA community in A Ephrimides, Maryland U, US Moderator: energy related matters at all scales. This session covers C Blumstein, California Institute for Energy and S Yoo, POSTECH, KR setting the scene for the day on energy, covering topics Environment, US from levels of micro Watts to Giga Watts. Medical implants integrate a large number of heterogeneous S Henry, RTE, FR components (computing, sensors, actuators, antenna, RF) to implement sophisticated functions. Unlike classic Until recently the electrical power industry has relied devices, the design of medical implants includes the Smart Energy Generation: solely on traditional technologies - copper and iron as building of application specific architecture and specific cables, transformers and machines as the mainstream 10.1.1 Design Automation and the solution for the generation, transmission and distribution interfaces and other kinds of packaging required to Smart-Grid efficiently interface with human body. This session of power. Whilst use of these materials and technologies is here to stay, improvements in power semiconductor introduces the key technologies for the design of such Room – Oisans 1100-1230 complex devices. technology mean that the industry is moving into a Organisers: position where more and faster control of power systems P Mitcheson, Imperial College, UK can be achieved. This high level control requires a sensing PANEL SESSION – Integrating P K Wright, UC Berkeley, US and communication infrastructure to be put in place across 8.1 the Real World Interfaces the network. At the same time, the use of electricity in Moderator: the home, through the potential of real time consumer P K Wright, UC Berkeley, US pricing requires new technologies. This panel session aims to pull together heavy current Room – Oisans 1700-1830 This session will look at issues relating to the supply side of the electrical grid, including smart grids and the role of electrical power engineers and light current electronic Organisers/Moderators: electric vehicles in future supply infrastructure and engineers to form a discussion and debate about the A Jerraya, CEA-LETI MINATEC, FR includes talks from both industry and academia. future role of EDA in applications which are being brought J Goodacre, ARM, UK about by changes in the functioning of the power industry. Power engineers from both industry and academia will Panellists: stimulate the discussion with requirements both from a P Urard, STMicroelectronics, FR Smart Energy Utilisation: system perspective and consumer perspective. The J Rabaey, UC Berkeley, US 11.1 From Circuits to Consumer representatives from the EDA side will respond with what R Bramley, STEricsson, FR Products contributions they believe EDA can make, what already A King-Smith, IMGTEC, UK exists or is a simple development problem and what Room – Oisans 1400-1530 W Burleson, Massachusetts U, US research issues remain in achieving these goals. In F Perruchot, CEA-LETI, FR Organisers: summary, this panel aims to provide motivation for the P Mitcheson, Imperial College, UK EDA industry to work on useful technology that can be Smart systems require interfacing more of the world in an P K Wright, UC Berkeley, US applied to heavy power systems with a view to improving integrated solution (Camera, gyroscope, compass, temp, global energy efficiency. direction…). This is imposed by social evolution and enabled Moderator: by new integration technologies. So far, many products P Mitcheson, Imperial College, UK featuring a variety of hardware and software have been developed and many more seems to be coming in a fast This session concentrates on smart use of energy at the growing market. The panel will present the most promising demand side - from energy issues at the circuit level to products and solutions and discuss the innovations enabling larger scale issues with consumer products and use of future smart systems. energy in the home. DATE 11 EVENT GUIDE 6 • THthuUrsRdaSy D17A mYa rc• h • FRIDAY • FRIDAY • FfRridIaDy 1A8Y m a• rch
10.1.2 SPECIAL DAY KEYNOTE Friday Workshops Room – Oisans 1330-1400 Organiser: 0730 WORKSHOP REGISTRATION & WELCOME REFRESHMENTS P K Wright, UC Berkeley, US
Keynote Speaker: BREAKS Please see individual workshop programmes for lunch and break times Carmelo Papa, Executive VP Industrial and Multisegment, STMicroelectronics, IT Room – Les Bans Room – Meije Room – Bayard Room – Berlioz 0830 W1 Workshop on Micro Power W2 Design Methods and Tools for W3 Third Friday Workshop on W4 Bringing Theory to Practice: SMART ENERGY AT ST Management for Macro Systems on FPGA-Based Acceleration of Designing for Embedded Parallel Predictability and Performance in TO Chip (uPM2SoC) Scientific Computing Computing Platforms: Architectures, Embedded Systems The exponential increase of world energy demand, with a 1700 Design Tools, and Applications forecasted raise of 45%[1] between 2010 and 2030, makes energy management one of the most urgent topics of the century and a key driver for semiconductors and electronics products evolution. The main solutions for Room – Stendhal Room – 7 Laux 4 Room – Belle-Etoile Room – Chartreuse world energy demand and global warming issues have been 0830 W5 3D Integration – Applications, W6 M-BED'2011, the 2nd Workshop W7 Hardware Dependent Software W8 1st International QEMU Users individuated in two main streams: an increasing offer from Technology, Architecture, Design, on Model Based Engineering for Solutions for SoC Design Forum (QUF) TO Automation, and Test Embedded Systems Design alternative energy sources and their integration into the 1700 new Smart Grid and a reduction of the demand through an increase of systems efficiency.
In energy supply and distribution, the Smart Grid is in fact impacting for an estimated 14% of CO2[2] emissions reduction in the global energy system by 2020. In addition it makes it possible to generate high cost savings for industrial and economic system (188 Billion$ per year DATE 11 estimated only for U.S.[2]) New measures for Energy Efficiency will contribute up to 8 OPENING PLENARY Giga-Tons of CO2 reduction (54% of total with the application of policy 450[1]) by 2020, mostly thanks to power electronics applications. Auditorium Dauphine Along these two areas of intervention, ST is investing to provide both effective power semiconductor technologies and ICs for new topologies for power conversion, but not only. New materials (SiC) for power transistors, innovative solutions for Biologically-inspired massively-parallel architectures – computing power management and digital control, wired and wireless ICs are some examples of ST offer that apply to energy related beyond a million processors applications like PV converters, Smart Metering, Connectivity, S Furber, ICL Professor of Computer Engineering, Building Automation, Electrical Traction and Motor Control. School of Computer Science, Manchester U, UK Along the energy theme, though at different orders of magnitude, innovation for portable systems is tackled at ST R&D: extremely low consuming CMOS technology for digital ICs, low power RF transceivers, milliWatt capable super thin batteries and 3D integration techniques are the base for miniaturised, long lasting battery based systems, that enable new scenarios How technology R&D leadership brings a competitive advantage in the especially in portable Healthcare and Wireless Autonomous Sensors Networks. fields of multimedia convergence and power applications P Magarshack, Group Vice-President, Technology R&D - General Manager, Central CAD [1] Source: International Energy Agency [2] Source: The Climate Group and Design Solutions, STMicroelectronics, FR [3] Source: Grid 2030 A National Vision for Electricity s Second 100 Years, United States Department of Energy, Office of Electric Transmission and Distribution
See you at DATE 12, 12-16 March 2012, ICC, Dresden, Germany
DATE 11 EVENT GUIDE 7 • EXHIBITION THEATRE • EXHIBITION TeHxhEibAitTioRn tEh e•atre 3.8 PANEL SESSION – Power Formats: * How do IP-XACT and assembly tools help with this internal management problem tuesday 15 march Beyond UPF and CPF • TUESDAY • * Are companies starting to organize 3rd party IP ET01 Highlights of DATE11 Exhibition 1430 - 1600 suppliers to provide virtual platform and RTL IP, as /Clustering – an Enabler for Micro and Organiser/ Moderator: well as IP-XACT B Pangrle, Mentor Graphics, US * What are the challenges in defining IP catalog Nanoelectronics Panellists: requirements to 3rd parties? J Biggs, ARM, UK * Are standards needed in addition to IP-XACT to 1045 - 1115 C Clavel, ST-Ericsson, FR enable freer IP creation and exchange? Organiser/Moderator: O Domerego, Texas Instruments, FR Juergen Haase, edacentrum, Germany K Just, Infineon/Intel, DE ET03 STMicroelectronics automates Speaker: B Moison, STMicroelectronics, FR Andreas Bruening, Silicon Saxony, Germany Abstract: Two formats for specifying power intent are quality monitoring for improved Abstract: Each morning Juergen Haase (edacentrum, currently in wide use in industry today and as designers design productivity Germany) will open DATE11 Exhibition with an overview continue to strive for more power efficient designs new about the highlights of the Exhibition program and provide issues arise that certainly need new solutions to improve 1730 - 1750 on today’s standards. This panel will discuss areas for brand-new information on “What’s hot today” to all Organiser: attendees . improving today’s power formats and the direction that these formats need to move in order to provide the most Satin Technologies, STMicroelectronics Andreas Brüning, in the Silicon Saxony Cluster (Germany) efficient flows for design and verification and especially Speaker: responsible for the work of the micro/nanoelectronic with regards to low-power. The scope of the formats and Indavong Vongsavady, ST CCDS devision, will invite all attendees to establish close their suitability from early ESL design exploration to back- collaboration between clusters like Grenoble and Dresden Abstract: The Central CAD and Design Solutions (CCDS) end sign-off checking will also be discussed along with any in his talk: group at STMicroelectronics is in charge of developing and issues that need to be addressed in order to make design Clustering: an Enabler for Micro and Nanoelectronics and verification engineers more productive. deploying design libraries, kits, flows and methodologies A short overview about Silicon Saxony will be followed by throughout the different groups at ST and ST-Ericsson. describing micro and nanoelectronics as an opportunity for ET02 What is missing to enable They also offer internal design services for very complex Europe as well as clustering as an enabler for micro and global IP collection, assembly, and chips. nanoelectronics based on the example Grenoble and In order to make design quality monitoring more timely Dresden. Presentation of Dresden & Genoble cluster as a virtual platform distribution? and accurate, ST CCDS has adopted VIP Lane to help cooperation for Europe and the expectation to strengthen 1615 - 1715 exchange in Design Automation experience. turning their design checklists into fully automated Organiser: dashboards. These dashboards are becoming the Magillem foundation for on-the-fly, fact-based communication 2.8 EMBEDDED TUTORIAL – Moderator: between all stakeholders of the same design project. Mladen Berekovic, University of Jena, Germany Addressing Critical Power This presentation will show the benefits of this approach Speakers/Panellists: Management Verification Issues in (sharing of more formal design practices, accurate Cyril Spasevski, Magillem, CTO, France Low Power Designs Michael McNamara, Cadence, VP and GM and System communication between design teams, shorter design Software Group, USA cycle) and illustrate these benefits with real life examples. 1130 - 1300 John Goodenough, ET04 Optimization of Power-MOS Organiser: ARM, VP Design Technology and Automation, UK B Kapoor, Mimasic, US Antoine Perrin, ST, CAD Manager, France Structures dedicated to Energy Moderator: Abstract: The domains of RTL design, virtual platforms, Management ICs K Just, Infineon, DE high level synthesis, and IP assembly automation are Abstract: Power management techniques that leverage converging to enhance the productivity and reliability of 1750 - 1810 voltage as a handle are being extensively used in power system level design methodology. A significant number of Organiser: companies are creating RTL IP catalogs and leveraging sensitive designs. These techniques include power gating, Edxact, ST-Ericsson power gating with retention, multiple supply voltages, assembly automation to rapidly produce incrementally Speaker: dynamic voltage scaling, adaptive voltage scaling, multi- innovative SoCs. Virtual platforms are enabling a growing threshold CMOS, and active body bias. The use of the practice pre-RTL software development. High level Jérôme Lescot, ST-Ericsson, France power management techniques also imply new challenges synthesis is increasing the productivity to create new RTL Abstract: Impact of metal routing on 'rdson' parameter of in validation and testing of designs as new power states IP. The confluence of these forces is creating a plethora of power-MOS devices is increasing with more advanced opportunities, and presenting several challenges. This are created. We look into verification issues along with process nodes (65n, 40n). Capacity of comanche tool to panel will explore and debate the priorities and benefits of the solutions to these issues using a verification strategy quickly extract thousands of pin to pin resistances enables that involves power-aware simulation, rule-based these emerging trends and discuss the following us to achieve layout optimization by analysing resistances structural checking, formal tools, and methodology questions: recommendations. We detail our varied experiences with * How far along are customers in creating internal distribution from pads to any individual transistor. In various design teams in addressing these low power virtual platform IP catalogs? addition, jivaro reduction makes possible the spice verification issues for applications such as the wireless * What are the challenges of organizing virtual simulation of the structure including both parasitic handset, low power microprocessors, and GPS. platform and RTL IP catalogs? resistors and functional devices to extract rdson parameter. Exhibition Theatre Overview
Tuesday 15th March Wednesday 16th March Thursday 17th March
1045 - 1115 ET01 Day 1 Opening Session: Highlights of 1000 - 1030 ET06 Day 2 Opening Session: Highlights of 1000 - 1010 ET09 Day 3 Opening Session: Highlights of Date11 Exhibition / Clustering – An Enabler for Date11 Exhibition / More Than Moore Solutions Date11 Exhibition / Testimonials Micro and Nanoelectronics for Automotive Products 1010 - 1030 ET10 Testimonial: System Level Power 1130 - 1300 2.8 Embedded Tutorial: Addressing Critical 1030 - 1050 ET07 Testimonial: Ball Grid Array Packages Integrity Analysis and Supply Network Power Management Verification Issues in Low Electrical Optimization Using Apache Package Optimization of a Dual Core CPU Power Designs Modeling Tools 1030 - 1050 ET11 Testimonial: Co-Verification of an 1430 - 1600 3.8 Panel: Power Formats: Beyond UPF and CPF 1100 - 1230 6.8 Panel: Embedded Software Debug and Test Interrupt Driven Firmware Subsystem using Cadence ISX and Coverage Driven Techniques 1615 - 1715 ET02 Panel: What is Missing to Enable Global 1315 - 1415 ET08 Panel: Process Variability: Challenges and IP Collection, Assembly, and Virtual Platform Solutions 1100 - 1230 10.8 Panel: State of the Art Verification Distribution? Methodologies in 2015 1430 - 1600 7.8 Embedded Tutorial: Predictable System 1730 - 1830 ET03 Testimonial: STMicroelectronics Integration 1245 - 1345 ET12 Panel: Early Timing and Power Automates Quality Monitoring for Improved Information of Complex So C Designs using 1700 - 1830 8.8 Embedded Tutorial: Communication Design Productivity Augmented Virtual Platforms Networks in Next Generation Automobiles ET04 Testimonial: Optimization of Power-Mos 1400 - 1530 11.8 Hot Topic: Stochastic Circuit Reliability Structures Dedicated to Energy Management ICS Analysis in Nanometer CMOS ET05 Testimonial: How Software Development 1700 - 1830 12.8 Hot Topic: Synthesis Supported Increase Can Take Benefit of a Platform Power Model of the Analog Design Efficiency
DATE 11 EVENT GUIDE 8 • EXHIBITION THEATRE • EXHIBITION TeHxhEibAitTioRn tEh e•atre ET05 How Software development can performances expected by the end users. Laurent Marechal joined STMicroelectronics in 2006 after Cost pressure is leading to reduction of area for the Silicon being graduated as M.S. degree in electrical engineering take benefit of a platform power and for the mass production packages will lead to a from Polytech’Lille. He joined the Corporate Packaging & model limitation to off-the-shelf technologies or development of Automation team to develop embedded passive devices. In new cost reduction processes and technologies. addition he is now in charge of accurate package modeling 1810 - 1830 Time to market is requesting first design to be the final using 3D Electromagnetical tools and of the support of the electrical driven co-design activity aimed to ensure the Organiser: product. This can only be achieved by an increase effort in best trade-off during BGA package design in close relation DOCEA Power, ST-Ericsson term of modelling. Modelling in therefore mandatory in all with the product Divisions. Speaker: fields, system level, component level, die level etc… All Patrick Arnould, Senior System Architect, physical domains are contributing: electrical, thermal, 6.8 PANEL SESSION – Embedded ST-Ericsson, France mechanical & thermo-mechanical. Software Debug and Test Abstract: The increasing complexity of applications Miniaturisation will request smaller package, thinner traces, running on multimedia mobile platforms is becoming more thinner substrate. All these aspects have consequences on 1100 - 1230 and more critical for battery life, so software optimization the electrical behaviour of the package. From a “electrical Organiser/Moderator: to take into account power consumption is crucial but transparent” media in the end of 1999, there are now M Winterholer, Cadence, DE becoming the bottlenecks in many applications. could become very painful without a dedicated Panellists: environment. A lot of power saving is possible at the In this talk we will first demonstrate the effects of these F Cerisier, EASii-IC, FR software level but the investigations are complex due to constraints on real package designs, in term of application S Davidmann, Imperas, UK the number of parameters involved in this optimization: speed, bandwidth of signals, and impact on the margins. L Ducuosso, STMicroelectronics, FR clock gating, dynamic power switching, dynamic voltage We will also explain why the counterpart of this increasing J Engblom, Simics Wind River, SE and frequency scaling, traffic, CPU and IP load. complexity in the package is requesting the help of new A Mayer, Infineon, DE tools that can bridge the several part of the system to In this testimonial, a validation environment will be used Abstract: Today’s complexity of embedded software is ensure a full system optimisation. as an example to show the benefit for software developers steadily increasing. The growing number of processors in a to have access to a combination of CPU load, traffic and Preliminary package studies are necessary to define the system and the increased communication and power figures phase per phase and power supply per power packaging technology that needs to be optimized versus synchronisation of all components requires scalable debug supply. It also outlines the challenges for a power the die and the board. It consists in impedance and test methods for each component as well as the modeling methodology to be able to target a wide range of computation, interfaces layout strategy and power delivery system as a whole. Considering today’s cost and time to applications, very low power and power hungry systems strategy. The used tools and the results expected from market sensitivity it is important to find and debug errors optimization. Taking the benefit of having a platform these preliminary studies may differ depending the as early as possible and to increase the degree of test and power model and before starting any software application and/or the interfaces. debug automation to avoid quality losses. These development, key decisions can be taken to focus very Digital consumer projects (TV, Computer, etc…) are usually challenges are not only requiring new tools and quickly on the best software option to gain power. using quite big packages as they are not constrained by a methodologies but also organisational changes since The testimonial scope goes from power model construction form factor. This enables the use of power & ground planes hardware and software developer have to work closer to fast software optimization on a real application showing on dedicated layers of the package. The package size and together to achieve the necessary productivity and quality the benefit to speed up software development and the interface speed are thus requesting a control of the gain. The panel will discuss new strategies in hardware platform power optimization. impedance for both single and differential signals. and software development to make embedded software We will show simulation results based mainly on digital more reliable and easy to debug. wednesday 16 march projects (TV applications, Computer & Broad band signals). ET08 Process Variability: Challenges • WEDNESDAY • Several modelling tools have been used: and Solutions ET06 Highlights of DATE11 Exhibition * 2D tools (Ansoft) are used to define the impedance guideline derived from the selected technology /More than Moore Solutions for 1315 - 1415 * Fast quasi-static modelling tools enables the Organiser/Moderator: Automotive Products extraction of the preliminary design databases models for Stephane Fiorillo, Infiniscale, France both signal nets and power delivery network Speakers/Panelists: 1000 - 1030 First order results will then permit to validate some early Trent McConaghy, Solido Design Automation, USA Organiser/Moderator: choices in term of technology and routing strategy. They Jean-Paul Morin, STMicroelectronics, France Juergen Haase, edacentrum, Germany are also used to start some preliminary simulation at Philippe Raynaud, Mentor Graphics, France Speaker: system level to ensure time to market objectives. Vincent Fischer, Infiniscale, France Andreas Bruening, ZMD, Germany More accurate models will generated later on during the Abstract: This panel will focus on the process variability Abstract: Each morning Juergen Haase (edacentrum, design phase to refine the simulations and get more affecting analog, mixed-signal, and custom digital designs, Germany) will open DATE11 Exhibition with an overview quantitative results (Apache Sentinel PSI, Ansoft HFSS) the various challenges it raises and the solutions that can about the highlights of the Exhibition program and provide Package and board resonances can also be studied once be applied to handle those issues. A presentation of the brand-new information on “What’s hot today” to all the design database are close to completion. Linking the various types of process variability (lot to lot or global attendees. package and board database leads to resonance variations, local variations such as mismatch, layout Andreas Brüning, director technology office of ZMD frequencies that need to be considered versus the effects…) will be done. The stakes of this variability will (Germany), will review the productivity in designing More application frequencies. be highlighted, in particular the effects on the yield. The than Moore applications and discuss what is required for Mobile platform system using multi-GHz CPU cores are various approaches to handle this variability will be analog-mixed signal automotive products in his talk: needing a proper methodology to handle the power presented. At simulation level, from PVT corner simulations Trends, Challenges and Solution Statements for More than integrity analysis and supply network.The optimization of to statistical analysis (Monte Carlo and enhanced Monte Moore concerning Analog-Mixed Signal Automotive the power delivery network (PDN) of a System on Chip Carlo), various approaches can help the designer to Products (SoC) is becoming more and more complex with the analyze the effects of the process variability, and to Analog Mixed Signal is a very healthy niche regarding increasing operating frequency of its CPU cores. determine the yield. The model-based approach, which micro-/nanoelectronics. Unfortunately the design The defined methodology is mainly using Apache tool uses simulation results to build a behavioural model, productivity has not developed much during the last features to generate the needed models and run the allows the designer to optimize the device sizes taking decade and is far behind the More Moore miniaturization. required analysis. The capabilities of Apache RedHawk are into account the process variability in order to minimize The talk is dealing with the increasing complexity and to extract a power model from a SOC, that can be reused in its effects and maximize the yield. Some concrete related productivity based on an analog-/mixed signal package centric tools to optimise further the power examples will be presented, with the presentation of the benchmark. Demonstrating design challenges, optimization delivery network at package (and board) level. On the design, the effects of process variability, the solutions that areas and existing solutions. As a result the hot topics for other side the package modelling tool (Apache Sentinel were implemented and the final results. Finally, the panel productivity increase are shown. NPE) is able to extracted a model that can be imported in will be concluded by on open discussion and questions from the audience. ET07 Ball Grid Array Packages the die voltage drop analysis tool (Apache RedHawk) to evaluate the impact of the package routing. electrical optimization using Apache 7.8 EMBEDDED TUTORIAL – Predictable System Integration package modeling tools SPEAKERS' BIOGRAPHIES Yvon Imbs joined STMicroelectronics in 2000 after being 1430 - 1600 1030 - 1050 graduated as a Ph.D from University of Limoges. He worked Organiser/Moderator: Organiser: for 4 years as responsible of electrical package modeling. W Kruijtzer, Synopsys, NL Apache / ST He started some activities on IC package co-design inside Abstract: Starting from the application side, we present Speakers: the Telecom, Peripheral & Automotive Division of ST. Then system functions and their implementations on CPUs and Yvon Imbs, ST Corporate Packaging & Automation, France he joined the Corporate Packaging & Automation team. In function-specific hardware using concrete examples from Laurent Marechal, ST Corporate Packaging addition to the electrical package modeling, he started a the video processing domain. This includes quantitative & Automation, France Package Design Kit activity linked to the ramp-up of the data on bandwidth and latency requirements and an Abstract: Today’s packages are facing many challenges IC-Package co-design activity. Now he’s is charge of the overview of challenges developers face if the SoC linked to cost pressure, Time to Market improvement, electrical driven co-design aimed to ensure the best trade- infrastructure lacks basic provisions for Quality-of-Service. miniaturisation. These evolutions are not, for some of off between cost & performances for the BGA packages. We then present how these challenges can be addressed by them, moving in the right direction to sustain the a combination of architectural principles and associated DATE 11 EVENT GUIDE 9 • EXHIBITION THEATRE • EXHIBITION TeHxhEibAitTioRn tEh e•atre analysis techniques, based on network calculus. Finally we regulator. From this analysis, a Chip Power Model (CPM) is ET12 Early Timing and Power show how these techniques can be applied in building generated to enable, in Apache Sentinel-PI and other real-life SoCs. Key benefits of the presented techniques tools, both package and board level analyses taking into Information of Complex SoC Designs are predictable performance and improved time-to-market, account the complete system. using Augmented Virtual Platforms while avoiding costly over-dimensioning to guarantee real- For the U8500 project, this study resulted in a PDN time behaviour. impedance reduction of about factor 6 in the critical 1245 - 1345 8.8 EMBEDDED TUTORIAL – frequency range and enabled an increase from a 600MHz to Organiser: a 1GHz ARM Dual Cortex A9. This also provided an efficient COMPLEX FP7 European integrated project Communication Networks in Next placement, number and value of decoupling capacitors. Moderator: Generation Automobiles The benefit of this solution is the consistency of models and Kim Grüttner, OFFIS, Germany analysis in the various environments, an access to a simple Speakers/Panellists: model (describing a CPU core power/ground grid and its 1700 - 1830 Kim Grüttner (OFFIS) current activity) that could be used with different simulation Organisers: Bart Vanthournout (Synopsys) setups, and an enabler for correlation with measurements. T Kazmierski, Southampton U, UK Franco Fummi (EDALab) This methodology also provides a first step to solve the C Grimm, TU Vienna, AT Emmanuel Vaumorin (Magillem Design Services) foreseen challenges of the next generations of CPU cores. Moderator: Abstract: Consideration of an embedded system’s timing C Grimm, TU Vienna, AT behavior and power consumption at system-level is an ambitious Abstract: The tutorial addresses upcoming technologies SPEAKERS' BIOGRAPHY task. Sophisticated tools and techniques exist for power and aimed at communication networks for automotive Olivier Bayet joined STMicroelectronics in 2000 after timing estimations of individual components such as custom applications. The first presentation will discuss graduating as a microelectronics engineer from ENSEIRB hard and software as well as IP components. But prediction of applications of networked or even autonomous sensors in a engineering school. He has worked as a CAD design engineer the composed system behavior can hardly be made. car. The second presentation will emphasize novel, cross- in the area of IC/Package assembly checks and Voltage Drop In this session we present the concept of an ESL industry communication technologies that enhance the analysis, and is currently leading in ST-Ericsson an framework for timing and power aware rapid virtual system standard IEEE 802.3 switched Ethernet. The third and IC/Package co-design and Signal & Power integrity activity prototyping of embedded HW/SW systems. Our proposed fourth presentations will introduce applications and for digital ICs embedded in mobile platforms. flow combines system-level timing and power estimation methods for the design of wireless communication in a car, ET11 Co-Verification of an interrupt techniques available in commercial tools with platform- including methods for wireless energy supply of sensor based rapid prototyping. Our proposal aims at the nodes in cars as well as design tools and methods for driven firmware sub-system using generation of executable virtual prototypes from a design of wireless sensor nodes. Cadence ISX and Coverage Driven functional C/C++ specification. These prototypes are techniques enriched by static and dynamic power values as well as thursday 17 march execution times. They allow a trade-off between different • THURSDAY • 1030 - 1050 platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. Organiser: ET09 Highlights of DATE11 Exhibition The proposed flow will be implemented in the COMPLEX EASii-IC, France /Testimonials FP7 European integrated project (http://complex.offis.de). Speaker/Panellist: 1000 - 1010 François Cerisier, Senior Verification Consultant and EDA 11.8 HOT TOPIC – Stochastic Circuit Organiser/Moderator: Activities Manager, EASii-IC, France Reliability Analysis in Nanometer Juergen Haase, edacentrum, Germany Abstract: As System-On-Chip complexity continues to CMOS Abstract: Each morning Juergen Haase (edacentrum, increase, complex state machines are being replaced by processor based sub-systems. The functionalities of such Germany) will open DATE11 Exhibition with an overview 1400 - 1530 about the highlights of the Exhibition program and provide sub-systems are partitioned between hardware blocks and dedicated interrupt based firmware. Organiser/Moderator: brand-new information on “What’s hot today” to all G Gielen, KU Leuven, BE attendees . Verifying such sub-systems faces the challenge of identifying bugs not only in both the hardware and the Abstract: Process variability causes statistical spread on This will be followed by testimonials providing attendees the performance of ICs, eventually limiting circuit yield. with experience gained in real-life projects: designers software parts, but also at the boundary of the two disciplines. In addition, aging effects in nanometer CMOS technologies present how they were able to solve major design cause a shift in transistor parameters over time, possibly Co-Verification methodologies have proved to be challenges with state-of-the-art methodologies and tools. causing circuit malfunction within the lifetime of the interesting approaches for critical software verification. circuit. Some of these wear-out phenomena are stochastic ET10 System level power integrity Existing methodologies are however based on the in nature, introducing asymmetry in circuits. To guarantee assumption that the software provides APIs or software analysis and supply network a reliable product over the entire lifetime, fast and interfaces. They therefore do not directly apply to interrupt efficient design tools can help a designer to estimate the optimization of a dual core CPU driven firmware of these sub-systems. impact of various reliability threats on his/her circuit, at We present here an approach which enables interrupt 1010 - 1030 design time. The stochastic nature of the phenomena based firmware verification for such partitioned Organiser: requires techniques well beyond current commercial tools. hardware/firmware sub-systems at the early stages of the Apache / ST-Ericsson This hot topic session addresses both accurate stochastic project and before the silicon is available. This transistor compact models that include reliability effects, Speakers/Panelists: methodology has been applied on an industrial complex as well as efficient stochastic CAD solutions to evaluate Olivier Bayet, System in Package (SiP) design, control sub-system. Hardware event controllability and the reliability of an IC at circuit level and at system level. ST-Ericsson, France observability is reached using extended hardware coverage In addition, alternative novel system approaches are Abstract: The optimization of the power delivery network driven verification techniques and the required software presented that exploit the stochasticity. (PDN) of a System on Chip (SoC) is becoming more and observability is achieved using the monitoring facilities of more complex with the increasing operating frequency of Cadence ISX tool (Incisiv Software Extension). 12.8 HOT TOPIC – Synthesis its CPU cores. Having a proper methodology to handle the power integrity analysis and supply network optimization 10.8 PANEL SESSION –State of the Art Supported Increase of Efficiency in is required to secure the integration of multi-GHz CPU Verification Methodologies in 2015 Analogue Design cores in a mobile platform system. The approach used for ST-Ericsson U8500, the industry’s 1100 - 1230 1600 - 1730 first dual core SMP platform integrating a HSPA+ modem, Organiser: Organiser: is based on a system level context available in the T Fitzpatrick, Mentor Graphics, US J Nowak, IMMS GmbH, DE simulation environments of each PDN contributor. For this Moderator: Moderator: project, the analysis goal was to reach an operating A Crone, Mentor Graphics, SE R Sommer, TU Ilmenau, DE frequency of 1GHz by optimizing the power integrity of the Panellists: Abstract: Analogue design still is the bottleneck in the ARM Dual Cortex A9 embedded in the U8500 platform. C Chevallaz, STMicroelectronics, FR development of mixed-signal ICs. This is due to the fact In this paper, the first part is describing the methodology B Dickman, ARM, UK that the three steps in analogue circuit design – topology and flow used to perform a CPU core power integrity check V Esen, Infineon Technologies, DE generation or modification, sizing and layout generation – in a core block level environment using a system level O Bringmann, FZI, DE are mainly carried out by hand. In this special session context. The second part is explaining how to extend it to M Rohleder, Freescale, DE four methods will be presented which allow a semi- an analysis in package or platform environment still using a Abstract: In the last few years, the industry has seen automated design process. These approaches include a system level context. For this methodology, Apache Design acceleration in the evolution of verification fully automated hierarchical topology generation for Solutions tools provide useful features and extracted methodologies. While the industry focus has been on analogue circuits, a generation of a compensation network models to enable power supply analysis at system level. enabling a standard based approach to help today’s by automated topology modification, a methodology for Taking into account the capabilities of Apache RedHawk to challenges, one can wonder what is needed to prepare us sizing based on a combination of analytic and numerical load a top level and package context even for a voltage self for the further verification challenges. The expert techniques and a method for modular layout generation. drop analysis at block level, a SoC partition is created and panellists will discuss the many aspects of verification The methods and the resulting tools relieve the designer plugged into the tool with models of a package and a methodologies, the requirements and predictions for from routine tasks, allow more space for creativity and board with its decoupling capacitors and a voltage verification methodologies needed 4-5 years from now on. enable re-use. DATE 11 EVENT GUIDE 10
• SOCIAL NETWORKING • SOCIAL NETWOsoRciaKl nIeNtwGor k• ing
The DATE 11 conference programme allows generous A number of specialist interest groups will be holding their meetings at DATE. Currently, the following opportunities for delegates to visit the exhibition and attend the presentations in the exhibition theatre. meetings are scheduled but a full list of fringe meetings with description of content will be found on the DATE web portal – www.date-conference.com COFFEE & LUNCH BREAKS Delegates coffee will be served in the main exhibition hall Time and the additional exhibition area. Lunch is available in Room Ecrins on the lower ground floor and in the Day Time Meeting & Contact Room Type exhibition hall there is a cash bar for visitors and Mon 1900-2100 EDAA/ACM PhD Forum Salle de Open exhibitors. Peter Marwedel
DATE PARTY 1930 - Wednesday 16 March This year the DATE party will take place in the World Trade Center on Wednesday 16 March. The evening will feature a buffet style dinner with plenty of buffet points and drinks to accompany dinner. Musical entertainment with the opportunity to dance will be provided by the popular neo- folk band DJAL. In an enjoyable atmosphere participants will have the opportunity to meet and mingle with their friends and colleagues. All conference attendees, users, vendors and their guests are encouraged to come to the party. Additional tickets for the full Evening Social Programme may be obtained for 70 Euros each (please ask at the registration desk). Entrance will be by ticket only, so please check that you receive the party ticket when you register. Commercial sponsor
The event is sponsored by: the European Design and Automation Association the EDA Consortium IEEE Council on EDA ECSI ACM - SIGDA RAS and is organised in cooperation with: ACM - SIGBED IEEE Computer Society IEEE Solid-State Circuits Society (SSCS) IFIP IET SAME
DATE 11 EVENT GUIDE 12 • MEDIA PARTNERS • MEDIA PARTNERmSed i• a partners The DATE organisation and sponsors would like to extend their warmest gratitude to all press journalists who give DATE coverage in their editorial pages. Listed below are the media houses and publications who generously agree to media partnership with DATE, and whose publications can be found at distribution points around the exhibition.
CHIP DESIGN MAGAZINE MICRONEWS
Chip Design covers all of the technical challenges and implementation Beginning in 1998 with Yole Développement, we have grown to options engineers face in the development and manufacture of today's become a group of companies providing market research, technology complex integrated circuits. Chip Design is the only media network analysis, strategy consulting, media in addition to finance services. dedicated to the advanced IC Design market. Visit With a solid focus on emerging applications using silicon and/or micro www.chipdesignmag.com to stay informed about the latest manufacturing Yole Développement group has expanded to include developments in chip modeling, architecture, design, test and more than 40 associates worldwide covering MEMS and microfluidics, manufacture, from EDA tools to digital and analog hardware issues. The Advanced Packaging, Compound Semiconductors, Power Electronics, System Level Design and Low Power Engineering Portals offer focused LED, and Photovoltaic. The group supports companies, investors and editorial content you won’t want to miss. And, be sure to visit R&D organizations worldwide to help them understand markets and www.http://eecatalog.com/ for valuable information about all of follow technology trends to develop their business. Extension Media's outstanding technology resources. Micronews Media includes our website, www.i-micronews.com, our bi- weekly magazine Micronews, and the four Technology Magazines: MEMS Trends, 3D Packaging, PV Manufacturing and Efficen'Si. EDA CONFIDENTIAL
EDA is a commercial-free publication providing a quiet place for conversation about the Electronic Design Automation industry and its TECH DESIGN FORUM companion technologies. The coverage does not intend to be comprehensive, but does intend to provide some food for thought. To that end, EDA Confidential includes "Recipes", Freddy Santamaria's Today’s electronic design engineers face broader challenges than ever "Gourmet Corner", as well as "Voices" of other contributing authors, before. Software is becoming as important as hardware. And in the IC "Off the Record" op-ed pieces, and "Conference" coverage. supply chain, former competitors are now collaborating to achieve success. Tech Design Forum publication (formerly called the EDA Tech Forum) is the premier guide for success in this complex environment. Focused on ELECTRONIQUES the design automation market, this publication and its rich website offer a wealth of practical advice on how to successfully negotiate the ElectroniqueS the reference monthly for decision makers and engineers day-to-day problems designers face. in the electronics sector Circulation of 10,000 copies www.electroniques.biz, the electronic professional’s web site Daily Newsletter, the day’s essential news about our industry’s major The IET sectors Sent to more than 26,000 free subscribers The IET is europe's largest professional body for engineers and Weekly newsletter, the newsletter that summarizes the previous 5 daily technologists, we offer a wide range of products, services and newsletters main topic professional qualifications to keep you ahead of the game. With 150,000 members based in 127 countries networking is key to their Sent to more than 23,000 free subscribers and your success - find out how to join and be part of the Knowledge Vertical newsletter, 3 subjects: Automotive / Mil-Aero / Medical Network by visiting us www.theiet.org 5 mailings a year (each 2 in 3 months)
ELEKTRONIK I NORDEN THE NEXT SILICON VALLEY
Elektronik i Norden, an important tool for the Nordic electronic The Next Silicon Valley is an independent media website that publishes industry. We want Elektronik i Norden to be the most important source global news and information about the world of innovation, of information for the Nordic electronic industry (Sweden, Finland, entrepreneurship, technology development, regional economic Norway and Denmark). A circulation of 25 800 personally addressed development, venture capital, and investment promotion across global copies proves we are the major electronics paper in this area. We markets. The Next Silicon Valley reaches readers in more than 90 publish news, comments and in-depth technical articles. countries and 400 cities worldwide.
If you would like to arrange a Media Partnership with DATE for future events, please contact: Claire Cartwright, Event Manager, European Conferences, tel: +44 (0) 203 052 8065 email: [email protected]
DATE 11 EVENT GUIDE 13 • TOOL SEMINARS • TOOL SEMINARS t•ool seminars DATE 2011 presents the Tool Seminar Track. The seminars listed below are FREE & OPEN TO ALL, however places are restricted. All seminars are held in Salle Berlioz on the Ground Floor, adjacent to the registration desk. Please collect a voucher from the registration desk.
Unifying IP-XACT platform assembly with virtual platform ADVANCES AT CMP modeling Thursday 17 March, 0900-1230 What’s new in the Europractice Wednesday 16 March, 1330-1630 CMP is a broker in ICs and MEMS for Cadence portfolio for 2011 – The goals for IP-XACT have expanded from prototyping and low volume production. Technical Update RTL IP warehousing and easier SoC assembly. Advanced industrial processes are available As virtual platform adoption has grown, the in CMOS, BiCMOS, SiGe BiCMOS, SOI, GaAs, Tuesday 15 March, 1330-1730 natural need arises to assemble TLM IP into MEMS and 3DIC. CMP distributes and supports Design Kits and several CAD tools. Today 386 institutes across Europe are using a virtual platform, and refine it into the Cadence tools via Europractice in their resulting RTL SoC. This tutorial will highlight The Seminar will review available processes education and research. The portfolio is the creation and assembly of SoCs starting as well as recently introduced processes like continuously evolving as new tools become from virtual platforms, key decisions to be 3DIC from Tezzaron, 20nm FDSOI from LETI, available from Cadence. This seminar gives taken, and potential issues to avoid. pHEMT GaAs from TRIQUINT. an update on the latest functionality from a Presenter: New processes will also be introduced like a technical viewpoint with special emphasis Jean-Michel Fernandez ([email protected]), magnetic-CMOS process. on digital, mixed signal and low power Cadence; Cyril Spasevski, Magillem design including chip planning. The seminar Presenter: also gives an opportunity for academic Bernard Courtois, Kholdoun Torki institutions to ask Cadence technical and R&D staff questions.
• EeUurRopOeaPnE EADAN v ilElaDge A INTERACTIVE A significant number of European EDA vendors will join forces and provide PRESENTATIONS the semiconductor industry with Interactive presentations allow dedicated innovation for chip and presenters to interactively discuss system development. In addition to novel ideas and work in progress that their booths in the European EDA may require additional research work village, presentations providing and discussion, with other researchers overviews and testimonials shall be working in the same area. Interested UNIVERSITY BOOTH taking place in the Exhibition Theatre, attendees can wal karound freely and along with workshops in conjunction DATE 11 will feature the University talk to any author they want in a vivid with client companies. face-to-face format. The author may Booth where system and VLSI Please see the current list of EDA illustrate his work with a slide show CADtools developed in Universities Village participants below: on a laptop computer, a and Research Institutes are demonstration, etc. IP presentations demonstrated as well as circuits in COMPANY NAME STAND NUMBER will also be accompanied by a poster. their working environment. This CISC Semiconductor Design + Each IP will additionally be introduced Consulting GmbH 43 in a relevant regular session prior to provides an alternative and more the IP Session in a one-minute, one- direct way of communicating CAD Concept Engineering GmbH 42 slide presentation. research results and displaying To give an overview, there will be one Docea 39 working silicon to the interested central projection displaying a list of INFINISCALE 40 all the presentations going on at the specialists.The University Booth will MunEDA 31 same time in the IP area. Interactive be located in the Exhibition Hall and Sessions will be held in the Salle de will be furnished with popular Nano-Tera.ch 45 Reception area in 30-minute time workstations. A rotating schedule will Satin Technologies 41 slots during coffee and exhibition operate throughout the three days. XYALIS 34 DATE 11 EVENT GUIDE 14 • VENUE PLAN • VENUE PLAN • VENUE PLAveNnu e• plan
DATE 11 EVENT GUIDE 15 • EXHIBITION FLOOR PLAN e• xhibition floor plan
DATE 11 EVENT GUIDE 16 • EXHIBITION FLOOR PLAN e• xhibition floor plan
DATE 11 EVENT GUIDE 17 • EXHIBITOR LIST • EXHIBITOR LIST e•x hibitor list
Company Stand Company Stand Company Stand
2PARMA (PARallel PAradigms and Run-time DELTA 47 MunEDA 31 MAnagement techniques for Many-core Architectures) FP7-ICT-248716 EP15 Design Automation Conference (DAC) 16 Nano-Tera.ch 45
ACCELONIX 12 DOCEA Power 39 nSilition 36
ADACSYS 8 Duolog Technologies Ltd 15 N. S. Mangat & Co. 55
ADICSYS 7 EASii-IC 29 Presto Engineering, Inc. 5
AgO Inc 10 EDA Confidential 20 ProximusDA 49
ANSYS / Ansoft 6 EDALab 48 R3LOGIC 52
ApS Brno Ltd., Codasip Division 37 edXact 23 SAME 18
Arteris, Inc. 54 ElectroniqueS 26 Satin Technologies 41
Asygn 53 Enterprise Ireland 15 SELEX Galileo 58
Atrenta Inc. 27 EUROPRACTICE 14 Silansys Semi 15
BLUE PEARL SOFTWARE 28 Fractal Technologies 11 SPRINGER 3
Chipright 15 GLOBALFOUNDRIES 1 & 2 Tanner EDA 35
CISC Semiconductor Design Gold Standard Simulations Ltd. 30 Target Compiler Technologies 4 + Consulting GmbH 43 HiPEAC NoE EP11 Tech Design Forum 19 CMP 32 INFINISCALE 40 The Next Silicon Valley 17 COCONUT EU project EP10 Infotech 57 TinnoTek Inc. 50 Compaan Design BV 44 IP SOC 11 21 TowerJazz 13 COMPLEX - COdesing and power Management in PLatform-based MADNESS - Methods for predictAble Design TRAMS (Terascale Reliable Adaptive design space EXploration EP16 of heterogeneous Embedded Systems with Memory Systems) EC FET-IST 248789 EP9 adaptivity and reliability Support EP12 Concept Engineering GmbH 42 Tyndall’s Design Technology Magillem Design Services 33 Evaluation Group 15 Cortus S.A. 10 MICROLOGIC Design Automation 51 University Booth 46 CréVinn 15 Midas 15 University of Southampton 22 CST - Computer Simulation Technology AG 56 MINALOGIC GRENOBLE ISERE 9 Veriest Venture 24
DEFACTO TECHNOLOGIES 25 MOSIS 35 XYALIS 34
DATE 11 EVENT GUIDE 18 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors associated with functional errors and enables stand EP15 stand 12 you to deliver more robust products. Today our offer consists of: A-Soft: the software only solution 2PARMA ACCELONIX For customers who already have their own Contact: Prof. Cristina Silvano Contact: Patrick Legenre FPGA board. Politecnico di Milano PA du Long Buisson, 260 rue Clément Ader A-Full: the complete integrated solution Dipartimento di Elettronica e Informazione 27000 Evreux This turn-key hardware and software product via Ponzio 34/5, I-20133 FRANCE includes A-Soft and an FPGA board, both Milano Italy Tel: +33 2 32 35 64 80 preconfigured. Tel: +39 02 2399 3692 Fax: +33 2 32 35 00 66 A-OD: the platform as a service version of A-Full Fax: +39 02 2399 3411 E-Mail: [email protected] This dematerialized and secure product is for E-Mail: [email protected] Website: www.accelonix.fr customers who want the immediate flexibility Website: www.2parma.eu of on-demand access in terms of capacity and ACCELONIX, société indépendante et added performance. The 2PARMA project focuses on the definition fournisseur de solutions équipements et PRODUCT FINDER of a parallel programming model combining logiciels pour l’assemblage et le test des ASIC and SOC Design: component-based and single-instruction cartes électroniques et microélectronique est Verification multiple-thread approaches, instruction set reconnue par ses CLIENTS pour son savoir- System-Level Design: virtualisation based on portable bytecode, faire, son expérience et son sens du service. Acceleration & Emulation run-time resource management policies and Dans ce cadre, ACCELONIX travaille avec des Test: mechanisms as well as design space fournisseurs offrant des solutions originales Design for Test exploration methodologies for Many-core dans le domaine du test et de la validation de System Test Computing Fabrics. composants. Services: The 2PARMA project will demonstrate Prototyping methodologies, techniques and tools by using PRODUCT FINDER Training innovative hardware platforms provided and Test: developed by the partners, including the Design for Test “Platform 2012”, an early implementation of Design for Manufacture and Yield Many-core Computing Fabric provided by Test Automation (ATPG, BIST) stand 7 STMicroelectronics. Boundary Scan To ensure a wide range of application Mixed-Signal Test scenarios comprising the typical System Test ADICSYS computation-intensive workload of a general- Hardware: Contact: Philippe DIEHL purpose computing system, a set of industrial FPGA & Reconfigurable Platforms 44 rue Cauchy high performance demanding applications will Development Boards 94110 ARCUEIL be used and customized by using the FRANCE techniques and methodologies developed in Tel: +33 1 55 01 04 35 2PARMA project. Applications’ architecture, stand 8 E-Mail: [email protected] development and integration will leverage in Website: www.adicsys.com particular from the acknowledged experience of three partners from the Consortium: HHI ADACSYS ADICSYS introduces a tool-set enabling an for Scalable Video Coding application, RWTH easy and transparent insertion of for Cognitive Radio, and IMEC for Multi View. Contact: Erik Hochapfel programmable logic for ASICs, SOCs and 7 rue de la Croix Martre silicon IPs in general. The great incentive to PRODUCT FINDER 91120 PALAISEAU implement this flexibility lies in the reduction ASIC and SOC Design: FRANCE of risks associated with errors, specification Behavioural Modelling & Simulation Tel: +33 0 1 69 19 72 72 changes and early adopters' challenges. The Power & Optimisation Fax: +33 0 1 69 19 72 72 development and verification time for critical System-Level Design: E-Mail: [email protected] blocks can be minimized while bring-up and Behavioural Modelling & Analysis Website: www.adacsys.com debugging capabilities are enhanced. Hardware/Software Co-Design In today's complex systems, customizable Services: Start verifying your FPGA IP blocs and logic can reveal itself as a key element for Design Consultancy designs from the very begining of your end user applications. Prototyping project... and on your final hardware target. ADICSYS solutions seamlessly integrate into Training ADACSYS provides innovative hardware existing design flows, making them simple Embedded Software Development: accelerated functional verification solutions and highly cost effective for customers Compilers enabling designers and developers to easily and Software/Modelling seamlessly shift from RTL software simulation PRODUCT FINDER Semiconductor IP: verification test benches to any FPGA board. Processor Platforms Our patented software compilation and Test: Application-Specific IP: runtime flow automatically maps your designs ASIC and SOC Design: Multimedia Graphics and test benches on any FPGA board. It Synthesis Wireless Communication enables you to quickly verify and certify your Services: FPGA IP blocs and designs on your selected Design Consultancy FPGA target. Semiconductor IP: Our solutions are easy to use and thus have Configurable Logic IP fast learning curves. They reduce your products time to market as well as the risks
DATE 11 EVENT GUIDE 19 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors boards and IC packages including packages stand 10 merged onto boards for complete channel PRODUCT FINDER analysis. SIwave extracts frequency ASIC and SOC Design: dependent circuit models of signal nets and Design Entry AgO Inc power distribution networks directly from System-Level Design: Contact: Dr Roddy Urquhart layout databases. Acceleration & Emulation Alpha Star Ltd HFSS™ is the industry-standard software for Hardware/Software Co-Design 10 Pitts Lane S-parameter extraction and 3-D Services: Andover electromagnetic field simulation of high- Design Consultancy SP10 2HY frequency and high-speed components. Signal Training UK integrity engineers use HFSS software to Embedded Software Development: Tel: +44 1264 369483 evaluate signal quality, including Compilers Fax: +44 1264 369483 transmission path losses, reflection loss due Debuggers E-Mail: [email protected] to impedance mismatches, parasitic coupling Software/Modelling Website: www.ago-inc.com and radiation. DesignerSI™ AgO is an EDA company, specialising in This easy to use design platform integrates stand 54 analog, RF and mixed-signal design tools. The rigorous EM analysis with circuit and system AnXplorer tool provides feasibility analysis, simulation in a highly accurate design flow. global optimisation and centering. It is Engineers using DesignerSI can leverage Arteris, Inc. multiple signal integrity simulation methods applicable to the design of circuits for Contact: Kurt Shuler such as traditional transient, fast wireless communications, automotive, 111 W. Evelyn Avenue, Suite 101, convolution, statistical, and IBIS-AMI industrial and medical applications. Sunnyvale, CA 94086, USA analyses in a single user interface. The feasibility analysis – using DC operating Tel: +1 408 470-7300 point simulations – identifies the part of the PRODUCT FINDER Fax: +1 408 470-7301 design space where the circuit is stable. Then E-Mail: [email protected] ASIC and SOC Design: AnXplorer's multi-algorithm strategy rigorously Website: www.arteris.com searches this space, and can find a global Behavioural Modelling & Simulation optimum in the presence of local optima. Power & Optimisation Arteris provides Network-on-Chip Circuit designers can use AnXplorer to rapidly Physical Analysis (Timing, Themal, Signal) interconnect IP to SoC makers so they can explore the design space to evaluate different Verification reduce cycle time, increase margins, and circuit topologies. It can also be used to find Analogue and Mixed-Signal Design easily add functionality. Unlike traditional a robust design solution over a range process, MEMS Design solutions, Arteris plug-and-play technology is temperature and supply voltage corners. This RF Design flexible and efficient, allowing designers to helps improve yield and enhances the System-Level Design: optimize for throughput, power, latency and probability of first time silicon success. Behavioural Modelling & Analysis floorplan. Arteris products reduce wire When using simulation-based optimisation Physical Analysis routing congestion and ease timing closure. AnXplorer can work with Eldo, HSpice, MSim Package Design and Spectre simulators. It also offers PCB & MCM Design PRODUCT FINDER Services: equation-based optimisation. Semiconductor IP: Training PRODUCT FINDER Encryption IP On-Chip Bus Interconnect ASIC and SOC Design: On-Chip Debug Analogue and Mixed-Signal Design RF Design stand 37
ApS Brno Ltd., Codasip stand 53 stand 6 Division Contact: Karel Masarik Asygn ANSYS / Ansoft Bozetechova 2 Contact: Andrew Betts 612 66 Brno Contact: Xavier Le Goaer 445 rue Lavoisier - F38330 Montbonnot, Czech Republic Immeuble Central Gare France Tel: +42 0608132875 1 Place Charles de Gaulle Tel: +33 4 76 89 80 27 Fax: +42 0541 211 479 78180 Montigny-le-Bretonneux E-Mail: [email protected] E-Mail: [email protected] Tel: +33 1 30 64 89 90 Website: www.asygn.com Website: www.codasip.com/ Fax: +33 1 30 64 89 91 E-Mail: [email protected] Asygn specialises in difficult analog/mixed- The Codasip® team is dedicated helping the Website: www.ansys.com signal and RF designs, providing specification customers to develop SoC’s using ASIP cores and verification solutions in the form of tools more efficiently while reducing time-to- ANSYS is a leading developer of high- and consulting. market significantly. Codasip® was founded in performance electronic design automation If you have issues simulating very large A/MS 2005. Codasip® is venture funded by Ministry software. The products are designed to or RF systems or in dealing with high-Q of Industry of the Czech Republic. simulate high performance electronics designs circuits, then come and see us. If you are fed found in mobile communication and internet up with huge simulation runtimes, caused by devices, broadband networking components signals with extremely different time and systems, integrated circuits, printed constants, then we may have a solution for circuit boards, and electromechanical systems. you. If you are tackling systems with Siwave™ analyzes entire printed circuit repeated analog content (such as imagers),
DATE 11 EVENT GUIDE 20 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors then you should look at our latest software. Asygn software products have been proven to PRODUCT FINDER stand 15 dramatically accelerate simulations on ASIC and SOC Design: complex analog systems such as mobile Synthesis phone radios, advanced MEMs sensors and Power & Optimisation Chipright complex imaging arrays. The products Physical Analysis (Timing, Themal, Signal) Contact: James O'Reilly integrate seamlessly into standard IC design Verification IIBC flows, ensuring design database consistency System-Level Design: GMIT from system-level down to circuit Physical Analysis Dublin Road implementation. Test: Galway Asygn also offers design services in the above Design for Test Ireland areas. Its extensive track record of successful Services: Tel: +353 91 444168 consulting projects includes custom tool Prototyping Fax: +353 91 444210 development – a very interesting solution for E-Mail: [email protected] companies with special challenges. Website: www.chipright.com
PRODUCT FINDER stand 28 Accelerate your SystemVerilog migration by ASIC and SOC Design: 50% with Chipright. Chipright provides Behavioural Modelling & Simulation BLUE PEARL SOFTWARE products and services for migration from Verification legacy verification languages and Analogue and Mixed-Signal Design Contact: Nichole Fox environments to the more widely supported MEMS Design 4677 Old Ironsides Drive IEEE SystemVerilog language. Our products RF Design Suite 430 and services can be utilised to speed up the System-Level Design: Santa Clara, CA 95054 USA transition timeframe's associated with Behavioural Modelling & Analysis Tel: +1 408 9610121 migration services. • Automation to jumpstart Services: Fax: +1 408 9610125 the creation of SystemVerilog test benches Design Consultancy E-Mail: [email protected] and transactors. • Training platform to Prototyping Website: www.bluepearlsoftware.com educate engineers on SystemVerilog Training verification methods. • Targeted mechanism Hardware: Blue Pearl Software provides tools which for migrating legacy verification technology FPGA & Reconfigurable Platforms lower design risk, improve the quality of into an advanced SystemVerilog solution. Development Boards results, save time and reduce the cost of their Chipright can convert legacy test benches chip design process. and BFM’s to SystemVerilog test environments Blue Pearl Software's RTL Analysis technology and transactors by utilising our extensive automatically checks HDL for compliance with verification know-how. Visit our stand today stand 27 user-selected and user-defined properties, to find out how we can migrate your existing including netlist checks and advanced test case libraries and infrastructure to Atrenta Inc. property checks for CDC. maximise the benefits on offer through using Blue Pearl's Timing Constraint Generation and SystemVerilog. We support VMM, OVM and Contact: Charu Puri Management reads RTL and statically identifies UVM. Visit www.chipright.com or email 2077 Gateway Place, Suite 300 complex false and multicycle paths that occur [email protected] San Jose due to complex control logic. Blue Pearl writes CA 95110 SDC, and writes assertions for testing paths PRODUCT FINDER USA with formal analysis tools. Blue Pearl also ASIC and SOC Design: Tel: +1 408 453 3333 merges and compares SDC and migrates Verification Fax: +1 408 453 3322 constraints up and down the design hierarchy. Services: E-Mail: [email protected] Blue Pearl's Timing Constraint Validation Design Consultancy Website: www.atrenta.com reads SDC files and validates them using Blue Training Pearl's powerful state space search Atrenta is the leading provider of Early Design technology. If paths are found invalid Blue Closure® solutions to radically improve design Pearl outputs a testbench and patterns that efficiency throughout the IC design flow. show how invalid paths can be sensitized. stand 43 Customers benefit from Atrenta tools and These three technologies have been methodologies to capture design intent, explore integrated into a single executable program CISC Semiconductor implementation alternatives, validate RTL and (The Blue Pearl Software Suite) for fast design optimize designs early, before expensive and analysis, CDC checking, and timing constraint Design + Consulting GmbH time-consuming detailed implementation. With generation, management, and validation. over 150 customers, including the world’s top Contact: Dr. Markus Pistauer 10 semiconductor companies, Atrenta provides PRODUCT FINDER Lakeside B07 the most comprehensive solution in the ASIC and SOC Design: 9020 Klagenfurt industry for Early Design Closure. Atrenta, Right Design Entry AUSTRIA from the Start! Tel: +43 463 508 808 Fax: +43 463 508 808-18 E-Mail: [email protected] WEDNESDAY 16 MARCH Website: www.cisc.at SPECIAL FOCUS DAY 1400 KEYNOTE CISC Semiconductor Design+Consulting GmbH Wireless Innovations for Hannu Kauppinen, Director, is a design and consulting service company Smartphones Head of Radio Systems Laboratory, for industries developing embedded Nokia Research Center, Finland microelectronic systems with extremely short
DATE 11 EVENT GUIDE 21 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors Time-To-Market cycles. Our core competences TEZZARON/GLOBALFOUNDRIES, and 150nm are: System design, modeling, simulation, pHEMT GaAs from TRIQUINT. ARM IP cores are stand 44 verification and optimization of available on 130nm µ and 65 nm CMOS. heterogeneous embedded microelectronic MEMS are available on various processes: systems with a particular focus on specific MEMS technologies (PolyMUMPS, Compaan Design BV Automotive and RFID systems. SOIMUMPS, MetalMUMPS from MEMSCAP, Contact: John van Brummen Our customers are represented in the SUMMIT from SANDIA). De Ruyterkade 113 Semiconductor, Automotive and RFID industry. Design kits for most IC CAD tools and 1011 AB Amsterdam CISC Semiconductor was founded in 1999 and is Engineering kits for MEMS are available. The Netherlands 100% privately owned. The company is managed Assembling is provided in a wide range of Tel: +31 20 5216686 by an international team of highest skilled plastic and ceramic packages. Fax: +31 20 6750389 experts. Our main office is situated in CAD software (tools for PCs, ARM suite of E-Mail: [email protected] Klagenfurt, Austria (close to well known tools, ...) are also proposed. Website: www.compaandesign.com Wörthersee) right in the heart of the Alpen- Adria-Region. We are proud to be able to PRODUCT FINDER Compaan Design develops technology for conduct our international business from this part Services: hotspot parallelization of legacy/certified ISO of the world and also enjoy our life with our Prototyping C applications. It offers innovative products families and friends within this beautiful nature. Foundry & Manufacturing that reliably compile and scale to state-of- Being an independent company, CISC the-art silicon with billions of transistors such furthermore is able to provide non CAD/CAE as x86 multicore, MPSoC and FPGA. market driven technology for individual The Compaan Design workflow guides step-by- customer solutions. CISC offers commercial tools stand EP10 step parallelization towards improved energy and techniques for simulation based system efficiency and computational throughput. development of embedded microelectronic COCONUT EU project Parallelism is exploited for streaming data systems including RFID systems. and increased architecture utilization. Exact Contact: Graziano Pravadelli dataflow analysis guarantees correctness and Dipartimento di Informatica - robustness of application execution. Code PRODUCT FINDER Università di Verona generation is heterogeneous and supports ASIC and SOC Design: Strada le Grazie 15, 37134 Verona, Italy flexible HW/SW codesign. Design Entry Tel: +39 045 8027081 It is a perfect solution for today's MPSoCs Behavioural Modelling & Simulation Fax: +39 045 8027068 composed of DSPs, FPGAs and System-Level Design: E-Mail: [email protected] microprocessors. It easily retargets to Behavioural Modelling & Analysis Website: www.coconut-project.eu customized processors and IP blocks. Hardware/Software Co-Design Test: The COCONUT project is intended to propose a PRODUCT FINDER System Test modelling and verification flow to enhance System-Level Design: Services: and speed-up embedded platform’s design Acceleration & Emulation Design Consultancy and configuration of mixed Hardware/Software Co-Design Prototyping continuous/discrete models. In this context, Embedded Software Development: Embedded Software Development: the scientific and technological objective of Compilers Software/Modelling the COCONUT project consists of developing a Software/Modelling Hardware: systematic methodology and a set of tools to Hardware: Development Boards integrate correct-by-construction FPGA & Reconfigurable Platforms refinement/abstraction and post-refinement Semiconductor IP: verification methods into a platform-based Embedded FPGA design flow. Application-Specific IP: stand 32 At the booth, COCONUT partners present the Data Communication project main flow, demo of tools, and Digital Signal Processing CMP relevant results. Telecommunication Contact: Bernard Courtois PRODUCT FINDER 46 avenue Felix Viallet ASIC and SOC Design: 38031 Grenoble Behavioural Modelling & Simulation OPENING PLENARY France Verification Tel: +33 476574617 System-Level Design: Biologically-inspired massively- Fax: +33 476473814 Behavioural Modelling & Analysis parallel architectures – computing E-Mail: [email protected] Hardware/Software Co-Design beyond a million processors Website: http://cmp.imag.fr S Furber, ICL Professor of Computer Engineering, CMP is a manufacturing broker for ICs and MEMS, School of Computer Science, Manchester U, UK for prototyping and low volume production. Since 1981, more than 1000 Institutions from How technology R&D leadership 60 countries have been served, more than brings a competitive advantage in 5300 projects have been prototyped through the fields of multimedia convergence 600 manufacturing runs, and more than 55 and power applications different technologies have been interfaced. Integrated Circuits are available on CMOS, Philippe Magarshack, SiGe BiCMOS, CMOS-Opto from Group Vice-President, Technology R&D - General Manager, Central CAD and Design STMicroelectronics and Austriamicrosystems, Solutions, STMicroelectronics, France 20 nm FDSOI from CEA-LETI, 3D-IC from
DATE 11 EVENT GUIDE 22 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors Eclipse-based IDE. A rich ecosystem of stand EP16 stand 42 development tools and RTOS is available. A building block approach ensures that the APS3 is an ideal processor for a very wide COMPLEX - COdesing and Concept Engineering GmbH range of requirements spanning low end, ultra power Management in Contact: Gerhard Angst low cost applications to high end, multi-core Boetzinger Str. 29 systems with multiple coherent caches. PLatform-based design 79111 Freiburg The core is well proven in many high volume space EXploration Germany applications in technologies ranging from Tel: +49 761 470940 32nm to 180nm. Contact: Adam Morawiec Fax: +49 761 4709429 ECSI, Electronic Chips & Systems design E-Mail: [email protected] PRODUCT FINDER Initiative Website: www.concept.de Services: Parc Equation Prototyping 2 avenue de Vignate Concept Engineering develops and markets Training 38610 Gières innovative visualization and debugging Embedded Software Development: France technology for commercial EDA vendors, Compilers OFFIS e.V. in-house CAD tool developers, FPGA and Debuggers Escherweg 2 IC designers. Software/Modelling Oldenburg Nlview WidgetsTM – a family of schematic Semiconductor IP: 26131 generation and visualization engines (Tcl/TK, Analogue & Mixed Signal IP Germany MFC, Qt, Java, Perl/Tk, wxWidgets) that can CPUs & Controllers Telephone:+49 441 97 22 0 be easily integrated into EDA tools. Encryption IP Tel: ECSI +33 476 63 4934 RTLVisionTM PRO – a graphical debugger for Physical Libraries Fax: ECSI +33 958 08 2413 SystemsVerilog, Verilog and VHDL based designs. Processor Platforms E-Mail: [email protected] GateVision® PRO – a customizable debugger Application-Specific IP: Website: http://complex.offis.de/ for Verilog, LEF/DEF and Analogue & Mixed Signal IP EDIF based designs. Digital Signal Processing The primary objective of the COMPLEX (COdesing SpiceVision® PRO – a customizable debugger Security and power Management in PLatform-based design for SPICE based designs. Wireless Communication space EXploration) European Integrated Project is SGvisionTM PRO – a customizable mixed-mode to develop an innovative, highly efficient and debugger (SPICE and Verilog). productive design methodology and a holistic PRODUCT FINDER stand 15 framework for iteratively exploring the design space of embedded HW/SW systems. COMPLEX will ASIC and SOC Design: focus on early, fast yet accurate platform-based Verification CréVinn Analogue and Mixed-Signal Design design space exploration at the system level. Contact: Tadhg Creedon The COMPLEX consortium develops a new design Test: Mixed-Signal Test CréVinn Teoranta environment for platform-based design-space Manor House exploration offering developers of next-generation Baile an tSagairt mobile embedded systems a highly efficient design An Spideal methodology and tool chain. The integrated stand 10 Ireland environment allows iterative exploration and Tel: +353 91-558090 refinement of advanced applications to meet Cortus S.A Fax: +353-91-558060 market requirements. The design technology in E-Mail: [email protected] particular enables fast simulation and assessment Contact: [email protected] Website: www.crevinn.com of the platform at Electronic System Level (ESL) Cortus S.A. with up to bus-cycle accuracy at the earliest Le Génésis CréVinn is a leading Silicon System Design instant in the design cycle. 97 rue de Freyr Consultancy company, with Design Centres in Partners: OFFIS (DE), STMicroelectronics (IT), 34000 Montpellier Galway and Dublin, Ireland. We work with key STMicroelectronics (CN), Thales France partners to develop innovative technology in Communications (FR), GMV (ES), Synopsys Tel: +44 1264 369483 the networking, computing, automotive and (BE), ChipVision (DE), EDALab (IT), Magillem Fax: +44 1264 369483 industrial markets. In addition, we are engaged Design Services (FR), Politecnico di Milano E-Mail: [email protected] in Silicon IP Core and Product Development in (IT), Universidad de Cantabria (ES), Politecnico Website: www.cortus.com the networking and storage fields. di Torino (IT), IMEC (BE), ECSI (FR) Cortus is the technology leader in ultra low PRODUCT FINDER power, compact 32-bit microcontroller IP ASIC and SOC Design: cores. The APS3 combines a power Design Entry consumption of 22 µW/DMIPS (TSMC 130 nm) Behavioural Modelling & Simulation with processing power similar to an ARM9. Power & Optimisation Yet the core itself is no larger than the 8051 System-Level Design: – making it a natural upgrade choice for 8- Behavioural Modelling & Analysis bit/16-bit core users – and is the smallest Hardware/Software Co-Design available core capable of running µCLinux. Embedded Software Development: Microprocessor Report crowned the APS3 the Compilers “King of Lilliput”. Real Time Operating Systems Software development with C/C++ is Software/Modelling supported by a complete toolchain and
DATE 11 EVENT GUIDE 23 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors give our customers a competitive edge in PRODUCT FINDER PRODUCT FINDER bringing products to market quickly and ASIC and SOC Design: ASIC and SOC Design: enabling a predictable path from IC Behavioural Modelling & Simulation Design Entry development via testing and mass production. Verification Behavioural Modelling & Simulation We offer supply chain management consisting of System-Level Design: Synthesis ASIC development, fabrication, packaging, Behavioural Modelling & Analysis Physical Analysis (Timing, Themal, Signal) testing, storage and shipping of ICs - to help Services: Verification address the key challenges fabless IC vendors’ Design Consultancy Analogue and Mixed-Signal Design face today, from prototypes to mass production. Prototyping MEMS Design Semiconductor vendors achieve faster time-to- Application-Specific IP: RF Design market of smaller, more robust, more profitable Data Communication System-Level Design: semiconductor products by utilising DELTA’s Digital Signal Processing Behavioural Modelling & Analysis turn-key solutions and professional services. Networking Physical Analysis DELTA’s experienced ASIC design team is Security Package Design specialised in payment systems, RFID, sensor Telecommunication PCB & MCM Design interfaces and opto chips. Wireless Communication Test: Flexibility, quality and competitiveness – Design for Test DELTA offers solutions at any part of the ASIC Embedded Software Development: development and production process to allow Software/Modelling the customer to get the most cost effective stand 56 combination of services. Get access to European and Far Eastern wafer CST Computer Simulation and packaging facilities via DELTA’s volume stand 25 purchasing power to obtain the best Technology AG possible prices. DELTA is established 70 years ago and is Contact: Jerome Mollet DEFACTO TECHNOLOGIES headquartered in Copenhagen, Denmark. Bad Nauheimer Str. 19 Contact: Chouki Aktouf 64289 Darmstadt 167 Rue De Mayoussard PRODUCT FINDER Germany 38430 Moirans Tel: +49 6151 7303 0 ASIC and SOC Design: France Fax: +49 6151 7303 100 Design Entry Tel: +33 476 668330 E-Mail: [email protected] Behavioural Modelling & Simulation Fax: +33 476 910067 Website: www.cst.com Synthesis E-Mail: [email protected] Power & Optimisation CST develops and markets high performance Website: www.defactotech.com Physical Analysis (Timing, Themal, Signal) software for the simulation of Verification electromagnetic fields in all frequency bands. DeFacTo enables designers to complete Analogue and Mixed-Signal Design Its products allow you to characterize, design planning, analysis and implementation of System-Level Design: and optimize electromagnetic devices all integrated circuit test logic before synthesis Behavioural Modelling & Analysis before going into the lab or measurement by delivering a high quality suite of DFT tools Package Design chamber. This can help save substantial costs working at the register transfer level (RTL). Test: especially for new or cutting edge products, PRODUCT FINDER Design for Test and also reduces design risk and improves Design for Manufacture and Yield overall performance and profitability. Test: Logic Analysis Its success is based on the implementation of Design for Test Test Automation (ATPG, BIST) leading edge technology in a user-friendly Test Automation (ATPG, BIST) Boundary Scan interface. Furthermore, CST’s “complete Services: Silicon Validation technology” complements its market and IP e-commerce & Exchange Mixed-Signal Test technology leading time domain solver (CST Semiconductor IP: System Test MICROWAVE STUDIO®), thus offering Test IP Services: unparalleled speed, accuracy and versatility Design Consultancy for all applications. Prototyping CST’s customers operate in industries as stand 47 Foundry & Manufacturing diverse as Telecommunications, Defense, Hardware: Automotive, Electronics, and Medical FPGA & Reconfigurable Platforms Equipment, and include market leaders such DELTA Application-Specific IP: Analogue & Mixed Signal IP as IBM, Intel, Mitsubishi, Samsung, and Contact: Mette Brunbjerg Olesen Data Communication Siemens. CST markets its products worldwide Venlighedsvej 4 Digital Signal Processing through a network of distribution and support 2970 Hoersholm Security centers which also provide comprehensive Denmark Telecommunication customer support and training. Tel: +45 721 94000 Wireless Communication More information at http://www.cst.com. Fax: +45 721 94001 E-Mail: [email protected] Website: www.asic.madebydelta.com
Are you looking for a complete ASIC supply chain solution? DELTA Microelectronics is the European leader in providing the semiconductor industry. We
DATE 11 EVENT GUIDE 24 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors DOCEA technology has been adopted by stand 16 world's largest semiconductor companies. PRODUCT FINDER ASIC and SOC Design: PRODUCT FINDER Design Entry Design Automation ASIC and SOC Design: Synthesis Power & Optimisation Verification Conference (DAC) System-Level Design: System-Level Design: Contact: Susie Horn Behavioural Modelling & Analysis Hardware/Software Co-Design MP Associates Test: Test: 1721 Boxelder Street, #107 System Test Design for Test Louisville, CO 80027 Services: Boundary Scan Tel: +1 303 530-4333 Training Services: Fax: +1 303 530-4334 Embedded Software Development: Design Consultancy E-Mail: [email protected] Software/Modelling Data Management and Collaboration Website: www.dac.com Semiconductor IP: Test IP The Design Automation Conference (DAC) is stand 15 Verification IO the world’s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and Duolog Technologies Ltd stand 29 EDA ecosystem learns, networks, and conducts business. DAC features hundreds Contact: Fearghal Hannaway technical sessions, panels, keynotes, Concourse Building (5th Floor) EASii-IC tutorials, workshops and events covering the Beacon Court latest in design methodologies, embedded Sandyford Contact: Francois CERISIER software and systems and EDA tool Dublin 18 90, avenue Léon Blum developments. The exhibition offers booths Ireland BP 2612 and suites from over 200 of the leading EDA, Tel: +353 1 2178425 38036 Grenoble Cedex 2 silicon, IP, embedded and design services E-Mail: [email protected] FRANCE providers. 48th Design Automation Website: www.duolog.com Tel: +33 4 56 580 580 Conference, June 5-10, 2011 in San Diego, CA Fax: +33 4 56 580 599 Duolog Technologies is a pioneering E-Mail: [email protected] developer of EDA tools that enable the rapid Website: www.easii-ic.com integration of today's increasingly complex stand 39 SoC, ASIC and FPGA designs. Duolog’s Strong of our experience in IC, electronics Socrates platform is a hub for chip and software services, we develop solutions DOCEA Power integration from IP register to Chip pin. It for radiation tests (ASER) and validation allows the capture of standardized views of (EASii-Board). Contact: Ridha HAMZA, IP-level and chip-level designs, validates the We also deliver EDA expert services and Marketing and Sales Director data to ensure correctness and generates EDA solutions. 166 B Rue du Rocher de Lorzier source views for different teams, including ASER: 38430 Moirans hardware and software views, design and Soft Error Test service is a complete solution FRANCE verification views, ESL and implementation to radiation effects characterization of space, Tel: +33 0 427 85 82 62 views. Socrates supports current and automotive or consumer products around Fax: +33 0 488 68 11 22 emerging standards such as IP-XACT, RAL, the world. E-Mail: [email protected] OVM and UVM. Socrates is delivering EASii-Board: Website: www.doceapower.com significant productivity improvements to A low cost logical pattern generator and Duolog’s customers including enhanced inter- analyzer bridging the gap between design and DOCEA Power develops and markets system- team communication, extensive bug validation, allowing you to build easy and level tools for modeling and optimizing elimination and major design cycle efficient validation platforms. power/thermal behavior of whole electronics reductions. Founded in 1999, Duolog EDA Solutions: systems. DOCEA's Aceplorer software Technologies is headquartered in Dublin, - Be-Spice: Your browser and visualizer for integrates a consistent power data Ireland with development centres in Galway, spice netlists and backannotated simulation management methodology for capturing and Ireland and Budapest, Hungary. Duolog also results. simulating power behavior. The "separation of has sales and support offices across Europe, - IDesignSpec (Agnisys): Register Automation concerns" approach makes power models US and Asia. and Management allowing easy design and usable across the teams and the design flow verification automation of register features. from system level to silicon measurements. - IVerifySpec (Agnisys): Presents a complete The Aceplorer innovative platform is the status of the verification project. It also solution for early power estimation, provides a collaborative tool for distributed architecture exploration, use case profiling, SPECIAL FOCUS verification teams that improves productivity package selection and other technology and quality. choices that impact specification. Dealing with EDA Services: power and/or thermal issues with Aceplorer at DAY State of the art methodology consulting, IP system level is fast, secure and efficient. and VIP development on partner tools: As a service, DOCEA Power generates SPICE- SMART ENERGY AT ST Agnisys, Breker, Jasper, Mentor. compliant compact thermal models of ICs, KEYNOTE – Thursday, March 17th, 13.30 On-Demand EDA support. SoCs, SiPs or on-board systems. Dynamic thermal simulations get ultra-fast, while Carmelo Papa, Executive VP Industrial and accuracy is kept under control. Multisegment, STMicroelectronics, IT
DATE 11 EVENT GUIDE 25 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors It has a workforce of about 15 people compare different extracted netlists. PRODUCT FINDER including partners, employees and external Several interfaces. ASIC and SOC Design: collaborators, united by a common passion Design Entry for IT and emerging technologies. PRODUCT FINDER Verification The young age and the personal motivation ASIC and SOC Design: Analogue and Mixed-Signal Design are at the base of the company's success in Physical Analysis (Timing, Themal, Signal) System-Level Design: being proactive and flexible. Verification Physical Analysis Our activity is focused on embedded system Analogue and Mixed-Signal Design Test: design both from the research point of RF Design Silicon Validation view and from a production standpoint. The System Test coexistence of these two souls is part of the Services: EDALab mission, which serves as innovation Design Consultancy driver for its customers. stand 26 Prototyping Related links: HIFSuite Tools -> Data Management and Collaboration http://hifsuite.edalab.it ElectroniqueS Training Hardware: PRODUCT FINDER Contact: Daniel Haussman FPGA & Reconfigurable Platforms ASIC and SOC Design: Tel: +33 01 71 18 54 40 Development Boards Behavioural Modelling & Simulation Fax: +33 01 71 18 53 01 Semiconductor IP: Verification E-Mail: [email protected] Analogue & Mixed Signal IP System-Level Design: Website: www.electroniques.biz Application-Specific IP: Behavioural Modelling & Analysis Analogue & Mixed Signal IP Hardware/Software Co-Design ElectroniqueS the reference monthly for Test: decision makers and engineers in the Logic Analysis electronics sector Test Automation (ATPG, BIST) Circulation of 10,000 copies stand 20 System Test www.electroniques.biz, the electronic Services: professional’s web site EDA Confidential Prototyping Daily Newsletter, the day’s essential news Embedded Software Development: about our industry’s major sectors Contact: Peggy Aycinena Compilers Sent to more than 26,000 free subscribers San Mateo, CA Real Time Operating Systems Weekly newsletter, the newsletter that 94402-2241 Software/Modelling summarizes the previous 5 daily newsletters U.S.A. Application-Specific IP: main topic Tel: +1 650 579 7952 Data Communication Sent to more than 23,000 free subscribers Fax: +1 650 579 7952 Networking Vertical newsletter, 3 subjects: Automotive / E-Mail: [email protected] Telecommunication Mil-Aero / Medical Website: www.aycinena.com Wireless Communication 5 mailings a year (each 2 in 3 months) EDA is a commercial-free publication providing a quiet place for conversation about the Electronic Design Automation stand 23 stand 15 industry and its companion technologies. The coverage does not intend to be Enterprise Ireland comprehensive, but does intend to provide edXact Contact: Paul McCloskey some food for thought. To that end, EDA Contact: Delphine Billon Enterprise Ireland, Industry House, Rossa Confidential includes "Recipes", Freddy Parc Work Center - Bât A Avenue, Bishopstown, Cork Santamaria's "Gourmet Corner", as well as Route des Bois Tel: +353 21 4800227 "Voices" of other contributing authors, "Off 38500 Voiron – France Fax: +353 21 4800271 the Record" op-ed pieces, and "Conference" Tel: +33 0 4 76 66 89 80 E-Mail: [email protected] coverage. Fax: +33 0 4 76 67 36 99 Website: www.enterprise-ireland.com E-Mail: [email protected] Website: www.edxact.com Chipright, Crevinn Teoranta, Duolog , Silansys stand 48 and Tyndall are all members MIDAS Ireland. EDXACT proposes software that helps to Enterprise Ireland is the government substantially raise the efficiency of postlayout organisation responsible for the development EDALab simulation and analysis flows. and growth of Irish enterprises in world Current offerings include: Contact: Walter Vendraminetto markets. It works in partnership with Irish JIVARO - netlist reduction platform, Strada Le Grazie, 15 enterprises to help them start, grow, innovate integrated into any design flow, several 37134 - Verona (VR) and win export sales on global markets. interfaces, many references. ITALY MIDAS Ireland (Microelectronic Industry Used in production for memory, mixed-signal, Tel: +39 045 8027062 Design Association) is a national cluster analog, RF flows. Timing. Speeding up Fax: +39 045 8027062 consisting of microelectronics design simulation time, increasing accuracy, reducing E-Mail: [email protected] companies and third level institutions in memory footprint. Industry-leading netlist Website: www.edalab.it Ireland. The membership currently consists of reduction. 7 multinational companies, 18 indigenous EDALab is a business reality located in COMANCHE - parasitics analysis platform. companies and 17 academic members Verona, in the north of Italy, which addresses Allows to quickly analyze interconnect representing all the courses in Ireland that issues of technological innovation in the parasitics in order to pinpoint problems. produce electronic engineering graduates. Its field of networked embedded systems. Allows to estimate timing, accurately aim is to promote the growth of
DATE 11 EVENT GUIDE 26 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors microelectronics in Ireland through collaboration in research, training and stand 11 education. Enterprise Ireland is an associate stand 30 member of MIDAS. Fractal Technologies Contact: Rene Donkers Gold Standard stand 14 US office, San Carlos, California, USA Simulations Ltd Europe Office, Eindhoven, the Netherlands Contact: Campbell Millar EUROPRACTICE Tel: +31 641539004 The Rankine Building, Fax: +31 847503816 Oakfield Avenue, Contact: Carl Das E-Mail: [email protected] Glasgow, Kapeldreef 75 Website: www.fract-tech.com G12 8LT B-3001 Heverlee The scope of Fractal Technologies is to check UK Belgium consistency and validate all different Tel: +44 141 330 4790 Tel: +32 16 281 248 dataformats used in your design and Fax: +44 141 330 4907 Fax: +32 16 281 584 subsequently improve the Quality of your E-Mail: [email protected] E-Mail: [email protected] Standard Cell Libraries, IO’s and IP’s Website: www.goldstandardsimulations.com Website: www.europractice-ic.com FRACTAL TECHNOLOGIES Gold Standard Simulations (GSS) is the world Your partner to: check consistency and The EUROPRACTICE IC service offers low cost leader in the simulation of statistical variability validate all different dataformats and and easy access to ASIC prototype and small in nano-CMOS devices. The services we offer subsequently improve the Quality of your volume fabrication. include the physical simulation of statistical Standard Cell Libraries, IO’s and IP’s The service is offered by IMEC (B) and variability, statistical compact model extraction FhG/IIS (D). and statistical circuit simulation using ‘push Low cost prototyping is achieved by offering button’ cluster-based technology. fabrication through regularly scheduled MPW PRODUCT FINDER (Multi Project Wafer) runs whereby many ASIC and SOC Design: PRODUCT FINDER Design Entry designs from different customers are merged ASIC and SOC Design: Verification onto the same fabrication run. These runs are Power & Optimisation Services: fabricated in industrial CMOS, BiCMOS and Physical Analysis (Timing, Themal, Signal) Design Consultancy SiGe processes from 0.7µ to 40nm at well- Services: known foundries (ONSemi, Training austriamicrosystems, IHP, LFoundry, TSMC, Embedded Software Development: UMC). A total integrated design and stands Software/Modelling manufacturing flow is offered including cell 1&2 library and design kit access and support, deep submicron netlist-to-layout, ASIC GLOBALFOUNDRIES prototyping on MPW or dedicated single stand EP11 Contact: Simone Wurm project prototype runs, volume fabrication, Dresden qualification, assembly and test. Volume Germany fabrication starts with wafer batches as low HiPEAC NoE Tel: +49 - 351 - 277 1018 as 12 wafers but can go up to more than Contact: Koen De Bosschere Fax: +49 - 351 - 277 91018 5000 wafers per year per ASIC. Universiteit GENT - ELIS, E-Mail: [email protected] 9000 GENT, BELGIUM Website: www.globalfoundries.com PRODUCT FINDER Tel: +32 9 264 42 58 ASIC and SOC Design: GLOBALFOUNDRIES is the world's first full- Fax: +32 9 264 35 94 Synthesis service semiconductor foundry with a truly E-Mail: [email protected] Power & Optimisation global manufacturing and technology Website: www.hipeac.net Physical Analysis (Timing, Themal, Signal) footprint. Launched in March 2009 through a Verification HiPEAC is a Network of Excellence on High partnership between AMD [NYSE: AMD] and Test: Performance and Embedded Architecture and the Advanced Technology Investment Design for Test Compilation. It gathers over 150 leading Company (ATIC), GLOBALFOUNDRIES provides Test Automation (ATPG, BIST) European academic and industrial computing- a unique combination of advanced Boundary Scan system researchers in one virtual center of technology, manufacturing excellence and Mixed-Signal Test excellence with the aim of coordinating their global operations. With the integration of System Test research, improving their mobility and Chartered in January 2010, GLOBALFOUNDRIES Services: collaborations, increasing their visibility. The significantly expanded its capacity and ability Prototyping network consists of nine research clusters to provide best-in-class foundry services from Foundry & Manufacturing that look into on-chip multi-cores technology mainstream to the leading edge. Semiconductor IP: and customisation, leading to heterogeneous GLOBALFOUNDRIES is headquartered in Silicon Physical Libraries multi-core systems. HiPEAC organizes several Valley with manufacturing operations in large networking events in Europe: the Singapore, Germany, and a new leading-edge ACACES Summer school, Computing Systems fab under construction in Saratoga County, Weeks (those are co-located with industrial New York. These sites are supported by a workshops), the HiPEAC conference. global network of R&D, design enablement, Additionally HiPEAC journals, newsletters and and customer support in Singapore, China, roadmaps are published on the regular basis. Taiwan, Japan, the United States, Germany, and the United Kingdom. For more information on GLOBALFOUNDRIES, visit http://www.globalfoundries.com. DATE 11 EVENT GUIDE 27 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors in the area of power management, memories PRODUCT FINDER and mixed-signal designs. PRODUCT FINDER ASIC and SOC Design: Infiniscale’s solutions enable designers ASIC and SOC Design: Behavioural Modelling & Simulation delivering products on time, while maximizing Design Entry Power & Optimisation robustness and yield. Behavioural Modelling & Simulation Physical Analysis (Timing, Themal, Signal) Synthesis Verification PRODUCT FINDER Power & Optimisation System-Level Design: ASIC and SOC Design: Physical Analysis (Timing, Themal, Signal) Behavioural Modelling & Analysis Behavioural Modelling & Simulation Verification Physical Analysis Analogue and Mixed-Signal Design Acceleration & Emulation Services: Hardware/Software Co-Design Design Consultancy Test: stand 57 Embedded Software Development: Test Automation (ATPG, BIST) Real Time Operating Systems Services: Infotech Hardware: Data Management and Collaboration FPGA & Reconfigurable Platforms Embedded Software Development: Contact: Abilash Reddy Gaddam Development Boards Compilers Infotech Enterprises GmbH Real Time Operating Systems Mollenbachstraße 37 Debuggers 71229 Leonberg Software/Modelling Germany stand 21 Hardware: Tel: +49 (0) 7152 9452-0 FPGA & Reconfigurable Platforms Fax: +49 (0) 7152 9452-90 IP SOC 11 Semiconductor IP: E-Mail: [email protected] Embedded FPGA Website: www.infotech-enterprises.com Contact: Gabriele Saucier Embedded Software IP IP SOC 11 On-Chip Bus Interconnect Infotech Enterprises provides leading-edge Design And Reuse SA Application-Specific IP: engineering solutions to major organizations 12 rue Ampere Digital Signal Processing worldwide. With Global Headquarters in 38016 Grenoble Multimedia Graphics Hyderabad, India, Infotech has 8,000+ FRANCE Networking engineers across 30 global locations and has Tel: +33 476 21 31 02 Telecommunication generated consolidated revenues of US $201 Fax: +33 476 49 00 52 Wireless Communication Million for the fiscal year ending March 2010. E-Mail: [email protected] Infotech provides concept to silicon and Website: www.design-reuse.com system prototype solutions for ASIC/FPGA Engineering and Embedded IP - SoC 2011 will be the 20th edition of the stand 40 Software Development. With over 12 years working conference on hot topics in the impeccable track record of "first-pass silicon design world, focusing for the past 9 years on INFINISCALE success" and "on-time IP-based SoC design and held in delivery" across 200+ ASIC tapeouts, we not Grenoble,organized by Design And Reuse . Contact: Stephane FIORILLO only help our customers meet Over the years, IPs have become Subsystems 186 chemin de l'étoile their current design requirements, but also or Platforms and thus as a natural applicative 38330 Montbonnot provide technology road maps and extension.IP-SoC will definitively include a France innovative solutions for future design trends. strong Embedded Systems track addressing a Tel: +33 04 76 51 25 27 Primary Service Offerings: continuous technical spectrum from IP to SoC Fax: +33 04 76 51 20 46 •ASIC and SOC Design to Embedded System. E-Mail: [email protected] •Embedded Software Design Website: www.infiniscale.com •FPGA & Board Design Key Highlights: stand EP12 About Infiniscale •12 years track record of “first pass silicon Variation-aware risk management solutions success” across 200+ ASIC Infiniscale provides a unique variation-aware tapeouts MADNESS custom IC design solutions dedicated to •Delivery center based out of San Jose, U.S. : Contact: Prof. Luigi Raffo analysis and optimization of performances Access to high-end DIEE - Department of Electric and Electronic and parametric yield for analog and mixed- electronics talent from the Silicon Valley Engineering signal designs. Infiniscale Lysis flow enables •Expertise in technology nodes down to University of Cagliari variation-aware design methods that can 28nm and as many as 100 million gates Piazza d'Armi - 09123 CAGLIARI (Italy) accurately and promptly estimate the risks •Deep understanding of ARM/MIPS/PowerPC- Tel: +390706755765 into variation sensitive devices. Then Lysis based SOCs with a strong grasp of Fax: +390706755782 can help the designer reducing or possibly memory and connectivity technologies E-Mail: [email protected] removing these risks. •Extensive background in multimedia (audio, Website: www.madnessproject.org With Lysis, the designer is able to run a video, speech and image) codecs million MC in seconds, to visualize PVT standards and frameworks The main goal of the project is to define influence on performances in real-time, and innovative methodologies for system-level to optimize parametric yield in an hour. design, able to guide designers and Lysis innovative approach to variation-aware researchers to the optimal composition of design is compatible with all the existing embedded MPSoC architecture, according to design flows, and fully integrated with the the requirements and the features of a given industry-leading EDA tools. Infiniscale works target application field. The proposed with several major semiconductor companies approach will tackle the new challenges,
DATE 11 EVENT GUIDE 28 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors related to both architecture and design methodologies, arising with the technology PRODUCT FINDER stand 15 scaling, the system reliability and the ever- ASIC and SOC Design: growing computational needs of modern Design Entry applications. Power & Optimisation MIDAS The proposed methodologies will extend the Physical Analysis (Timing, Themal, Signal) Contact: Paul McCloskey classic concept of design space exploration Verification Enterprise Ireland, Industry House, Rossa to: Analogue and Mixed-Signal Design Avenue, Bishopstown, Cork * Improve design predictability, bridging the System-Level Design: Tel: +353 21 4800227 so called "implementation gap", i.e. the gap Hardware/Software Co-Design Fax: +353 21 4800271 between the results that can be predicted Package Design E-Mail: [email protected] during the system-level design phase and Services: Website: www.enterprise-ireland.com those eventually obtained after the on-silicon Design Consultancy implementation. Data Management and Collaboration MIDAS Ireland (Microelectronic Industry * Consider, in addition to traditional metrics Training Design Association) is a national cluster (such as cost, performance and power Semiconductor IP: consisting of microelectronics design consumption), continued availability of Memory IP companies and third level institutions in service, taking into account fault resilience as Ireland. The membership currently consists of one of the optimization factors to be satisfied. 7 multinational companies, 18 indigenous * Support adaptive runtime management of stand 51 companies and 17 academic members the architecture, considering, while tailoring representing all the courses in Ireland that the architecture, new metrics posed by novel produce electronic engineering graduates. Its dynamic strategies and advanced support for MICROLOGIC Design aim is to promote the growth of communication issues that will be defined. Automation microelectronics in Ireland through collaboration in research, training and Contact: Christophe Bianchi education. Enterprise Ireland is an associate stand 33 157 Yaffo Street member of MIDAS. AMOT Building Magillem Design Services Haifa 35251 Israel stand 9 Contact: Lamia Lakehal Tel: +972-4-8538835 4, rue de la Pierre Levée Fax: +972-4-8527785 75011 E-Mail: [email protected] MINALOGIC GRENOBLE Paris France Website: www.micrologic-da.com ISERE Tel: +33 0 1 40 21 35 50 Fax: +33 0 1 53 36 75 08 Micrologic interactive nanoToolBox solutions Contact: Véronique Pequignat E-Mail: [email protected] accelerate the signoff of complex deep Grenoble Isere - AEPI, 1 Place Firmin Website: www.magillem.com nanometer designs with: Gautier 38027 Grenoble · Faster time to market Minalogic: Maison des Micro et Magillem provides to customers in the · Improved performance Nanotechnologies,3 Parvis Louis Néel 38054 electronic industry tools and services that · Enhanced reliability Grenoble drastically reduce the global cost of complex · Lower costs France design. Micrologic's nanoToolBox is a plugin suite of Tel: +33 04 76 70 97 04 Magillem has developed an easy to use, state tools for Virtuoso™, consisting of Fax: +33 04 76 70 97 19 of the art platform solution to cover complementary Design Rule Verification E-Mail: [email protected] electronic systems design flow challenges in a (DRC), Reliability Verification (RV) and Layout Website: www.grenoble-isere.com/ context where complexity, interoperability Versus Schematic (LVS) checkers. Permanently www.minalogic.com and design re-use are becoming critical issues on watch, these programs check, inform and to manage design cycle time of SOC. Main guide the layout process, allowing you to AEPI is the economic development agency for benefits include: converge to a signoff-ready layout in the Grenoble-Isere/France, and provides * Maximizing Design and IP Re-use minimum possible time. complimentary information and services to * Using a virtual platform to configure their companies exploring business opportunities. system and IPs PRODUCT FINDER The Grenoble area, smart valley in * Controlling the Design Flow ASIC and SOC Design: southeastern France, is Europe’s top center in * Exploring their Design Flow architecture Physical Analysis (Timing, Themal, Signal) micro-nanotechnologies and derived and optimizing it Verification applications, with the whole food chain of * Improving their independence from CAD the Industry being represented in the area, tools vendors from EDA to design, component makers, * Improving interoperability, communication equipment suppliers and end users. AEPI is * Benefiting from better user interfaces to also a member of the local board of the new raise productivity Semi Europe Grenoble office, located on the * Relying on worldwide adopted standards Minatec Campus. Our Motto: Global competitive cluster Minalogic fosters Methodology tools should adapt to the trends research-led innovation in intelligent in SoC design and help streamline the design miniaturized products and solutions for flows without disrupting existing processes industry. Located in Grenoble, France, the cluster channels in a single physical location a range of highly-specialized skills and resources from knowledge creation to the development and production of intelligent
DATE 11 EVENT GUIDE 29 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors miniaturized services for industry. The technology for analysis, modelling and converter IP cores with resolutions of up to technologies developed at the cluster are optimization of yield and performance of 16 bits. These converters are available as applicable to all business sectors : analog, mixed-signal and digital designs. ready-to-use semiconductor hard macros for healthcare, energy efficiency, mobility, MunEDA´s products and solutions enable most popular silicon processes. imagery, including more traditional industries. customers to reduce the design times of their Our design team has many years of hands-on Minalogic brings together major corporations, circuits and to maximize robustness, industrial Analog and Mixed-Signal IC design small and mid-sized businesses, government reliability and yield. MunEDA´s solutions are experience. We will support you through the agencies, and organizations from the public in industrial use by leading semiconductor whole integration and product validation phase. and private sectors. companies in the areas of communication, nSilition also provides all other required computer, memories, automotive, and Analog and Mixed-Signal IP and IC design consumer electronics. services: from financial and technical stand 35 feasibility studies up to characterization tests, production validation and yield stand 45 improvement. MOSIS nSilition services several main customers Contact: Lynne Wright active in applications area like wireline EDA Solutions Limited Nano-Tera.ch communication, industrial, medical and Unit A5, Segengworth Business Centre Contact: Patrick Mayor aerospace. Segensworth Road Nano-Tera.ch We invite you to visit our booth for more Fareham EPFL / AA details. Hants PO15 5RQ INF 332 Station 14 United Kingdom CH-1015 Lausanne PRODUCT FINDER Tel: +44 1489 564 253 Tel: +41 21 693 81 66 ASIC and SOC Design: Fax: +44 01489 557 367 Fax: +41 21 693 81 60 Design Entry E-Mail: [email protected] E-Mail: [email protected] Behavioural Modelling & Simulation Website: www.eda-solutions.com Website: www.nano-tera.ch Verification Analogue and Mixed-Signal Design MOSIS offer low cost and low volume access The Nano-Tera.ch program is a broad System-Level Design: to a wide range of IC technologies from engineering program in Switzerland for health Behavioural Modelling & Analysis 1.5um down to the latest 65nm processes. and security of humans and the environment, PCB & MCM Design Our services include wafer fabrication and currently funded by the Swiss government. Test: plastic assembly services, via the foundires The program rationale is rooted in advances Design for Test AMIS, austriamicrosystems, IBM and TSMC, in engineering nano-scale materials and their Design for Manufacture and Yield and assembly house I2A. exploitation in a variety of systems, requiring Silicon Validation You can chose between low cost shared extreme integration and coordinated control Mixed-Signal Test access multi project wafer (MPW) runs, of diverse micro/nano-scale components. Services: yielding up to hundreds of samples, or Embodiments of such systems can be found in Design Consultancy dedicated mask and wafer runs where higher lightweight, mobile and personalized products Prototyping volumes are required. embedded in the environment and on/in the Hardware: With MOSIS there are no die size constraints, body. These products will enable us, for Development Boards so you receive exactly what you need. example, to detect in real time different Semiconductor IP: MOSIS are represented in Europe by EDA health risks and conditions through Analogue & Mixed Signal IP Solutions, who will be happy to explain more integrated bio probing, to reveal security Application-Specific IP: to you about our services, and answer any risks through smart buildings and Analogue & Mixed Signal IP questions you may have. Why not come to environments, to save energy through Telecommunication Stand 35 or visit the EDA Solutions website ambient sensing, and to detect and monitor www.eda-solutions.com for more details. environmental hazards such as floods and avalanches from space and/or inaccessible PRODUCT FINDER positions on earth. The outstanding novelty stand 55 Services: and power of these systems stem from their Prototyping connectedness and the integration of Foundry & Manufacturing heterogeneous components. N S Mangat & Co Semiconductor IP: Contact: Mr. Ajit Singh Physical Libraries N.S. Mangat & Company stand 36 C 86 Hari Nagar Clock Tower nSilition New Delhi 110064 stand 31 India Contact: Thierry Delmot Tel: +91 11 65175357 MunEDA Boulevard Dolez, 31 Fax: +91 11 41694370 7000 Mons E-Mail: [email protected] Contact: Jin Qiu Belgium Website: www.nsmangat.com Stefan-George-Ring 29 Tel: +32-65-37.42.40 81929 Munich Fax: +32-65-37.42.41 N.S. Mangat & Company, is the leading Tel: +49 89 930 86 330 E-Mail: [email protected] technical conference and Exhibition of Fax: +49 89 930 86 407 Website: www.nsilition.com System design, modeling and design E-Mail: [email protected] automation in worldwide. And N.S.M is Website: www.muneda.com nSilition is a leader in the development and institute of Tasting Quality & Maintenanace the qualification of industrial quality, very MunEDA provides leading EDA software was founded in 1993 and is 100% privately high performance, low power A/D and D/A owned. The company is managed by an DATE 11 EVENT GUIDE 30 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors international team of highest skilled experts and is promoted by a group of qualified and PRODUCT FINDER stand 52 experienced professional that has wide ASIC and SOC Design: exposure to various traits. RF Design System-Level Design: R3LOGIC The NSM company has built up a reputation Package Design Contact: Patrick BOTTI providing prompt services and quality PCB & MCM Design R3Logic France assurance and in the same connection the Test: BHT-Minatec company is always on a look out for Design for Test 7 Parvis Louis Néel innovations in the domestic as well as Design for Manufacture and Yield 38000 Grenoble international market. Boundary Scan France PRODUCT FINDER Silicon Validation R3Logic, Inc. Mixed-Signal Test 19A Crosby Drive ASIC and SOC Design: System Test Suite 150 Design Entry Services: Bedford, MA 01730 System-Level Design: Design Consultancy USA Package Design Prototyping Tel: +33 (0)9 77 72 10 22 Test: Foundry & Manufacturing Fax: +1 781 276 7818 Design for Manufacture and Yield E-Mail: [email protected] Website: www.r3logic.com stand 49 stand 5 R3Logic, Inc. is a privately-held company, founded in 2000, specializing in the design of ProximusDA 3D integrated circuits. Since 2001, working Presto Engineering, Inc. with DARPA-sponsored research programs, we Contact: Philippe Metsu Contact: Richard Curtin have developed a unique set of EDA tools for ProximusDA GmbH Tuerkenstr. 71, Munich, 3D integrated circuit design and analysis, 3907 North First Street 80799, Germany San Jose, CA 95134 especially tools for true 3D integration and Tel: +49 89 38157177-0 custom design. Tel: - +1 408 434 1808 Fax: +49 89 38157177-3 Fax: - +1 408 434 6842 R3Logic-France, sister-company to R3Logic E-Mail: [email protected] Inc. and located in Grenoble, France, was E-Mail: [email protected] Website: www.proximusda.com Website: www.presto-eng.com established in 2008 following an invitation to ProximusDA provides solutions for System Level join a European Consortium with STM and Presto Engineering, an ISO 9001 company, Design using a new computing paradigm to CEA-LETI. In the following year, R3Logic delivers Design Success Analysis, integrated enable efficient development and use of today's France created a common lab with CEA-LETI test and product engineering solutions to IDM multi-processing compute capabilities. The to research and develop new solutions for 3D and fabless companies, helping to improve company’s "Proximus" development framework Integration and participate as one of the the speed and predictability of new product implements transaction level based methodology main players in the Grenoble 3D EDA releases. Presto combines unique technical to specify, design, simulate and execute targeted ecosystem. expertise, extensive industry experience and parallel systems consisting of hardware and state-of-the-art ATE for SoC and RF, software. ProximusDA delivers products for PRODUCT FINDER reliability, failure analysis and fault isolation system architects, system validation engineers ASIC and SOC Design: capabilities to offer a complete product and embedded software developers. By providing Design Entry engineering solution designed to complement an alternative to traditional serial hardware and MEMS Design the internal resources of its customers. software design flows, Proximus shortens the RF Design Presto now offers it's product engineering embedded system development cycle and services from two sites -- the Silicon Valley enables true system level optimization. hub in San Jose and the newly established lab in Normandy, France, after transfer from PRODUCT FINDER stand 18 NXP to Presto in 2010. ASIC and SOC Design: Presto’s product-engineering services from Design Entry SAME first silicon characterization to production Behavioural Modelling & Simulation release include: Verification Contact: Anne Claire DESNEULIN • New product debug and failure analysis System-Level Design: C/o SKEMA • ATE for digital and RF designs Behavioural Modelling & Analysis 60 Rue Dostoïevski -BP 085 • e-Testing and characterization Acceleration & Emulation 06902 Sophia Antipolis - France • Sample preparation Hardware/Software Co-Design Tel: +33 492 294 825 • Reliability testing Test: Fax: +33 492 294 321 Engineering staff at Presto have extensive System Test E-Mail: anne-claire.desneulin industry experience with: Services: @same-association.org • In-silicon analysis docked with ATE Design Consultancy Website: www.same-conference.org • Backside silicon FIB and electrical failure Embedded Software Development: • SAME’s Mission: analysis for CSP and flip-chip packages Real Time Operating Systems Valorize, promote and develop excellence in • Dynamic analysis of leakage. interconnect, Debuggers the microelectronics sector covering the and timing Software/Modelling design technology for advanced electronic • Scan-chain analysis and debug Semiconductor IP: circuits in the South of France. Embedded Software IP • SAME Objective: - To organize the SAME Forum to promote the microelectronic industry within the region.
DATE 11 EVENT GUIDE 31 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors • SAME in Action: - SAME 2011 Forum: October 12 & 13, 2011 stand 58 PRODUCT FINDER and SAFA Workshops - Sophia Antipolis, ASIC and SOC Design: France. Design Entry Main Topic: Digital Mobility SELEX Galileo Behavioural Modelling & Simulation More information on Contact: Sergio Pellegrini Synthesis www.same-conference.org Via A. Einstein 35, Power & Optimisation - "SAME goes back to School": Presents 50013 Campi Bisenzio (FI) Physical Analysis (Timing, Themal, Signal) information on careers in microelectronics ITALY Verification engineering to regional high school students Tel: +39 055 89501 Analogue and Mixed-Signal Design with the aim of encouraging them to take Fax: +39 055 8950600 RF Design engineering degrees. E-Mail: [email protected] System-Level Design: - Promoting microelectronic start-ups: Website: www.selexgalileo.com Behavioural Modelling & Analysis individualised analysis and assistance on Physical Analysis everything from defining market strategy to SELEX Galileo, a Finmeccanica Company, Hardware/Software Co-Design client/partner prospecting. develops integrated capability solutions Package Design - CIM PACA provides academic and industrial which deliver enhanced situation awareness, PCB & MCM Design entities with leading-edge tools to design ICs security, and safety across land, sea and air. Test: for the next generation of secure mobile Solutions from surveillance, imaging, Design for Test communication devices. tracking, targeting to protection and Design for Manufacture and Yield - Sophia Academy: is an initiative of leaders’ navigation control systems for military and Logic Analysis company. They want to propose to their government missions. Customers across 5 Test Automation (ATPG, BIST) employees a local access to high level continents have already selected SELEX Boundary Scan trainings. They want to share their Galileo as their partner of choice to provide Silicon Validation experiences and mutualize their needs. total awareness, total protection solutions for Mixed-Signal Test their present and future needs. System Test Services: stand 41 Design Consultancy Prototyping Data Management and Collaboration Satin Technologies stand 15 IP e-commerce & Exchange Contact: Michel Tabusse Foundry & Manufacturing Cap Omega, Rond-Point Benjamin Franklin Silansys Semi Hardware: CS 39521 FPGA & Reconfigurable Platforms 34960 Montpellier Cedex 2, France Contact: Niall O’Hearcain Development Boards Tel: +33 467 13 00 86 Adelaide Chambers Workstations & IT Infrastructure Fax: +33 467 13 00 10 Peter Street Semiconductor IP: E-Mail: [email protected] Dublin 8 Analogue & Mixed Signal IP Website: www.satin-tech.com Ireland Application-Specific IP: Tel: +353 1 4830840 Analogue & Mixed Signal IP Satin Technologies delivers software solutions E-Mail: [email protected] Data Communication for fact-based design quality monitoring and Website: www.silansys.com Digital Signal Processing closure. Networking Silansys develops and supplies innovative Working within customers' design flows, the Wireless Communication company’s VIP Lane® turns customers' design turnkey ASIC products and provides a full practices (for IP blocks, SoCs, embedded range of Design Services to industry-leading systems) into a robust and reliable set of companies worldwide. Silansys is a qualified quality criteria and metrics. These customer- product and services supplier to a wide range stand 3 based parameters are used to create of blue-chip OEM and top-5 semiconductor automated, sharable dashboards and quality companies worldwide in markets ranging from compliance reports. consumer communications to hi-rel industrial SPRINGER sensors. Silansys has a world-class track- By providing an alternative to manually filled, Contact: Lothar Minicka record in architecting and delivering time-consuming checklists and documents, Tiergartenstr. 17 successful commercial products that integrate VIP Lane® delivers effective flow integration 69121 Heidelberg innovative RF, Mixed-Signal and Digital and on-the-fly quality monitoring at zero Germany technology into single-chip SoC products. overhead to design teams. Tel: +49 6221 4870 PRODUCT FINDER Fax: +49 6221 4878366 E-Mail: [email protected] Services: Website: www.springer.com Data Management and Collaboration Springer is one of the world-leaders in book publishing, boasting a broad range of subject KEYNOTE – matter, and a history of working with the SPECIAL FOCUS Wednesday, March 16th, 1400 most prestigious scholars in the field. Hannu Kauppinen, Additionally, Springer publishes an astute collection of Journals, with a track record of DAY Director, Head of Radio generating the latest sought after content. WIRELESS INNOVATIONS FOR Systems Laboratory, For additional information about all our engineering publications, please stop by our SMARTPHONES Nokia Research Center, Finland booth, or visit us at springer.com
DATE 11 EVENT GUIDE 32 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors The "IP Designer" tool suite has been applied stand 35 by customers worldwide for diverse stand 50 application domains, including GSM/WCDMA/HSDPA handsets, VoIP, Tanner EDA audio/video/image codec/processing, TinnoTek Inc. Contact: Lynne Wright automotive, ADSL/VDSL modems, wireless Contact: Shan-Chien Fang EDA Solutions Liimited LAN, hearing instruments, and mobile/low- 121R, Innovation Incubator, National Tsing Unit A5, Segensworth Business Centre, power applications. Hua University, 101, Sec. 2, Kuang-Fu Segenswoth Road, URL: www.retarget.com Rd.,Hsinchu 300, Taiwan, R.O.C. Fareham Tel: +886 3 5741082 Hants PO15 5RQ PRODUCT FINDER Fax: +886 3 5741084 United Kingdom ASIC and SOC Design: E-Mail: [email protected] Tel: +44 1489 564 253 Design Entry Website: www.tinnotek.com.tw Fax: +44 1489 557 367 System-Level Design: E-Mail: [email protected] Acceleration & Emulation Website: www.eda-solutions.com Hardware/Software Co-Design PRODUCT FINDER Services: ASIC and SOC Design: Tanner EDA develops and markets electronic Design Consultancy Power & Optimisation design automation software for designers of Embedded Software Development: Physical Analysis (Timing, Themal, Signal) mixed-signal and analog ICs, and MEMS Compilers Services: circuits. Our L-Edit Pro layout and verification Debuggers IP e-commerce & Exchange software and T-Spice Pro design entry and Software/Modelling Semiconductor IP: simulation software provide a complete, Configurable Logic IP productive and cost-effective design solution. Tanner Tools are easy-to-use and truly affordable, with a powerful range of features and industry-standard file formats. With over stand 19 25,000 licenses sold worldwide these are the stand 13 best and most reliable products for IC Design Tech Design Forum for Windows PC. We are represented in Europe by EDA Contact: Sandra Sillion TowerJazz Solutions (www.eda-solutions.com). Come and Tel: +1 949 226 2011 Contact: Melinda Jarrell meet us and see for yourself the Power E-Mail: [email protected] 4321 Jamboree Road Behind the Tool! Website: www.edatechforum.com Newport Beach, CA 92660 USA PRODUCT FINDER Today’s electronic design engineers face Tel: 001 9494358181 ASIC and SOC Design: broader challenges than ever before. Software Fax: 001 949-435-8757 Design Entry is becoming as important as hardware. And in E-Mail: [email protected] Behavioural Modelling & Simulation the IC supply chain, former competitors are Website: www.towerjazz.com Verification now collaborating to achieve success. Analogue and Mixed-Signal Design Tech Design Forum publication (formerly TowerJazz is recognized for our industry MEMS Design called the EDA Tech Forum) is the premier leading models and tools which give our RF Design guide for success in this complex customers a significant competitive market Services: environment. Focused on the design advantage with first time design success, Design Consultancy automation market, this publication and its optimal performance, and the shortest time- Semiconductor IP: rich website offer a wealth of practical advice to-market at reduced cost. Our extensive Analogue & Mixed Signal IP on how to successfully negotiate the day-to- design enablement infrastructure provides an Physical Libraries day problems designers face. environment optimized for analog and RF Application-Specific IP: designs. This includes silicon verified and Analogue & Mixed Signal IP highly scalable device models and robust physical design tools for up front design stand 17 optimization. Unique tools such as Monte stand 4 Carlo statistical and PCM based models allow the user to maximize the performance-yield The Next Silicon Valley tradeoff. In addition, MOSVAR model libraries Target Compiler Contact: Richard Wallace improve simulation accuracy reducing product Tel: +1 631 907-2559 development time. The Jazz Inductor Toolbox Technologies (JIT) provides advanced modeling capability Contact: Jeroen De Lille E-Mail: [email protected] Website: www.thenextsiliconvalley.com for octagonal and square inductors to provide Technologielaan 11-0002, designers flexibility in choosing the right 3001 Leuven, The Next Silicon Valley is an independent inductors when designing their products. Our Belgium media website that publishes global news and powerful and efficient tools enable Tel: +32 16 38 1030 information about the world of innovation, unprecedented accuracy in device models and Fax: +32 16 38 1049 entrepreneurship, technology development, our unparalleled customer support at every E-Mail: [email protected] regional economic development, venture stage of the design flow ensures confidence Website: www.retarget.com capital, and investment promotion across in designs at near zero risk. Target Compiler Technologies is the leading global markets. The Next Silicon Valley provider of software tools to automate and reaches readers in more than 90 countries optimize the design and programming of and 400 cities worldwide. application-specific processor cores (ASIPs). DATE 11 EVENT GUIDE 33 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors
PRODUCT FINDER stand 15 stand 46 ASIC and SOC Design: Verification MEMS Design Tyndall’s Design Technology University Booth RF Design Evaluation Group Contacts: Volker Schöber (Germany), Services: Contact: Ted O’Shea Lorena Anghel (France) Foundry & Manufacturing University College Cork edacentrum GmbH, Schneiderberg 32, 30167 Semiconductor IP: Dyke Parade Hannover, Germany Analogue & Mixed Signal IP Cork TIMA Laboratory, 46 avenue Felix Viallet, Application-Specific IP: Ireland 38031 Grenoble, France Analogue & Mixed Signal IP Tel: +353 21 4904159 Tel: +49 (511) 762 19688 (Germany), Wireless Communication E-Mail: [email protected] +33 (4) 7657 4696 (France) Website: www.tyndall.ie/DTE Fax: +49 (511) 762 19695 (Germany), +33 (4) 7657 4981 (France) stand EP9 Tyndall's Design Technology Evaluation (DTE) E-Mail: university-booth@date- group performs Intellectual Property patent conference.com infringement investigation for key European Website: date-conference.com/ TRAMS and US companies. This group implements a group/exhibition/u-booth Contact: Antonio Rubio complete 'tear down' of an IC's design, its The University Booth is part of the DATE c/ Jordi Girona 31, 08034 Barcelona, Spain technology, its assembly and system; then program and is sponsored by the DATE Sponsor Tel: +34934017485 compare with a portfolio of patents in order Society. The University Booth will be organized Fax: +34934016756 to ascertain if infringement has occurred. A for EDA software and hardware demonstrations. E-Mail: [email protected] report is then generated providing clear Universities and public research institutes are Website: www.trams-project.eu evidence in relation to specific patents. Where necessary, staff will also support its presenting innovative hardware and software Technology projections indicate that future findings as a 'facts expert witness' in a court demonstrations. All demonstrations will take electronic devices will keep shrinking, being of law. In support of our IP investigation place during the exhibition within a dedicated faster and consuming less energy per work is an extensive infrastructure of analysis time slot. The University Booth is organized by operation. In the next decade, a single chip equipment in excess of €35 Million. This Lorena Anghel (TIMA Laboratory) and Volker will be able to perform trillions of operations group also performs extensive electrical Schöber (edacentrum). per second and provide trillions of bytes per characterisation of 'mixed signal' designs. PRODUCT FINDER second in off-chip bandwidth. This is the so ASIC and SOC Design: called Terascale Computing era, where PRODUCT FINDER Design Entry terascale performance will be mainstream, ASIC and SOC Design: Behavioural Modelling & Simulation available in personal computer, and being the Physical Analysis (Timing, Themal, Signal) Synthesis building block of large data centers with System-Level Design: Power & Optimisation petascale computing capabilities. However, Acceleration & Emulation Physical Analysis (Timing, Themal, Signal) these smaller devices will be much more Hardware/Software Co-Design Verification susceptible to faults and its performance will Test: Analogue and Mixed-Signal Design exhibit a significant degree of variability. As Design for Test MEMS Design a consequence, to unleash these impressive Design for Manufacture and Yield RF Design computing capabilities, a major hurdle in Logic Analysis System-Level Design: terms of reliability has to be overcome. The Test Automation (ATPG, BIST) Behavioural Modelling & Analysis TRAMS project is the bridge for reliable, Boundary Scan Physical Analysis energy efficient and cost effective computing Silicon Validation Acceleration & Emulation in the era of nanoscale challenges and System Test Hardware/Software Co-Design teraflop opportunities. Services: Design Consultancy Package Design PRODUCT FINDER IP e-commerce & Exchange Test: ASIC and SOC Design: Foundry & Manufacturing Design for Manufacture and Yield Design Entry Training Logic Analysis Behavioural Modelling & Simulation Hardware: Test Automation (ATPG, BIST) Synthesis FPGA & Reconfigurable Platforms Boundary Scan Physical Analysis (Timing, Themal, Signal) Development Boards Silicon Validation Verification Semiconductor IP: Mixed-Signal Test System-Level Design: Analogue & Mixed Signal IP System Test Behavioural Modelling & Analysis Memory IP Services: Physical Analysis On-Chip Debug Design Consultancy Semiconductor IP: Test IP Prototyping CPUs & Controllers Verification IO Data Management and Collaboration Memory IP Application-Specific IP: IP e-commerce & Exchange On-Chip Bus Interconnect Analogue & Mixed Signal IP Training Physical Libraries Security Embedded Software Development: Compilers Software/Modelling Hardware: FPGA & Reconfigurable Platforms Development Boards
DATE 11 EVENT GUIDE 34 • EXHIBITORS • EXHIBITORS • EXHIBITORSex h• ibitors PRODUCT FINDER stand 22 stand 24 ASIC and SOC Design: Design Entry University of Southampton Veriest Venture Behavioural Modelling & Simulation Synthesis Contact: Dr Steve Beey Contact: Berg Tara Power & Optimisation University of Southampton 22A Raul Walenberg St. Beit Zamir, Ramat Verification School of Electronics and Computer Science Hachayal, Tel Aviv, Israel System-Level Design: Highfield, Southampton, SO17 1BJ Tel: +972.73.705.2530 Behavioural Modelling & Analysis UK Fax: +972.3.644.0737 Acceleration & Emulation Tel: +44 2380 596663 E-Mail: [email protected] Hardware/Software Co-Design Fax: +44 2380 592901 Website: www.veriest-v.com PCB & MCM Design E-Mail: [email protected] Veriest Venture is a novel IC and EDS design Services: Website: www.ecs.soton.ac.uk house providing forefront ASIC and FPGA Design Consultancy The School of Electronics and Computer Science design services and Electronic Design complex Prototyping (ECS) is at the forefront of electronics systems System engineering services. Our family of Data Management and Collaboration design for energy harvesting applications. ECS customers includes leading companies across IP e-commerce & Exchange has a strong international reputation in the field the networking, data, communication, Training of energy harvesting and is at the forefront of consumer electronics and wireless industries. Embedded Software Development: research activities in this area. ECS is leading the Our skilled and creative team can effectively Software/Modelling EPSRC funded project 'Next Generation Energy promote architecture design, implementation, Hardware: Harvesting Electronics: Holistic Approach' and is system integration and advanced verification. FPGA & Reconfigurable Platforms also managing on behalf of the community the Veriest's scope of expertise extends form Development Boards EPSRC funded Network on Energy Harvesting. ECS silicon to system specification, and is a Semiconductor IP: also a partner on two ongoing EU Framework 7 design leader in system and micro Configurable Logic IP projects on energy harvesting, TRIADE and architecture, frontend VSLI, functional and CPUs & Controllers TIBUCON, and togther these research activities formal verification and FPGA emulation. Embedded FPGA combine state of the art development of flexible Owing to our productive partnerships with Memory IP energy harvesting systems with practical major EDA companies, such as Cadence, On-Chip Bus Interconnect applications in aeronautics and building Synopsys and Mentor Graphics, Veriest has Processor Platforms management. The energy harvesting network become one of the early adopters of the Verification IO provides an important focus for the community latest in chip design and EDA technologies. Application-Specific IP: with the objective of raising the profile of Our highly trained design quality engineers Data Communication research in this area and identifying future and process analysts ensure we continue to Digital Signal Processing opportunities. In 2004, ECS formed Perpetuum provide leading applications and ASIC, SoC, Multimedia Graphics Ltd, a University spin-out based upon vibration FPGA design and verification services. Networking energy harvesting research. From specification to first-time-right silicon, Telecommunication our expertise in architecture, high speed and Wireless Communication PRODUCT FINDER low power design and methodology enables ASIC and SOC Design: our customers to achieve enhanced Behavioural Modelling & Simulation performance and faster time-to-market. Synthesis Power & Optimisation Analogue and Mixed-Signal Design yield by automating frame generation, Multi- MEMS Design stand 34 Project Wafers assembly, intuitive mask set System-Level Design: creation, and wafer map optimization, and by Behavioural Modelling & Analysis streamlining the mask order process. XYALIS' Acceleration & Emulation XYALIS solutions have been developed in cooperation Hardware/Software Co-Design Contact: Rene Donkers with major semiconductor industry leaders and PCB & MCM Design US office, San Carlos, California, USA have been used in production for years. Test: Europe Office, Eindhoven, the Netherlands Design for Test Tel: +31 641539004 PRODUCT FINDER Design for Manufacture and Yield Fax: +31 847503816 Test: Mixed-Signal Test E-Mail: [email protected] Design for Manufacture and Yield System Test Website: www.fract-tech.com Services: Services: Data Management and Collaboration Design Consultancy XYALIS is an EDA company offering a fully Embedded Software Development: Prototyping integrated Mask Data Preparation solution to Software/Modelling Data Management and Collaboration eliminate the risk of error, reduce time to IP e-commerce & Exchange manufacturing, and increase manufacturing Embedded Software Development: Software/Modelling Semiconductor IP: Analogue & Mixed Signal IP Embedded FPGA Embedded Software IP Application-Specific IP: Analogue & Mixed Signal IP Digital Signal Processing DATE 11 EVENT GUIDE 35 March 12-16, 2012, ICC, Dresden, Germany
Scope of the Event Structure of the Event The 15th DATE conference and exhibition The five-day event consists of a conference with plenary invited papers, regular is the main European event bringing papers, panels, hot-topic sessions, tutorials, workshops, two special focus days and a together designers and design track for executives. The scientific conference is complemented by a commercial automation users, researchers and exhibition showing the state-of-the-art in design and test tools, methodologies, IP vendors, as well as specialists in the and design services, reconfigurable and other hardware platforms, embedded software, hardware and software design, test and and (industrial) design experiences from different application domains, such as manufacturing of electronic circuits and automotive, wireless, telecom and multimedia applications. The organisation of user systems. It puts strong emphasis on group meetings, fringe meetings, a university booth, a PhD forum, vendor both ICs/SoCs, reconfigurable hardware presentations and social events offers a wide variety of extra opportunities to meet and embedded systems, including and exchange information on relevant issues for the design and test community. embedded software. Special space will also be allocated for EU-funded projects to show their results. More details are given on the DATE website (www.date-conference.com).
Areas of Interest Within the scope of the conference, the main areas of interest are: embedded systems, design methodologies, CAD languages, algorithms and tools, testing of electronic circuits and systems, embedded software, applications design and industrial design experiences. Topics of interest include, but are not restricted to: • System Specification and Modeling • Communication, Consumer and Multimedia Systems • System Design, Synthesis and Optimization • Transportation Systems • Simulation and Validation • Medical and Healthcare Systems • Design of Low Power Systems • Energy Generation, Recovery and Management Systems • Power Estimation and Optimization • Secure, Dependable and Adaptive Systems • Emerging Technologies, Systems and Applications • Test for Defects, Variability, and Reliability • Formal Methods and Verification • Test Generation, Simulation and Diagnosis • Network on Chip • Test for Mixed-Signal, Analog, RF, MEMS • Architectural and Microarchitectural Design • Test Access, Design-for-Test, Test Compression, System Test • Architectural and High-Level Synthesis • On-Line Testing and Fault Tolerance • Reconfigurable Computing • Real-time, Networked and Dependable Systems • Logic and Technology Dependent Synthesis for • Compilers and Code Generation for Embedded Systems; Software- Deep-Submicron Circuits centric System Design Exploration • Physical Design and Verification • Model-based Design and Verification for Embedded Systems • Analogue and Mixed-Signal Circuits and Systems • Embedded Software Architectures and Principles; Software for MPSoC, Multi/many-core and GPU-based Systems • Interconnect, EMC, EMD and Packaging Modeling • Computing Systems
Submission of Papers DATE Secretariat Chairs All papers have to be submitted European Conferences General Chair: Wolfgang Rosenstiel, electronically by September 11th, 2011 3 Coates Place, University of Tuebingen, Germany, via: http://www.date- Edinburgh, EH3 7AA, UK [email protected] conference.com/submit.html Papers can be submitted either for Tel: +44-131-225-2892 Program Chair: Lothar Thiele, standard oral presentation or for Fax: +44-131-225-2925 ETH Zurich, Switzerland, interactive presentation Email: [email protected] [email protected]
DATE 11 EVENT GUIDE 36