Synthesis of a Constrained Random Testbench Framework
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EP Activity Report 2014
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Formal Hardware Specification Languages for Protocol Compliance Verification
Formal Hardware Specification Languages for Protocol Compliance Verification ANNETTE BUNKER and GANESH GOPALAKRISHNAN University of Utah and SALLY A. MCKEE Cornell University The advent of the system-on-chip and intellectual property hardware design paradigms makes pro- tocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally in- tended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the devel- opment of the language, an evaluation of the language’s utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered. Categories and Subject Descriptors: B.4.3 [Input/Output and Data Communications]: Inter- connections (Subsystems)—Interfaces; B.4.5 [Input/Output and Data Communications]: Reli- ability, Testing, and Fault-Tolerance—Hardware reliability; B.7.2 [Integrated Circuits]: Design aids—Verification; C.2.2 [Computer-Communication Networks]: Network Protocols—Protocol verification; D.3.3 [Programming Languages]: Language Constructs and Features—Data types -
Technical Portion
50 50 YEARS OF INNOVATION DESIGN AUTOMATION CONFERENCE Celebrating 50 Years of Innovation! www.DAC.com JUNE 2-6, 2013 AUSTIN CONVENTION CENTER - AUSTIN, TX SPONSORED BY: IN TECHNICAL COOPERATION WITH: 1 2 TABLE OF CONTENTS General Chair’s Welcome ....................................................................................................................... 4 Sponsors ................................................................................................................................................. 5 Important Information ............................................................................................................................ 6 Networking Receptions .......................................................................................................................... 7 Keynotes ....................................................................................................................................8,9,13-15 Kickin’ it up in Austin Party .................................................................................................................. 10 Global Forum ........................................................................................................................................ 11 Awards .................................................................................................................................................. 12 Technical Sessions ..........................................................................................................................16-36 -
EP Activity Report 2015
EUROPRACTICE IC SERVICE THE RIGHT COCKTAIL OF ASIC SERVICES EUROPRACTICE IC SERVICE OFFERS YOU A PROVEN ROUTE TO ASICS THAT FEATURES: · .QYEQUV#5+%RTQVQV[RKPI · (NGZKDNGCEEGUUVQUKNKEQPECRCEKV[HQTUOCNNCPFOGFKWOXQNWOGRTQFWEVKQPSWCPVKVKGU · 2CTVPGTUJKRUYKVJNGCFKPIYQTNFENCUUHQWPFTKGUCUUGODN[CPFVGUVJQWUGU · 9KFGEJQKEGQH+%VGEJPQNQIKGU · &KUVTKDWVKQPCPFHWNNUWRRQTVQHJKIJSWCNKV[EGNNNKDTCTKGUCPFFGUKIPMKVUHQTVJGOQUVRQRWNCT%#&VQQNU · 46.VQ.C[QWVUGTXKEGHQTFGGRUWDOKETQPVGEJPQNQIKGU · (TQPVGPF#5+%FGUKIPVJTQWIJ#NNKCPEG2CTVPGTU +PFWUVT[KUTCRKFN[FKUEQXGTKPIVJGDGPG«VUQHWUKPIVJG'74124#%6+%'+%UGTXKEGVQJGNRDTKPIPGYRTQFWEVFGUKIPUVQOCTMGV SWKEMN[CPFEQUVGHHGEVKXGN[6JG'74124#%6+%'#5+%TQWVGUWRRQTVUGURGEKCNN[VJQUGEQORCPKGUYJQFQP°VPGGFCNYC[UVJG HWNNTCPIGQHUGTXKEGUQTJKIJRTQFWEVKQPXQNWOGU6JQUGEQORCPKGUYKNNICKPHTQOVJG¬GZKDNGCEEGUUVQUKNKEQPRTQVQV[RGCPF RTQFWEVKQPECRCEKV[CVNGCFKPIHQWPFTKGUFGUKIPUGTXKEGUJKIJSWCNKV[UWRRQTVCPFOCPWHCEVWTKPIGZRGTVKUGVJCVKPENWFGU+% OCPWHCEVWTKPIRCEMCIKPICPFVGUV6JKU[QWECPIGVCNNHTQO'74124#%6+%'+%UGTXKEGCUGTXKEGVJCVKUCNTGCF[GUVCDNKUJGF HQT[GCTUKPVJGOCTMGV THE EUROPRACTICE IC SERVICES ARE OFFERED BY THE FOLLOWING CENTERS: · KOGE.GWXGP $GNIKWO · (TCWPJQHGT+PUVKVWVHWGT+PVGITKGTVG5EJCNVWPIGP (TCWPJQHGT++5 'TNCPIGP )GTOCP[ This project has received funding from the European Union’s Seventh Programme for research, technological development and demonstration under grant agreement N° 610018. This funding is exclusively used to support European universities and research laboratories. © imec FOREWORD Dear EUROPRACTICE customers, We are at the start of the -
Introduction to Verilog HDL
Introduction to Verilog HDL Jorge Ramírez Corp Application Engineer Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez Outline Lexical elements • HDL Verilog Data type representation Structures and Hierarchy • Synthesis Verilog tutorial Operators • Assignments Synthesis coding guidelines Control statements • Verilog - Test bench Task and functions Generate blocks • Fine State Machines • References Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez HDL VERILOG Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez What is HDL? • Hard & Difficult Language? – No, means Hardware Description Language • High Level Language – To describe the circuits by syntax and sentences – As oppose to circuit described by schematics • Widely used HDLs – Verilog – Similar to C – SystemVerilog – Similar to C++ – VHDL – Similar to PASCAL Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez Verilog • Verilog was developed by Gateway Design Automation as a proprietary language for logic simulation in 1984. • Gateway was acquired by Cadence in 1989 • Verilog was made an open standard in 1990 under the control of Open Verilog International. • The language became an IEEE standard in 1995 (IEEE STD 1364) and was updated in 2001 and 2005. Synopsys University Courseware Copyright © 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez SystemVerilog • SystemVerilog is the industry's first unified hardware description and verification language • Started with Superlog language to Accellera in 2002 • Verification functionality (base on OpenVera language) came from Synopsys • In 2005 SystemVerilog was adopted as IEEE Standard (1800-2005). The current version is 1800-2009 Synopsys University Courseware Copyright © 2011 Synopsys, Inc. -
Tarasenko Magistr.Pdf
НАЦІОНАЛЬНИЙ ТЕХНІЧНИЙ УНІВЕРСИТЕТ УКРАЇНИ «КИЇВСЬКИЙ ПОЛІТЕХНІЧНИЙ ІНСТИТУТ імені ІГОРЯ СІКОРСЬКОГО» ФАКУЛЬТЕТ ПРИКЛАДНОЇ МАТЕМАТИКИ КАФЕДРА СИСТЕМНОГО ПРОГРАМУВАННЯ І СПЕЦІАЛІЗОВАНИХ КОМП’ЮТЕРНИХ СИСТЕМ «На правах рукопису» «До захисту допущено» УДК 004.31 Завідувач кафедри СПСКС __________ В.П.Тарасенко_ (підпис) (ініціали, прізвище) “___”_____________2018р. Магістерська дисертація на здобуття ступеня магістра зі спеціальності 123 Комп‘ютерна інженерія (Спеціалізовані комп‘ютерні системи) на тему: «Методи захисту спеціалізованих моніторингових комп’ютерних засобів на ПЛІС» Виконав: студент II курсу, групи КВ-63м (шифр групи) Тарасенко Георгій Олегович (прізвище, ім’я, по батькові) (підпис) Науковий керівник к.т.н., доцент Клятченко Ярослав Михайлович (посада, науковий ступінь, вчене звання, прізвище та ініціали) (підпис) Рецензент д.т.н., професор Симоненко Валерій Павлович (посада, науковий ступінь, вчене звання, науковий ступінь, прізвище та ініціали) (підпис) Засвідчую, що у цій магістерській дисертації немає запозичень з праць інших авторів без відповідних посилань. Студент _____________ (підпис) Київ – 2018 року НАЦІОНАЛЬНИЙ ТЕХНІЧНИЙ УНІВЕРСИТЕТ УКРАЇНИ «КИЇВСЬКИЙ ПОЛІТЕХНІЧНИЙ ІНСТИТУТ імені ІГОРЯ СІКОРСЬКОГО» Факультет прикладної математики Кафедра системного програмування і спеціалізованих комп’ютерних систем Рівень вищої освіти – другий (магістерський) Спеціальність 123 Комп‘ютерна інженерія Спеціалізовані комп‘ютерні системи ЗАТВЕРДЖУЮ Завідувач кафедри СПСКС __________ _В.П.Тарасенко__ (підпис) (ініціали, прізвище) «___»_____________2018р. -
UVM Verification Framework
UVM Verification Framework Mads Bergan Roligheten Electronics System Design and Innovation Submission date: June 2014 Supervisor: Kjetil Svarstad, IET Co-supervisor: Vitaly Marchuk, Atmel Norway AS Norwegian University of Science and Technology Department of Electronics and Telecommunications i Problem description Atmel has a wide range of IP designs and a good, reusable and efficient verification framework is extremely important to have short time to market. UVM (Universal Verification Methodology) is a methodology for functional verification using Sys- temVerilog, which is a set of standardized libraries of SystemVerilog. The student will investigate how UVM can be used to build a reusable verification framework. He has to take decisions on the following tasks: - Synchronization between transaction level and RTL design; - Packing and unpacking transactions and driving them to the design under test; - Configuration database and reusability; - Constrained randomization; - Functional coverage and test execution control; The verification framework can be used on any open source RTL. This is interesting and challenging work on top edge of industry verification. It requires knowledge of SystemVerilog, object-oriented programming and digital systems. Assignment given: January 2014 Supervisor: Kjetil Svarstad, IET Assignment proposer / Co-supervisor: Vitaly Marchuk, Atmel Norway AS ii Abstract iii Abstract The importance of verification is increasing with the size of hardware designs, and reducing the effort required for is necessary to increase productivity. This thesis covers the creation of a reusable verification framework for processor verification using the Universal Verification Methodology (UVM). The framework is used to verify three simple processor designs to evaluate its potential for reuse. The three processors include a synchronous, asynchronous and a stack based processor. -
C 2011 MICHAEL KAHN KATELMAN a META-LANGUAGE for FUNCTIONAL VERIFICATION
c 2011 MICHAEL KAHN KATELMAN A META-LANGUAGE FOR FUNCTIONAL VERIFICATION BY MICHAEL KAHN KATELMAN DISSERTATION Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate College of the University of Illinois at Urbana-Champaign, 2011 Urbana, Illinois Doctoral Committee: Professor Jos´eMeseguer, Chair and Director of Research Professor Arvind, Massachusetts Institute of Technology Associate Professor Grigore Ros, u Professor Josep Torrellas ABSTRACT This dissertation perceives a similarity between two activities: that of coordi- nating the search for simulation traces toward reaching verification closure, and that of coordinating the search for a proof within a theorem prover. The programmatic coordination of simulation is difficult with existing tools for dig- ital circuit verification because stimuli generation, simulation execution, and analysis of simulation results are all decoupled. A new programming language to address this problem, analogous to the mechanism for orchestrating proof search tactics within a theorem prover, is defined wherein device simulation is made a first-class notion. This meta-language for functional verification is first formalized in a parametric way over hardware description languages using rewriting logic, and subsequently a more richly featured software tool for Verilog designs, implemented as an embedded domain-specific language in Haskell, is described and used to demonstrate the novelty of the programming language and to conduct two case studies. Additionally, three hardware description languages are given formal semantics using rewriting logic and we demonstrate the use of executable rewriting logic tools to formally analyze devices implemented in those languages. ii This dissertation is dedicated to MIPS Technologies, Inc., in appreciation for having provided me with the opportunity to closely observe the functional verification effort of the 74K microprocessor. -
Vysok´E Uˇcení Technick´E V Brnˇe
VYSOKEU´ CENˇ ´I TECHNICKE´ V BRNEˇ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMACNˇ ´ICH TECHNOLOGI´I USTAV´ POCˇ ´ITACOVˇ YCH´ SYSTEM´ U˚ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF COMPUTER SYSTEMS NEW METHODS FOR INCREASING EFFICIENCY AND SPEED OF FUNCTIONAL VERIFICATION DIZERTACNˇ ´I PRACE´ PHD THESIS AUTOR PRACE´ Ing. MARCELA SIMKOVˇ A´ AUTHOR BRNO 2015 VYSOKEU´ CENˇ ´I TECHNICKE´ V BRNEˇ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMACNˇ ´ICH TECHNOLOGI´I USTAV´ POCˇ ´ITACOVˇ YCH´ SYSTEM´ U˚ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF COMPUTER SYSTEMS METODY AKCELERACE VERIFIKACE LOGICKYCH´ OBVODU˚ NEW METHODS FOR INCREASING EFFICIENCY AND SPEED OF FUNCTIONAL VERIFICATION DIZERTACNˇ ´I PRACE´ PHD THESIS AUTOR PRACE´ Ing. MARCELA SIMKOVˇ A´ AUTHOR VEDOUC´I PRACE´ Doc. Ing. ZDENEKˇ KOTASEK,´ CSc. SUPERVISOR BRNO 2015 Abstrakt Priˇ vyvoji´ soucasnˇ ych´ cˇ´ıslicovych´ system´ u,˚ napr.ˇ vestavenˇ ych´ systemu´ a pocˇ´ıtacovˇ eho´ hardware, je nutne´ hledat postupy, jak zvy´sitˇ jejich spolehlivost. Jednou z moznostˇ ´ı je zvysovˇ an´ ´ı efektivity a rychlosti verifikacnˇ ´ıch procesu,˚ ktere´ se provad´ ejˇ ´ı v ranych´ faz´ ´ıch navrhu.´ V teto´ dizertacnˇ ´ı praci´ se pozornost venujeˇ verifikacnˇ ´ımu prˇ´ıstupu s nazvem´ funkcnˇ ´ı verifikace. Je identifikovano´ nekolikˇ vyzev´ a problemu´ tykaj´ ´ıc´ıch se efektivity a rychlosti funkcnˇ ´ı verifikace a ty jsou nasledn´ eˇ reˇ senyˇ v c´ılech dizertacnˇ ´ı prace.´ Prvn´ı c´ıl se zameˇrujeˇ na redukci simulacnˇ ´ıho casuˇ v prub˚ ehuˇ verifikace komplexn´ıch system´ u.˚ Duvodem˚ je, zeˇ simulace inherentneˇ paraleln´ıho hardwaroveho´ systemu´ trva´ velmi dlouho v porovnan´ ´ı s behemˇ v skutecnˇ em´ hardware. Je proto navrhnuta optimalizacnˇ ´ı technika, ktera´ umist’uje verifikovany´ system´ do FPGA akceleratoru,´ zat´ım co cˇast´ verifikacnˇ ´ıho prostredˇ ´ı stale´ beˇzˇ´ı v simulaci. -
Parallel Systemc Simulation for Electronic System Level Design
Parallel SystemC Simulation for Electronic System Level Design Von der Fakultät für Elektrotechnik und Informationstechnik der Rheinisch–Westfälischen Technischen Hochschule Aachen zur Erlangung des akademischen Grades eines Doktors der Ingenieurwissenschaften genehmigte Dissertation vorgelegt von Diplom–Ingenieur Jan Henrik Weinstock aus Göttingen Berichter: Universitätsprofessor Dr. rer. nat. Rainer Leupers Universitätsprofessor Dr.-Ing. Diana Göhringer Tag der mündlichen Prüfung: 19.06.2018 Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfügbar. Abstract Over the past decade, Virtual Platforms (VPs) have established themselves as essential tools for embedded system design. Their application fields range from rapid proto- typing over design space exploration to early software development. This makes VPs a core enabler for concurrent HW/SW design – an indispensable design approach for meeting today’s aggressive marketing schedules. VPs are essentially a simulation of a complete microprocessor system, detailed enough to run unmodified target binary code. During simulation, VPs provide non-intrusive debugging access as well as re- porting on non-functional system parameters, such as execution timing and estimated power and energy consumption. To accelerate the construction of a VP for new systems, developers typically rely on pre-existing simulation environments. SystemC is a popular example for this and has become the de-facto reference for VP design since it became an official IEEE stan- dard in 2005. Since then, however, SystemC has failed to keep pace with its user’s demands for high simulation speed, especially when embedded multi-core systems are concerned. Because SystemC only utilizes a single processor of the host computer, the underlying sequential discrete event simulation algorithm becomes a performance bottleneck when simulating multiple virtual processors. -
DAC Final Program Ad.Indd 1 4/5/2012 11:09:02 AM
New Resources for ACM Members! ACM is the computing organization for practitioners, researchers, academics and students. Check out these new ACM Learning Center resources to advance your career and life-long learning goals: More than 130 new eBooks from Morgan Kaufmann: full-text versions of eBook titles published by Morgan Kaufmann and Syngress, in addition to the hundreds of online books and courses offered in the Learning Center: http://learning.acm.org. New Tech Pack on Business Intelligence and Data Management. Other Tech Packs, which are learning packages on cutting-edge topics that include both traditional and non-traditional learning resources, cover Cloud Computing, Parallel Computing, Enterprise Architecture, and Mobility. Webinars on Cloud Computing and Security: This year, ACM launched a free learning webinar series. "The Cloud in Your Hands: Marriage of Cloud Computing with Smart Devices" provides an introduction to the exciting new world of cloud-enabled mobile computing. "Security: Computing in an Adversarial Environment" introduces security fundamentals, describes the security mindset, and highlights the difficulties of achieving security. More topics are planned for this popular series! If you’re not already a member, join ACM now, and enjoy these valuable benefits: Communications of the ACM Career resources http://cacm.acm.org http://jobs.acm.org Discounted subscription to ACM’s Digital Library ACM Local Chapters http://dl.acm.org http://www.acm.org/chapters Discounts on Special Interest Group conferences ACM Special Interest Groups http://www.acm.org/calendar-of-events www.acm.org/sigs Go to www.acm.org/conf to join ACM, and start expanding your professional network today! TUESDAY, June 5, 12:00 pm - 2:00 pm | Room 303 IEEE CEDA Presents: Digital Analog Design Organizer: Joel Phillips, Cadence Design Systems Speaker: Mark Horowitz, Stanford University The past 30 years have seen enormous growth in the power and sophistication of digital- design tools, whereas progress in analog tools has been far more modest. -
Writing Testbenches.Book
PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification. Unlike synthesizeable coding, there is no particular coding style nor language required for verification. The freedom of using any lan- guage that can be interfaced to a simulator and of using any features of that language has produced a wide array of techniques and approaches to verification. The absence of constraints and historical lack of available expertise and references in verification has resulted in ad hoc approaches. The consequences of an informal verification process can range from a non-functional design requir- ing several re-spins, through a design with only a subset of the intended functionality, to a delayed product shipment. WHY THIS BOOK IS IMPORTANT Take a survey of the books about Verilog or VHDL currently avail- able. You will notice that the majority of the pages are devoted to explaining the details of the languages. In addition, several chapters are focused on the synthesizeable—or RTL—coding style replete with examples. Some books are even devoted entirely to the subject of RTL coding. When verification is addressed, only one or two chapters are dedi- cated to the topic. And often, the primary focus is to introduce more language constructs. Verification is usually presented in a very rudi- Writing Testbenches: Functional Verification of HDL Models xix Preface mentary fashion, using simple, non-scalable techniques that become tedious in large-scale, real-life designs. The first edition of this book was the first book specifically devoted to functional verification techniques for hardware models.