The One-Transistor, One-Capacitor (1T1C) Dynamic Random Access Memory (DRAM), and Its Impact on Society
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Run Capacitor Info-98582
Run Cap Quiz-98582_Layout 1 4/16/15 10:26 AM Page 1 ® Run Capacitor Info WHAT IS A CAPACITOR? Very simply, a capacitor is a device that stores and discharges electrons. While you may hear capacitors referred to by a variety of names (condenser, run, start, oil, etc.) all capacitors are comprised of two or more metallic plates separated by an insulating material called a dielectric. PLATE 1 PLATE 2 A very simple capacitor can be made with two plates separated by a dielectric, in this PLATE 1 PLATE 2 case air, and connected to a source of DC current, a battery. Electrons will flow away from plate 1 and collect on plate 2, leaving it with an abundance of electrons, or a “charge”. Since current from a battery only flows one way, the capacitor plate will stay BATTERY + – charged this way unless something causes current flow. If we were to short across the plates with a screwdriver, the resulting spark would indicate the electrons “jumping” from plate 2 to plate 1 in an attempt to equalize. As soon as the screwdriver is removed, plate 2 will again collect a PLATE 1 PLATE 2 charge. + BATTERY – Now let’s connect our simple capacitor to a source of AC current and in series with the windings of an electric motor. Since AC current alternates, first one PLATE 1 PLATE 2 MOTOR plate, then the other would be charged and discharged in turn. First plate 1 is charged, then as the current reverses, a rush of electrons flow from plate 1 to plate 2 through the motor windings. -
Chapter 7: AC Transistor Amplifiers
Chapter 7: Transistors, part 2 Chapter 7: AC Transistor Amplifiers The transistor amplifiers that we studied in the last chapter have some serious problems for use in AC signals. Their most serious shortcoming is that there is a “dead region” where small signals do not turn on the transistor. So, if your signal is smaller than 0.6 V, or if it is negative, the transistor does not conduct and the amplifier does not work. Design goals for an AC amplifier Before moving on to making a better AC amplifier, let’s define some useful terms. We define the output range to be the range of possible output voltages. We refer to the maximum and minimum output voltages as the rail voltages and the output swing is the difference between the rail voltages. The input range is the range of input voltages that produce outputs which are not at either rail voltage. Our goal in designing an AC amplifier is to get an input range and output range which is symmetric around zero and ensure that there is not a dead region. To do this we need make sure that the transistor is in conduction for all of our input range. How does this work? We do it by adding an offset voltage to the input to make sure the voltage presented to the transistor’s base with no input signal, the resting or quiescent voltage , is well above ground. In lab 6, the function generator provided the offset, in this chapter we will show how to design an amplifier which provides its own offset. -
Switched-Capacitor Circuits
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto ([email protected]) ([email protected]) University of Toronto 1 of 60 © D. Johns, K. Martin, 1997 Basic Building Blocks Opamps • Ideal opamps usually assumed. • Important non-idealities — dc gain: sets the accuracy of charge transfer, hence, transfer-function accuracy. — unity-gain freq, phase margin & slew-rate: sets the max clocking frequency. A general rule is that unity-gain freq should be 5 times (or more) higher than the clock-freq. — dc offset: Can create dc offset at output. Circuit techniques to combat this which also reduce 1/f noise. University of Toronto 2 of 60 © D. Johns, K. Martin, 1997 Basic Building Blocks Double-Poly Capacitors metal C1 metal poly1 Cp1 thin oxide bottom plate C1 poly2 Cp2 thick oxide C p1 Cp2 (substrate - ac ground) cross-section view equivalent circuit • Substantial parasitics with large bottom plate capacitance (20 percent of C1) • Also, metal-metal capacitors are used but have even larger parasitic capacitances. University of Toronto 3 of 60 © D. Johns, K. Martin, 1997 Basic Building Blocks Switches I I Symbol n-channel v1 v2 v1 v2 I transmission I I gate v1 v p-channel v 2 1 v2 I • Mosfet switches are good switches. — off-resistance near G: range — on-resistance in 100: to 5k: range (depends on transistor sizing) • However, have non-linear parasitic capacitances. University of Toronto 4 of 60 © D. Johns, K. Martin, 1997 Basic Building Blocks Non-Overlapping Clocks I1 T Von I I1 Voff n – 2 n – 1 n n + 1 tTe delay 1 I fs { --- delay V 2 T on I Voff 2 n – 32e n – 12e n + 12e tTe • Non-overlapping clocks — both clocks are never on at same time • Needed to ensure charge is not inadvertently lost. -
Nanotechnology ? Nram (Nano Random Access
International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions. -
Kirchhoff's Laws in Dynamic Circuits
Kirchhoff’s Laws in Dynamic Circuits Dynamic circuits are circuits that contain capacitors and inductors. Later we will learn to analyze some dynamic circuits by writing and solving differential equations. In these notes, we consider some simpler examples that can be solved using only Kirchhoff’s laws and the element equations of the capacitor and the inductor. Example 1: Consider this circuit Additionally, we are given the following representations of the voltage source voltage and one of the resistor voltages: ⎧⎧10 V fortt<< 0 2 V for 0 vvs ==⎨⎨and 1 −5t ⎩⎩20 V forte>+ 0 8 4 V fort> 0 We wish to express the capacitor current, i 2 , as a function of time, t. Plan: First, apply Kirchhoff’s voltage law (KVL) to the loop consisting of the source, resistor R1 and the capacitor to determine the capacitor voltage, v 2 , as a function of time, t. Next, use the element equation of the capacitor to determine the capacitor current as a function of time, t. Solution: Apply Kirchhoff’s voltage law (KVL) to the loop consisting of the source, resistor R1 and the capacitor to write ⎧ 8 V fort < 0 vvv12+−=ss0 ⇒ v2 =−= vv 1⎨ −5t ⎩16− 8et V for> 0 Use the element equation of the capacitor to write ⎧ 0 A fort < 0 dv22 dv ⎪ ⎧ 0 A fort < 0 iC2 ==0.025 =⎨⎨d −5t =−5t dt dt ⎪0.025() 16−> 8et for 0 ⎩1et A for> 0 ⎩ dt 1 Example 2: Consider this circuit where the resistor currents are given by ⎧⎧0.8 A fortt<< 0 0 A for 0 ii13==⎨⎨−−22ttand ⎩⎩0.8et−> 0.8 A for 0 −0.8 e A fort> 0 Express the inductor voltage, v 2 , as a function of time, t. -
Capacitive Voltage Transformers: Transient Overreach Concerns and Solutions for Distance Relaying
Capacitive Voltage Transformers: Transient Overreach Concerns and Solutions for Distance Relaying Daqing Hou and Jeff Roberts Schweitzer Engineering Laboratories, Inc. Revised edition released October 2010 Previously presented at the 1996 Canadian Conference on Electrical and Computer Engineering, May 1996, 50th Annual Georgia Tech Protective Relaying Conference, May 1996, and 49th Annual Conference for Protective Relay Engineers, April 1996 Previous revised edition released July 2000 Originally presented at the 22nd Annual Western Protective Relay Conference, October 1995 CAPACITIVE VOLTAGE TRANSFORMERS: TRANSIENT OVERREACH CONCERNS AND SOLUTIONS FOR DISTANCE RELAYING Daqing Hou and Jeff Roberts Schweitzer Engineering Laboratories, Inc. Pullman, W A USA ABSTRACT Capacitive Voltage Transformers (CVTs) are common in high-voltage transmission line applications. These same applications require fast, yet secure protection. However, as the requirement for faster protective relays grows, so does the concern over the poor transient response of some CVTs for certain system conditions. Solid-state and microprocessor relays can respond to a CVT transient due to their high operating speed and iflCreased sensitivity .This paper discusses CVT models whose purpose is to identify which major CVT components contribute to the CVT transient. Some surprises include a recom- mendation for CVT burden and the type offerroresonant-suppression circuit that gives the least CVT transient. This paper also reviews how the System Impedance Ratio (SIR) affects the CVT transient response. The higher the SIR, the worse the CVT transient for a given CVT . Finally, this paper discusses improvements in relaying logic. The new method of detecting CVT transients is more precise than past detection methods and does not penalize distance protection speed for close-in faults. -
Solid State Drives Data Reliability and Lifetime
Solid State Drives Data Reliability and Lifetime White Paper Alan R. Olson & Denis J. Langlois April 7, 2008 Abstract The explosion of flash memory technology has dramatically increased storage capacity and decreased the cost of non-volatile semiconductor memory. The technology has fueled the proliferation of USB flash drives and is now poised to replace magnetic hard disks in some applications. A solid state drive (SSD) is a non-volatile memory system that emulates a magnetic hard disk drive (HDD). SSDs do not contain any moving parts, however, and depend on flash memory chips to store data. With proper design, an SSD is able to provide high data transfer rates, low access time, improved tolerance to shock and vibration, and reduced power consumption. For some applications, the improved performance and durability outweigh the higher cost of an SSD relative to an HDD. Using flash memory as a hard disk replacement is not without challenges. The nano-scale of the memory cell is pushing the limits of semiconductor physics. Extremely thin insulating glass layers are necessary for proper operation of the memory cells. These layers are subjected to stressful temperatures and voltages, and their insulating properties deteriorate over time. Quite simply, flash memory can wear out. Fortunately, the wear-out physics are well understood and data management strategies are used to compensate for the limited lifetime of flash memory. Floating Gate Flash Memory Cells Flash memory was invented by Dr. Fujio Masuoka while working for Toshiba in 1984. The name "flash" was suggested because the process of erasing the memory contents reminded him of the flash of a camera. -
Embedded DRAM
Embedded DRAM Raviprasad Kuloor Semiconductor Research and Development Centre, Bangalore IBM Systems and Technology Group DRAM Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example References Slide 1 Acknowledgement • John Barth, IBM SRDC for most of the slides content • Madabusi Govindarajan • Subramanian S. Iyer • Many Others Slide 2 Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example Slide 3 Memory Classification revisited Slide 4 Motivation for a memory hierarchy – infinite memory Memory store Processor Infinitely fast Infinitely large Cycles per Instruction Number of processor clock cycles (CPI) = required per instruction CPI[ ∞ cache] Finite memory speed Memory store Processor Finite speed Infinite size CPI = CPI[∞ cache] + FCP Finite cache penalty Locality of reference – spatial and temporal Temporal If you access something now you’ll need it again soon e.g: Loops Spatial If you accessed something you’ll also need its neighbor e.g: Arrays Exploit this to divide memory into hierarchy Hit L2 L1 (Slow) Processor Miss (Fast) Hit Register Cache size impacts cycles-per-instruction Access rate reduces Slower memory is sufficient Cache size impacts cycles-per-instruction For a 5GHz -
Aluminum Electrolytic Vs. Polymer – Two Technologies – Various Opportunities
Aluminum Electrolytic vs. Polymer – Two Technologies – Various Opportunities By Pierre Lohrber BU Manager Capacitors Wurth Electronics @APEC 2017 2017 WE eiCap @ APEC PSMA 1 Agenda Electrical Parameter Technology Comparison Application 2017 WE eiCap @ APEC PSMA 2 ESR – How to Calculate? ESR – Equivalent Series Resistance ESR causes heat generation within the capacitor when AC ripple is applied to the capacitor Maximum ESR is normally specified @ 120Hz or 100kHz, @20°C ESR can be calculated like below: ͕ͨ͢ 1 1 ͍̿͌ Ɣ Ɣ ͕ͨ͢ ∗ ͒ ͒ Ɣ Ɣ 2 ∗ ∗ ͚ ∗ ̽ 2 ∗ ∗ ͚ ∗ ̽ ! ∗ ̽ 2017 WE eiCap @ APEC PSMA 3 ESR – Temperature Characteristics Electrolytic Polymer Ta Polymer Al Ceramics 2017 WE eiCap @ APEC PSMA 4 Electrolytic Conductivity Aluminum Electrolytic – Caused by the liquid electrolyte the conductance response is deeply affected – Rated up to 0.04 S/cm Aluminum Polymer – Solid Polymer pushes the conductance response to much higher limits – Rated up to 4 S/cm 2017 WE eiCap @ APEC PSMA 5 Electrical Values – Who’s Best in Class? Aluminum Electrolytic ESR approx. 85m Ω Tantalum Polymer Ripple Current rating approx. ESR approx. 200m Ω 630mA Ripple Current rating approx. 1,900mA Aluminum Polymer ESR approx. 11m Ω Ripple Current rating approx. 5,500mA 2017 WE eiCap @ APEC PSMA 6 Ripple Current >> Temperature Rise Ripple current is the AC component of an applied source (SMPS) Ripple current causes heat inside the capacitor due to the dielectric losses Caused by the changing field strength and the current flow through the capacitor 2017 WE eiCap @ APEC PSMA 7 Impedance Z ͦ 1 ͔ Ɣ ͍̿͌ ͦ + (͒ −͒ )ͦ Ɣ ͍̿͌ ͦ + 2 ∗ ∗ ͚ ∗ ͍̿͆ − 2 ∗ ∗ ͚ ∗ ̽ 2017 WE eiCap @ APEC PSMA 8 Impedance Z Impedance over frequency added with ESR ratio 2017 WE eiCap @ APEC PSMA 9 Impedance @ High Frequencies Aluminum Polymer Capacitors have excellent high frequency characteristics ESR value is ultra low compared to Electrolytic’s and Tantalum’s within 100KHz~1MHz E.g. -
Basic DC Motor Circuits
Basic DC Motor Circuits Living with the Lab Gerald Recktenwald Portland State University [email protected] DC Motor Learning Objectives • Explain the role of a snubber diode • Describe how PWM controls DC motor speed • Implement a transistor circuit and Arduino program for PWM control of the DC motor • Use a potentiometer as input to a program that controls fan speed LWTL: DC Motor 2 What is a snubber diode and why should I care? Simplest DC Motor Circuit Connect the motor to a DC power supply Switch open Switch closed +5V +5V I LWTL: DC Motor 4 Current continues after switch is opened Opening the switch does not immediately stop current in the motor windings. +5V – Inductive behavior of the I motor causes current to + continue to flow when the switch is opened suddenly. Charge builds up on what was the negative terminal of the motor. LWTL: DC Motor 5 Reverse current Charge build-up can cause damage +5V Reverse current surge – through the voltage supply I + Arc across the switch and discharge to ground LWTL: DC Motor 6 Motor Model Simple model of a DC motor: ❖ Windings have inductance and resistance ❖ Inductor stores electrical energy in the windings ❖ We need to provide a way to safely dissipate electrical energy when the switch is opened +5V +5V I LWTL: DC Motor 7 Flyback diode or snubber diode Adding a diode in parallel with the motor provides a path for dissipation of stored energy when the switch is opened +5V – The flyback diode allows charge to dissipate + without arcing across the switch, or without flowing back to ground through the +5V voltage supply. -
Measurement Error Estimation for Capacitive Voltage Transformer by Insulation Parameters
Article Measurement Error Estimation for Capacitive Voltage Transformer by Insulation Parameters Bin Chen 1, Lin Du 1,*, Kun Liu 2, Xianshun Chen 2, Fuzhou Zhang 2 and Feng Yang 1 1 State Key Laboratory of Power Transmission Equipment & System Security and New Technology, Chongqing University, Chongqing 400044, China; [email protected] (B.C.); [email protected] (F.Y.) 2 Sichuan Electric Power Corporation Metering Center of State Grid, Chengdu 610045, China; [email protected] (K.L.); [email protected] (X.C.); [email protected] (F.Z.) * Correspondence: [email protected]; Tel.: +86-138-9606-1868 Academic Editor: K.T. Chau Received: 01 February 2017; Accepted: 08 March 2017; Published: 13 March 2017 Abstract: Measurement errors of a capacitive voltage transformer (CVT) are relevant to its equivalent parameters for which its capacitive divider contributes the most. In daily operation, dielectric aging, moisture, dielectric breakdown, etc., it will exert mixing effects on a capacitive divider’s insulation characteristics, leading to fluctuation in equivalent parameters which result in the measurement error. This paper proposes an equivalent circuit model to represent a CVT which incorporates insulation characteristics of a capacitive divider. After software simulation and laboratory experiments, the relationship between measurement errors and insulation parameters is obtained. It indicates that variation of insulation parameters in a CVT will cause a reasonable measurement error. From field tests and calculation, equivalent capacitance mainly affects magnitude error, while dielectric loss mainly affects phase error. As capacitance changes 0.2%, magnitude error can reach −0.2%. As dielectric loss factor changes 0.2%, phase error can reach 5′. -
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 6, JUNE 2011 1495 A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H. Kim, Senior Member, IEEE Abstract—Circuit techniques for enabling a sub-0.9 V logic-com- for achieving low static power and high operating speed. patible embedded DRAM (eDRAM) are presented. A boosted 3T SRAMs have been the embedded memory of choice due to gain cell utilizes Read Word-line (RWL) preferential boosting to their logic compatibility and fast access time. Recently, em- increase read margin and improve data retention time. Read speed is enhanced with a hybrid current/voltage sense amplifier that al- bedded DRAMs (eDRAMs) have been gaining popularity in lows the Read Bit-line (RBL) to remain close to VDD. A regu- the research community due to features such as small cell size, lated bit-line write scheme for driving the Write Bit-line (WBL) is low cell leakage, and non-ratioed circuit operation. There have equipped with a steady-state storage node voltage monitor to over- been a number of successful eDRAM designs based on tradi- come the data ‘1’ write disturbance problem of the PMOS gain cell without introducing another boosted supply for the Write Word- tional 1T1C DRAM cells as well as logic-compatible gain cells line (WWL) over-drive. An adaptive and die-to-die adjustable read [2]–[9]. 1T1C cells are denser than gain cells, but at the cost of a reference bias generator is proposed to cope with PVT variations.