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Clock gating
Instruction-Level Distributed Processing
Clock Gating for Power Optimization in ASIC Design Cycle: Theory & Practice
Saber Eletrônica, Designers Pois Precisamos Comprovar Ao Meio Anunciante Estes Números E, Assim, Carlos C
Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: a Practical Approach∗
Register Allocation and VDD-Gating Algorithms for Out-Of-Order
A 65 Nm 2-Billion Transistor Quad-Core Itanium Processor
Optimization of Clock Gating Logic for Low Power LSI Design
Clock Gating
Mutual Impact Between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators
White P Aper
1/2 - 2008 Elektronik Industrie
Low Power Data-Dependent Transform Video and Still Image Coding
Physically Constrained Architecture for Chip Multiprocessors
IBM Z6 – the Next-Generation Mainframe Microprocessor
15-740/18-740 Computer Architecture Lecture 4: ISA Tradeoffs
A Dual-Mode Synchronous/Asynchronous CORDIC Processor
Low-Power Flip-Flop Using Internal Clock Gating and Adaptive Body Bias" (2006)
Practical Power Gating and Dynamic Voltage/Frequency Scaling Issues | August 17, 2011 | Stephen Kosonocky OUTLINE
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Arm® Corelink™ MMU-600 System Memory Management Unit Revision: R0p1
Power Reduction Through RTL Clock Gating
LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications
Coverstory by Markus Levy, Technical Editor
CORDIC Implementation for Ultralow Power Applications Patricia L
Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency
Dual Core Archietecture for Celluar Handsets
Dynamic Voltage Scaling
18-447 Computer Architecture Lecture 3: ISA Tradeoffs
Dynamic Power Reduction of Digital Circuits by Clock Gating
A Clock-Gated, Double Edge-Triggered Flip-Flop
A 23.52Μw / 0.7V Multi-Stage Flip-Flop Architecture Steered by a LECTOR-Based Gated Clock
Intelr С Atomtm Processor Core Made FPGA-Synthesizable
Optimization of CMOS 8-Bit Counter Using SLA and Clock Gating Technique
A Low Power Clock Gating Based on Look Ahead Clock Gating Aparna S
Software Controlled Clock Modulation for Energy Efficiency Optimization
Low Power Implementation of RISC-V Processor
Energy Efficient Reconfigurable Applications Using Clock Gated Autonomous Power Gating
Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability
IBM POWER8 Memory Buffer User's Manual
The Influence of Clock-Gating on NBTI-Induced Delay Degradation
Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode
Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance
Deterministic Clock Gating to Reduce Microprocessor Power
AN4830: Mpc574xg Mcus Cookbook – Application Note
Based on Prospective Dynamic Frequency Scale Power Optimize Method for Multi-Cores Processor’S I/O System
Design of On-Chip Bus of Heterogeneous 3DIC Micro-Processors (Under the Direction of Dr
Design of Clock Distribution in High Performance Processors
A Hardware/Software Co-Design Architecture for Thermal, Power, and Reliability Management in Chip Multiprocessors
Design Verification of Power Management Scenarios in X86 Based SOC
New Clock-Gating Techniques for Low-Power Flip-Flops
Galaxy Low Power Solution
Intel Opensource HD Graphics Programmer's Reference Manual
Effect of Clock and Power Gating on Power Distribution Network Noise in 2D and 3D Integrated Circuits
Clock Gating
Reappraisal of Clock Gating Methods in Different Conditions
Deterministic Clock Gating for Low Power Vlsi Design
Design and Microarchitecture of the IBM System Z10 Microprocessor
The Benefits of Using Clock Gating in the Design of Networks-On-Chip
Active Mode Sub-Clock Power Gating Jatin Mistry, James Myers, Bashir M
Lecture 21 Power Optimization (Part 2)
Adaptative Techniques to Reduce Power in Digital Circuits
18-741 Advanced Computer Architecture Lecture 1: Intro And
The Limit of Dynamic Voltage Scaling and Insomniac Dynamic Voltage
Dynamic Power Gating Implementation on Intel
A Dual-Core, Dual-Thread Itanium Processor
Optimizing Pipelines for Power and Performance
Mikrocontroller ˘ Softwareentwicklungswerkzeuge Unterstützen Parallelisierung ˘ Ist Ein Standard Außerhalb Der X Welt Möglich? ˘
Design of Coarse-Grained Power Gating for a Fine-Grained Many-Core Processor Array
Verification and Synthesis of Clock-Gated Circuits