DOCSLIB.ORG

Low-Power Flip-Flop Using Internal Clock Gating and Adaptive Body Bias" (2006)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Low-Power Flip-Flop Using Internal Clock Gating and Adaptive Body Bias University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School 2006 Low-power flip-flop sinu g internal clock gating and adaptive body bias Jorge Alberto Galvis University of South Florida Follow this and additional works at: http://scholarcommons.usf.edu/etd Part of the American Studies Commons Scholar Commons Citation Galvis, Jorge Alberto, "Low-power flip-flop using internal clock gating and adaptive body bias" (2006). Graduate Theses and Dissertations. http://scholarcommons.usf.edu/etd/2528 This Dissertation is brought to you for free and open access by the Graduate School at Scholar Commons. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. Low-Power Flip-Flop Using Internal Clock Gating And Adaptive Body Bias by Jorge Alberto Galvis A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Wilfrido Moreno, Ph.D. Fernando Falquez, Ph.D. James Leffew, Ph.D. Srinivas Katkoori, Ph.D. Hua Cao, Ph.D. Date of Approval: March 28, 2006 Keywords: Clocked Storage Elements, Logical Effort, Spice Simulations, Power Consumption, Clocked Logical Units. © Copyright 2006, Jorge Alberto Galvis ACKNOWLEDGEMENTS I wish to thank Dr. Wilfrido Moreno, my major professor, for his friendship, encouragement and support. Without Dr. Moreno’s support this Ph.D. process would truly not have been completed. I wish to thank Dr. James T. Leffew for his arduous work in the revision and correction of the dissertation document. I wish to thank Dr. Fernando Falquez for his guidance and counseling throughout the process of this dissertation. I wish to thank Dr. Srinivas Katkoori for his guidance and teachings during my years as a graduate student and throughout the process of this dissertation. I wish to thank Dr. Hua Cao for his gentle help in this dissertation. I wish to thank Dr. A. N. V. Rao for his friendly help in this dissertation. I wish to thank my family for their sincere and valuable support. TABLE OF CONTENTS LIST OF TABLES iii LIST OF FIGURES iv ABSTRACT vii CHAPTER 1 BACKGROUND 1 1.1 Power Consumption 1 1.2 Leakage Current 2 1.2.1 pn Junction Reverse-Bias Current 3 1.2.2 Subthreshold Leakage 4 1.2.2.1 Drain-Induced Barrier Lowering, (DIBL) 6 1.2.2.2 Body Effect 7 1.2.2.3 Narrow-Width Effect 8 1.2.2.4 Effect of Channel Length and VTH Rolloff 8 1.2.3 Tunneling Into and Through Gate Oxide 9 1.2.3.1 Fowler-Nordheim (FN) Tunneling 9 1.2.3.2 Direct Tunneling 9 1.2.4 Injection of Hot Carriers from Substrate to Gate Oxide 10 1.2.5 Gate-Induced Drain Leakage 10 1.2.6 Punchthrough 10 1.2.7 Leakage Reduction Techniques 11 1.2.8 Process-Level Leakage Reduction Techniques 11 1.2.8.1 Retrograde Doping 12 1.2.8.2 Halo Doping 12 1.2.9 Circuit-Level Leakage Reduction Techniques 12 1.2.9.1 Transistor Stacking, (Self-Reverse Bias) 13 1.2.9.2 Multiple VTH Designs 13 1.2.9.3 Multiple Channel Doping 14 1.2.9.4 Multiple Oxide CMOS 14 1.2.9.5 Multiple Body-Biases 14 1.2.9.6 Supply Voltage Scaling 18 1.3 Logical Effort 19 1.4 Clocked Storage Elements 22 1.4.1 Latch-Based Clocked Storage Elements, (CSE) 22 1.4.2 Transmission-Gate Flip-Flop, (TGFF) 24 1.4.3 True-Single-Phase-Clock Latch 26 i 1.4.4 Transmission-Gate Flip-Flop with Input Gate Isolation 26 1.4.5 C2MOS Flip-Flop 27 1.4.6 Pulse-Triggered Latches 28 1.4.7 Pulse Register Single Latch 29 1.4.8 Purely Digital Flip-Flop 30 1.4.9 Time Window-Based Flip-Flops 31 1.4.9.1 Semi-Dynamic Flip-Flop, (SDFF) 31 1.4.9.2 Hybrid-Latch Flip-Flop, (HLFF) 32 1.4.10 Differential-Input Differential-Output Flip-Flops 33 1.4.10.1 Sense Amplifier Based Flip-Flop, (SAFF) 33 1.4.10.2 Modified Sense Amplifier Flip-Flop, (modSAFF) 34 1.4.11 Flip-Flops with Internal Clock Gating 36 1.4.11.1 Data-Transition Look-Ahead D Flip-Flop, (DL-DFF) 37 1.4.11.2 Clock-on-Demand Flip-Flop, (COD-FF) 38 1.4.11.3 Conditional-Capture Flip-Flop, (CCFF) 39 1.4.11.4 Gated TGFF, (TGCGFF) 39 1.5 Proposed Desig 41 1.6 Environment Setup 43 CHAPTER 2 METHODS 47 CHAPTER 3 RESULTS 55 CHAPTER 4 CONCLUSIONS 78 REFERENCES 80 APPENDICES 83 Appendix A Simulation Results 84 Appendix B Interface Programs 140 ABOUT THE AUTHOR End Page ii LIST OF TABLES Table 2.1: Fan-out for Each Cell Size 50 Table 2.2: Transistor Sizing for Each Cell 52 Table 3.1: Delay Measurements 56 Table 3.2: Power Consumption Measurements 58 Table 3.3: Total Transistor Area and Area Overhead 60 iii LIST OF FIGURES Figure 1.1: Using the Body Effect through Body-Bias Control 15 Figure 1.2: Global RBB Scheme 16 Figure 1.3: n-well Body-Bias Scheme 16 Figure 1.4: Adaptive Body-Bias Control Structure 17 Figure 1.5: Simple Latch 23 Figure 1.6: Clocked D Latch 23 Figure 1.7: Earl’s Latch 24 Figure 1.8: Conventional Transmission Gate Flip-Flop 25 Figure 1.9: Transmission-Gate Master Slave Latch, Used in the PowerPC 603 Microprocessor 25 Figure 1.10: True Single Phase Clock, (TSPC), Master Slave Latch 26 Figure 1.11: 6-stage Transmission Gate Flip-Flop 27 Figure 1.12: C2MOS Flip-Flop 28 Figure 1.13: Intel Pulsed Latch 29 Figure 1.14: Texas Instruments SN7474 D-type Flip-Flop 30 Figure 1.15: Semi-Dynamic Flip-Flop 32 Figure 1.16: Hybrid-Latch Flip-Flop 32 Figure 1.17: Sense Amplifier Flip-Flop 34 Figure 1.18: Modified Sense Amplifier Flip-flop, (modSAFF) 36 iv Figure 1.19: Data-Transition Look-Ahead D Flip-Flop 37 Figure 1.20: Clock-on-Demand Flip-Flop, (COD-FF) 38 Figure 1.21: Conditional-Capture Flip-Flop, (CCFF) 39 Figure 1.22: Gated TGFF 40 Figure 1.23: Proposed Design 41 Figure 1.24: Test Bench Used for the Simulations 46 Figure 2.1: Flip-Flop Time Measurements 48 Figure 2.2: Procedure Followed in the Comparison of the Flip-flops 49 Figure 2.3: Active Circuit Limiting Clock-Q Delay 50 Figure 3.1: Clock-to-Q delay with D Rising, (cqR) 62 Figure 3.2: Clock-to-Q Delay with D Falling, (cqF) 63 Figure 3.3: D-to-Q Delay with D Rising, (dqR) 64 Figure 3.4: D-to-Q Delay with D Falling, (dqF) 65 Figure 3.5: Power Consumption with 1111 as Input Pattern 66 Figure 3.6: Power Consumption with 0101 as Input Pattern 67 Figure 3.7: Power Consumption with 1001 as Input Pattern 68 Figure 3.8: Power Consumption with 0000 as Input Pattern 69 Figure 3.9: Power Consumption with the Input Pattern Comprised of 20 Ones 70 Figure 3.10: Power Consumption with the Input Pattern Comprised of 50 Ones 71 Figure 3.11: Power Consumption with the Input Pattern Comprised of 100 Ones 72 Figure 3.12: Power Consumption with the Input Pattern Comprised of 20 Zeros 73 Figure 3.13: Power Consumption with the Input Pattern Comprised of 50 Zeros 74 Figure 3.14: Power Consumption with the Input Pattern Comprised of 100 Zeros 75 v Figure 3.15: Power Consumed by the FF During the Total Simulation Period, (FFp) 76 Figure 3.16: Power Consumed by the Test Bench Circuit During the Total Simulation Period, (tbP) 77 vi LOW-POWER FLIP-FLOP USING INTERNAL CLOCK GATING AND ADAPTIVE BODY-BIAS Jorge Alberto Galvis ABSTRACT This dissertation presents a new systematic approach to flip-flop design using Internal Clock Gating, (ICG), and Adaptive Body-Bias, (ABB), in order to reduce power consumption. The process requires careful transistor resizing in order to maintain signal integrity and the functionality of the flip-flop at the target frequency. A novel flip-flop architecture, based on the Transmission Gate Flip-Flop, (TGFF), which incorporated ICG and ABB techniques, was designed. This architecture was simulated intensively in order to determine under what conditions its use is appropriate. In addition, it was necessary to establish a methodology for creating a standard testbench and environment setup for the required Hspice simulations. Software tools were written in C++ and Perl in order to facilitate the interface between Cadence Design Tools and Hspice. The new flip-flop, which was named the Low-Power Flip-Flop, (LPFF), was compared to the Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate with Clock-Gating Flip-Flop, (TGCGFF). Comprehensive Hspice simulations of the three flip-flop designs, implemented with Bsim3v3 transistor models for TSMC 180 nm technology, were used as the means of comparison. vii Simulations demonstrated that the new flip-flop is appropriate for applications that require low switching activity. In such a situation the LPFF consumes 7.8% to 95.7% less power than the TGFF and 0.8% to 23.7% less power than the TGCGFF. Power savings obtained by the LPFF increase as the length of the period with no switching activity increases, especially when the input data is all zeros. The trade-off is an increase in the D-to-Q delays and in the flip-flop area.
Load more

Recommended publications
  • Instruction-Level Distributed Processing
    COVER FEATURE Instruction-Level Distributed Processing Shifts in hardware and software technology will soon force designers to look at microarchitectures that process instruction streams in a highly distributed fashion. James E. or nearly 20 years, microarchitecture research In short, the current focus on instruction-level Smith has emphasized instruction-level parallelism, parallelism will shift to instruction-level distributed University of which improves performance by increasing the processing (ILDP), emphasizing interinstruction com- Wisconsin- number of instructions per cycle. In striving munication with dynamic optimization and a tight Madison F for such parallelism, researchers have taken interaction between hardware and low-level software. microarchitectures from pipelining to superscalar pro- cessing, pushing toward increasingly parallel proces- TECHNOLOGY SHIFTS sors. They have concentrated on wider instruction fetch, During the next two or three technology generations, higher instruction issue rates, larger instruction win- processor architects will face several major challenges. dows, and increasing use of prediction and speculation. On-chip wire delays are becoming critical, and power In short, researchers have exploited advances in chip considerations will temper the availability of billions of technology to develop complex, hardware-intensive transistors. Many important applications will be object- processors. oriented and multithreaded and will consist of numer- Benefiting from ever-increasing transistor budgets ous separately
    [Show full text]
  • Clock Gating for Power Optimization in ASIC Design Cycle: Theory & Practice
    Clock Gating for Power Optimization in ASIC Design Cycle: Theory & Practice Jairam S, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, Udayakumar H, Jagdish Rao SoC Center of Excellence, Texas Instruments, India (sjairam, bgm-rao, jithendra, pari, uday, j-rao) @ti.com 1 AGENDA • Introduction • Combinational Clock Gating – State of the art – Open problems • Sequential Clock Gating – State of the art – Open problems • Clock Power Analysis and Estimation • Clock Gating In Design Flows JS/BGM – ISLPED08 2 AGENDA • Introduction • Combinational Clock Gating – State of the art – Open problems • Sequential Clock Gating – State of the art – Open problems • Clock Power Analysis and Estimation • Clock Gating In Design Flows JS/BGM – ISLPED08 3 Clock Gating Overview JS/BGM – ISLPED08 4 Clock Gating Overview • System level gating: Turn off entire block disabling all functionality. • Conditions for disabling identified by the designer JS/BGM – ISLPED08 4 Clock Gating Overview • System level gating: Turn off entire block disabling all functionality. • Conditions for disabling identified by the designer • Suspend clocks selectively • No change to functionality • Specific to circuit structure • Possible to automate gating at RTL or gate-level JS/BGM – ISLPED08 4 Clock Network Power JS/BGM – ISLPED08 5 Clock Network Power • Clock network power consists of JS/BGM – ISLPED08 5 Clock Network Power • Clock network power consists of – Clock Tree Buffer Power JS/BGM – ISLPED08 5 Clock Network Power • Clock network power consists of – Clock Tree Buffer
    [Show full text]
  • Saber Eletrônica, Designers Pois Precisamos Comprovar Ao Meio Anunciante Estes Números E, Assim, Carlos C
    editorial Editora Saber Ltda. Digital Freemium Edition Diretor Hélio Fittipaldi Nesta edição comemoramos o fantástico número de 258.395 downloads da edição 460 digital em PDF que tivemos nos primeiros 50 dias de circu- www.sabereletronica.com.br lação. Assim, esperamos atingir meio milhão em twitter.com/editora_saber seis meses. Na fase de teste, no ano passado, com Editor e Diretor Responsável a Edição Digital Gratuita que chamamos de “Digital Hélio Fittipaldi Conselho Editorial Freemium (Free + Premium) Edition”, já atingimos João Antonio Zuffo este marco e até ultrapassamos. Redação Fica aqui nosso agradecimento a todos os que Hélio Fittipaldi Augusto Heiss seguiram nosso apelo, para somente fazerem Revisão Técnica Eutíquio Lopez download das nossas edições através do link do Portal Saber Eletrônica, Designers pois precisamos comprovar ao meio anunciante estes números e, assim, Carlos C. Tartaglioni, Diego M. Gomes obtermos patrocínio para manter a edição digital gratuita. Publicidade Aproveitamos também para avisar aos nossos leitores de Portugal, Caroline Ferreira, cerca de 6.000 pessoas, que infelizmente os custos para enviarmos as Nikole Barros revistas impressas em papel têm sido altos e, por solicitação do nosso Colaboradores Alexandre Capelli, distribuidor, não enviaremos mais os exemplares impressos em papel Bruno Venâncio, para distribuição no mercado português e ex-colônias na África. César Cassiolato, Dante J. S. Conti, Em junho teremos a edição especial deste semestre e o assunto prin- Edriano C. de Araújo, cipal é a eletrônica embutida (embedded electronic), ou como dizem os Eutíquio Lopez, Tsunehiro Yamabe espanhóis e portugueses: electrónica embebida. Como marco teremos também no Centro de Exposições Transamérica em São Paulo, a 2ª edição da ESC Brazil 2012 e a 1ª MD&M, o maior evento de tecnologia para o mercado de design eletrônico que, neste ano, estará sendo promovido PARA ANUNCIAR: (11) 2095-5339 pela UBM junto com o primeiro evento para o setor médico/odontoló- [email protected] gico (a MD&M Brazil).
    [Show full text]
  • Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: a Practical Approach∗
    IEICE TRANS. INF. & SYST., VOL.E101–D, NO.4 APRIL 2018 1116 PAPER Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach∗ Carlos Cesar CORTES TORRES†a), Nonmember, Hayate OKUHARA†, Student Member, Nobuyuki YAMASAKI†, Member, and Hideharu AMANO†, Fellow SUMMARY In the past decade, real-time systems (RTSs), which must in RTSs. These techniques can improve energy efficiency; maintain time constraints to avoid catastrophic consequences, have been however, they often require a large amount of power since widely introduced into various embedded systems and Internet of Things they must control the supply voltages of the systems. (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we in- Body bias (BB) control is another solution that can im- vestigated the RTS energy efficiency by analyzing the ability of body bias prove RTS energy efficiency as it can manage the tradeoff (BB) in providing a satisfying tradeoff between performance and energy. between power leakage and performance without affecting We propose a practical and realistic model that includes the BB energy and the power supply [4], [5].Itseffect is further endorsed when timing overhead in addition to idle region analysis. This study was con- ducted using accurate parameters extracted from a real chip using silicon systems are enabled with silicon on thin box (SOTB) tech- on thin box (SOTB) technology. By using the BB control based on the nology [6], which is a novel and advanced fully depleted sili- proposed model, about 34% energy reduction was achieved.
    [Show full text]
  • Register Allocation and VDD-Gating Algorithms for Out-Of-Order
    Register Allocation and VDD-Gating Algorithms for Out-of-Order Architectures Steven J. Battle and Mark Hempstead Drexel University Philadelphia, PA USA Email: [email protected], [email protected] Abstract—Register Files (RF) in modern out-of-order micro- 100 avg Int avg FP processors can account for up to 30% of total power consumed INT → → by the core. The complexity and size of the RF has increased due 80 FP to the transition from ROB-based to MIPSR10K-style physical register renaming. Because physical registers are dynamically 60 allocated, the RF is not fully occupied during every phase of the application. In this paper, we propose a comprehensive power 40 management strategy of the RF through algorithms for register allocation and register-bank power-gating that are informed by % of runtime 20 both microarchitecture details and circuit costs. We investigate algorithms to control where to place registers in the RF, when to 0 disable banks in the RF, and when to re-enable these banks. We 60 80 100 120 140 160 include detailed circuit models to estimate the cost for banking Num. Registers Occupied and power-gating the RF. We are able to save up to 50% of the leakage energy vs. a baseline monolithic RF, and save 11% more Fig. 1. Average Reg File occupancy CDF for SPEC2006 workloads. leakage energy than fine-grained VDD-gating schemes. 1 1 Index Terms—Computer architecture, Gate leakage, Registers, SRAM cells 0.8 0.8 I. INTRODUCTION 0.6 0.6 F.cactus I.astar 0.4 0.4 Out-of-order superscalar processors, historically found only F.gems I.libq in high-performance computing environments, are now used in F.milc I.go 0.2 F.pov 0.2 Imcf a diverse range of energy-constrained applications from smart- F.zeus Iomn phones to data-centers.
    [Show full text]
  • A 65 Nm 2-Billion Transistor Quad-Core Itanium Processor
    18 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 A 65 nm 2-Billion Transistor Quad-Core Itanium Processor Blaine Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul Gronowski, Dan Krueger, Charles Morganti, and Steve Troyer Abstract—This paper describes an Itanium processor imple- mented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105 C. High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s. Index Terms—65-nm process technology, circuit design, clock distribution, computer architecture, microprocessor, on-die cache, voltage domains. I. OVERVIEW Fig. 1. Die photo. HE next generation in the Intel Itanium processor family T code named Tukwila is described. The 21.5 mm by 32.5 mm die contains 2.05 billion transistors, making it the first two billion transistor microprocessor ever reported. Tukwila combines four ported Itanium cores with a new system interface and high speed serial interconnects to deliver greater than 2X performance relative to the Montecito and Montvale family of processors [1], [2]. Tukwila is manufactured in a 65 nm process with 8 layers of copper interconnect as shown in the die photo in Fig. 1. The Tukwila die is enclosed in a 66 mm 66 mm FR4 laminate package with 1248 total landed pins as shown in Fig.
    [Show full text]
  • Optimization of Clock Gating Logic for Low Power LSI Design
    Optimization of Clock Gating Logic for Low Power LSI Design Xin MAN September 2012 Waseda University Doctoral Dissertation Optimization of Clock Gating Logic for Low Power LSI Design Xin MAN Graduate School of Information, Production and Systems Waseda University September 2012 Abstract Power consumption has become a major concern for usability and reliability problems of semiconductor products, especially with the significant spread of portable devices, like smartphone in recent years. Major source of dynamic power consumption is the clock tree which may account for 45% of the system power, and clock gating is a widely used technique to reduce this portion of power dissipation. The basic idea of clock gating is to reduce the dynamic power consumption of registers by switching off unnecessary clock signals to the registers selectively depending on the control signal without violating the functional correctness. Clock gating may lead to a considerable power reduction of overall system with proper control signals. Since the clock gating logic consumes chip area and power, it is imperative to minimize the number of inserted clock gating cells and their switching activity for power optimization. Commercial tools support clock gating as a power optimization feature based on the guard signal described in HDL and the minimum number of registers injecting the clock gating cell specified as the synthesis option (structural method). However, this approach requires manual identification of proper control signals and the proper grouping of registers to be gated. That is hard and designer-intensive work. Automatic clock gating generation and optimization is necessary. In this dissertation, we focus on the optimization of clock gating logic i ii based on switching activity analysis including clock gating control candidate extraction from internal signals in the original design and optimum control signal selection considering sharing of a clock gating cell among multiple registers for power and area optimization.
    [Show full text]
  • Clock Gating
    EDA Challenges for Low Power Design Anand Iyer, Cadence Design Systems Agenda • ItIntrod ucti on • LP techniques in detail • Challenges to low power techniques • Guidelines for choosinggq various techniques Why is Power an Issue? Leakage Power Active Performance = Power 180 130 90 65 Source: Intel, 2004 mW/MHzProcess Technology (nm) PhPower hungry process Source: EETimes, 2004 Complex System Sluggish Battery Life Improvement 2000 2001 2002 2003 2004 Approaches To Power Management • System Architecture (multi-core) Leakage Active • Software/Hardware power management system – ARM IEM Design and System Level • Voltage scaling / frequency scaling Optimizat io n • Multiple voltage islands •We Clock gating, will logic discuss structuring this •Multi-Vth cell selection to reduce leakage Implementation • Support for multiin voltagedetail islands (aka “multi-vdd” aka “MSV”) implementation • Signoff accurate analysis •SOI Process Level Optimization • High-K, Gate Stack, power gating, etc. • LLD Controlling Power in Implementation Dynamic power Leakage power 2 (≈ k•Ck • C L •V• V DD •f• f CLK) (≈ VDD • Ileakage) • Clock gating (including de-clone) • Multi-Vt cell optimization • Area optimization • Substrate biasing (VT CMOS) • Static voltage scaling (MSV)* • Power shut-off (PSO) – aka • Dynamic voltage frequency scaling MTCMOS - including State retention (DVFS)* • Adaptive voltage scaling (AVS)* – Fine grain control – Coarse grain control * Techniques that affect both dynamic and leakage power Techniques and Trade-offs Power reduction Leakage Dynamic
    [Show full text]
  • Mutual Impact Between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators
    electronics Article Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators Francesco Ratto 1 , Tiziana Fanni 2 , Luigi Raffo 1 and Carlo Sau 1,* 1 Dipartimento di Ingegneria Elettrica ed Elettronica, Università degli Studi di Cagliari, Piazza d’Armi snc, 09123 Cagliari, Italy; [email protected] (F.R.); [email protected] (L.R.) 2 Dipartimento di Chimica e Farmacia, Università degli Studi di Sassari, Via Vienna 2, 07100 Sassari, Italy; [email protected] * Correspondence: [email protected] Abstract: With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.
    [Show full text]
  • White P Aper
    WHITE PAPER CREATING LOW-POWER DIGITAL INTEGRATED CIRCUITS – THE IMPLEMENTATION PHASE INTRODUCTION Power consumption has now moved to the forefront of digital integrated circuit (IC) development con- cerns. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Furthermore, with every new pro- cess generation, leakage power consumption increases at an exponential rate. In recent years, a wide variety of techniques have been developed to address the various aspects of the power problem and to meet ever more aggressive power specifications. These techniques include clock gating, multi-switching threshold (multi-Vt) transistors, multi-supply multi-voltage (MSMV), substrate biasing, dynamic voltage and frequency scaling (DVFS), and power shut-off (PSO). Figure 1 illustrates the power, timing, and area tradeoffs among the various power management techniques. Power-reduction Power Timing Area Methodology Impact Benefit Penalty Penalty Technique Architecture Design Verification Implementation Multi-Vt Optimization Medium Little Little Low Low None Low Clock Gating Medium Little Little Low Low None Low Multi-supply Voltage Large Some Little High Medium Low Medium Power Shut-off HUGE Some Some High High High High Dynamic and Large Some Some High High High High Adaptive Voltage Frequency Scaling Substrate Biasing Large Some Some Medium None None High Figure 1. Tradeoffs associated with the various power management techniques Notably, designers cannot simply “bolt on” low power” at the end of the development process. The size and complexity of today’s ICs makes it imperative to consider power throughout the design phases—the chip/system architecture, power architecture, and design (including micro-architecture decisions)—and all the way to implementation with power-aware synthesis, placement, and routing.
    [Show full text]
  • 1/2 - 2008 Elektronik Industrie
    EI_Titel 29.01.2008 14:27 Uhr Seite 1 Februar 2008 branchenorientierte applikationen für elektronik-entwickler 39. JAHRGANG 14,00 € unverbindliche Preisempfehlung Nr.1/2 D 19067 39. JAHRGANG Was Entwickler wissen müssen! www.elektronik-industrie.de 1/2 - 2008 elektronik industrie elektronik BESUCHEN EMV 2008 SIE UNS: Stand-Nr.: Embedded World CCD-320 Halle 10.0 Stand: 10-406 EMBEDDED SYSTEME Embedded-Systeme, Programmierbare Logik, Labormesstechnik, Kfz-Elektronik Neues vom PowerPC ÿ 24 UNIT Testing neu formuliert ÿ 40 Flexible BIOS- Konfiguration ÿ 44 PROGRAMMIERBARE LOGIK Abgleich der Pin-Belegung ÿ 83 Mikrocontroller-Design inin FPGAsFPGAs ÿ 86 LABOR- MESSTECHNIK Oszilloskope: Warum analog? ÿ 56 Signalintegrietätsanalyse und Compliance Testing ÿ 60 www.elektronik-industrie.de www.automobil-elektronik.de 2008 MESSE AUTOMOBIL ELEKTRONIK SPEZIAL KFZ-ELEKTRONIK EMV 2008 DÜSSELDORF Eine Sonderausgabe der Fachmagazine elektronik industrie und AUTOMOBIL ELEKTRONIK Mikrocontroller steuern AutoSar Demonstrator ÿ 90 ININ DIESERDIESER AUSGABE ˘ TITELSTORY: ÿ erfolgsmedien für experten Ethernet für „Grenzenlose Verbindung“ 22 Entdecken Sie weitere interessante Artikel und News zum Thema auf all-electronics.de! Hier klicken & informieren! Wir messen die Performance von Mobilgeräten in ␮A und MHz. Bei Handheld-Entwicklungen gilt, analog is everywhere. ADI Produkte, optimiert für Handheld-Entwicklungen Anwendungsoptimierte ICs vereinfachen und Klasse-D-Verstärker SSM2301 Geringe EMI, niedrige THD beschleunigen Ihre Entwicklung Audio Mikrofon-Vorverstärker
    [Show full text]
  • Low Power Data-Dependent Transform Video and Still Image Coding
    Low Power Data-Dependent Transform Video and Still Image Coding by Thucydides Xanthopoulos Bachelor of Science in Electrical Engineering Massachusetts Institute of Technology, June 1992 Master of Science in Electrical Engineering and Computer Science Massachusetts Institute of Technology, February 1995 Submitted to the Department of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology February 1999 c 1999 Massachusetts Institute of Technology. All rights reserved. Signature of Author Department of Electrical Engineering and Computer Science February 1, 1999 Certified by Anantha Chandrakasan, Ph.D. Associate Professor of Electrical Engineering Thesis Supervisor Accepted by Arthur Clarke Smith, Ph.D. Professor of Electrical Engineering Graduate Officer 2 Low Power Data-Dependent Transform Video and Still Image Coding by Thucydides Xanthopoulos Submitted to the Department of Electrical Engineering and Computer Science on February 1, 1999 in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science Abstract This work introduces the idea of data dependent video coding for low power. Algorithms for the Discrete Cosine Transform (DCT) and its inverse are introduced which exploit sta- tistical properties of the input data in both the space and spatial frequency domains in order to minimize the total number of arithmetic operations. Two VLSI chips have been built as a proof-of-concept of data dependent processing implementing the DCT and its inverse (IDCT). The IDCT core processor exploits the presence of a large number of zero- valued spectral coefficients in the input stream when stimulated with MPEG-compressed video sequences.
    [Show full text]